Ferroelectric tunnel junction and method of fabrication

Abstract

The application relates to the technical field of semiconductors, and discloses a ferroelectric tunnel junction and a preparation method. The ferroelectric tunnel junction comprises a ferroelectric functional layer and an interposed layer. The interposed layer is arranged on one side of the ferroelectric functional layer; wherein the material of the interposed layer is a two-dimensional material. The interposed layer made of the two-dimensional material is added on the basis of a traditional metal-ferroelectric layer-metal structure ferroelectric tunnel junction, the asymmetry of the interface charge before and after the polarization reversal is increased by arranging the interposed layer. The unique energy band structure of the two-dimensional material increases the asymmetry degree of the energy band bending caused by the different polarization directions of the ferroelectric, and the energy band position of the two-dimensional material is changed by the charge injection of the ferroelectric polarization reversal. By the two-dimensional material, the intermetallic gap state can be reduced, the contact resistance is reduced, the on-off ratio can be improved, the off-state current can be inhibited and the on-state current can be increased, the durability and the retention characteristics of the ferroelectric tunnel junction are improved, and the stability and the rectification ratio of the ferroelectric tunnel junction are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a ferroelectric tunnel junction and its preparation method. Background Technology

[0002] Ferroelectric tunnel junctions (FTJs) are non-volatile memory devices that sandwich a ferroelectric functional layer between electrodes. They achieve storage functionality by utilizing the differences in shielding capabilities between the electrodes, allowing the device to possess different resistance states under different polarization states. However, due to the limitations of electrode shielding characteristics, their on / off ratio is not high. Among these, hafnium zirconium oxide (HZO)-based FTJs have attracted considerable attention due to their high-speed switching, lossless readout characteristics, and good compatibility with complementary metal-oxide-semiconductor (CMOS) processes.

[0003] Existing ferroelectric hafnium zirconium oxide materials are prepared by doping zirconium into hafnium oxide (HfO2) and rapidly annealing it at high temperature to obtain the o phase (orthorhombic phase) with ferroelectric properties. Its polarization state can be switched under an applied voltage and will not change when the applied voltage is removed. This property makes it suitable for use in binary memory. Common ferroelectric memories include ferroelectric random access memory (FeRAM), ferroelectric field-effect transistor (FeFET), and ferroelectric tunnel junction (FTJ).

[0004] However, hafnium-zirconium oxide-based ferroelectric tunnel junctions still face several key challenges in practical applications. First, in traditional metal-ferroelectric layer-metal (MFM) ferroelectric tunnel junctions, information storage relies on the asymmetric shielding effect of the two metal electrodes on the ferroelectric polarization charge, resulting in different resistive states before and after polarization reversal, thus achieving binary storage. However, due to the limited difference in shielding capability between the metal electrodes, the on / off ratio (i.e., the ratio of current between the high-resistance state and the low-resistance state) of these devices is typically low, exhibiting a significant disadvantage compared to two-terminal memories such as resistive random access memory (RRAM).

[0005] To improve the on / off ratio, current mainstream research often employs composite structures, such as metal-insulator-ferroelectric-metal (MIFM) or semiconductor-insulator-ferroelectric-metal (SIFM). While these structures can enhance the resistive on / off ratio to some extent, they also introduce new problems: the additional insulating layer inevitably increases the device's barrier height, leading to a significant reduction in on-state current. This not only limits the device's application in miniaturization scenarios but also increases the demand for external current amplifiers, thereby diminishing the integration density advantage originally expected of ferroelectric tunnel junctions.

[0006] To improve on-state current, many studies have focused on reducing the thickness of the ferroelectric layer. However, this strategy also faces significant challenges. On the one hand, the ferroelectricity of hafnium zirconium oxide degrades significantly with decreasing thickness, thus weakening the on / off ratio; simultaneously, ultrathin ferroelectric layers place extremely stringent requirements on the fabrication process. On the other hand, although previous studies have achieved ferroelectricity in 1-nanometer-thick hafnium zirconium oxide films and successfully fabricated ferroelectric tunnel junctions, the stability of the devices is generally poor. The main reason for this is that reducing the thickness of the ferroelectric layer significantly enhances the depolarization field, exacerbates polarization relaxation and performance degradation, thereby affecting the reliability and lifespan of the devices.

[0007] In addition, after HZO is prepared, it needs to be rapidly annealed under specific coating electrodes (e.g., titanium nitride, tungsten, nickel, platinum, etc.) to prepare the ferroelectric phase. The annealing temperature is usually 400℃ to 900℃. The higher the temperature, the better the ferroelectricity, but the more internal defects there are, and the fabricated device is prone to forming a large leakage current. Summary of the Invention

[0008] This invention provides a ferroelectric tunnel junction and its preparation method, which solves at least one of the defects in the prior art and achieves the effect of significantly improving the switching ratio and on-state current of the ferroelectric tunnel junction.

[0009] The first aspect of the present invention provides a ferroelectric tunnel junction, comprising: Ferroelectric functional layer; An insertion layer is disposed on one side of the ferroelectric functional layer, wherein the material of the insertion layer is a two-dimensional material; The first electrode layer is disposed on the side of the ferroelectric functional layer away from the insertion layer; The second electrode layer is disposed on the side of the insertion layer away from the ferroelectric functional layer.

[0010] According to the ferroelectric tunnel junction provided by the present invention, the two-dimensional material includes one of two-dimensional perovskite material, graphene, and boron nitride.

[0011] The ferroelectric tunnel junction provided by the present invention further includes: A first dielectric layer is disposed between the ferroelectric functional layer and the insertion layer; or, the first dielectric layer is disposed between the insertion layer and the second electrode layer; or, the first dielectric layer is disposed between the first electrode layer and the ferroelectric functional layer.

[0012] According to the ferroelectric tunnel junction provided by the present invention, the thickness of the first dielectric layer is less than the thickness of the ferroelectric functional layer.

[0013] According to the ferroelectric tunnel junction provided by the present invention, the material of the first electrode layer includes a conductive metal or a conductive metal compound, and / or the material of the second electrode layer includes a conductive metal or a conductive metal compound.

[0014] According to the ferroelectric tunnel junction provided by the present invention, the conductive metal includes at least one of titanium, gold and platinum; the conductive metal compound includes titanium nitride.

[0015] According to the ferroelectric tunnel junction provided by the present invention, the ferroelectric functional layer is prepared from ferroelectric materials.

[0016] According to the ferroelectric tunnel junction provided by the present invention, the ferroelectric material includes at least one of hafnium zirconium oxide, lead titanate, and two-dimensional ferroelectric materials.

[0017] A second aspect of the present invention provides a method for preparing a ferroelectric tunnel junction, characterized in that the method for preparing the ferroelectric tunnel junction according to any one of the above-mentioned methods includes: A first electrode layer, a ferroelectric functional layer, and a top electrode layer are sequentially deposited on a substrate; The top electrode layer is then etched away after annealing. The insertion layer is moved to the side of the ferroelectric functional layer away from the first electrode layer.

[0018] According to the method for preparing a ferroelectric tunnel junction provided by the present invention, when the ferroelectric functional layer is a ferroelectric hafnium zirconium oxide layer, the annealing process conditions are: annealing temperature 450°C to 650°C, heating for 25 to 35 seconds, cooling for 25 to 35 seconds, and then holding for 50 to 70 seconds.

[0019] The ferroelectric tunnel junction provided by this invention is equivalent to adding an insertion layer to the traditional metal-ferroelectric layer-metal structure ferroelectric tunnel junction. By setting this insertion layer, the asymmetry of the interface charge before and after polarization reversal can be increased, which can effectively reduce the on-state barrier. Compared with the traditional metal-ferroelectric layer-metal structure ferroelectric tunnel junction, it can achieve a simultaneous improvement in on-state ratio and on-state current. Utilizing the band structure of the two-dimensional material, the degree of band bending asymmetry caused by the ferroelectric functional layer in different polarization directions is increased, and the charge injection during ferroelectric polarization reversal also changes the band position of the two-dimensional material. This can suppress the off-state current and increase the on-state current, thereby improving the on-state ratio of the ferroelectric tunnel junction. In addition, the two-dimensional material can also reduce the metal gap state, thereby reducing the contact resistance and improving the durability and retention characteristics of the device, ultimately obtaining a ferroelectric tunnel junction with higher stability and better rectification ratio. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the ferroelectric tunnel junction provided by the present invention.

[0022] Figure 2 This is a flowchart of the preparation method of the ferroelectric tunnel junction provided by the present invention.

[0023] Figure 3 In the diagram, (a) and (c) represent ferroelectric tunnel junctions with MFM configurations of different polarization directions, i.e., MFM-FTJ; (b) and (d) represent ferroelectric tunnel junctions with graphene (GR) inserted as the intercalation layer of different polarization directions, i.e., GR-FTJ.

[0024] Figure 4 (a) shows the current (I)-voltage (V) graphs for MFM-FTJ, Gr-FTJ, and BN-FTJ; (b) shows the relationship between the on-state current and on-state ratio of MFM-FTJ and Gr-FTJ as a function of the thickness of HfO2.

[0025] Figure 5 This is a current (I)-voltage (V) curve for Comparative Example 1 and Example 8.

[0026] Figure 6 These are the test results of PUND for Comparative Example 1 and Example 8.

[0027] Figure 7 This is the retention curve of Example 8.

[0028] Figure 8 This is the erase and write resistance curve of Example 8. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0030] In the description of this specification, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are used only for the convenience of describing this specification. They do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this specification. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] In the description of this specification, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this invention based on the specific circumstances.

[0032] In this specification, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0033] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0034] In the embodiments of this specification, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0035] like Figure 1 As shown, a first aspect of the present invention provides a ferroelectric tunnel junction. The ferroelectric tunnel junction includes a ferroelectric functional layer and an insertion layer. The insertion layer is disposed on one side of the ferroelectric functional layer; wherein the material of the insertion layer is a two-dimensional material. In other words, the insertion layer is laid on one side of the ferroelectric functional layer.

[0036] This is equivalent to adding an insertion layer to the traditional metal-ferroelectric layer-metal (MIFM) ferroelectric tunnel junction. By setting this insertion layer, the asymmetry of the interface charge before and after polarization reversal can be increased, which can reduce the on-state barrier. Compared with the traditional metal-ferroelectric layer-metal ferroelectric tunnel junction, it can achieve a simultaneous increase in on-state ratio and on-state current.

[0037] Optionally, the insertion layer is made of a two-dimensional material. The band structure of the two-dimensional material increases the asymmetry of band bending caused by the ferroelectric layer under different polarization directions. Furthermore, the charge injection during ferroelectric polarization reversal also changes the band position of the two-dimensional material. This can suppress off-state current and increase on-state current, thereby improving the on / off ratio of the ferroelectric tunnel junction. In addition, the two-dimensional material layer can reduce the metal gap states, thereby reducing contact resistance and improving the device's durability and retention characteristics, ultimately resulting in a ferroelectric tunnel junction with higher stability and a better rectification ratio.

[0038] It should be noted that two-dimensional materials refer to materials in which electrons can move freely (e.g., planar motion) only in two dimensions at a non-nanoscale (e.g., 1nm to 100nm), such as nanofilms, superlattices, and quantum wells.

[0039] Optionally, the two-dimensional material includes at least one selected from two-dimensional perovskite materials, graphene, and boron nitride. Preferably, the two-dimensional material is graphene or boron nitride.

[0040] When constructing atomic-level structures using density functional theory (DFT) and calculating interface barriers and transport properties using the non-equilibrium Green's function (NEGF) method, it was found that the introduction of graphene as an intercalation layer can reduce the on-state barrier, achieving a simultaneous improvement in on-state ratio and on-state current compared to traditional FTJ structures. The low quantum capacitance of graphene helps to modulate the metal-induced gap states (MIGS) at the metal-ferroelectric interface. DFT calculations show that graphene can alter the interface charge distribution and suppress the Fermi pinning effect. Therefore, the introduction of the graphene intercalation layer enhances the on-state characteristics of the FTJ and increases the on-state current. Experiments demonstrate that the graphene intercalation layer can also reduce the dead layer thickness and decrease the interface defect concentration. These effects work together to improve the on-state current of the device and further enhance the on-state ratio by suppressing leakage current. Furthermore, the device exhibits a lower depolarization field and superior interface quality compared to traditional metal-semiconductor contacts, thereby improving device reliability.

[0041] Optionally, the ferroelectric functional layer is prepared from a ferroelectric material. Specifically, the material of the ferroelectric functional layer includes any ferroelectric material that can be used to manufacture the device.

[0042] It should be noted that ferroelectric materials refer to a class of materials that exhibit ferroelectric effect. They are a special type of dielectric material, whose fundamental characteristic is that they have spontaneous polarization, and the direction of spontaneous polarization can be reversed or reoriented by an applied electric field.

[0043] Optionally, the material of the ferroelectric functional layer includes at least one of hafnium zirconium oxide, ferroelectric perovskite materials, and two-dimensional ferroelectric materials.

[0044] Preferably, the ferroelectric perovskite material includes lead titanate. Two-dimensional ferroelectric materials include one of indium selenide, copper indium sulfide phosphorus, or black phosphorus.

[0045] In specific embodiments of the present invention, the thickness of the ferroelectric functional layer is not limited. In other words, in specific embodiments of the present invention, the ferroelectric functional layer can be of any thickness, which reduces the difficulty of fabricating the device.

[0046] In one embodiment of the present invention, the ferroelectric tunnel junction further includes a first electrode layer and a second electrode layer; the first electrode layer is disposed on the side of the ferroelectric functional layer away from the insertion layer; the second electrode layer is disposed on the side of the insertion layer away from the ferroelectric functional layer. In other words, the first electrode layer and the insertion layer are respectively laid on opposite sides of the ferroelectric functional layer, and the second electrode layer and the ferroelectric functional layer are respectively laid on opposite sides of the insertion layer. The first electrode layer and the second electrode layer together form a complete "electrode-functional layer-electrode" sandwich structure, thereby providing a complete electrical path for the entire ferroelectric tunnel junction device. By applying a voltage between the second electrode layer and the first electrode layer, a controllable electric field can be generated in the ferroelectric functional layer to drive the reversal of the ferroelectric polarization state, realizing the writing operation of the high and low resistance states of the device. At the same time, this complete electrical path is also the basis for reading the resistance state of the device. By applying a small read voltage, the magnitude of the tunneling current flowing through the tunnel junction can be detected, thereby identifying the information stored in the device without loss. Furthermore, the choice of material for the second electrode layer and the interface characteristics formed with the two-dimensional material insertion layer can further optimize the band structure and contact resistance of the device, and work synergistically with the insertion layer to enhance the tunnel electrical resistance (TER) effect, ultimately improving the overall performance of the device.

[0047] Optionally, the material of the first electrode layer includes at least one of conductive metals, conductive metal compounds, and conductive non-metals.

[0048] Optionally, the material of the second electrode layer includes at least one of conductive metals, conductive metal compounds, and conductive non-metals.

[0049] Preferably, the conductive metal includes at least one of titanium, gold, and platinum. Conductive metal compounds include titanium nitride. Conductive nonmetals include conductive two-dimensional materials such as graphene.

[0050] In some embodiments of the present invention, the ferroelectric tunnel junction further includes a first dielectric layer; the first dielectric layer is disposed between the ferroelectric functional layer and the insertion layer. In other words, the ferroelectric functional layer and the insertion layer are respectively deposited on opposite sides of the first dielectric layer; or, the first dielectric layer is disposed between the insertion layer and the second electrode layer, in other words, the insertion layer and the second electrode layer are respectively deposited on opposite sides of the first dielectric layer; or, the first dielectric layer is disposed between the first electrode layer and the ferroelectric functional layer, in other words, the first electrode layer and the ferroelectric functional layer are respectively deposited on opposite sides of the first dielectric layer. The introduction of this first dielectric layer, as an additional functional interface layer, provides additional degrees of control for optimizing device performance. As an insulating layer, the first dielectric layer can also suppress leakage current caused by possible interface defect states, thereby reducing the device's off-state power consumption and improving the accuracy of read / write operations.

[0051] Specifically, regardless of its location, the first dielectric layer can optimize interface quality. For example, it can act as a diffusion barrier layer, effectively reducing the risk of atomic interdiffusion or chemical reactions between adjacent material layers during device fabrication or operation, thereby ensuring the steepness and chemical stability of the interface, which helps improve the overall reliability and durability of the device.

[0052] Furthermore, by selecting the material and thickness of the first dielectric layer, the barrier profile of the entire tunnel junction can be engineered with greater precision. This first dielectric layer itself constitutes part of the tunneling barrier, and its dielectric constant and band gap directly affect the height and shape of the barrier. This allows designers to further finely control the electron tunneling probability. This control can be combined with the ferroelectric polarization reversal effect and the band modulation effect of the two-dimensional material insertion layer to synergistically enhance the switching modulation of the tunneling current, ultimately achieving a higher tunnel electroresistivity (TER) ratio.

[0053] Optionally, the thickness of the first dielectric layer is less than the thickness of the ferroelectric functional layer. Designing the first dielectric layer to be thinner than the ferroelectric functional layer serves two purposes. First, it ensures that the ferroelectric polarization effect of the ferroelectric functional layer dominates the entire device, thus guaranteeing that the switching characteristics of the tunneling resistance are primarily modulated by ferroelectric polarization switching, rather than being weakened or masked by the additional first dielectric layer. Second, since the applied driving voltage is divided across the entire stacked structure according to the thickness and dielectric constant of each layer, a thinner first dielectric layer means it bears a smaller voltage. This ensures that most of the applied driving voltage can effectively act on the ferroelectric functional layer to achieve efficient polarization switching, thereby effectively reducing the overall operating voltage and write power consumption of the device. Furthermore, from the perspective of quantum tunneling, the total tunneling barrier thickness is a factor affecting the tunneling current. Maintaining a smaller thickness for the first dielectric layer avoids the problem of a sharp decrease in tunneling probability due to an excessively thick barrier layer, thus ensuring that the device still has a sufficiently large readable current in the on-state.

[0054] Optionally, the material of the first dielectric layer includes at least one of magnesium oxide, aluminum oxide, silicon oxide, and silicon. Preferably, the silicon is p-type silicon.

[0055] In other embodiments of the present invention, the ferroelectric tunnel junction further includes a semiconductor layer or a second dielectric layer. The semiconductor layer is disposed on the side of the ferroelectric functional layer away from the insertion layer; in other words, a semiconductor layer and an insertion layer are respectively deposited on opposite sides of the ferroelectric functional layer. The second dielectric layer is disposed on the side of the ferroelectric functional layer away from the insertion layer; in other words, a second dielectric layer and an insertion layer are respectively deposited on opposite sides of the ferroelectric functional layer.

[0056] The semiconductor layer is disposed on the side of the ferroelectric functional layer away from the insertion layer; in other words, the semiconductor layer and the insertion layer are respectively deposited on opposite sides of the ferroelectric functional layer. By introducing the semiconductor layer, the carrier concentration of the semiconductor layer can be modulated using the polarization electric field of the ferroelectric functional layer, thus realizing the field-effect gate control function and achieving an on / off ratio far higher than that of traditional tunnel junction structures. Furthermore, this structure based on channel conductivity modulation supports non-destructive read operations, improving device durability and data retention capabilities, and is beneficial for realizing high-density, low-power non-volatile memories.

[0057] The second dielectric layer is disposed on the side of the ferroelectric functional layer away from the insertion layer. In other words, the second dielectric layer and the insertion layer are respectively deposited on opposite sides of the ferroelectric functional layer. By setting this second dielectric layer, it can form a composite tunnel barrier together with the ferroelectric functional layer. This composite structure can suppress the leakage current of the device, thereby reducing off-state power consumption and improving the switching ratio. At the same time, the second dielectric layer can also act as a buffer layer, improving interface quality, reducing defect states, and enhancing the overall stability and breakdown resistance of the device. It further enhances the asymmetry of the overall barrier of the ferroelectric tunnel junction, which helps to obtain a better tunneling electroresistivity effect.

[0058] Optionally, the semiconductor layer may be made of silicon or silicon oxide.

[0059] Optionally, the material of the second dielectric layer includes at least one of magnesium oxide, aluminum oxide, silicon oxide, and silicon. Preferably, the silicon is p-type silicon.

[0060] Example 1 This embodiment 1 provides a ferroelectric tunnel junction. The ferroelectric tunnel junction includes a titanium nitride layer, a hafnium zirconium oxide layer, a graphene layer, and a titanium layer. The titanium nitride layer is the first electrode layer, the hafnium zirconium oxide layer is the ferroelectric functional layer, the graphene layer is the insertion layer, and the titanium layer is the second electrode layer.

[0061] Example 2 This embodiment 2 provides a ferroelectric tunnel junction. The ferroelectric tunnel junction includes a titanium nitride layer, a lead titanate (PbTiO3) layer, a graphene layer, and a gold layer. Among them, the titanium nitride layer is the first electrode layer, the lead titanate (PbTiO3) layer is the ferroelectric functional layer, the graphene layer is the insertion layer, and the gold layer is the second electrode layer.

[0062] Example 3 This embodiment 3 provides a ferroelectric tunnel junction. The ferroelectric tunnel junction includes a platinum layer, a hafnium-zirconium oxide layer, an aluminum oxide layer, a boron nitride layer, and a gold layer. The platinum layer is the first electrode layer, the hafnium-zirconium oxide layer is the ferroelectric functional layer, the aluminum oxide layer is the first dielectric layer, the boron nitride layer is the insertion layer, and the gold layer is the second electrode layer.

[0063] Example 4 This embodiment 4 provides a ferroelectric tunnel junction. The ferroelectric tunnel junction includes a titanium nitride layer, a hafnium zirconium oxide layer, a graphene layer, an alumina layer, and a titanium layer. The titanium nitride layer is the first electrode layer, the hafnium zirconium oxide layer is the ferroelectric functional layer, the graphene layer is the insertion layer, the alumina layer is the first dielectric layer, and the titanium layer is the second electrode layer.

[0064] Example 5 This embodiment 5 provides a ferroelectric tunnel junction. The ferroelectric tunnel junction includes a titanium layer, a silicon oxide layer, a hafnium zirconium oxide layer, a graphene layer, and a titanium layer. The titanium layer is the first electrode layer, the silicon oxide layer is the first dielectric layer, the hafnium zirconium oxide layer is the ferroelectric functional layer, the graphene layer is the insertion layer, and the titanium layer is the second electrode layer.

[0065] Example 6 This embodiment 6 provides a ferroelectric tunnel junction. The ferroelectric tunnel junction includes a silicon layer, a hafnium zirconium oxide layer, a graphene layer, and a titanium layer. The silicon layer is a semiconductor layer, the hafnium zirconium oxide layer is a ferroelectric functional layer, the graphene layer is an insertion layer, and the titanium layer is a second electrode layer.

[0066] Example 7 This embodiment 7 provides a ferroelectric tunnel junction. The ferroelectric tunnel junction includes a silicon oxide layer, a hafnium zirconium oxide layer, a graphene layer, and a titanium layer. The silicon oxide layer is a semiconductor layer, the hafnium zirconium oxide layer is a ferroelectric functional layer, the graphene layer is an insertion layer, and the titanium layer is a second electrode layer.

[0067] like Figure 2 As shown, a specific embodiment of the second aspect of the present invention provides a method for preparing a ferroelectric tunnel junction. This method, used to prepare the ferroelectric tunnel junction according to any one of the above claims, includes: S110. Sequentially deposit the first electrode layer, the ferroelectric functional layer, and the top electrode layer on the substrate.

[0068] Specifically, the first electrode layer, the ferroelectric functional layer, and the top electrode layer are sequentially deposited on a silicon substrate using atomic deposition (ALD).

[0069] S120, annealing is performed, and then the top electrode layer is etched away.

[0070] Specifically, the product obtained from S110 is subjected to rapid annealing, followed by wet etching to remove the top electrode layer.

[0071] S130, The insertion layer is moved to the side of the ferroelectric functional layer away from the first electrode layer.

[0072] Specifically, the prepared insertion layer is transferred to the side of the ferroelectric functional layer away from the first electrode layer.

[0073] Optionally, after successfully transferring the insertion layer, a second electrode layer is prepared on the side of the insertion layer away from the ferroelectric functional layer. Finally, the insertion layer not covered by the second electrode layer is etched clean by plasma etching.

[0074] The ferroelectric tunnel junction of Example 1 was prepared by the following method.

[0075] First, a silicon oxide layer is oxidized on a silicon substrate. Then, using atomic deposition (ALD) technology, a 30nm bottom titanium nitride layer (i.e., the first electrode layer), an 8nm hafnium zirconium oxide layer (i.e., the ferroelectric functional layer), and a 60nm top titanium nitride layer are sequentially deposited on the side of the silicon oxide layer away from the silicon. Next, an annealing process is performed using a rapid annealing furnace. The temperature inside the rapid annealing furnace is raised to the target temperature within a first preset time, followed by a second preset time at which the temperature is lowered to room temperature and maintained for a third preset time. Subsequently, the top titanium nitride layer is wet-etched away, transferring the prepared graphene layer to the hafnium zirconium oxide layer. Finally, a titanium layer is prepared on the side of the graphene layer away from the hafnium zirconium oxide layer, and the portion of the graphene layer not covered by the titanium layer is etched away completely.

[0076] Optionally, the first preset time and the second preset time are the same, which can be 25 seconds to 35 seconds. Preferably, the first preset time and the second preset time can both be 25 seconds, both be 30 seconds, or both be 35 seconds.

[0077] Optionally, the third preset time is 50 to 70 seconds. Preferably, the third preset time can be 50 seconds, 60 seconds, or 70 seconds.

[0078] Preferably, the target temperature can be 450℃ or 650℃. More preferably, the target temperature is 550℃. For example, the ferroelectric tunnel junction of Example 1 was prepared by the following method: First, a layer of silicon oxide was oxidized on a silicon substrate. Then, using atomic deposition technology, a 30 nm bottom titanium nitride layer (i.e., the first electrode layer), an 8 nm hafnium zirconium oxide layer (i.e., the ferroelectric functional layer), and a 60 nm top titanium nitride layer were sequentially deposited on the side of the silicon oxide away from silicon. Next, annealing was performed using a rapid annealing furnace. The temperature inside the rapid annealing furnace was raised to 550 °C within 30 seconds, and then lowered to room temperature within 30 seconds, and held for 60 seconds. Subsequently, the top titanium nitride layer was wet-etched away, and the prepared graphene layer was transferred to the hafnium zirconium oxide layer. Finally, a titanium layer was prepared on the side of the graphene layer away from the hafnium zirconium oxide layer, and the portion of the graphene layer not covered by the titanium layer was etched clean.

[0079] Based on first-principles calculations, we constructed the traditional MFM-configured FTJ (i.e., Pd-HfO2-Pd), the Gr-FTJ with graphene (Gr) intercalation layer (i.e., Pd-HfO2-Gr-Pd), and the BN-FTJ with boron nitride (BN) intercalation layer (i.e., Pd-HfO2-BN-Pd). Figure 3 These are structural diagrams of the constructed MFM-configured ferroelectric tunnel junction (FTJ) and the Gr-FTJs proposed in this embodiment. After the structures were constructed, the electrical properties of each FTJ were calculated using the non-equilibrium Green's function (NEGF) method. It was found that when using 2nm thick HfO2, the on / off ratios of Gr-FTJ and BN-FTJ, at a readout voltage of 0.5V, increased from approximately 1 to 62 (Gr-FTJ) and 95 (BN-FTJ), respectively, with on-state currents increasing by 66 and 68 times, respectively. Due to the larger bandgap of BN, its off-state current is relatively lower and it exhibits a higher on / off ratio.

[0080] pass Figure 4 As shown in (b), the on / off ratio can be further improved by adjusting the thickness of HfO2. When the thickness of HfO2 is 3.5 nm, the on / off ratio of Gr-FTJ increases to 1.3 × 10⁻⁶. 4 The MFM-FTJ has an on / off ratio of only 7, but its on-state current is increased by 1.18 × 10⁻⁶ compared to the MFM-FTJ. 4 times.

[0081] As can be seen from the above theoretical calculations, the ferroelectric tunnel junction with an added two-dimensional material layer (i.e., an insertion layer) provided by the embodiments of the present invention has a large on / off ratio and a high on-state current.

[0082] Next, this invention studies the performance of two ferroelectric tunnel junction structures using Example 8 and Comparative Example 1 as examples.

[0083] Example 8 provides a ferroelectric tunnel junction comprising a titanium nitride (TiN) layer, a hafnium zirconium oxide (HZO) layer, a graphene (Gr) layer, and a gold (Au) layer. The ferroelectric tunnel junction of Example 8 is denoted as TiN / HZO / Gr / Au, or simply Gr-FTJ. The titanium nitride (TiN) layer has a thickness of 30 nm, the hafnium zirconium oxide (HZO) layer has a thickness of 8 nm, the graphene (Gr) layer has a thickness of 0.335 nm, and the gold (Au) layer has a thickness of 20 nm.

[0084] Comparative Example 1 provides a conventional ferroelectric tunnel junction, including a titanium nitride (TiN) layer, a hafnium zirconium oxide (HZO) layer, and a gold (Au) layer. The ferroelectric tunnel junction of Comparative Example 1 is denoted as TiN / HZO / Au, or simply MFM-FTJ.

[0085] In other words, the ferroelectric tunnel junction of Example 8 has an additional graphene layer compared to the ferroelectric tunnel junction of Comparative Example 1, and the graphene layer is located between the hafnium zirconium oxide and gold layers.

[0086] It should be noted that the graphene layer in Example 8 can be a multilayer graphene structure or a single-layer graphene structure. When the graphene layer is a multilayer graphene structure, it is preferably a 2- to 3-layer graphene structure. The thickness of the single-layer graphene structure is 0.335 nm.

[0087] Figure 5 This is a current (I)-voltage (V) curve diagram for Comparative Example 1 and Example 8. From... Figure 5 As can be seen, the breakdown voltage of MFM-FTJ is 4.5 V, while that of Gr-FTJ is 5.25 V, indicating an improvement in the breakdown voltage of Gr-FTJ. The maximum switching ratio of Gr-FTJ has increased from 10 times to 10. 4 The overall on-state current was increased by one to two orders of magnitude. Both the on-state current and the switching ratio of the Gr-FTJ were improved, consistent with theoretical conclusions. Furthermore, the Gr-FTJ exhibited a high performance of up to 10 at a read voltage of 1.5 V. 4 The high rectification ratio helps to fabricate selectorless arrays in the integration of FTJs.

[0088] Figure 6 These are the test results for PUND in Examples 1 and 8. From... Figure 6 It can be seen that the 2Pr value of Gr-FTJ increased from 20 to 34 μC / cm. 2 This indicates that the structure can not only improve the performance of FTJ, but also improve the ferroelectricity of ferroelectric capacitors.

[0089] Figure 7 This is the retention curve of Example 8. Figure 8 This is the erase and write resistance curve of Example 8. From... Figure 7 and Figure 8 It can be seen that the switching current of the Gr-FTJ in Example 8 is 10 4 The voltage remains essentially unchanged after 10 seconds, while the device can achieve a switching ratio of more than 10 times under pulses of (+6.5 V / 200 ns, -5 V / 200 ns), achieving a fast response, and the device can withstand 10 seconds of voltage fluctuation. 10 10 cycles 10 After the cycle, there will still be discrete resistive states.

[0090] The ferroelectric tunnel structure provided in this embodiment of the invention has the following advantages: Compared to traditional MFM, the ferroelectric tunnel junction with MFIM structure can achieve a much higher on / off ratio. In a specific embodiment of the invention, a two-dimensional material layer (i.e., an insertion layer) is introduced, increasing the asymmetry of the interface charge before and after polarization reversal. The band structure of the two-dimensional material amplifies the band bending asymmetry caused by different ferroelectric polarization directions. The charge injection during ferroelectric polarization reversal also changes the band position of the two-dimensional material. DFT calculations have demonstrated that band structures such as graphene can suppress off-state current and increase on-state current.

[0091] Compared to traditional MFM, the ferroelectric tunnel junction with MFIM structure achieves a significantly larger on-state current while maintaining the on-state ratio. Both theoretical and experimental results demonstrate that this on-state current is higher than that of MFM, thus solving the miniaturization problem of HZO-FTJ-based devices. Furthermore, the two-dimensional material layer reduces the metal gap states and lowers the contact resistance.

[0092] Compared to the traditional HZO-FTJ structure, the ferroelectric tunnel junction provided in this embodiment of the invention achieves better stability, with a read voltage of 1.5 V and a stability of 10 4 The current remains essentially unchanged after switching, and it can be within 10 10 The discrete resistive state is maintained after cycling. This is mainly because van der Waals contacts reduce defects in metal / semiconductor contacts. Simultaneously, the layer thickness of the two-dimensional material and the lower shielding length result in a smaller depolarization field compared to MFIM configurations of the same thickness, leading to better stability.

[0093] The ferroelectric tunnel junction in this embodiment achieves a high switching ratio and on-state current of up to 10 while maintaining a relatively high switching ratio and on-state current. 4 The high rectification ratio is beneficial for the integration of FTJs and for the fabrication of selectorless arrays.

[0094] Compared to the traditional MFM structure ferroelectric tunnel junction, the ferroelectric tunnel junction provided in this embodiment of the invention improves the ferroelectricity of the FTJ capacitor. This is because the van der Waals contact reduces the dead layer between the top electrode and the FE layer, increases the effective ferroelectric layer thickness, and reduces the impact of defects on ferroelectricity.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A ferroelectric tunnel junction, characterized in that, include: Ferroelectric functional layer; An insertion layer is disposed on one side of the ferroelectric functional layer, wherein the material of the insertion layer is a two-dimensional material; The first electrode layer is disposed on the side of the ferroelectric functional layer away from the insertion layer; The second electrode layer is disposed on the side of the insertion layer away from the ferroelectric functional layer.

2. The ferroelectric tunnel structure according to claim 1, characterized in that, The two-dimensional material includes at least one of two-dimensional perovskite material, graphene, and boron nitride.

3. The ferroelectric tunnel structure according to claim 1, characterized in that, Also includes: A first dielectric layer is disposed between the ferroelectric functional layer and the insertion layer; or, the first dielectric layer is disposed between the insertion layer and the second electrode layer; or, the first dielectric layer is disposed between the first electrode layer and the ferroelectric functional layer.

4. The ferroelectric tunnel structure according to claim 3, characterized in that, The thickness of the first dielectric layer is less than the thickness of the ferroelectric functional layer.

5. The ferroelectric tunnel structure according to claim 1, characterized in that, The material of the first electrode layer includes a conductive metal or a conductive metal compound, and / or the material of the second electrode layer includes a conductive metal or a conductive metal compound.

6. The ferroelectric tunnel structure according to claim 5, characterized in that, The conductive metal includes at least one of titanium, gold, and platinum; the conductive metal compound includes titanium nitride.

7. The ferroelectric tunnel junction according to any one of claims 1 to 6, characterized in that, The ferroelectric functional layer is prepared from ferroelectric materials.

8. The ferroelectric tunnel structure according to claim 7, characterized in that, The ferroelectric material includes at least one of hafnium zirconium oxide, lead titanate, and two-dimensional ferroelectric materials.

9. A method for preparing a ferroelectric tunnel junction, characterized in that, The method for preparing the ferroelectric tunnel junction according to any one of claims 1 to 8 comprises: A first electrode layer, a ferroelectric functional layer, and a top electrode layer are sequentially deposited on a substrate; The top electrode layer is then etched away after annealing. The insertion layer is moved to the side of the ferroelectric functional layer away from the first electrode layer.

10. The method for preparing a ferroelectric tunnel junction according to claim 9, characterized in that, When the ferroelectric functional layer is a ferroelectric hafnium zirconium oxide layer, the annealing process conditions are: annealing temperature 450℃ to 650℃, heating for 25 to 35 seconds, cooling for 25 to 35 seconds, and then holding for 50 to 70 seconds.

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