Image sensor and forming method thereof
By depositing doped polycrystalline silicon in deep trenches and performing nitriding treatment, combined with the application of negative potential, the interface electric field and carrier distribution of small-pixel image sensors were optimized, solving the problems of charge storage capacity and noise suppression in small-pixel structures and improving imaging performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-17
AI Technical Summary
In small pixel structures, existing technologies struggle to optimize isolation trenches, charge storage regions, and interface electric fields in a coordinated manner without significantly increasing process complexity, thereby improving charge storage capacity and suppressing noise caused by interface defects.
By depositing a doped polycrystalline silicon layer inside a deep trench and introducing nitriding treatment into the oxide layer, a stable surface pinning layer is formed. Combined with the application of a negative potential, the interfacial electric field and carrier distribution are optimized, reducing the number of dark currents and white spots.
It significantly improves the charge storage capacity and imaging performance of small-pixel image sensors, reduces dark current and white spot defects, and improves overall image quality.
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Figure CN121888710A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of image sensor technology, and in particular to an image sensor and a method for forming the same. Background Technology
[0002] With the continuous improvement of imaging quality in applications such as mobile terminals, security monitoring, and automotive imaging, the pixel structure of image sensors continues to evolve towards smaller scales. As pixel size continues to shrink, achieving high full-well capacity, low white point count, and low dark current within a limited pixel area has become a core challenge for current technological development. Existing technologies typically employ deep trench isolation structures between pixels, forming reinforced insulating interfaces on the trench sidewalls to suppress optical crosstalk and reduce carrier recombination at the boundaries. However, as the width and depth of the trench isolation structure become further limited with pixel shrinkage, the impact of interface defects on pixel performance significantly increases, especially in high-potential regions where interface pinning is more likely to occur, leading to a decrease in charge storage capacity.
[0003] To improve the photoelectric conversion efficiency of pixels, existing processes often employ methods such as trench bottom extension and sidewall doping adjustment to optimize potential distribution and carrier transport paths. However, these methods often face challenges under small pixel conditions, including narrowing process windows, non-uniform interface electric fields, and difficulty in precisely controlling trench morphology. This makes it difficult to simultaneously achieve optimal pixel full-well capacity, white point suppression, and dark current performance. Furthermore, as trench isolation occupies a larger proportion of pixels, the effective area available for photodiodes and charge storage structures is further reduced, leading to a decrease in the device's dynamic range and limiting overall imaging performance.
[0004] Therefore, how to synergistically optimize the isolation trenches, charge storage regions, and interface electric fields in small pixel structures without significantly increasing process complexity, so as to improve charge storage capacity and suppress noise caused by interface defects, has become an urgent problem to be solved in current image sensor manufacturing technology. Summary of the Invention
[0005] To address the technical problems existing in the prior art, this invention proposes an image sensor and its formation method, which can simultaneously improve low noise and increase reliability while taking into account the high energy storage capacity of small pixels.
[0006] Specifically, the present invention provides a method for forming an image sensor, comprising the following steps: providing a substrate, forming trenches on the substrate; depositing an oxide layer in the trenches; forming an oxide nitride layer on the surface of the oxide layer; and forming a doped polysilicon layer in the trenches to allow doped ions to diffuse to the surface of the trenches, thereby improving the surface pinning effect of the image sensor.
[0007] Furthermore, the method for forming the nitrided oxide layer includes the following steps: performing a nitriding treatment on the oxide layer, wherein the nitriding treatment includes one or more of plasma nitriding, thermal nitriding, and ion implantation nitrogen processes.
[0008] Furthermore, after the nitride oxide layer is formed, the nitride oxide layer is annealed to control the distribution of nitrogen in the oxide layer.
[0009] Furthermore, the doped polycrystalline silicon is boron-doped polycrystalline silicon.
[0010] Furthermore, after forming the nitride oxide layer, an oxide layer is formed on the surface of the nitride oxide layer.
[0011] Furthermore, the doped polysilicon layer is connected to a conductive layer in a subsequent process to apply a negative potential to the doped polysilicon layer.
[0012] Furthermore, the present invention also provides an image sensor prepared by the method described above, comprising: a substrate having a plurality of trench arrays; an oxide nitride layer formed on the bottom and sidewalls of the trenches; a doped polysilicon layer filled in the trenches; and the doped polysilicon layer being connected to a negative potential to improve the surface pinning effect.
[0013] Furthermore, a dielectric layer is formed on the surface of the nitride oxide layer, wherein the dielectric layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride; furthermore, the dielectric layer is a single layer or multiple layers.
[0014] Compared with the prior art, the present invention has the following technical effects: First, this invention deposits doped polycrystalline silicon inside deep trenches, allowing the doped boron to diffuse towards the trench sidewalls during subsequent conventional thermal processing, forming a stable surface pinning layer on the silicon surface. This significantly weakens the impact of deep trench interface defects on carrier recombination, improving the pixel's charge storage capacity. Furthermore, by nitriding the trench oxide layer, the diffusion rate of boron into the silicon body can be effectively reduced, allowing for more precise control of diffusion depth and concentration. This prevents excessive boron intrusion into the shallow regions of the photodiode, avoiding reverse doping and achieving a high full-well capacity without sacrificing isolation performance.
[0015] Secondly, introducing nitrogen into the sidewall oxide layer can increase the dielectric constant of the dielectric, thereby enhancing the sidewall capacitance, further increasing the controlled charge density at the trench interface, improving the local hole concentration, and making the surface pinning effect more complete. Combined with applying a negative potential to the doped polysilicon within the deep trenches, a stronger band bending effect can be formed at the trench interface, making it more difficult for charge carriers to accumulate and recombine near the interface, thus effectively reducing the number of white spots and suppressing dark current.
[0016] Through the synergistic optimization of the above structure and process, this invention achieves comprehensive control of the electric field, carrier distribution and doping diffusion behavior at the deep trench interface without adding complex process steps. It can simultaneously improve the full-well capacity of pixels, white point suppression capability and dark current characteristics, and significantly improve the overall imaging performance of small pixel image sensors. Attached Figure Description
[0017] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.
[0018] Figures 1-4 This is a schematic diagram illustrating the formation process of an image sensor according to an embodiment of the present invention.
[0019] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation
[0020] The present invention will now be described in detail with reference to the accompanying drawings and several embodiments.
[0021] In existing image sensor manufacturing processes, deep trench isolation structures are typically formed between pixels to suppress optical crosstalk and reduce carrier recombination at boundaries. Reinforced insulating interfaces are then constructed on the trench sidewalls to enhance isolation. However, as pixel sizes continue to shrink, the width and depth of these deep trenches are subject to stricter process limitations, and the impact of sidewall interface defects on pixel charge behavior becomes increasingly apparent. For example, in some existing designs, insufficient interface quality on the trench sidewalls leads to significant interface pinning in high-potential regions, causing carriers to remain near the interface. This weakens the effective charge storage capacity in the photodiode region, limiting the overall charge capacity of the pixel. This situation is particularly pronounced in small-pixel devices, becoming one of the key factors limiting further performance improvements.
[0022] Embodiments of the present invention provide a method for forming an image sensor, specifically, as follows: Figures 1-4 As shown, a substrate 100 is provided, and a plurality of deep trench arrays are formed on the substrate 100 by etching. The depth of the deep trenches is typically 1-6 μm. Next, an oxide layer 101 is formed on the surface of the deep trenches 110. The oxide layer 101 is made of silicon oxide and has a thickness of 20-800 Å. The oxide layer 101 is formed using one or more of the following processes: CVD, PVD, MBE, PLD, and ALD.
[0023] In some embodiments, an oxide layer 101 can also be formed directly on the surface of the substrate 100 by in-situ oxidation. Specifically, processes such as thermal oxidation, rapid thermal oxidation, in-situ cavity oxidation, and low-temperature plasma oxidation can be used.
[0024] like Figure 3 As shown, the oxide layer 101 is then subjected to nitriding. Nitriding of the oxide layer 101 can be achieved using various mature processes, including plasma nitriding, thermal nitriding, or nitrogen ion implantation, allowing for flexible selection of the appropriate nitrogen introduction method based on the device structure and thermal budget. Preferably, by controlling the energy, time, and atmosphere of the nitriding process, nitrogen is primarily distributed within the oxide layer rather than diffused into the silicon substrate, thus avoiding the formation of additional defect sites in the silicon bulk and ensuring that the dark current and recombination characteristics of the photodiode or active region are not adversely affected. Optionally, after initial nitriding, a high-temperature annealing process can be performed to further stabilize the nitrided layer structure and adjust the spatial distribution of nitrogen in the oxide layer, thereby reducing the interface state density and improving dielectric reliability.
[0025] Furthermore, after oxide nitriding, a second oxide layer can be grown or other dielectric layers can be deposited, such as silicon nitride, silicon oxynitride, or high-dielectric-constant thin films, to construct a composite dielectric structure and further improve the electrical isolation performance and environmental stability of the device. The above steps can be flexibly combined according to specific application requirements to obtain optimal interface quality and device performance.
[0026] like Figure 4 As shown, after completing the nitriding process of oxide layer 101, this embodiment further fills the deep trench region with polysilicon to construct a stable trench sidewall potential control structure. Specifically, LPCVD or similar methods are preferably used to deposit a polysilicon film in the deep trench, and boron is introduced in situ for doping during the deposition process to give the polysilicon a predetermined P-type conductivity characteristic. The boron doping concentration can be adjusted according to the device's potential control capability requirements, typically ranging from 1×10⁻⁶. 15 cm -3 Up to 1×10 22 cm -3 This allows for effective control of the potential within the trench. Alternatively, polycrystalline silicon can also be obtained by first depositing amorphous silicon and then achieving a crystal transformation during subsequent annealing, thus making it suitable for lower temperature budget processes.
[0027] After the polysilicon deposition, the present invention can proceed with other conventional image sensor process steps, including photodiode structure formation, transmission gate fabrication, metal interconnection, and passivation. Preferably, the deep trench polysilicon electrodes are brought out in the subsequent layout and interconnection design, enabling them to be applied with a set potential during the integration and readout processes of the actual image sensor. By applying a negative potential to the deep trench polysilicon in the operating state, the interface pinning capability at the trench sidewalls and pixel boundaries can be further enhanced, effectively suppressing carrier diffusion and interface recombination in the pixel edge region, thereby significantly reducing dark current and improving pixel charge retention performance and imaging uniformity. The above-described polysilicon deposition and potential utilization scheme can work synergistically with the nitrided interface structure of the present invention, enabling deep trench isolation to maintain excellent isolation effect and image quality even under small pixel conditions.
[0028] In this embodiment, by depositing boron-doped polysilicon inside a deep trench and then using a subsequent conventional heat treatment process to diffuse boron to the trench sidewalls, a stable surface pinning layer can be formed on the silicon surface. This effectively weakens the impact of deep trench interface defects on carrier recombination and improves the pixel's charge storage capacity. Furthermore, nitriding the sidewall oxide layer reduces the diffusion rate of boron into the silicon mass, allowing for precise control of diffusion depth and concentration. This prevents reverse doping in the shallow region of the photodiode, thus achieving a higher full-well capacity while maintaining isolation performance. In addition, nitrogen in the sidewall oxide layer increases the local dielectric constant and enhances the trench interface capacitance, increasing the controlled charge density and making the surface pinning effect more significant. Applying a negative potential to the deep trench polysilicon further strengthens the interface bandgap modulation capability, suppressing carrier accumulation and recombination at the interface, and effectively reducing dark current and white spot defects. Through the above structural and process combination, this embodiment achieves synergistic optimization of the deep trench interface electric field, carrier distribution, and doping diffusion behavior, significantly improving the overall imaging performance of the small-pixel image sensor. While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for determining the travel distance of an image sensor, characterized in that, Includes the following steps: Provide a substrate, on which trenches are formed; An oxide layer is deposited in the trench; A nitride oxide layer is formed on the surface of the oxide layer; A doped polysilicon layer is formed in the trench to allow doped ions to diffuse to the surface of the trench, thereby improving the surface pinning effect of the image sensor.
2. The method as described in claim 1, characterized in that, The method for forming the nitride oxide layer includes the following steps: The oxide layer is subjected to nitriding treatment, which includes one or more of plasma nitriding, thermal nitriding, and ion implantation nitrogen processes.
3. The method as described in claim 1, characterized in that, After the nitride oxide layer is formed, the nitride oxide layer is annealed to control the distribution of nitrogen in the oxide layer.
4. The method as described in claim 1, characterized in that, The doped polycrystalline silicon is boron-doped polycrystalline silicon.
5. The method as described in claim 1, characterized in that, After the nitride oxide layer is formed, an oxide layer is formed on the surface of the nitride oxide layer.
6. The method as described in claim 1, characterized in that, The doped polysilicon layer is connected to a conductive layer in a subsequent process to apply a negative potential to the doped polysilicon layer.
7. An image sensor prepared by the method according to any one of claims 1-6, characterized in that, include: A substrate having a plurality of trench arrays; The bottom and sidewalls of the trench are formed with a nitrided oxide layer; The trench is filled with a doped polycrystalline silicon layer; The doped polycrystalline silicon layer is connected to a negative potential to improve the surface pinning effect.
8. The image sensor as claimed in claim 7, characterized in that, A dielectric layer is also formed on the surface of the nitride oxide layer. The dielectric layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride. The dielectric layer can be a single layer or multiple layers.