A device for controlling the output of a complementary PWM signal.

Abstract

This application discloses a device for controlling the output of a complementary PWM signal. Compared with the prior art, it adds a first processing module, a second processing module, and a calculation module. The triggers in the first processing module, the second processing module, and the calculation module delay the signal by one system clock cycle. The first processing module and the second processing module perform AND operations on the original signal and the delayed signal, respectively, to obtain a third signal and a fourth signal, which can ensure that the third signal and the fourth signal will not be high at the same time. The calculation module performs an OR operation on the original control signal and the delayed third signal, and outputs the AND operation result under the control of the OR operation result, thereby ensuring that the final output signal has a safe timing margin. Even if the application environment is complex and the timing changes, the motor will not short-circuit, ensuring the normal use of the equipment.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a device for controlling the output of a complementary PWM signal. Background Technology

[0002] In industrial control, motor drives typically employ PWM (Pulse Width Modulation) complementary output circuits. These circuits achieve safety control by outputting a set of complementary signals, pwm_out and pwm_n_out. A schematic diagram of a PWM complementary output circuit is shown below. Figure 1 As shown, its working principle is as follows: The PWM generation module outputs an OCREF (Output Compare Reference) signal to the dead-time transmitter. This signal is then processed by a 3-way selector, a NOT gate, and a 2-way selector to output two signals, Pwm_do and Pwm_n_do. Pwm_do and Pwm_n_do are respectively ANDed with the original control signal Pwm_obe generated by the output control module to output complementary signals Pwm_out and Pwm_n_out. Pwm_n_out and Pwm_out form the dead time. The dead time prevents the upper and lower bridge arms in the full-bridge / H-bridge circuit from conducting simultaneously, thereby avoiding the risk of a power supply short circuit and ensuring the safe and stable operation of the circuit.

[0003] Figure 2 The diagram shows the logic timing of a PWM complementary output circuit. When the PWM output circuit is turned on, the dead time has not yet been established. Ideally, Pwm_obe should change synchronously with Pwm_do and Pwm_n_do. However, in actual circuits, due to signal transmission delays (such as gate circuit delays, wiring parasitic parameters, etc.), the timing of Pwm_obe and Pwm_do and / or Pwm_n_do may be misaligned. For example, when the PWM output circuit is turned on, Pwm_do may change from high to low after a delay. This timing deviation may cause Pwm_out and Pwm_n_out to briefly be high simultaneously. Similarly, when the PWM output circuit is turned off, the dead time circuit stops working. If Pwm_n_do changes from low to high prematurely, the simultaneously changing Pwm_out and Pwm_n_out will also briefly be high simultaneously. Figure 2 As shown, if both Pwm_out and Pwm_n_out are high simultaneously, it will cause a short circuit in the motor. The instantaneous short-circuit current will impact the motor and drive circuit, causing the motor to burn out.

[0004] To address this issue, existing technologies typically employ external protection circuitry (such as hardware interlock logic, RC delay networks, or dedicated driver chips) placed between the control chip and the motor to forcibly isolate complementary signals. However, this approach has the following drawbacks:

[0005] Increased costs: External protection circuits require additional components (such as comparators, diodes, capacitors, etc.), leading to increased system costs;

[0006] Response delay: The intervention of the protection circuit introduces additional signal processing time, which may cause control delay, especially during the motor start-up and shutdown phase, affecting dynamic response performance.

[0007] Therefore, there is an urgent need to propose a PWM output control scheme based on hardware logic optimization, which can ensure that Pwm_out and Pwm_n_out are strictly complementary through internal timing optimization without relying on external protection circuits, thereby ensuring the safe operation of the motor and maintaining the high efficiency of the system. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a device for controlling the output of complementary PWM signals.

[0009] In a first aspect, an embodiment of the present invention provides an apparatus for controlling the output of a complementary PWM signal, comprising: a PWM generation module, a dead-time transmitter, a first selection module, a second selection module, an output control module, an enable control output module, a first processing module, a second processing module, and a calculation module;

[0010] The first selection module is connected to the enable control output module through the first processing module;

[0011] The second selection module is connected to the enable control output module through the second processing module;

[0012] The output control module is connected to the enable control output module through the calculation module;

[0013] The PWM generation module is used to generate an output comparison reference signal and output it to the dead-time transmitter, the first selection module and the second selection module;

[0014] The dead-time transmitter is used to insert a dead time into the output comparison reference signal output by the PWM generation module, generate a positive signal and a negative signal, and output them to the first selection module and the second selection module respectively, wherein the edges of the positive signal and the negative signal are staggered.

[0015] The first selection module is used to take the output comparison reference signal output by the PWM generation module, the positive signal output by the dead-time transmitter, and the low-level signal as input signals, and output a first signal to the first processing module under the control of the selection control signal.

[0016] The second selection module is used to take the output comparison reference signal output by the PWM generation module, the inverted signal output by the dead-time transmitter, and the low-level signal as input signals, and output a second signal to the second processing module under the control of the selection control signal.

[0017] The first processing module is used to delay the first signal output by the first selection module and then perform a bitwise AND operation with the signal output by the first selection module, and output the result to the enable control output module.

[0018] The second processing module is used to delay the second signal output by the second selection module and then perform a bitwise AND operation with the signal output by the second selection module, and output the result to the enable control output module.

[0019] The output control module is used to generate raw control signals and output them to the calculation module;

[0020] The calculation module is used to perform delay processing on the original control signal output by the output control module, and to perform an OR operation on the delay processing result and the original control signal to obtain an enable control signal and output it to the enable control output module.

[0021] The enable control output module is used to output the signals output by the first processing module and the second processing module under the control of the enable control signal output by the calculation module.

[0022] Compared with the prior art, the present invention has the following advantages: This application provides a device for controlling the output of complementary PWM signals, which is arranged inside the control chip. It not only effectively solves the unsafe state that occurs instantaneously when the motor is turned on and off, but also reduces the equipment cost compared with the external protection circuit scheme, and is safe and convenient to use. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a PWM complementary output circuit in the prior art;

[0024] Figure 2 This is a logic timing diagram of a PWM complementary output circuit in the prior art;

[0025] Figure 3 This is a schematic diagram of an implementation device for controlling the output of a complementary PWM signal according to Embodiment 1 of the present invention;

[0026] Figure 4 This is a logic timing diagram of an implementation device for controlling the output of a complementary PWM signal, provided in Embodiment 1 of the present invention. Detailed Implementation

[0027] This application proposes an apparatus for controlling the output of a complementary PWM signal. The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. Examples of the embodiments are shown in the drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0028] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Example 1

[0030] Embodiment 1 of the present invention provides a device for controlling the output of a complementary PWM signal. This device is installed in a chip on the motor and is suitable for scenarios where the dead time has not been established when the motor is powered on, at which time the dead time function of the dead time transmitter is not enabled. The device is as follows: Figure 3 As shown, it includes a PWM generation module, a dead-time transmitter, a first selection module, a second selection module, a first processing module, a second processing module, an output control module, a calculation module, and an enable control output module. The first selection module is connected to the enable control output module through the first processing module, the second selection module is connected to the enable control output module through the second processing module, and the output control module is connected to the enable control output module through the calculation module.

[0031] The PWM generation module is connected to the dead-time transmitter, the first selection module and the second selection module, and is used to generate an OCREF signal and output it to the dead-time transmitter, the first selection module and the second selection module.

[0032] The dead-time transmitter is connected to the PWM generation module, the first selection module, and the second selection module. It is used to insert dead time into the OCREF signal, generate a positive signal OC_DT and a negative signal OCN_DT, and output them to the first selection module and the second selection module respectively. The edges of the positive signal OC_DT and the negative signal OCN_DT are staggered.

[0033] Optionally, in this embodiment, the dead-time transmitter inserts a dead time when the OCREF signal changes from high to low and inverts it to generate an inverted signal OCN_DT. When the OCREF signal changes from low to high, it inserts a dead time to generate a positive signal OC_DT. The positive signal OC_DT and the inverted signal OCN_DT are output to the first selection module and the second selection module, respectively. The timing diagrams of the positive signal OC_DT and the inverted signal OCN_DT are shown below. Figure 4 As shown;

[0034] The first selection module is connected to the PWM generation module, the dead-time transmitter, and the first processing module. It takes the OCREF signal output by the PWM generation module, the positive signal OC_DT output by the dead-time transmitter, and the low-level signal as input signals, and outputs the first signal Pwm_do to the first processing module under the control of the selection signal.

[0035] Specifically, in this embodiment, the first selection module includes: a 3-way selector, a NOT gate, and a 2-way selector. The 3-way selector is used to select and output the OCREF signal, the positive signal OC_DT, and the low-level signal under the control of selection control signals S2 and S1. The NOT gate is used to invert the signal output by the 3-way selector and output it to the 2-way selector. The 2-way selector is used to select the signal output by the 3-way selector and the signal output by the NOT gate under the control of the phase enable signal and output the first signal Pwm_do to the first processing module.

[0036] The 3-channel selector input source includes 3 signals X0 (X means that the high-order value is not important), 01, and 11. The 2-bit selection control signals S2 and S1 select which signal to output. Specifically: if the selection control signals S2 and S1 are 00 or 10, input source 0 (long low level) is selected as the selector output; if the selection control signals S2 and S1 are 01, input source OCREF is selected as the selector output; if the selection control signals S2 and S1 are 11, input source OC_DT is selected as the selector output.

[0037] The output signal of the 2-way selector is controlled by a 1-bit phase enable signal. Specifically, if the phase enable signal is 0, the selection signal is not changed and is output directly, which is the signal output by the 3-way selector. If the phase enable signal is 1, the selection signal is inverted and output, which is the signal output by the NOT gate.

[0038] Specifically, in this embodiment, the selection control signals S2 and S1 of the 3-way selector in the first selection module are 11, and the phase enable signal of the 2-way selector is 1. That is, the first signal Pwm_do output by the first selection module is the inverted output of OC_DT. The timing diagram of the first signal Pwm_do is as follows. Figure 4 As shown;

[0039] The second selection module is connected to the PWM generation module, the dead-time transmitter, and the second processing module. It takes the OCREF signal output by the PWM generation module, the inverted signal OCN_DT output by the dead-time transmitter, and the low-level signal as input signals, and outputs the second signal Pwm_n_do to the second processing module under the control of the selection signal.

[0040] Specifically, in this embodiment, the second selection module includes: a 3-way selector, a NOT gate, and a 2-way selector. The 3-way selector is used to select and output the OCREF signal, the inverted signal OCN_DT, and the low-level signal under the control of selection control signals S2 and S1. The NOT gate is used to invert the signal output by the 3-way selector and output it to the 2-way selector. The 2-way selector is used to select the signal output by the 3-way selector and the signal output by the NOT gate under the control of the phase enable signal and output the second signal Pwm_n_do to the second processing module.

[0041] The 3-channel selector input source includes 3 signals X0 (X means that the high-order bit value is not important), 01, and 11. The output signal is selected by the values ​​of the 2-bit selection control signals S2 and S1. Specifically: if the selection control signals S2 and S1 are 00 or 10, input source 0 (long low level) is selected as the selector output; if the selection control signals S2 and S1 are 01, input source OCREF is selected as the selector output; if the selection control signals S2 and S1 are 11, input source OCN_DT is selected as the selector output.

[0042] The output signal of the 2-way selector is controlled by a 1-bit phase enable signal. Specifically, if the phase enable signal is 0, the selection signal is not changed and is output directly, which is the signal output by the 3-way selector. If the phase enable signal is 1, the selection signal is inverted and output, which is the signal output by the NOT gate.

[0043] Specifically, in this embodiment, the selection control signals S2 and S1 of the 3-way selector in the second selection module are 11, and the phase enable signal of the 2-way selector is 0. That is, the second signal Pwm_n_do output by the second selection module is OCN_DT, and the timing diagram of the second signal Pwm_n_do is as follows. Figure 4 As shown;

[0044] The first processing module is connected to the first selection module and the enable control output module. It is used to delay the first signal output by the first selection module and then perform a bitwise AND operation with the first signal output by the first selection module, and output the operation result to the enable control output module.

[0045] Specifically, in this embodiment, the first processing module includes a flip-flop and an AND gate. The flip-flop is used to delay the first signal Pwm_do output by the first selection module and output a first delayed signal Pwm_do_dl to the AND gate. The AND gate is used to perform an AND operation on the first signal Pwm_do output by the first selection module and the first delayed signal Pwm_do_dl output by the flip-flop, and output the result (i.e., the third signal Pwm_do_mux) to the enable control output module. The timing diagrams of the first delayed signal Pwm_do_dl and the third signal Pwm_do_mux are as follows: Figure 4 As shown;

[0046] The second processing module is connected to the second selection module and the enable control output module. It is used to delay the second signal output by the second selection module and then perform a bitwise AND operation with the second signal output by the second selection module, and output the operation result to the enable control output module.

[0047] Specifically, in this embodiment, the second processing module includes a flip-flop and an AND gate. The flip-flop is used to delay the second signal Pwm_n_do output by the second selection module and output a second delayed signal Pwm_n_do_dl to the AND gate. The AND gate is used to perform an AND operation on the second signal Pwm_n_do output by the second selection module and the second delayed signal Pwm_n_do_dl output by the flip-flop, and output the result (i.e., the fourth signal Pwm_n_do_mux) to the enable control output module. The timing diagram of the second delayed signal Pwm_n_do_dl and the fourth signal Pwm_n_do_mux is shown below. Figure 4 As shown;

[0048] The output control module is connected to the calculation module and is used to generate raw control signals and output them to the calculation module.

[0049] In this embodiment, the timing diagram of the original control signal Pwm_obe is as follows: Figure 4 As shown;

[0050] The calculation module is connected to the output control module and the enable control output module. It is used to perform delay processing on the original control signal output by the output control module, and to perform an OR operation on the delay processing result and the original control signal to obtain the enable control signal and output it to the enable control output module.

[0051] Specifically, in this embodiment, the calculation module includes a flip-flop and an OR gate. The flip-flop is used to delay the original control signal Pwm_obe output by the output control module and output a third delayed signal Pwm_obe_dl to the OR gate. The OR gate is used to perform an OR operation on the original control signal Pwm_obe output by the output control module and the third delayed signal Pwm_obe_dl output by the flip-flop to obtain an enable control signal Pwm_obe_mux and output it to the enable control output module. The timing diagram of the enable control signal Pwm_obe_mux is shown below. Figure 4 As shown;

[0052] The enable control output module is connected to the first processing module, the second processing module, and the calculation module, and is used to output the signals output by the first processing module and the second processing module under the control of the enable control signal output by the calculation module.

[0053] Specifically, in this embodiment, the enable control output module includes two AND gates. One AND gate performs calculations on the signal output by the first processing module and the enable control signal output by the calculation module, and then outputs the result. The other AND gate performs calculations on the signal output by the second processing module and the enable control signal output by the calculation module, and then outputs the result. The timing diagrams of the signals Pwm_out and Pwm_n_out output by the enable control output module are shown below. Figure 4 As shown.

[0054] Compared to existing technologies, this embodiment adds a first processing module, a second processing module, and a calculation module. The triggers in these modules delay the signal by one system clock cycle. The first and second processing modules perform AND operations on the original signal and the delayed signal, respectively, to obtain a third signal Pwm_do_mux and a fourth signal Pwm_n_do_mux. This ensures that the third signal Pwm_do_mux and the fourth signal Pwm_n_do_mux will not be simultaneously high. The calculation module performs an OR operation on the original control signal and the delayed enable control signal, and outputs the AND operation result under the control of the OR operation result. This ensures that the final output signals Pwm_out and Pwm_n_out have a safe timing margin, preventing short circuits in the motor even in complex application environments with timing variations, thus ensuring normal equipment operation.

[0055] The control PWM complementary signal output implementation device provided in this embodiment is arranged on the control chip. It is implemented by adding flip-flops, AND gates and NOT gates to the existing control chip. The delay is achieved by using flip-flops. This not only effectively solves the unsafe state that occurs instantaneously when the PWM is turned on and off, but also has extremely low cost of the added components. Compared with the external protection circuit solution, it greatly reduces the equipment cost and is safe and convenient to use.

[0056] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0057] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A device for controlling the output of a complementary PWM signal, comprising a PWM generation module, a dead-time transmitter, a first selection module, a second selection module, an output control module, and an enable control output module, characterized in that, Also includes: The system comprises a first processing module, a second processing module, and a calculation module. The first selection module is connected to the enable control output module through the first processing module; The second selection module is connected to the enable control output module through the second processing module; The output control module is connected to the enable control output module through the calculation module; The PWM generation module is used to generate an output comparison reference signal and output it to the dead-time transmitter, the first selection module and the second selection module; The dead-time transmitter is used to insert a dead time into the output comparison reference signal output by the PWM generation module, generate a positive signal and a negative signal, and output them to the first selection module and the second selection module respectively, wherein the edges of the positive signal and the negative signal are staggered. The first selection module is used to take the output comparison reference signal output by the PWM generation module, the positive signal output by the dead-time transmitter, and the low-level signal as input signals, and output a first signal to the first processing module under the control of the selection signal; The second selection module is used to take the output comparison reference signal output by the PWM generation module, the inverted signal output by the dead-time transmitter, and the low-level signal as input signals, and output a second signal to the second processing module under the control of the selection signal; The first processing module is used to delay the first signal output by the first selection module and then perform a bitwise AND operation with the signal output by the first selection module, and output the result to the enable control output module. The second processing module is used to delay the second signal output by the second selection module and then perform a bitwise AND operation with the signal output by the second selection module, and output the result to the enable control output module. The output control module is used to generate the original control signal and output it to the calculation module; The calculation module is used to perform delay processing on the original control signal output by the output control module, and to perform an OR operation on the delay processing result and the original control signal to obtain an enable control signal and output it to the enable control output module. The enable control output module is used to output the signals output by the first processing module and the second processing module under the control of the enable control signal output by the calculation module.

2. The apparatus as claimed in claim 1, characterized in that, The first processing module includes a flip-flop and an AND gate. The flip-flop is used to delay the first signal output by the first selection module and output a first delayed signal to the AND gate. The AND gate is used to perform an AND operation on the first signal output by the first selection module and the first delayed signal output by the flip-flop, and output the operation result to the enable control output module.

3. The apparatus as described in claim 1, characterized in that, The second processing module includes a flip-flop and an AND gate. The flip-flop is used to delay the second signal output by the second selection module and output a second delayed signal to the AND gate. The AND gate is used to perform an AND operation on the second signal output by the second selection module and the second delayed signal output by the flip-flop, and output the operation result to the enable control output module.

4. The apparatus as claimed in claim 1, characterized in that, The calculation module includes a flip-flop and an OR gate. The flip-flop is used to delay the original control signal output by the output control module and output a third delayed signal to the OR gate. The OR gate is used to perform an OR operation on the original control signal output by the output control module and the third delayed signal output by the flip-flop to obtain an enable control signal and output it to the enable control output module.

5. The apparatus as claimed in claim 1, characterized in that, The first selection module includes a 3-way selector, a NOT gate, and a 2-way selector. The 3-way selector is used to select and output a comparison reference signal, a positive signal, and a low-level signal under the control of a selection control signal. The NOT gate is used to invert the signal output by the 3-way selector and output it to the 2-way selector. The 2-way selector is used to select the signal output by the 3-way selector and the signal output by the NOT gate under the control of a phase enable signal and output a first signal to the first processing module.

6. The apparatus as claimed in claim 1, characterized in that, The second selection module includes a 3-way selector, a NOT gate, and a 2-way selector. The 3-way selector is used to select and output a comparison reference signal, an inverted signal, and a low-level signal under the control of a selection control signal. The NOT gate is used to invert the signal output by the 3-way selector and output it to the 2-way selector. The 2-way selector is used to select the signal output by the 3-way selector and the signal output by the NOT gate under the control of a phase enable signal and output a second signal to the second processing module.

7. The apparatus as claimed in claim 1, characterized in that, The enable control output module includes two AND gates. One AND gate performs calculations on the signal output by the first processing module and the enable control signal output by the calculation module, and outputs the result. The other AND gate performs calculations on the signal output by the second processing module and the enable control signal output by the calculation module, and outputs the result.

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