Nonvolatile memory based on ferroelectric thin film transistor and method of manufacturing the same

Abstract

Embodiments of the present application relate to a ferroelectric thin film transistor based nonvolatile memory and a preparation method thereof. A hetero-multilayer thin film (including a ferroelectric layer) is grown by using a plasma enhanced atomic layer deposition (PE-ALD) process. The ferroelectric thin film transistor grown by using the PE-ALD process has a polarization state of the ferroelectric layer directly changing a threshold voltage of the transistor, and a residual polarization of the ferroelectric layer maintaining an electrical state of the transistor after a gate voltage programming and erasing operation, so as to realize nonvolatile storage. The PE-ALD process has a relatively low heat budget, a high thin film crystallization quality, and can realize 3D device integration.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a non-volatile memory based on ferroelectric thin-film transistors and its fabrication method. Background Technology

[0002] Ferroelectric materials are a class of materials exhibiting spontaneous polarization, the direction of which can be reoriented by changing the direction of an applied electric field. Spontaneous polarization refers to the non-coincidence of positive and negative charge centers within the inherent cellular structure of the material, resulting in an electric dipole moment. By changing the direction of the applied electric field, the orientation of the ferroelectric domains within the crystal can be affected, thereby reversing the spontaneous polarization direction. Therefore, the ferroelectricity of ferroelectric materials is closely related to their intrinsic crystal structure.

[0003] To obtain ferroelectric materials with good ferroelectric properties, ensuring a high-quality and complete specific crystal structure is the primary prerequisite. Currently, the mainstream technologies for preparing ferroelectric materials in this field include molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), pulsed laser deposition (PLD), and physical vapor deposition (PVD) (e.g., magnetron sputtering). Among these, ferroelectric materials prepared by MBE have high crystal quality, but MBE usually requires a high substrate temperature, which can easily affect the formed device structure. It also has high precision requirements, high cost, and low efficiency. Furthermore, the beam directionality of MBE is good, making it difficult to maintain the shape of three-dimensional structures. Summary of the Invention

[0004] In view of this, the present application provides a non-volatile memory based on ferroelectric thin-film transistors and a method for fabricating the same, in order to solve at least one problem existing in the background art.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a non-volatile memory based on a ferroelectric thin-film transistor, the method comprising:

[0006] A substrate is provided, the substrate comprising a base, a nucleation layer and an active layer stacked sequentially;

[0007] A first atomic layer deposition process is performed to form a seed layer on the active layer, wherein the material of the seed layer is a binary nitride.

[0008] A second atomic layer deposition process is performed to form a ferroelectric layer on the seed layer, wherein the material of the ferroelectric layer is a ternary nitride; wherein the binary nitride is composed of elements from the ternary nitride;

[0009] A third atomic layer deposition process is performed to form a capping layer on the ferroelectric layer;

[0010] A source and a drain are formed that penetrate at least through the capping layer and the ferroelectric layer;

[0011] An isolated active region is formed within the active layer;

[0012] A gate is formed on the cap layer;

[0013] Lead electrodes are formed on the source, the drain, and the gate.

[0014] The substrate is thinned and a dicing process is performed.

[0015] In conjunction with the first aspect of this application, in an optional embodiment, the step of performing a second atomic layer deposition process to form a ferroelectric layer on the seed layer includes: performing multiple supercycles until the thickness of the formed ferroelectric layer reaches a desired thickness; wherein each supercycle includes: sequentially performing m first sub-cycles and n second sub-cycles to form m first sub-layers and n second sub-layers respectively, where m≥1 and n≥1; the materials of the first sub-layers and the second sub-layers are binary nitrides, the materials of the first sub-layers and the second sub-layers are different, and the materials of the first sub-layers and the seed layer are the same.

[0016] In conjunction with the first aspect of this application, in an optional embodiment, the ferroelectric layer is made of AlScN, where 1:2 ≤ m:n ≤ 1:5.

[0017] In conjunction with the first aspect of this application, in an optional embodiment, the first atomic layer deposition process, the second atomic layer deposition process, and the third atomic layer deposition process are performed in the same growth chamber.

[0018] In conjunction with the first aspect of this application, in an optional embodiment, the first atomic layer deposition process, the second atomic layer deposition process, and the third atomic layer deposition process include a plasma-enhanced atomic layer deposition process, wherein the plasma source in the plasma-enhanced atomic layer deposition process includes a hollow cathode plasma source.

[0019] In conjunction with the first aspect of this application, in an optional embodiment, the material of the ferroelectric layer includes Sc; the Sc precursor in the second atomic layer deposition process includes diisopropylamine scandium and / or trimethylcyclopentadienyl scandium.

[0020] In conjunction with the first aspect of this application, in an optional embodiment, forming a source and drain that at least penetrate the capping layer and the ferroelectric layer includes: etching the capping layer, the ferroelectric layer, and the seed layer to form an opening extending into the interior of the seed layer; and forming a source and drain within the opening.

[0021] In conjunction with the first aspect of this application, in an optional embodiment, the etching of the capping layer, the ferroelectric layer, and the seed layer includes:

[0022] An inductively coupled plasma etching process is performed to etch through the capping layer and the ferroelectric layer;

[0023] Perform atomic layer etching to etch part of the seed layer.

[0024] Secondly, embodiments of this application provide a non-volatile memory based on a ferroelectric thin-film transistor, which is fabricated using the fabrication method of a non-volatile memory based on a ferroelectric thin-film transistor as described in the first aspect; wherein, the gate is used to apply a voltage to the ferroelectric layer, at least controlling the ferroelectric layer to switch between two polarization states, so as to realize data programming and erasure.

[0025] In conjunction with a second aspect of this application, in an optional embodiment, the gate is further configured to regulate the polarization of the ferroelectric layer, introducing an intermediate state between the two polarization states to achieve multi-bit data storage.

[0026] The non-volatile memory based on ferroelectric thin-film transistors and its fabrication method provided in this application form a ferroelectric layer through atomic layer deposition (ALD). Compared with molecular beam epitaxy (MBE), ALD is performed at a relatively low temperature, effectively reducing the adverse effects of high-temperature processes. It has high process compatibility, can control the thickness of the ferroelectric layer with atomic precision, and has high conformability in the three-dimensional device structure, making it more suitable for large-scale applications. Furthermore, a seed layer sharing metal elements with the ferroelectric layer is set, providing high-density, low-boundary-energy nucleation sites for the deposition of the ferroelectric layer, which is more conducive to the growth of the ferroelectric layer and improves the crystal quality.

[0027] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0029] Figure 1A schematic flowchart illustrating the fabrication method of a non-volatile memory based on a ferroelectric thin-film transistor provided in this application embodiment;

[0030] Figures 2 to 4 A cross-sectional structural diagram of a non-volatile memory based on a ferroelectric thin-film transistor provided in an embodiment of this application during its fabrication process;

[0031] Figure 5 Figure 1 shows the polarization state of the ferroelectric layer in the non-volatile memory programming state, where (a) is a cross-sectional structural diagram and (b) is a band structure diagram.

[0032] Figure 6 The diagram shows the polarization state of the ferroelectric layer in the erase state of a non-volatile memory, where (a) is a cross-sectional view and (b) is a band structure diagram.

[0033] Figure 7 This is a graph showing the transfer characteristics of a non-volatile memory based on a ferroelectric thin-film transistor.

[0034] Explanation of reference numerals in the attached figures:

[0035] 10. Substrate; 100. Base; 200. Nucleation layer; 300. Active layer; 400. Seed layer; 500. Ferroelectric layer; 600. Capping layer; 710. Source; 720. Drain; 730. Gate. Detailed Implementation

[0036] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0043] This application provides a method for fabricating a non-volatile memory based on a ferroelectric thin-film transistor. Please refer to [link / reference]. Figure 1 The preparation methods include:

[0044] Step S1: Provide a substrate, the substrate comprising a base, a nucleation layer and an active layer stacked sequentially;

[0045] Step S2: Perform the first atomic layer deposition process to form a seed layer on the active layer. The material of the seed layer is a binary nitride.

[0046] Step S3: Perform the second atomic layer deposition process to form a ferroelectric layer on the seed layer. The material of the ferroelectric layer is a ternary nitride; wherein, the binary nitride is composed of the elements in the ternary nitride.

[0047] Step S4: Perform the third atomic layer deposition process to form a capping layer on the ferroelectric layer;

[0048] Step S5: Form source and drain electrodes that penetrate at least through the capping layer and the ferroelectric layer;

[0049] Step S6: Form an isolated active region within the active layer;

[0050] Step S7: Form the gate on the capping layer;

[0051] Step S8: Form lead electrodes on the source, drain, and gate;

[0052] Step S9: Thin the substrate and perform a dicing process.

[0053] This application embodiment forms a ferroelectric layer using atomic layer deposition (ALD). Compared to molecular beam epitaxy (MBE), ALD is performed on a relatively low-temperature growth surface, effectively reducing the adverse effects of high-temperature processes. It offers high process compatibility, allowing for atomic-level precision control of the ferroelectric layer thickness and high conformability in three-dimensional device structures, making it more suitable for large-scale applications. Furthermore, a seed layer sharing metal elements with the ferroelectric layer provides high-density, low-boundary-energy nucleation sites for ferroelectric layer deposition, further promoting ferroelectric layer growth and improving crystal quality.

[0054] First, please refer to Figure 2 Step S1 is performed, providing a substrate 10, which includes a substrate 100, a nucleation layer 200, and an active layer 300 stacked sequentially. In one example, providing the substrate 10 may include: providing the substrate 100; and sequentially growing the nucleation layer 200 and the active layer 300 on the substrate 100.

[0055] The material of the substrate 100 may include Si, GaN, SiC, and sapphire, and this application does not limit it. The thickness of the substrate 100 ranges from 400 μm to 500 μm.

[0056] After providing the substrate 100, the preparation method may further include: performing a surface pretreatment on the substrate 100. This can remove impurities from the substrate 100. The surface pretreatment may include cleaning and degassing by heating.

[0057] The nucleation layer 200 helps improve the crystal quality of the active layer 300 and reduce the leakage current of the ferroelectric thin-film transistor (FeTFT). The thickness of the nucleation layer 200 ranges from 5 nm to 50 nm.

[0058] The active layer 300 is a material layer used to form the channel in a ferroelectric thin-film transistor. In this embodiment, the active layer 300 is specifically an undoped active layer, and the material of the active layer 300 is, for example, GaN, with a thickness ranging from 1 μm to 2 μm.

[0059] The process for growing the nucleation layer 200 and the active layer 300 may include metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0060] Before transferring the substrate 10 to the growth chamber, the preparation method may further include: surface pretreatment of the substrate 10. Surface pretreatment may include wet cleaning and heating / baking. Wet cleaning includes inorganic cleaning, organic cleaning, and immersion; the cleaning agents in inorganic cleaning include SC-1 inorganic solution and SC-2 inorganic solution; the cleaning agents in organic cleaning include acetone, isopropanol, and deionized water; the immersion solution in immersion is ammonia water, the temperature is 50℃, and the duration is 5min. Wet cleaning can remove surface contaminants such as particles, metal ions, and organic matter. Heating / baking can remove surface-adsorbed water vapor, organic matter, and other impurities, specifically by baking at 500℃~600℃ for 0.5h~1h. After surface pretreatment, a cooling treatment is performed, and the substrate 10 is transferred to the growth chamber under conditions that do not disrupt the vacuum (low vacuum).

[0061] Next, step S2 is executed to perform the first atomic layer deposition process to form a seed layer 400 on the active layer 300. The material of the seed layer 400 is a binary nitride. Step S3 is executed to perform the second atomic layer deposition process to form a ferroelectric layer 500 on the seed layer 400. The material of the ferroelectric layer 500 is a ternary nitride. The binary nitride is composed of elements from the ternary nitride.

[0062] Compared to molecular beam epitaxy (MBE), atomic layer deposition (ALD) offers advantages such as high conformability, precise thickness control, high thickness uniformity, high compositional uniformity, and relatively low substrate temperature. It also meets the requirements of deep-hole filling processes for complex structures, playing a crucial role in advanced integrated circuit manufacturing. However, the low surface temperature means that precursor molecules, after deposition, do not receive sufficient thermal energy, limiting their migration and diffusion on the growth surface. They cannot effectively move to the lowest energy lattice sites but instead randomly "freeze" near their initial landing points. This growth mode readily forms amorphous or polycrystalline films containing only fine grains, with numerous grain boundaries and defects. Therefore, ALD sacrifices the crystal quality of the ferroelectric layer 500, but the ferroelectricity of the ferroelectric layer 500 depends on its specific internal crystal structure. Based on this, this application further sets up a seed layer 400, the material of the seed layer 400 is a binary nitride, and the material of the ferroelectric layer 500 is a ternary nitride. The binary nitride is composed of elements in the ternary nitride, so that the crystal structures of the seed layer 400 and the ferroelectric layer 500 are similar, which is more conducive to the nucleation of the ferroelectric layer 500, reduces the defect density of the ferroelectric layer 500, and ensures the crystal quality.

[0063] In some embodiments, performing a second atomic layer deposition process to form a ferroelectric layer 500 on a seed layer 400 may include: performing multiple supercycles until the thickness of the formed ferroelectric layer 500 reaches a desired thickness; wherein each supercycle includes: sequentially performing m first sub-cycles and n second sub-cycles to form m first sub-layers and n second sub-layers respectively, where m≥1 and n≥1; the materials of the first sub-layers and the second sub-layers are binary nitrides, the materials of the first sub-layers and the second sub-layers are different, and the materials of the first sub-layers and the seed layer are the same.

[0064] Therefore, the first sublayer and the seed layer 400 are made of the same material, which means that the growth of the ferroelectric layer 500 begins with the deposition of the same material on the same material surface. This eliminates the unavoidable initial interface lattice mismatch and chemical abrupt change in traditional heteroepitaxial growth, providing an ideal epitaxial interface with atomically flat and chemically continuous bonding, and significantly reducing the nucleation barrier.

[0065] Understandably, when preparing multi-component compounds using atomic layer deposition (ALD), due to the difficulty in obtaining precursors simultaneously containing multiple components, the art typically employs a supercycle, combining multiple binary compound sub-cycles in a specific order and proportion, to achieve the deposition of multi-component compounds with controllable chemical composition. A sub-cycle specifically refers to the complete ALD process required to deposit one layer of a binary compound, including four steps: precursor pulse exposure, purging, co-reactant precursor pulse exposure, and purging. Specifically, precursors of different elements are selectively and alternately exposed to the growth surface, where they undergo chemisorption and reaction to form a thin film. Between precursor pulses, an inert carrier gas is used to blow away any remaining unreacted precursors (including byproducts), allowing the film to grow layer by layer on the surface with atomic precision.

[0066] In the initial stage of atomic layer deposition, it is difficult to form stable and continuous nucleation centers on the heterogeneous surface, causing growth to be unable to proceed at a stable rate immediately. The growth rate is lower than the steady-state growth rate of the material, and this phenomenon in the initial stage can be called "nucleation delay". Therefore, in order to form effective atomic-level thin film deposition, additional sub-cycles are required in each supercycle.

[0067] In some embodiments, the material of the first sublayer is AlN, where 3 ≤ m ≤ 10. Understandably, in an AlN sub-cycle, at least the first two sub-cycles may be ineffective; therefore, setting the number of the first sub-cycles within this range ensures effective deposition. It should be noted that atomic layer deposition processes include thermal atomic layer deposition (TLD) and plasma-enhanced atomic layer deposition (PEAD). Generally, PAD has higher reactivity due to the free radicals generated by plasma, resulting in fewer nucleation delay cycles compared to TLD. This embodiment specifically uses PAD as an example; those skilled in the art can adaptively adjust the number of cycles according to the process used in actual production.

[0068] In some embodiments, the ferroelectric layer 500 is made of AlScN, with a ratio of 1:2 ≤ m:n ≤ 1:5. When the ferroelectric layer is made of AlScN, the first sublayer and the second sublayer are AlN and ScN, respectively. The nucleation delay of ScN is more severe than that of AlN. Setting the ratio of AlN subcycles to ScN subcycles within this range can ensure effective deposition.

[0069] Based on this, the ratio of the first sub-cycle and the second sub-cycle can be adjusted according to the elemental composition of the ferroelectric layer 500 material, but this application does not limit this.

[0070] In some implementations, the crystal structure of the seed layer 400 is the same as that of the ferroelectric layer 500. This reduces interface defects caused by lattice mismatch, lowers the nucleation barrier, ensures the purity of the crystal phase, avoids the formation of non-ferroelectric impurities from the growth source, and ensures the stability and reliability of ferroelectric properties.

[0071] Optionally, the ferroelectric layer 500 may be made of AlScN, AlBN, AlYN, or GaScN. In a specific example, the ferroelectric layer 500 may be made of AlScN, AlBN, or AlYN, and the seed layer 400 may be made of AlN; or, the ferroelectric layer 500 may be made of GaScN, and the seed layer 400 may be made of GaN. Thus, the ferroelectric layer 500 has a wurtzite structure, and the seed layer 400 also has a wurtzite structure.

[0072] In a specific example where the active layer 300 is made of GaN, the seed layer 400 is made of AlN, and the ferroelectric layer 500 is made of AlScN, the active layer 300 and the seed layer 400 form a heterojunction. A two-dimensional electron gas is formed on the side of the active layer 300 near the seed layer 400. The seed layer 400 not only improves the crystal quality of the ferroelectric layer 500, but also introduces greater band bending and piezoelectric polarization, resulting in a higher concentration of the two-dimensional electron gas. It can also reduce the severe alloy scattering of the ferroelectric layer 500 at the heterojunction, resulting in a higher mobility of the two-dimensional electron gas and thus better performance of the ferroelectric thin-film transistor.

[0073] In some embodiments, the first atomic layer deposition process and the second atomic layer deposition process include a plasma-enhanced atomic layer deposition process, wherein the plasma source in the plasma-enhanced atomic layer deposition process includes a hollow cathode plasma source.

[0074] Understandably, Plasma Enhanced Atomic Layer Deposition (PE-ALD) processes generally employ two different plasma generation methods: Capacitively Coupled Plasma (CCP) sources and Inductively Coupled Plasma (ICP) sources. CCP sources apply radio frequency power through two parallel plate electrodes, utilizing the oscillating electric field formed between them to accelerate electrons, causing them to collide with gas molecules to generate plasma. ICP sources apply radio frequency power through a coil, using a changing current to generate a changing magnetic field, which in turn induces a vortex electric field to excite and maintain the plasma. CCP sources produce high-energy ions but are easily damaged, while ICP sources, although capable of achieving high-density, low-energy plasmas, are complex systems. Hollow Cathode Plasma (HCP) sources can generate extremely high-density, extremely bright plasmas at the cathode, thus enabling lower oxygen impurities, lower plasma damage, better crystallinity, and higher growth rates.

[0075] After the substrate 10 is placed in the growth chamber of the atomic layer deposition apparatus, the fabrication method may further include performing a remote plasma pretreatment. This removes the native oxide layer on the surface with minimal damage. Specifically, NH3, Ar, and N2 can be used sequentially as precursors at a substrate temperature of 300°C.

[0076] In some embodiments, the first atomic layer deposition process and the second atomic layer deposition process are performed in the same growth chamber. Therefore, by continuously performing the first and second atomic layer deposition processes in the same growth chamber, the seed layer 400 and the ferroelectric layer 500 are grown in situ in a single step, resulting in good process continuity and avoiding the risks of interface exposure and contamination during multi-chamber transfer.

[0077] In a specific example where the seed layer 400 is made of AlN, the Al precursor is trimethylaluminum (TMAl), the N precursor is NH3 or a mixture of H2 and N2 gas, the carrier gas is Ar, the substrate temperature range is 300℃~350℃, the RF power range is 200W~300W, the growth chamber pressure range during precursor pulse is 0.3Torr~0.5Torr, the reaction chamber pressure range during purging is 1Torr~1.5Torr, and the plasma frequency is 13.56MHz.

[0078] In some examples, the thickness of the seed layer 400 ranges from 2 nm to 5 nm.

[0079] In some embodiments, the ferroelectric layer material includes Sc; the Sc precursor in the second atomic layer deposition process includes diisopropylamine scandium and / or trimethylcyclopentadienyl scandium. Diisopropylamine scandium (Sc( i PrFMD)3) and / or trimethylcyclopentadienylscandium (Sc(MeCp)3) contain no other metal elements and have fewer impurities, which further improves the crystal quality.

[0080] When the material of the ferroelectric layer 500 is AlScN, and the second atomic layer deposition process is plasma-enhanced atomic layer deposition, the Al precursor is trimethylaluminum (TMAl), the Sc precursor is diisopropylamine scandium or trimethylcyclopentadienyl scandium, the N precursor is NH3 or a mixture of H2 and N2 gas, the carrier gas is Ar, the substrate temperature range is 300℃~350℃, the RF power range is 200W~600W, the Sc precursor is heated to about 150℃, the growth chamber pressure range during precursor pulse is 0.3Torr~0.5Torr, the reaction chamber pressure range during purging is 1Torr~1.5Torr, and the plasma frequency is 13.56MHz.

[0081] In a specific example where the ferroelectric layer 500 is made of AlScN, the Sc composition can range from 10% to 30%. Understandably, the Sc composition has a significant impact on ferroelectricity; within this range, the ferroelectric layer 500 exhibits good ferroelectricity. Further, a Sc composition ranging from 15% to 25% provides good lattice matching with the GaN active layer 300, resulting in fewer crystal defects and relatively low leakage current at the gate 730. Even further, a Sc composition of 18% is used. 0.82 Sc 0.18 N and GaN are lattice matched, resulting in the fewest defects.

[0082] In some embodiments, the thickness of the ferroelectric layer 500 ranges from 10 nm to 20 nm.

[0083] In some embodiments, before forming the seed layer, the fabrication method may further include forming a channel layer (not shown) on the active layer 300, the thickness of which is less than the thickness of the active layer 300. Specifically, the thickness of the channel layer is 10 nm. This optimizes defects on the growth surface, and the seed layer 400 and the channel layer constitute a heterojunction, forming a two-dimensional electron gas within the channel layer. The material of the channel layer is the same as that of the active layer 300. In a specific example where the active layer 300 is made of GaN, the channel layer is also made of GaN.

[0084] In one example, the process for forming the channel layer includes a fourth atomic layer deposition process, which is performed in the same growth chamber as the first atomic layer deposition process. This results in better process compatibility.

[0085] Optionally, the fourth atomic layer deposition process includes a plasma-enhanced atomic layer deposition process.

[0086] In a specific example where the channel layer material is GaN, the Ga precursor is trimethylgallium (TMGa), the N precursor is NH3 or a mixture of H2 and N2 gas, the carrier gas is Ar, the substrate temperature range is 250℃~300℃, the RF power range is 300W~500W, the growth chamber pressure during precursor pulse is 0.3Torr~0.5Torr, the reaction chamber pressure during purging is 1Torr~1.5Torr, and the plasma frequency is 13.56MHz.

[0087] Next, step S4 is performed to execute the third atomic layer deposition process, forming a capping layer 600 on the ferroelectric layer 500. This capping layer 600 prevents oxidation of the ferroelectric layer 500. This is especially important when the ferroelectric layer 500 contains Sc, which is highly susceptible to oxidation.

[0088] In some embodiments, the crystal structure of the capping layer 600 is the same as that of the ferroelectric layer 500. This avoids stress caused by lattice mismatch between the capping layer 600 and the ferroelectric layer 500, which could affect the crystal structure of the ferroelectric layer 500 and consequently its ferroelectricity. In one example, both the ferroelectric layer 500 and the capping layer 600 have a wurtzite structure. Specifically, the material of the capping layer 600 can be GaN or AlN.

[0089] Optionally, the third atomic layer deposition process is a plasma-enhanced atomic layer deposition process.

[0090] In a specific example where the capping layer 600 is made of GaN, the Ga precursor is trimethylgallium (TMGa), the N precursor is NH3 or a mixture of H2 and N2 gas, the carrier gas is Ar, the substrate temperature range is 250℃~300℃, the RF power range is 300W~500W, the growth chamber pressure during precursor pulse is 0.3Torr~0.5Torr, the reaction chamber pressure during purging is 1Torr~1.5Torr, and the plasma frequency is 13.56MHz.

[0091] In one example, the second, first, and third atomic layer deposition processes are performed within the same growth chamber. A seed layer 400, a ferroelectric layer 500, and a cap layer 600 are grown in situ in a single step using atomic layer deposition. During this process, the substrate temperature can be controlled within the overlapping temperature window of the three material layers' atomic layer deposition processes; specifically, the substrate temperature is 300°C. This allows for better process compatibility.

[0092] In some embodiments, the thickness of the capping layer 600 ranges from 3 nm to 5 nm.

[0093] In this embodiment, the seed layer 400, the ferroelectric layer 500, and the capping layer 600 constitute the gate dielectric layer of the FeTFT.

[0094] Next, please refer to Figure 3 Step S5 is executed to form a source 710 and a drain 720 that penetrate at least through the capping layer 600 and the ferroelectric layer 500. Specifically, the capping layer 600, the ferroelectric layer 500, and the seed layer 400 are etched to form an opening extending into the seed layer 400; the source 710 and the drain 720 are formed within the opening. By retaining a portion of the thickness of the seed layer 400, the two-dimensional electron gas channels formed in the active layer 300 can be avoided, and the source 710 and the drain 720 can form an ohmic contact with the active layer 300. In some examples, the distance between the bottom wall of the opening and the side of the seed layer 400 away from the ferroelectric layer 500 is 2 nm to 4 nm.

[0095] In a specific example, the ohmic contact region can be formed using a photolithography-etching process; the source 710 and drain 720 can be formed using a photolithography, evaporation, and lift-off process. Specifically, organic cleaning is first performed to remove surface impurities, followed by HMDS (hexamethyldisilazane) pretreatment to increase the adhesion between the photoresist and the capping layer 600 surface; the photoresist is then formed and patterned through exposure and development; finally, plasma is used to remove the underresist to fully open the etching window. This completes the fabrication of the etching mask.

[0096] The capping layer 600 and the ferroelectric layer 500 are etched through using ICP etching; a portion of the seed layer 400 is etched using atomic layer etching (ALE). Understandably, while ICP etching offers a fast etching rate, it is difficult to precisely control the etching depth. To precisely control the etching depth and reduce plasma-induced damage, atomic layer etching is used after ICP etching. This sequential self-limiting etching method allows for atomically precise control of the etching rate and yields a smoother etched interface.

[0097] In ICP etching, the etching gas includes Cl-based gases. For example, the etching gas is a mixture of Cl2 and BCl3, to which Ar may be added, or it can be a mixture of Cl2, BCl3, and N2. In atomic layer etching, the etching gas includes Cl2 and Ar.

[0098] A double-layer metal film is formed using an electron beam evaporation process. Specifically, a 20nm Ti layer is deposited first, followed by a 150nm Au layer.

[0099] Next, the photoresist is removed using a stripping process. Specifically, the photoresist is removed by immersion in acetone (60°C water bath) or N-methylpyrrolidone / Microposit Remover 1165 (NMP, 80°C water bath). Appropriate ultrasonication can be used during the process to achieve better stripping results.

[0100] Next, please refer to Figure 4 Step S6 is executed to form an isolated active region within the active layer 300. Specifically, a mesa structure is formed through a photolithography-etching process. After the cleaning process, HMDS pretreatment is performed to form a photoresist adhesion layer. Then, photoresist is spin-coated on a spin coater. Specific photoresists include AZ5214, AZ6112, AZ1500, SPR955, SPR220, and S1805, with a thickness ranging from 1μm to 2μm. The base resist is removed by anti-plasma dry etching. After spin-coating the photoresist, it is pre-baked to remove solvent and form a film. The pre-baking temperature range is 95℃ to 100℃, and the time range is 60s to 90s. Specific details can be found in the user manuals for different photoresists. The photoresist is then subjected to ultraviolet optical exposure, specifically contact ultraviolet lithography and optical direct-write lithography. After exposure, the photoresist undergoes development to achieve pattern transfer. The developer includes an organic alkaline developer, specifically a 2.38% TMAH solution, such as MF CD26 or MF319 (2.45% TMAH), with a development time of 60-120 seconds. Following development, the photoresist is post-baked to improve its resistance to dry etching. The post-baking temperature range is 100°C-120°C, and the time range is 1-3 minutes. After post-baking, residual photoresist is removed in an oxygen plasma stripper at 200W RF power for 2 minutes. Then, etching is performed in an ICP plasma etching machine using a Cl-based gas, etching to the interior of the active layer 300, with an etching depth ranging from 70 nm to 90 nm. After etching, the photoresist is removed and cleaned. The photoresist remover includes N-methylpyrrolidone or Microposit Remover 1165 (NMP). The photoresist is soaked in an 80°C water bath for 30 to 60 minutes and sonicated. Then it is cleaned with ethanol and deionized water and finally dried with N2.

[0101] In some other embodiments, the active region can be isolated using F ion implantation. This eliminates the need to etch the mesa structure.

[0102] Next, please refer to Figure 4Step S7 is executed to form the gate 730 on the capping layer 600. In a specific example, the gate 730 can be formed using photolithography, evaporation, and lift-off processes. Specifically, after the organic cleaning process, HMDS pretreatment, spin coating, UV lithography exposure, development, and plasma stripping are performed sequentially. In an electron beam evaporation apparatus, a double-layer metal film is deposited, for example, first a 20nm Ni layer, then a 120nm Au layer. The lift-off process is performed in acetone (60°C water bath) or N-methylpyrrolidone / Microposit Remover 1165 (NMP, 80°C water bath). Appropriate ultrasonication can be used during the process to achieve better lift-off results. Finally, the gate 730 is obtained by cleaning and drying. In this embodiment, the length of the gate 730 ranges from 1μm to 2μm, the width of the gate 730 ranges from 10μm to 20μm, the distance between the gate 730 and the source 710 ranges from 1μm to 2μm, and the distance between the gate 730 and the drain 720 ranges from 3μm to 10μm.

[0103] Then, step S8 is executed to form lead electrodes (not shown in the figure) on the source 710, drain 720, and gate 730, respectively. In a specific example, the lead electrodes can be formed using photolithography, evaporation, and lift-off processes. Specifically, after cleaning, HMDS pretreatment, photoresist coating, UV lithography exposure, development, and plasma resist removal are performed sequentially. In an electron beam evaporation apparatus, a double-layer metal film is deposited, for example, first depositing a 20nm Ni layer, then depositing a 250nm Au layer. The lift-off process is performed in acetone (60°C water bath) or N-methylpyrrolidone / Microposit Remover 1165 (NMP, 80°C water bath). During the process, appropriate ultrasonication can be used to achieve better lift-off results, forming the lead electrodes.

[0104] Finally, step S9 is performed to thin the substrate by 100 μm and then perform a dicing process. For example, for a sapphire substrate, it can be thinned to 200 μm, and then laser dicing is used to dice and cleave it into individual ferroelectric thin-film transistors. For other substrates, such as Si and SiC, corresponding thinning equipment and dicing machines (laser or diamond blades) are required.

[0105] In practical applications, a wire drawing machine can be used to draw the three lead electrodes to the lead frame or PCB board electrodes.

[0106] Correspondingly, this application also provides a non-volatile memory based on a ferroelectric thin-film transistor, which is prepared using the fabrication method of the non-volatile memory based on a ferroelectric thin-film transistor provided in the above embodiments; wherein, the gate is used to apply a voltage to the ferroelectric layer, at least to control the switching of the ferroelectric layer between two polarization states, so as to realize the programming and erasing of data.

[0107] The non-centrosymmetry of the ferroelectric layer's cell structure causes the centers of positive and negative charges to not coincide, forming spontaneously generated dipole moments, i.e., spontaneous polarization. Due to the irregular polarization orientation of the initial state of the ferroelectric layer, the macroscopic appearance is that the polarization intensity is zero (the electric dipole moment per unit volume is called the spontaneous polarization intensity). Under the influence of an applied electric field, the spontaneous polarization orientation gradually becomes uniform, and the polarization intensity gradually increases. When the external electric field is sufficiently large, the polarization intensity reaches a saturation value, called the saturation polarization value. Applying an external electric field opposite to the spontaneous polarization direction causes the polarization intensity to return to zero. At this point, the electric field is called the coercive electric field Ec of the ferroelectric layer, which reflects the ferroelectric layer's ability to resist polarization reversal. Understandably, ferroelectric domains will only reverse when the applied electric field intensity is greater than the coercive electric field Ec. When the applied electric field reaches a certain negative value, the polarization intensity will again tend to saturate. Therefore, the degree of polarization of the ferroelectric layer can be controlled by adjusting the intensity of the applied electric field. Furthermore, when the electric field decreases to zero, the polarization intensity of the ferroelectric layer does not decrease to zero; a residual value remains, called the residual polarization value. Therefore, the electrical characteristics of ferroelectric thin-film transistors can be maintained for a long time after each modulation, exhibiting non-volatility. Non-volatile memory utilizes the non-volatility of ferroelectric thin-film transistors to achieve data storage.

[0108] Non-volatile memory has two states: Program (PGM) and Erase (ERS). Programming specifically refers to storing data, while erasing specifically refers to removing the stored data.

[0109] During programming, a positive gate voltage is applied to the gate 730, while the source 710 and drain 720 are grounded. The electric field generated by the gate voltage is greater than the coercive electric field Ec of the ferroelectric layer 500. At this time, the ferroelectric layer 500 will polarize along the direction of the external electric field; in fact, the tiny ferroelectric domains (electric dipole moments) in the ferroelectric layer 500 align with the external electric field. Due to the random distribution and non-uniform size of the ferroelectric domains, the polarization reversal of the ferroelectric domains has a certain delay. Specifically, a positive pulse signal can be applied to the gate 730; the AlScN thickness ranges from 10nm to 20nm, the voltage signal amplitude ranges from 7V to 15V, and the pulse width ranges from 1ms to 50ms. The pulse signal can include multiple consecutive short pulse signals. The pulse signal can include a square wave voltage signal or a triangular wave voltage signal. Please refer to [reference needed]. Figure 5 The polarization intensity direction is from the gate 730 to the active layer 300 (e.g., Figure 5 As shown by the arrow in ferroelectric layer 500 in Figure (a), or Figure 5(As indicated by the arrow in Figure (b)). When the positive gate voltage is removed, the ferroelectric layer 500 still maintains a strong residual polarization intensity, generating bound positive polarization charges at the interface of the ferroelectric layer 500 / seed layer 400. At this time, the bound positive polarization charges can attract a large number of electrons and accumulate in the channel below the gate 730, thereby increasing the electron concentration in the channel.

[0110] During erasure, a negative gate voltage is applied to the gate 730, while the source 710 and drain 720 are grounded. The electric field generated by the gate voltage is greater than the coercive electric field Ec of the ferroelectric layer 500. At this time, the ferroelectric layer 500 will also be polarized along the external electric field; in fact, the tiny ferroelectric domains in the ferroelectric layer 500 align with the external electric field. Specifically, a negative pulse voltage signal can be applied to the gate 730; the AlScN thickness ranges from 10nm to 20nm, the voltage signal amplitude ranges from -15V to -7V, and the pulse width ranges from 1ms to 50ms. The pulse signal can include multiple consecutive short pulse signals. The pulse signal can include a square wave voltage signal or a triangular wave voltage signal. Please refer to [reference needed]. Figure 6 The polarization intensity direction is from the active layer 300 to the gate 730 (e.g., Figure 6 As shown by the arrow in ferroelectric layer 500 in Figure (a), or Figure 6 (As indicated by the arrow in Figure (b)). When the negative gate voltage is removed, the ferroelectric layer 500 still maintains a strong remanent polarization intensity, generating bound negative polarization charges at the interface of ferroelectric layer 500 / seed layer 400. At this time, these bound negative polarization charges will repel electrons in the channel, causing the electron concentration in the channel to decrease or even be completely depleted. It should be noted that... Figure 6 Figure (b) is specifically the band diagram during the erasure operation, not the band diagram that reaches the equilibrium state after the gate voltage is finally removed. The diagram uses the accumulation of holes at the channel to illustrate the repulsion of electrons.

[0111] Non-volatile memory has transfer characteristics in both programmed and erased states. Please refer to [reference needed]. Figure 7After programming the ferroelectric layer 500 (i.e., in the PGM state), the threshold voltage Vth shifts towards a negative voltage due to the increased channel electron concentration. Similarly, after erasing the ferroelectric layer 500 (i.e., in the ERS state), the threshold voltage Vth shifts towards a positive voltage (Vth is near 0V) due to the decreased channel electron concentration. The difference between the threshold voltages Vth in these two states is the storage window of the non-volatile memory. When the non-volatile memory is in the programming or erasing state, a voltage is applied to the drain 720, placing the gate 730 voltage within the storage window range. If the non-volatile memory is in the programming state, a relatively large drain current will be measured; if the non-volatile memory is in the erasing state, a relatively small drain current will be measured. Data can be read non-destructively by reading the drain current. When it is necessary to change the accessed data, corresponding programming and erasing pulse signals can be applied to the gate 730. Due to the extremely high ferroelectric polarization switching speed, the programming and erasing speeds can reach the nanosecond level.

[0112] In some embodiments, the gate 730 is also used to regulate the polarization of the ferroelectric layer 500, introducing an intermediate state between two polarization states to achieve multi-bit data storage. Specifically, by applying an appropriate pulse signal to the gate 730, partial polarization reversal can be achieved, thereby adjusting the threshold voltage Vth between the two extreme state values ​​(programming state and erase state) to achieve multi-bit storage (i.e., the non-volatile memory can operate at different channel currents or conductances under different programming or erasing voltage operations), effectively improving data storage density. For a 20nm AlScN ferroelectric layer, in one example, the amplitude range of the pulse signal applied to the gate is 5V~7V, and the pulse width is on the order of milliseconds. In another example, the amplitude range of the pulse signal is 30V~40V, and the pulse width is on the order of microseconds; or, the amplitude range of the pulse signal is 30V~40V, and the pulse signal consists of multiple short pulse signals.

[0113] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for fabricating a non-volatile memory based on a ferroelectric thin-film transistor, characterized in that, The method comprises: providing a substrate comprising a substrate, a nucleation layer and an active layer stacked in sequence; performing a first atomic layer deposition process to form a seed layer on the active layer, the seed layer being of a binary nitride; performing a second atomic layer deposition process to form a ferroelectric layer on the seed layer, the ferroelectric layer being of a ternary nitride; wherein the performing of the second atomic layer deposition process to form the ferroelectric layer on the seed layer comprises performing a plurality of super cycles until the thickness of the formed ferroelectric layer reaches an expected thickness; wherein each super cycle comprises sequentially performing m first sub-cycles and n second sub-cycles to form m first sub-layers and n second sub-layers respectively, m≥1, n≥1; the first sub-layers and the second sub-layers are of binary nitrides, the materials of the first sub-layers and the second sub-layers are different, and the material of the first sub-layers is the same as that of the seed layer; the binary nitrides are composed of elements in the ternary nitride; performing a third atomic layer deposition process to form a cap layer on the ferroelectric layer; forming a source and a drain at least through the cap layer and the ferroelectric layer; forming an isolated active region in the active layer; forming a gate on the cap layer; forming a lead electrode on the source, the drain and the gate; thinning the substrate and performing a dicing process.

2. The method of claim 1, wherein the ferroelectric thin film transistor based nonvolatile memory is prepared by the steps of: The material of the ferroelectric layer is AlScN, and 1:2≤m:n≤1:

5.

3. The method for fabricating a non-volatile memory based on a ferroelectric thin-film transistor according to claim 1, characterized in that, The first atomic layer deposition process, the second atomic layer deposition process and the third atomic layer deposition process are performed in the same growth chamber.

4. The preparation method of the ferroelectric thin film transistor-based nonvolatile memory according to claim 1, wherein The first atomic layer deposition process, the second atomic layer deposition process and the third atomic layer deposition process comprise a plasma-enhanced atomic layer deposition process, and a plasma source in the plasma-enhanced atomic layer deposition process comprises a hollow cathode plasma source.

5. The method for fabricating a non-volatile memory based on a ferroelectric thin-film transistor according to claim 1, characterized in that, The material of the ferroelectric layer comprises Sc elements; and a Sc precursor in the second atomic layer deposition process comprises diisopropylamine scandium and / or trimethylcyclopentadienyl scandium.

6. The method for fabricating a non-volatile memory based on a ferroelectric thin-film transistor according to claim 1, characterized in that, The forming of the source and the drain at least through the cap layer and the ferroelectric layer comprises: etching the cap layer, the ferroelectric layer and the seed layer to form an opening extending into the seed layer; and forming the source and the drain in the opening.

7. The method for fabricating a non-volatile memory based on a ferroelectric thin-film transistor according to claim 6, characterized in that, The etching of the cap layer, the ferroelectric layer and the seed layer comprises: performing an inductively coupled plasma etching process to etch through the cap layer and the ferroelectric layer; performing an atomic layer etching process to etch part of the seed layer.

8. A ferroelectric thin film transistor based nonvolatile memory, comprising: a ferroelectric thin film transistor; and a ferroelectric capacitor. The ferroelectric thin film transistor-based nonvolatile memory is prepared by using the preparation method of the ferroelectric thin film transistor-based nonvolatile memory according to any one of claims 1 to 7; wherein the gate is configured to apply a voltage to the ferroelectric layer, to at least control the switching of the ferroelectric layer between two polarization states, so as to realize the programming and erasing of data.

9. The ferroelectric thin film transistor based nonvolatile memory according to claim 8, wherein, The gate is further configured to control the polarization degree of the ferroelectric layer, to introduce an intermediate state between the two polarization states, so as to realize the multi-bit storage of data.

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