Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a channel layer, a barrier layer, a source electrode and a drain electrode. The channel layer is located on one side of the substrate; the barrier layer is located on the side of the channel layer away from the substrate, and the barrier layer comprises a first surface facing away from the channel layer, the first surface comprising an ohmic contact region, the ohmic contact region comprising at least one first ohmic contact region and at least one second ohmic contact region, the surface of the same ohmic contact region comprising a first sub-surface and a second sub-surface, the second sub-surface being located on at least one side of the first sub-surface; in the adjacent first ohmic contact region and the second ohmic contact region, the second sub-surface of the first ohmic contact region comprises at least a first sub-region located on the side of the first sub-surface facing the second ohmic contact region, and the first sub-region of the first ohmic contact region is at least partially recessed relative to the first sub-surface thereof. The current conduction efficiency of the semiconductor device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a semiconductor device and its fabrication method. Background Technology

[0002] Semiconductor devices can include heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs), high electron mobility transistors (HEMTs), and modulation-doped FETs (MODFETs). Among them, the high electron mobility transistor (HEMT) is a field-effect transistor that operates based on a two-dimensional electron gas (2DEG) at the heterojunction interface. Due to its excellent characteristics such as high electron mobility, high saturation velocity, high operating frequency, and high power density, it has become a core device in radio frequency communication, power electronics, and millimeter-wave devices. Summary of the Invention

[0003] This application provides a semiconductor device, including:

[0004] Substrate;

[0005] A channel layer is located on one side of the substrate;

[0006] A barrier layer is located on the side of the channel layer away from the substrate. The barrier layer includes a first surface facing away from the channel layer. The first surface includes an ohmic contact region, which includes at least one first ohmic contact region and at least one second ohmic contact region. The surface of the same ohmic contact region includes a first sub-surface and a second sub-surface, with the second sub-surface located on at least one side of the first sub-surface. In adjacent first and second ohmic contact regions, the second sub-surface of the first ohmic contact region includes at least a first sub-region located on the side of the first sub-surface facing the second ohmic contact region, and the first sub-region of the first ohmic contact region is at least partially recessed relative to its first sub-surface. And / or, in adjacent first and second ohmic contact regions, the second sub-surface of the second ohmic contact region includes at least a second sub-region located on the side of the first sub-surface facing the first ohmic contact region, and the second sub-region of the second ohmic contact region is at least partially recessed relative to its first sub-surface. The average height of the first sub-surface is higher than the average height of the second sub-surface.

[0007] At least one source electrode, each of the source electrodes being in contact with a first ohmic contact region;

[0008] At least one drain electrode, each of which is in contact with a second ohmic contact region.

[0009] In some embodiments, at least a portion of the first sub-surface is a smooth curved surface;

[0010] In some embodiments, at least a portion of the second sub-surface is a smooth curved surface.

[0011] In some embodiments, the first sub-surface and the second sub-surface are smoothly connected.

[0012] In some embodiments, the first surface further includes a third sub-surface, the third sub-surface comprising a portion of the first surface excluding the ohmic contact region, wherein...

[0013] The position on the first sub-surface that is furthest from the channel layer is farther from the channel layer than the third sub-surface;

[0014] And / or, the location where the second sub-surface is closest to the channel layer is closer to the channel layer than the third sub-surface.

[0015] In some embodiments, the barrier layer further includes a second surface opposite to the first surface, and the ratio between the maximum distance between the first sub-surface and the second surface and the minimum distance between the second sub-surface and the second surface in the direction of the channel layer pointing to the barrier layer is in the range of 1 to 2.

[0016] In some embodiments, the barrier layer further includes a second surface opposite to the first surface, the first sub-surface protruding away from the second surface, and the second sub-surface recessed toward the second surface; the ratio between the width of the first sub-surface and the width of the second sub-surface is in the range of 0.5 to 1.5 in a direction parallel to the side surface of the barrier layer away from the channel layer.

[0017] In some embodiments, the semiconductor device further includes a gate, an ohmic electrode including at least one of a source and a drain, the gate being located between the source and the drain, and the ratio of the width of the ohmic electrode to the width of the gate being between 10 and 200 in a direction parallel to the side surface of the barrier layer away from the channel layer.

[0018] In some embodiments, the width of the ohmic contact region ranges from 5µm to 100µm in a direction parallel to the side surface of the barrier layer away from the channel layer.

[0019] In some embodiments, the width of the gate ranges from 0.1µm to 2µm in a direction parallel to the side surface of the barrier layer away from the channel layer.

[0020] In some embodiments, the semiconductor device is a GaN radio frequency device.

[0021] In some embodiments, the semiconductor device further includes a passivation layer located on the side of the barrier layer away from the channel layer, the passivation layer having at least one first via, wherein the orthographic projection of the same first via on the substrate overlaps with the orthographic projection of an ohmic contact region on the substrate.

[0022] This application also provides a semiconductor device, including:

[0023] Substrate;

[0024] The heterojunction layer includes a channel layer and a barrier layer sequentially stacked on one side of the substrate;

[0025] At least one source and at least one drain are located on the side of the heterojunction layer away from the substrate; the source or the drain includes a fourth sub-surface and a fifth sub-surface facing the substrate, the fifth sub-surface being located on at least one side of the fourth sub-surface; in adjacent source and drain electrodes, the fifth sub-surface of the source electrode includes at least a third sub-region located on the fourth sub-surface facing the drain electrode, and the third sub-region of the source electrode protrudes at least partially relative to its fourth sub-surface toward the substrate; and / or, in adjacent source and drain electrodes, the fifth sub-surface of the drain electrode includes at least a fourth sub-region located on the fourth sub-surface facing the source electrode, and the fourth sub-region of the drain electrode protrudes at least partially relative to its fourth sub-surface toward the substrate; the average height of the fourth sub-surface relative to the substrate is higher than the average height of the fifth sub-surface relative to the substrate.

[0026] In some embodiments, the surface of the heterojunction layer away from the substrate includes an ohmic contact region, the ohmic contact region including at least one first ohmic contact region and at least one second ohmic contact region, one first ohmic contact region being in contact with one of the source electrodes, and one second ohmic contact region being in contact with one of the drain electrodes; the surface of the same ohmic contact region includes a first ohmic contact sub-surface and a second ohmic contact surface, the second ohmic contact surface being located on at least one side of the first ohmic contact surface; the first ohmic contact sub-surface is in contact with the fourth sub-surface, and the second ohmic contact surface is in contact with the fifth sub-surface.

[0027] In some embodiments, the first ohmic contact surface includes at least a portion of the side surface of the barrier layer away from the substrate, wherein,

[0028] The second ohmic contact surface includes at least a portion of the barrier layer's surface away from the substrate; and / or, the second ohmic contact surface includes at least a portion of the channel layer's surface away from the substrate.

[0029] In some embodiments, the first ohmic contact surface includes at least a portion of the side surface of the channel layer away from the substrate, and the second ohmic contact surface includes at least a portion of the side surface of the channel layer away from the substrate.

[0030] In some embodiments, the semiconductor device further includes a passivation layer located on the side of the barrier layer away from the channel layer, the passivation layer having at least one first via, wherein the orthographic projection of the same first via on the substrate overlaps with the orthographic projection of an ohmic contact region on the substrate.

[0031] In some embodiments, the heterojunction layer includes an ohmic contact region on the side of its surface away from the substrate. The ohmic contact region includes at least one first ohmic contact region and at least one second ohmic contact region. One first ohmic contact region contacts one of the source electrodes, and one second ohmic contact region contacts one of the drain electrodes. The surface of the same ohmic contact region includes a third ohmic contact sub-surface. The semiconductor device further includes a passivation layer located on the side of the barrier layer away from the channel layer. The passivation layer includes an insulating portion and a first via located on at least one side of the insulating portion. The first via exposes the third ohmic contact sub-surface. The side of the insulating portion away from the substrate contacts the fourth sub-surface, and the third ohmic contact sub-surface contacts the fifth sub-surface.

[0032] In some embodiments, the third ohmic contact surface includes at least a portion of the side surface of the barrier layer away from the substrate;

[0033] And / or, the third ohmic contact surface includes at least a portion of the side surface of the channel layer away from the substrate.

[0034] In some embodiments, in the direction from the channel layer to the barrier layer, the height of the insulating portion is less than the height of the passivation layer excluding the first via and the insulating portion.

[0035] In some embodiments, the semiconductor device further includes a gate located between the source and the drain, wherein a portion of the fifth sub-surface near the gate is closer to the substrate than a portion of the fifth sub-surface away from the gate.

[0036] In some embodiments, at least a portion of the fourth sub-surface is a smooth curved surface;

[0037] And / or, at least a portion of the fifth sub-surface is a smooth curved surface.

[0038] In some embodiments, the fourth sub-surface and the fifth sub-surface are smoothly connected.

[0039] In some embodiments, the fifth sub-surface is disposed around the fourth sub-surface.

[0040] In some embodiments, the semiconductor device further includes a gate, the ohmic electrode includes a source and a drain, the ohmic electrode includes at least one of the source and the drain, the gate is located between the source and the drain, and the ratio of the width of the ohmic electrode to the width of the gate is between 10 and 200 in a direction parallel to the side surface of the barrier layer away from the channel layer.

[0041] In some embodiments, the width of the ohmic electrode ranges from 5µm to 100µm in a direction parallel to the side surface of the barrier layer away from the channel layer.

[0042] In some embodiments, the width of the gate ranges from 0.1µm to 2µm in a direction parallel to the side surface of the barrier layer away from the channel layer.

[0043] In some embodiments, the semiconductor device is a GaN radio frequency device.

[0044] This application also provides a method for fabricating a semiconductor device, comprising:

[0045] A channel layer and a barrier layer thin film are sequentially formed on the substrate;

[0046] The barrier layer film is patterned on the side of the barrier layer film away from the channel layer to form a barrier layer. The barrier layer includes a first surface away from the channel layer. The first surface includes an ohmic contact region, which includes at least one first ohmic contact region and at least one second ohmic contact region. The surface of the same ohmic contact region includes a first sub-surface and a second sub-surface, with the second sub-surface located on at least one side of the first sub-surface. In adjacent first and second ohmic contact regions, the second sub-surface of the first ohmic contact region includes at least a first sub-region located on the side of the first sub-surface facing the second ohmic contact region, and the first sub-region of the first ohmic contact region is at least partially recessed relative to its first sub-surface. And / or, in adjacent first and second ohmic contact regions, the second sub-surface of the second ohmic contact region includes at least a second sub-region located on the side of the first sub-surface facing the first ohmic contact region, and the second sub-region of the second ohmic contact region is at least partially recessed relative to its first sub-surface.

[0047] A source and a drain are formed on the side of the barrier layer away from the channel layer, with the source in contact with the first ohmic contact region and the drain in contact with the second ohmic contact region.

[0048] The patterning process for the surface of the barrier layer film away from the channel layer includes:

[0049] A mask layer is formed on the side of the barrier layer film away from the channel layer. The mask layer has mask openings that expose the ohmic contact region of the barrier layer film. The ohmic contact region includes a first patterned region and a second patterned region.

[0050] The first patterned area is etched with an etching gas having a functional gas ratio of a first proportion to form the first sub-surface, and the second ohmic contact opening area is etched with an etching gas having a functional gas ratio of a second proportion to form the second sub-surface, wherein the first proportion is less than the first proportion.

[0051] Remove the mask layer.

[0052] In some embodiments, the method for fabricating the semiconductor device further includes:

[0053] A passivation layer film is formed, and the passivation layer film is patterned to form a first through hole;

[0054] The step of patterning the passivation layer film and the step of patterning the surface of the passivation layer film away from the channel layer to form a barrier layer are performed by the same patterning process.

[0055] The beneficial effects of this application include:

[0056] When carriers flow between the source above the first ohmic contact region and the drain above the second ohmic contact region, the edge region of the source closer to the drain requires a higher current density than the middle region as carriers are transferred from the source to the drain surrounding it. In this embodiment, the minimum thickness of the edge region of the first ohmic contact region on the barrier layer is designed to be smaller than the maximum thickness of the middle region. This reduces the resistance of the edge region, lowers conduction losses, and facilitates higher conduction current between the source and drain in the semiconductor device, thereby improving device efficiency.

[0057] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0058] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0059] Figures 1-13 The diagram shown is a cross-sectional view of several semiconductor devices provided in an exemplary embodiment of this application;

[0060] Figures 14-18 The diagram shown is a schematic representation of the steps in a method for fabricating a semiconductor device according to an exemplary embodiment of this application.

[0061] Figures 19-23 The diagram shown is a schematic representation of the steps in a method for fabricating a semiconductor device according to an exemplary embodiment of this application.

[0062] Figures 24-29 The diagram shown is a cross-sectional view of several semiconductor devices provided in an exemplary embodiment of this application.

[0063] In the figure: 1-substrate; 20-heterojunction layer; 2011-first ohmic contact surface; 2012-second ohmic contact surface; 2013-third ohmic contact surface; 2-channel layer; 3-barrier layer; 31-first surface; 311 / 201-ohmic contact region; 311a / 201a-first ohmic contact region; 311b / 201b-second ohmic contact region; 3111-first sub-surface; 3112-third ohmic contact surface; 20-heterojunction layer ... 312-Second sub-surface; 32-Second surface; 301-Recessed structure; 302-Protruding structure; 3a-Concave hole; 303-Third through hole; 30-Barrier layer film; 4-Passivation layer; 41-First through hole; 42-Second through hole; 43-Insulating part; 40-Passivation layer film; 5-Ohmic electrode; 51-Source; 52-Drain; 501-Fourth sub-surface; 502-Fifth sub-surface; 6-Gate; 7-Cap layer. Detailed Implementation

[0064] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0065] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0066] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0067] The semiconductor devices and their fabrication methods in the embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments may complement or combine with each other.

[0068] This application provides a semiconductor device, such as... Figure 1 and Figure 2 As shown, the semiconductor device includes a substrate 1, a channel layer 2, a barrier layer 3, at least one source 51, and at least one drain 52. The barrier layer 3 is located on the side of the channel layer 2 away from the substrate. The barrier layer 3 includes a first surface 31 facing away from the channel layer 2. The first surface 31 includes an ohmic contact region 311, which includes at least one first ohmic contact region 311a and at least one second ohmic contact region 311b. The surface of the same ohmic contact region 311 includes a first sub-surface 3111 and a second sub-surface 3112, with the second sub-surface 3112 located on at least one side of the first sub-surface 3111. In adjacent first ohmic contact regions 311a and second ohmic contact regions 311b, the second sub-surface 3112 of the first ohmic contact region 311a includes at least one first ohmic contact region 311a located on the side of the first sub-surface 311a facing the second ohmic contact region 311b. A sub-region (not shown in the figure), and the first sub-region of the first ohmic contact region 311a is at least partially recessed relative to its first sub-surface 3111; and / or, in adjacent first ohmic contact regions 311a and second ohmic contact regions 311b, the second sub-surface of the second ohmic contact region 311b includes at least a second sub-region located on the side of the first sub-surface facing the first ohmic contact region 311a, and the second sub-region of the second ohmic contact region 311b is at least partially recessed relative to its first sub-surface; the average height of the first sub-surface 3111 is higher than the average height of the second sub-surface 3112; the source electrode 51 is in contact with a first ohmic contact region 311a; each drain electrode 52 is in contact with a second ohmic contact region 311b.

[0069] In this embodiment, taking the first ohmic contact region 311a as an example, when the area of ​​the second sub-surface 3112 of the first ohmic contact region 311a facing the second ohmic contact region 311b is recessed relative to the first sub-surface 3111, the direction of the channel layer 2 pointing towards the barrier layer 3 is upward. The lowest point B1 / B2 of the second sub-surface 3112 is closer to the channel layer 2 than the highest point A of the first sub-surface 3111. That is, the distance d2 between the lowest point B1 / B2 (e.g., B1) of the second sub-surface 3112 and the channel layer 2 is less than the distance d1 between the highest point A of the first sub-surface 3111 and the channel layer 2. When the device is working, combined with Figure 2As shown, when carriers flow between the source 51 above the first ohmic contact region 311a and the drain 52 above the second ohmic contact, the edge region of the source 51 closer to the drain 52 requires a higher current density than the middle region because carriers are transferred from the source to the drain 52 surrounding it. In this embodiment, the minimum thickness of the edge region of the first ohmic contact region 311a on the barrier layer 3 is designed to be smaller than the maximum thickness of the middle region. This reduces the resistance of the edge region, lowers conduction losses, and facilitates higher conduction current between the source 51 and the drain 52 in the semiconductor device, thereby improving device efficiency.

[0070] It should be noted that the average height of the first sub-surface 3111 is higher than the average height of the second sub-surface 3112. Furthermore, the overall height of the second sub-surface 3112 can be lower than that of the first sub-surface 3111. Thus, the overall current transfer efficiency of the source 51 / drain 52 in the edge region of the ohmic contact region 311 is higher than that in the middle region.

[0071] In some embodiments, combined with Figure 2 As shown, the barrier layer 3 includes multiple ohmic contact regions 311. At least one ohmic contact region 311 contacts the source electrode 51 to form a first ohmic contact region 311a, and at least one ohmic contact region 311 contacts the drain electrode 52 to form a second ohmic contact region 311b. It should be noted that the ohmic contact region 311 mentioned below refers to the first ohmic contact region 311a. The structural features of the second ohmic contact region 311b are similar to those of the first ohmic contact region 311a, and will not be described again below.

[0072] In some embodiments, the second sub-surface 3112 has a plurality of lowest points (e.g., B1, B2). In one example, the spacing between the plurality of lowest points of the second sub-surface and the channel layer 2 is different. In another example, at least two of the plurality of lowest points of the second sub-surface are spaced the same distance from the channel layer. Taking an embodiment of this application as an example, the spacing between lowest point B1 and lowest point B2 and the channel layer can be the same or different.

[0073] It should be noted that, in combination Figure 1As shown, when the first sub-surface 3111 and the second sub-surface 3112 are connected, on a longitudinal section passing through the highest point A of the first sub-surface 3111 and the lowest point B1 / B2 of the second sub-surface 3112 simultaneously, the boundary point between the first sub-surface 3111 and the second sub-surface 3112 is the intersection point C1 / C2 between the central axis L1 / L2 between the highest point A of the first sub-surface 3111 and the lowest point B1 / B2 of the second sub-surface 3112 and the first surface 31. For example, in a direction parallel to the side surface of the barrier layer 3 away from the channel layer 2, the distance x1 from the central axis L1 to the highest point A of the first sub-surface 3111 is equal to the distance x2 from the central axis to the lowest point B1 of the second sub-surface 3112. Furthermore, when at least one of the first sub-surface 3111 and the second sub-surface 3112 is a flat surface parallel to the second surface 32, the highest or lowest point of the first sub-surface 3111 / second sub-surface 3112 can be taken as the midpoint of the longitudinal section of the first sub-surface 3111 / second sub-surface 3112. The following embodiments are similar and will not be described again below.

[0074] In some embodiments, the second sub-surface 3112 is disposed around the first sub-surface 3111, specifically, the second sub-surface 3112 may be located in at least a portion of the periphery of the first sub-surface 3111. In one example, the orthographic projection of the first sub-surface 3111 onto the substrate 1 is rectangular, including four sequentially connected sides. The second sub-surface 3112 may be located outside at least one side of the first sub-surface 3111. For example, if the second sub-surface 3112 is located outside one of the sides, then the orthographic projection of the second sub-surface 3112 onto the substrate 1 may be strip-shaped. The second sub-surface 3112 may also be located outside opposite two sides, then the orthographic projection of the second sub-surface 3112 onto the substrate 1 may be two spaced-apart stripes. The second sub-surface 3112 may also be located outside adjacent two sides, then the orthographic projection of the second sub-surface 3112 onto the substrate 1 may be L-shaped. The second sub-surface 3112 may also be located outside three sequentially connected sides, then the orthographic projection of the second sub-surface 3112 onto the substrate 1 may be U-shaped. The second sub-surface 3112 can also be located outside the four sides and connected to form a ring. The shape of the orthogonal projection of the second sub-surface 3112 on the substrate 1 is a square ring.

[0075] In some embodiments, the second sub-surface 3112 is connected to the first sub-surface 3111. In other embodiments, the second sub-surface 3112 may also be spaced apart from the first sub-surface 3111.

[0076] In some embodiments, substrate 1 may comprise silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs) or other semiconductor materials, and may also comprise sapphire, silicon-on-insulator (SOI) or other suitable materials.

[0077] In some embodiments, the channel layer 2 can be a material with high electron mobility, such as gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium phosphide (InP), or indium gallium arsenide (In). x Ga 1-x As, where 0 < x < 1, aluminum gallium nitride (Al x Ga 1- x N, where 0 < x < 1, etc. Preferably, the channel layer 2 can be gallium nitride (GaN), and the band gap of GaN is about 3.4 eV. In addition, a buffer layer (not shown in the figure) can be provided between the channel layer 2 and the substrate 1. The buffer layer is used to reduce the lattice mismatch between the substrate 1 and the channel layer 2.

[0078] In some embodiments, the barrier layer 3 can be a wide-bandgap semiconductor material, which may include group III-V compounds, such as aluminum gallium nitride (Al₂O₃). x Ga 1-x N, where x≤1), AlGaAs, InAlGaNi (In a Al b Ga 1-a-b N, where a+b≤1), aluminum indium phosphide (AlInP), aluminum gallium nitride (Al... x Ga 1-x N, where x≤1), indium aluminum nitrogen (In x Al 1-x N, where x < 1). The band gap of the barrier layer 3 can be larger than the band gap of the channel layer 2. Preferably, the barrier layer 3 can be indium gallium nitride (InGaN). x Ga 1-x N, where x≤1), Al x Ga 1-x The band gap of N is approximately 3.4 to 6.2 eV.

[0079] It should be noted that due to the band difference between the channel layer 2 and the barrier layer 3, the barrier layer 3 can form a potential well for electrons, which restricts the movement of electrons in the direction perpendicular to the barrier layer 3, while allowing them to move freely in the plane of the barrier layer 3, thus forming a two-dimensional electron gas (2DEG) region.

[0080] In some embodiments, such as Figure 1As shown, in the direction parallel to the surface of the barrier layer 3 away from the channel layer 2, the ratio of the width k1 of the ohmic electrode 5 to the width k2 of the gate 6 is between 10 and 200. The ohmic electrode 5 and gate 6 of the semiconductor device are generally elongated structures. The length direction of the ohmic electrode 5 and gate 6 refers to the length Y direction of a single ohmic electrode 5 and gate 6, the width direction refers to the width X direction of a single ohmic electrode and gate 6, and the thickness direction refers to the thickness Z direction of a single ohmic electrode 5 and gate 6. The ohmic electrodes 5 and gate 6 are arranged at intervals along the width X direction. In some embodiments, the width of a single ohmic electrode 5 in the thickness direction is not completely uniform; for example, the width of a single ohmic electrode 5 may gradually decrease in the thickness direction. Similarly, in some embodiments, the width of a single gate 6 in the thickness direction is not completely uniform; for example, the width of a single gate 6 may gradually decrease in the thickness direction. In this case, the width of the ohmic electrode 5 can be taken as the width of the bottommost part of the ohmic electrode 5 in the thickness direction, i.e., the side closest to the substrate 1, and the width of the gate 6 can be taken as the width of the bottommost part of the gate 6 in the thickness direction, i.e., the side closest to the substrate 1. In some embodiments, in the direction parallel to the surface of the barrier layer 3 away from the channel layer 2, the width k1 of the ohmic contact region 311 (i.e., the ohmic electrode) ranges from 5µm to 100µm. This avoids the situation where the width of the ohmic contact region 311 is too small, preventing the formation of a first sub-surface 3111 and a second sub-surface 3112 with a relative height difference due to process limitations, and also avoids the ohmic contact region 311 being too large, which does not meet the requirements for device miniaturization and integration. In some examples, the width k1 of the ohmic contact area 311 can be 5µm, 10µm, 20µm, 50µm or 100µm.

[0081] In some embodiments, such as Figure 3 and Figure 4 As shown, in the direction parallel to the side surface of the barrier layer 3 away from the channel layer 2, the width k2 of the gate 6 ranges from 0.1µm to 2µm.

[0082] In some embodiments, such as Figure 1 As shown, the barrier layer 3 also includes a second surface 32 opposite to the first surface 31. In the direction from the channel layer 2 to the barrier layer 3, the ratio between the maximum distance d1 between the first sub-surface 3111 and the second surface 32 and the minimum distance d2 between the second sub-surface 3112 and the second surface 32 is in the range of 1 to 2.

[0083] In this embodiment, the maximum distance between the first sub-surface 3111 and the second surface 32 can be the distance d1 between the highest point of the first sub-surface 3111 and the second surface 32, and the minimum distance between the second sub-surface 3112 and the second surface 32 can be the distance d2 between the lowest point of the second sub-surface 3112 and the second surface 32. The ratio of d1 to d2 ranges from 1 to 2. In some embodiments, the ratio of d1 to d2 can be 1, 1.5, or 2. Preferably, the ratio of d1 to d2 can be 1.5. In one example, the value of d1 can be 8 to 10 µm, and the value of d2 can be 6 to 8 µm. This setting avoids the ohmic contact region 311 of the barrier layer 3 being too thin, which would affect the two-dimensional electron gas (2DEG) region. At the same time, it avoids the ohmic contact region 311 being too thick, which would be detrimental to the reduction of contact resistance.

[0084] In some embodiments, such as Figure 1 As shown, the barrier layer 3 also includes a second surface 32 opposite to the first surface 31. The first sub-surface 3111 protrudes away from the second surface 32, and the second sub-surface 3112 is recessed towards the second surface 32. In the direction parallel to the side surface of the barrier layer 3 away from the channel layer 2, the ratio between the width w1 of the first sub-surface 3111 and the width w2 of the second sub-surface 3112 ranges from 0.5 to 1.5. For example, the ratio between the width w1 of the first sub-surface 3111 and the width w2 of the second sub-surface 3112 can be 1. This results in a more uniform width design for the first sub-surface 3111 and the second sub-surface 3112, which is beneficial for maintaining the structural stability of the semiconductor device. The following embodiments are similar and will not be described again.

[0085] In some embodiments, at least a portion of the first sub-surface 3111 is a smooth curved surface. This minimizes the formation of sharp corner regions on the first sub-surface 3111, which can lead to tip effects, causing localized current density concentrations and device failure. Additionally, it can reduce contact resistance and improve electron migration efficiency. For example, as... Figure 1 As shown, the entire first sub-surface 3111 is a smooth surface. In other examples, a portion of the first sub-surface is a smooth surface, while another portion is a non-smooth surface.

[0086] In some embodiments, at least a portion of the second sub-surface 3112 is a smooth curved surface. Similar to the foregoing embodiments, this also reduces contact resistance and lowers the risk of device burn-out. In some embodiments, such as Figure 1 As shown, the entire second sub-surface 3112 is a smooth curved surface. In other embodiments, such as Figure 3As shown, the portion of the second sub-surface 3112 closest to the first sub-surface 3111 is a smooth curved surface. In other embodiments, the portion of the second sub-surface 3112 furthest from the first sub-surface 3111 is a smooth curved surface (not shown in the figure).

[0087] In some embodiments, such as Figure 1 As shown, both the first sub-surface 3111 and the second sub-surface 3112 are smooth curved surfaces.

[0088] In some embodiments, such as Figure 1 As shown, the first sub-surface 3111 and the second sub-surface 3112 are smoothly connected. This improves the continuity between the first sub-surface 3111 and the second sub-surface 3112, reduces contact resistance, and lowers the risk of device burn-out.

[0089] In some embodiments, at least one of the first sub-surface 3111 and the second sub-surface 3112 is a rough surface. This reduces the difficulty of fabrication and improves fabrication efficiency compared to forming a smooth surface. In one example, such as... Figure 4 As shown, both the first sub-surface 3111 and the second sub-surface 3112 are rough surfaces.

[0090] In some embodiments, such as Figure 5 As shown, the longitudinal section of the second sub-surface 3112 can be a circular arc. Forming a surface with a regular shape can help control the electron migration rate of each ohmic contact region 311 to form a standard, which is beneficial to the consistency of the control device structure.

[0091] In other embodiments, such as Figure 6 As shown, the second sub-surface can also be a folded surface formed by connecting at least two straight surfaces. In this embodiment, the shape of the second sub-surface can be adaptively adjusted according to the specific fabrication process, which can simplify the fabrication process of the corresponding semiconductor device.

[0092] In some embodiments, the first surface 31 further includes a third sub-surface 312, which includes the portion of the first surface 31 excluding the ohmic contact region 311, and the third sub-surface 312 may be planar. Figure 5 As shown, the closest point between the second sub-surface 3112 and the channel layer 2 is closer to the channel layer 2 than that between the third sub-surface. That is, the distance d3 between the lowest point of the second sub-surface 3112 and the channel layer 2 is smaller than the distance d4 between the third sub-surface 312 and the channel layer 2. Therefore, in this embodiment, multiple annular recessed structures 301 can be formed on the first surface 31 of the barrier layer 3. The surface of the recessed structure 301 is the second sub-surface 3112, and the middle region of the recessed structure 301 is the first sub-surface 3111. In other embodiments, Figure 6 Similarly, with Figure 5 The difference is Figure 6 The longitudinal section of the recessed structure 301 shown is an inverted trapezoid. It should be noted that the longitudinal section of the recessed structure 301 can also be rectangular, arc-shaped, semi-circular, or inverted triangular, and can be adapted to actual needs.

[0093] In some embodiments, the first surface 31 further includes a third sub-surface 312, which includes the portion of the first surface 31 excluding the ohmic contact region 311, such as... Figure 7 As shown, the position furthest from the channel layer 2 on the first sub-surface 3111 is farther from the channel layer 2 than that on the third sub-surface 312. That is, the distance d6 between the highest point of the first sub-surface 3111 and the channel layer 2 is greater than the distance d5 between the third sub-surface 312 and the channel layer 2. Therefore, in this embodiment, multiple protrusion structures 302 can be formed on the first surface 31 of the barrier layer 3. The surface of the protrusion structure 302 is the first sub-surface 3111, and at least a portion of the area surrounding the protrusion structure 302 is the second sub-surface 3112. In other embodiments, Figure 8 Similarly, with Figure 7 The difference is Figure 8 The longitudinal section of the raised structure 302 shown is trapezoidal. It should be noted that the longitudinal section of the raised structure 302 can be rectangular, arc-shaped, semi-circular, or triangular, and can be adapted to actual needs.

[0094] In some embodiments, the first surface 31 further includes a third sub-surface 312, which includes the portion of the first surface 31 excluding the ohmic contact region 311, such as... Figure 9 As shown, the position furthest from the channel layer 2 on the first sub-surface 3111 is farther from the channel layer 2 than the position furthest from the third sub-surface 312, and the position closest to the channel layer 2 on the second sub-surface 3112 is closer to the channel layer 2 than the position furthest from the third sub-surface 312. That is, the distance d7 between the highest point of the first sub-surface 3111 and the channel layer 2 is greater than the distance d8 between the third sub-surface 312 and the channel layer 2, and the distance d9 between the lowest point of the second sub-surface 3112 and the channel layer 2 is less than the distance d8 between the third sub-surface 312 and the channel layer 2. Therefore, in this embodiment, a protruding structure 302 and a recessed structure 301 surrounding the protruding structure 302 can be formed simultaneously on the first surface 31 of the barrier layer 3. The surface of the protruding structure 302 forms the first sub-surface 3111, and the surface of the recessed structure 301 forms the second sub-surface 3112.

[0095] In some embodiments, the source electrode 51 may include a conductive material, which may include a metal, alloy, doped semiconductor material (e.g., doped crystalline silicon) or other suitable conductive material, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials.

[0096] In some embodiments, the drain 52 may include a conductive material, which may include a metal, alloy, doped semiconductor material (e.g., doped crystalline silicon) or other suitable conductive material, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials.

[0097] In some embodiments, such as Figure 2 As shown, the orthographic projection of the same source electrode 51 on the substrate 1 completely coincides with the orthographic projection of a first ohmic contact region 311a on the substrate 1, and the orthographic projection of the same drain electrode 52 on the substrate 1 completely coincides with the orthographic projection of a second ohmic contact region 311b on the substrate 1.

[0098] In other embodiments, such as Figure 10 As shown, the outline of the orthogonal projection of the same source electrode 51 on the substrate 1 is located outside the outline of a first ohmic contact region 311a on the substrate 1, and the outline of the orthogonal projection of the same drain electrode 52 on the substrate 1 is located outside the outline of a second ohmic contact region 311b on the substrate 1.

[0099] In some embodiments, the semiconductor device further includes a passivation layer 4 located on the side of the barrier layer 3 away from the channel layer 2. The passivation layer 4 has at least one first via 41, and the orthographic projection of the same first via 41 on the substrate 1 overlaps with the orthographic projection of an ohmic contact region 311 on the substrate 1. In this embodiment, the first via on the passivation layer 4 can expose the ohmic contact region 311 to achieve contact between the source 51, the drain 52, and the barrier layer 3.

[0100] In some embodiments, the material of the passivation layer 4 can be phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y ), aluminum oxide (Al2O3), etc.

[0101] In some embodiments, such as Figure 2 , Figure 10 , Figure 11 or Figure 12 As shown, the orthographic projection of the same first via 41 on the substrate 1 completely coincides with the orthographic projection of an ohmic contact region 311 on the substrate 1. Therefore, in the semiconductor fabrication process, when the ohmic contact region 311 is an ohmic contact opening, the first via 41 and the ohmic contact opening can be formed in the same fabrication process, which simplifies the fabrication process.

[0102] In other embodiments, such as Figure 13 As shown, the outline of the orthographic projection of the same first via 41 onto the substrate 1 lies inside the outline of the orthographic projection of an ohmic contact region 311 onto the substrate 1. Therefore, the ohmic contact region 311 is larger than the area of ​​the first via 41, which can further shorten the distance between the source 51 and the drain 52 and improve electron migration efficiency.

[0103] In some embodiments, such as Figure 10 , Figure 11 or Figure 12 As shown, the semiconductor device also includes a gate 6, and the passivation layer 4 further includes a second via 42, at least a portion of which is located within the second via 42 and in contact with the barrier layer 3.

[0104] In some embodiments, the gate 6 is located between the source 51 and the drain 52.

[0105] In some embodiments, the material of the gate 6 may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and its compounds (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloys (Al-Cu)) or other suitable materials.

[0106] In some embodiments, such as Figure 11 or Figure 12 As shown, the semiconductor device also includes a cap layer 7, which is located between the gate 6 and the barrier layer 3. The cap layer 7 can adjust the work function of the gate 6, improve the controllability of the threshold voltage (Vth), and protect the barrier layer 3.

[0107] In some embodiments, the cap layer 7 may be made of p-type GaN.

[0108] In some embodiments, such as Figure 11 As shown, the cap layer 7 is located inside the second through-hole of the passivation layer 4.

[0109] In some embodiments, such as Figure 12 As shown, the barrier layer 3 has a recessed hole 3a, and the cap layer 7 is located inside the recessed hole 3a. This can reduce the overall thickness of the device.

[0110] Based on the same inventive concept, this application also provides a method for fabricating a semiconductor device, comprising the following steps:

[0111] Step 110: As Figure 14 As shown, a channel layer 2 and a barrier layer thin film 30 are sequentially formed on the substrate 1;

[0112] Step 120: As Figure 15As shown, the surface of the barrier layer film 30 away from the channel layer 2 is patterned to form the barrier layer 3. The barrier layer 3 includes a first surface 31 away from the channel layer 2. The first surface 31 includes an ohmic contact region 311. The ohmic contact region 311 includes at least one first ohmic contact region 311a and at least one second ohmic contact region 311b. The surface of the same ohmic contact region 311 includes a first sub-surface 3111 and a second sub-surface 3112. The second sub-surface 3112 is located on at least one side of the first sub-surface 3111. In adjacent first ohmic contact regions 311a and second ohmic contact regions 311b, the first ohmic contact region 311a... The second sub-surface 3112 of the contact area 311a includes at least a first sub-region located on the side of the first sub-surface 3111 facing the second ohmic contact area 311b, and the first sub-region of the first ohmic contact area 311a is at least partially recessed relative to its first sub-surface 3111; and / or, in adjacent first ohmic contact areas 311a and second ohmic contact areas 311b, the second sub-surface of the second ohmic contact area 311b includes at least a second sub-region located on the side of the first sub-surface facing the first ohmic contact area 311a, and the second sub-region of the second ohmic contact area 311b is at least partially recessed relative to its first sub-surface;

[0113] Step 130: As Figure 16 As shown, a source 51 and a drain 52 are formed on the side of the ohmic contact region 311 of the barrier layer 3 away from the substrate 1. The source 51 is in contact with the first ohmic contact region 311a, and the drain 52 is in contact with the second ohmic contact region 311b.

[0114] In this embodiment, similar to the previous embodiment, the electron migration efficiency of the device can be improved by setting different thicknesses in the middle and edge regions of the ohmic contact region 311.

[0115] Furthermore, in this embodiment, the patterning process performed on the side of the barrier layer film 30 away from the channel layer 2 in step 120 to form the barrier layer 3 can be carried out in a step-by-step patterning process or a partitioned patterning process to form the first sub-surface 3111 and the second sub-surface 3112. For example, the first sub-surface 3111 and the second sub-surface 3112 of different depths can be formed by controlling the proportion of functional gas in the etching gas during the patterning process.

[0116] Specifically, step 120 may include the following steps:

[0117] Step 121: A mask layer is formed on the side of the barrier layer film away from the channel layer. The mask layer has mask openings that expose the ohmic contact region of the barrier layer film. The ohmic contact region includes a first patterned region and a second patterned region.

[0118] Step 122: Use an etching gas with a functional gas ratio of 1 to etch the first patterned area to form a first sub-surface, and use an etching gas with a functional gas ratio of 2 to etch the second ohmic contact opening area to form a second sub-surface, wherein the first ratio is less than the first ratio.

[0119] Step 123: Remove the mask layer.

[0120] It should be noted that the functional gas and etching gas in step 120 can be flexibly designed according to the specific preparation process and equipment, so that the ohmic contact region 311 can form the first sub-surface and the second sub-surface.

[0121] In some embodiments, the method further includes the following after step 130:

[0122] Step 140: As Figure 17 As shown, a passivation layer 4 is formed on the side of the source electrode 51 and the drain electrode 52 away from the barrier layer 3, and the passivation layer 4 is provided with a second via 42.

[0123] Step 150: As Figure 18 As shown, the gate 6 is filled in the second through hole 42.

[0124] Based on the same inventive concept, this application also provides another method for fabricating a semiconductor device, comprising the following steps:

[0125] Step 210: As Figure 19 As shown, a channel layer 2, a barrier layer film 30, and a passivation layer film 40 are sequentially formed on a substrate 1.

[0126] Step 220: As Figure 20 As shown, the passivation layer film 40 and the barrier layer film 30 are patterned to form a passivation layer 4 with a first via and a barrier layer 3 with an ohmic contact region 311. The orthographic projection of the first via 41 on the substrate 1 coincides with the orthographic projection of the ohmic contact region 311 on the substrate 1. The barrier layer 3 includes a first surface 31 facing away from the channel layer 2. The first surface 31 includes at least one ohmic contact region 311. The surface of the same ohmic contact region 311 includes a first sub-surface 3111 and a second sub-surface 3112. The second sub-surface 3112 is disposed around the first sub-surface 3111. In the direction from the channel layer 2 to the barrier layer 3, the position of the second sub-surface 3112 closest to the channel layer 2 is closer to the channel layer 2 than the position of the first sub-surface 3111 farthest from the channel layer 2.

[0127] In this embodiment, after the passivation layer 4 is formed, the first sub-surface 3111 and the second sub-surface 3112 of the first through hole 41 and the ohmic contact area 311 can be formed in the same patterning process step. Therefore, during the patterning process, the total depth of the recessed portion of the first through hole 41 and the ohmic contact area 311 is relatively deep. The deeper etching depth is easier to control than the shallower etching depth, thus reducing the difficulty of the fabrication process.

[0128] In some embodiments, the method further includes the following after step 220:

[0129] Step 230: As Figure 21 As shown, a source 51 and a drain 52 are formed on the side of the ohmic contact region 311 of the barrier layer 3 away from the substrate 1, and at least a portion of the source 51 and the drain 52 are in contact with the barrier layer 3.

[0130] Step 240: As Figure 22 As shown, a second via 42 is formed on the passivation layer 4;

[0131] Step 250: As Figure 23 As shown, the gate 6 is filled in the second through hole 42.

[0132] Based on the same inventive concept, this application also provides a semiconductor device, such as... Figures 24-29 As shown in any of the accompanying figures, the semiconductor device includes a substrate 1, a heterojunction layer 20, at least one source 51, and at least one drain 52. The heterojunction layer 20 includes a channel layer 2 and a barrier layer 3 sequentially stacked on one side of the substrate 1; at least one source 51 and at least one drain 52 are both located on the side of the heterojunction layer 20 away from the substrate 1; the source 51 or drain 52 includes a fourth sub-surface 501 and a fifth sub-surface 502 facing the substrate 1, the fifth sub-surface 502 being located on at least one side of the fourth sub-surface 501; among adjacent source 51 and drain 52, the fifth sub-surface 502 of the source 51 includes at least a third sub-region located on the fourth sub-surface 501 facing the drain 52. Furthermore, the third sub-region of the source electrode 51 protrudes at least partially relative to its fourth sub-surface 501 toward the substrate 1; and / or, in the adjacent source electrode 51 and drain electrode 52, the fifth sub-surface 502 (not shown in the figure) of the drain electrode 52 includes at least a fourth sub-region located on the fourth sub-surface 501 (not shown in the figure) toward the source electrode 51, and the fourth sub-region of the drain electrode 52 protrudes at least partially relative to its fourth sub-surface 501 toward the substrate 1; the average height of the fourth sub-surface 501 relative to the substrate 1 is higher than the average height of the fifth sub-surface 502 relative to the substrate 1.

[0133] In this embodiment, similar to the semiconductor device provided in the previous embodiment, taking the source 51 as an example, in the horizontal direction, the lower point of the edge region of the source 51 closer to the drain 52 is closer to the substrate 1. Therefore, when the device is working, when the carriers flow between the source 51 and the drain 52, since the carriers are transferred from the source 51 to the drain 52 located around it, the edge region of the source 51 closer to the drain 52 requires a higher current density than the middle region. In this embodiment, by setting the fifth sub-surface 502 of the surface of the source 51 close to the substrate 1 closer to the substrate 1, the resistance of the edge region of the source 51 can be reduced, the conduction loss can be reduced, and it is beneficial for the semiconductor device to achieve a higher conduction current between the source 51 and the drain 52, thereby improving the device efficiency.

[0134] It should be noted that the average height of the fourth sub-surface 501 relative to the substrate 1 is higher than the average height of the fifth sub-surface 502 relative to the substrate 1. That is, the overall height of the fifth sub-surface 502 is lower than that of the fourth sub-surface 501. As a result, the overall current transfer efficiency of the edge region of the source 51 near the drain 52 and the edge region of the drain 52 near the source 51 is higher than that of the middle region.

[0135] In some embodiments, the semiconductor device further includes a passivation layer 4 located on the side of the barrier layer 3 away from the channel layer 2. The passivation layer 4 has at least one first via 41, and the orthographic projection of the same first via 41 on the substrate 1 overlaps with the orthographic projection of an ohmic contact region 311 on the substrate 1. In this embodiment, the first via on the passivation layer 4 can expose the ohmic contact region 311 to achieve contact between the source 51, the drain 52, and the barrier layer 3. The beneficial effects are the same as in the previous embodiments, and will not be repeated here.

[0136] In some embodiments, the material of the passivation layer 4 can be phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y ), aluminum oxide (Al2O3), etc.

[0137] In some embodiments, such as Figures 25-28 As shown in any of the accompanying figures, the orthographic projection of the same first via 41 on the substrate 1 completely coincides with the orthographic projection of an ohmic contact region 311 on the substrate 1. Therefore, in the semiconductor fabrication process, when the ohmic contact region 311 is an ohmic contact opening, the first via 41 and the ohmic contact opening can be formed in the same fabrication process, which simplifies the fabrication process.

[0138] In some embodiments, such as Figures 24-29 As shown in any of the figures, the surface of the heterojunction layer 20 away from the substrate 1 includes an ohmic contact region 201. The ohmic contact region 201 includes at least one first ohmic contact region 201a and at least one second ohmic contact region 201b. One first ohmic contact region 201a contacts a source electrode 51, and one second ohmic contact region 201b contacts a drain electrode 52. The surface of the same ohmic contact region 201 includes a first ohmic contact sub-surface 2011 and a second ohmic contact sub-surface 2012. The second ohmic contact sub-surface 2012 is located on at least one side of the first ohmic contact sub-surface 2011. The first ohmic contact sub-surface 2011 contacts a fourth sub-surface 501, and the second ohmic contact sub-surface 2012 contacts a fifth sub-surface 502. With this configuration, an ohmic contact region 201 corresponding to the source 51 / drain 52 can be formed on the surface of the heterojunction layer 20 away from the substrate 1. The shape of the ohmic contact region 201 is interlocked with the shape of the source 51 / drain 52 to improve current efficiency.

[0139] In some embodiments, such as Figure 24 , Figure 25 or Figure 26 As shown, the first ohmic contact sub-surface 2011 includes at least a portion of the side surface of the barrier layer 3 away from the substrate 1. Thus, an electrical connection can be formed by contacting the surface of the barrier layer 3 and the fourth sub-surface 501 by providing an ohmic contact region 201 on the side of the barrier layer 3 away from the substrate 1.

[0140] At this time, since the height of the second ohmic contact surface 2012 is lower than that of the first ohmic contact surface 2011, in some embodiments, such as Figure 24 As shown, the second ohmic contact surface 2012 includes at least a portion of the surface of the barrier layer 3 away from the substrate 1. In other embodiments, such as Figure 25 As shown, the second ohmic contact surface 2012 includes at least a portion of the surface of the channel layer 2 away from the substrate 1. Since the channel layer 2 is located on the side of the barrier layer 3 closer to the substrate 1, a third via 303 can be formed on the barrier layer 3, exposing a portion of the channel layer 2 in contact with the edge regions of the source 51 / drain 52. This arrangement brings the edge region of the source 51 closer to its adjacent drain 52, or the edge region of the drain 52 closer to its adjacent source 51, which also improves current transport efficiency. In some other embodiments, such as... Figure 26 As shown, the second ohmic contact surface 2012 includes at least a portion of the barrier layer 3 on the side surface away from the substrate 1 and at least a portion of the channel layer 2 on the side surface away from the substrate 1.

[0141] In some embodiments, such as Figure 27As shown, the first ohmic contact surface 2011 includes at least a portion of the side surface of the channel layer 2 away from the substrate 1, and the second ohmic contact surface 2012 includes at least a portion of the side surface of the channel layer 2 away from the substrate 1. This configuration brings the middle and edge regions of the source 51 closer to its adjacent drain 52, which also helps improve current transmission efficiency.

[0142] In some embodiments, such as Figure 28 or Figure 29 As shown, the heterojunction layer 20 includes an ohmic contact region 201 on the side of the substrate 1 away from the substrate 1. The ohmic contact region 201 includes at least one first ohmic contact region 201a and at least one second ohmic contact region 201b. The first ohmic contact region 201a contacts a source electrode 51, and the second ohmic contact region 201b contacts a drain electrode 52. The surface of the same ohmic contact region 201 includes a third ohmic contact sub-surface 2013. The semiconductor device also includes a passivation layer 4, which is located on the side of the barrier layer 3 away from the channel layer 2. The passivation layer 4 includes an insulating portion 43 and a first via 41 located on at least one side of the insulating portion 43. The first via 41 exposes the third ohmic contact sub-surface 2013. The side of the insulating portion 43 away from the substrate 1 contacts a fourth sub-surface 501, and the third ohmic contact sub-surface 2013 contacts a fifth sub-surface 502. In this embodiment, the middle region of the source 51 / drain 52 is in contact with the passivation layer 4. At this time, the edge region of the source 51 / drain 52 serves as a channel for carrier transmission to achieve current transmission.

[0143] In some embodiments, such as Figure 28 As shown, the third ohmic contact sub-surface 2013 includes at least a portion of the surface of the barrier layer 3 away from the substrate 1. In this case, only the first via 41 on the passivation layer 4 needs to expose at least a portion of the surface of the barrier layer 3 away from the substrate 1 to contact the fifth sub-surface 502. In other embodiments, such as... Figure 29 As shown, the third ohmic contact surface 2013 includes at least a portion of the surface of the channel layer 2 away from the substrate 1. In this case, a third via 303 needs to be provided on the barrier layer 3, exposing a portion of the channel layer 2 in contact with the edge region of the source 51 / drain 52. The source 51 / drain 52 passes through the barrier layer 3 to contact the channel layer 2. In some other embodiments, the third ohmic contact surface 2013 includes at least a portion of the surface of the barrier layer 3 away from the substrate 1 and at least a portion of the surface of the channel layer 2 away from the substrate 1.

[0144] In some embodiments, in the direction from the channel layer 2 to the barrier layer 3, the height of the insulating portion 43 is less than the height of the passivation layer 4 excluding the first via 41 and the insulating portion 43. This arrangement is beneficial to the film continuity of the source / drain 52 itself, preventing the insulating portion 43 from disconnecting the source / drain 52 from its own structure. At the same time, at least a portion of the source / drain 52 can cover the side of the insulating portion 43 away from the substrate 1, reducing the impact of the thickness of the source / drain 52 on the overall thickness of the semiconductor device.

[0145] In some embodiments, such as Figure 26 As shown, the semiconductor device also includes a gate 6, which is located between the source 51 and the drain 52. The portion of the fifth sub-surface 502 closer to the gate 6 is closer to the substrate 1 than the portion of the fifth sub-surface 502 further away from the gate 6. In this embodiment, the distance between the portions of the fifth sub-surface 502 located on opposite sides of the fourth sub-surface 501 and the substrate 1 can be different, and can be flexibly designed.

[0146] In some embodiments, at least a portion of the fourth sub-surface 501 is a smooth curved surface; and / or, at least a portion of the fifth sub-surface 502 is a smooth curved surface. This can minimize the formation of sharp corner regions on the fourth sub-surface 501 / fifth sub-surface 502, which can lead to tip effects, causing localized current density concentrations that can result in device failure.

[0147] In some embodiments, the fourth sub-surface 501 and the fifth sub-surface 502 are smoothly connected. This improves the continuity between the fourth sub-surface 501 and the fifth sub-surface 502, reduces contact resistance, and lowers the risk of device burn-through.

[0148] In some embodiments, the fifth sub-surface 502 is disposed around the fourth sub-surface 501. Similarly to the aforementioned embodiments, the fifth sub-surface 502 may be located in at least a portion of the periphery of the fourth sub-surface 501. In one example, the orthographic projection of the fourth sub-surface 501 onto the substrate 1 is rectangular, including four sequentially connected sides. The fifth sub-surface 502 may be located outside at least one side of the fourth sub-surface 501. For example, if the fifth sub-surface 502 is located outside one of the sides, the orthographic projection of the fifth sub-surface 502 onto the substrate 1 may be strip-shaped. The fifth sub-surface 502 may also be located outside opposite two sides, in which case the orthographic projection of the fifth sub-surface 502 onto the substrate 1 may be two spaced-apart stripes. The fifth sub-surface 502 may also be located outside adjacent two sides, in which case the orthographic projection of the fifth sub-surface 502 onto the substrate 1 may be L-shaped. The fifth sub-surface 502 may also be located outside three sequentially connected sides, in which case the orthographic projection of the fifth sub-surface 502 onto the substrate 1 may be U-shaped. The fifth sub-surface 502 can also be located outside the four sides and connected to form a ring. In this case, the orthogonal projection of the fifth sub-surface 502 onto the substrate 1 will be a square ring.

[0149] In some embodiments, such as Figure 24 As shown, the semiconductor device also includes a gate 6, and an ohmic electrode 5 including at least one of a source 51 and a drain 52. The gate 6 is located between the source 51 and the drain 52. In a direction parallel to the surface of the barrier layer 3 away from the channel layer 2, the ratio of the width k1 of the ohmic electrode 5 to the width k2 of the gate 6 is between 10 and 200.

[0150] In some embodiments, the width k1 of the ohmic electrode 5 ranges from 5µm to 100µm in the direction parallel to the side surface of the barrier layer 3 away from the channel layer 2.

[0151] In some embodiments, the width k2 of the gate 6 ranges from 0.1µm to 2µm in the direction parallel to the side surface of the barrier layer 3 away from the channel layer 2.

[0152] In this embodiment Figures 24-29 Other features of the structure shown are similar to Figures 1-23 The same parts in the structure shown have the same characteristics, which will not be repeated here.

[0153] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0154] The terms “center,” “upper,” “lower,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0155] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0156] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0157] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer away from the substrate. The barrier layer includes a first surface facing away from the channel layer. The first surface includes an ohmic contact region, which includes at least one first ohmic contact region and at least one second ohmic contact region. The surface of the same ohmic contact region includes a first sub-surface and a second sub-surface, with the second sub-surface located on at least one side of the first sub-surface. In adjacent first and second ohmic contact regions, the second sub-surface of the first ohmic contact region includes at least a first sub-region located on the side of the first sub-surface facing the second ohmic contact region, and the first sub-region of the first ohmic contact region is at least partially recessed relative to its first sub-surface. And / or, in adjacent first and second ohmic contact regions, the second sub-surface of the second ohmic contact region includes at least a second sub-region located on the side of the first sub-surface facing the first ohmic contact region, and the second sub-region of the second ohmic contact region is at least partially recessed relative to its first sub-surface. The average height of the first sub-surface is higher than the average height of the second sub-surface. At least one source electrode, each of the source electrodes being in contact with a first ohmic contact region; At least one drain electrode, each of which is in contact with a second ohmic contact region.

2. The semiconductor device according to claim 1, characterized in that, At least a portion of the first sub-surface is a smooth curved surface; And / or, at least a portion of the second sub-surface is a smooth curved surface.

3. The semiconductor device according to claim 1 or 2, characterized in that, The first sub-surface and the second sub-surface are smoothly connected.

4. The semiconductor device according to claim 1, characterized in that, The first surface further includes a third sub-surface, the third sub-surface comprising the portion of the first surface excluding the ohmic contact region, wherein, The position on the first sub-surface that is furthest from the channel layer is farther from the channel layer than the third sub-surface; And / or, the location where the second sub-surface is closest to the channel layer is closer to the channel layer than the third sub-surface.

5. The semiconductor device according to claim 1, characterized in that, The barrier layer further includes a second surface opposite to the first surface, and the ratio between the maximum distance between the first sub-surface and the second surface and the minimum distance between the second sub-surface and the second surface in the direction of the channel layer pointing to the barrier layer is in the range of 1 to 2.

6. The semiconductor device according to claim 1, characterized in that, The barrier layer further includes a second surface opposite to the first surface, the first sub-surface protruding away from the second surface, and the second sub-surface recessed toward the second surface; in a direction parallel to the side surface of the barrier layer away from the channel layer, the ratio between the width of the first sub-surface and the width of the second sub-surface ranges from 0.5 to 1.

5.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a gate, an ohmic electrode including at least one of a source and a drain, the gate being located between the source and the drain, and the ratio of the width of the ohmic electrode to the width of the gate being between 10 and 200 in a direction parallel to the side surface of the barrier layer away from the channel layer.

8. The semiconductor device according to claim 7, characterized in that, The width of the ohmic contact region ranges from 5µm to 100µm in a direction parallel to the side surface of the barrier layer away from the channel layer.

9. The semiconductor device according to claim 7, characterized in that, The width of the gate ranges from 0.1µm to 2µm in the direction parallel to the side surface of the barrier layer away from the channel layer.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor device is a GaN radio frequency device.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a passivation layer located on the side of the barrier layer away from the channel layer. The passivation layer has at least one first via, and the orthographic projection of the same first via on the substrate overlaps with the orthographic projection of an ohmic contact region on the substrate.

12. A semiconductor device, characterized in that, include: Substrate; The heterojunction layer includes a channel layer and a barrier layer sequentially stacked on one side of the substrate; At least one source and at least one drain are located on the side of the heterojunction layer away from the substrate; the source or the drain includes a fourth sub-surface and a fifth sub-surface facing the substrate, the fifth sub-surface being located on at least one side of the fourth sub-surface; in adjacent source and drain electrodes, the fifth sub-surface of the source electrode includes at least a third sub-region located on the fourth sub-surface facing the drain electrode, and the third sub-region of the source electrode protrudes at least partially relative to its fourth sub-surface toward the substrate; and / or, in adjacent source and drain electrodes, the fifth sub-surface of the drain electrode includes at least a fourth sub-region located on the fourth sub-surface facing the source electrode, and the fourth sub-region of the drain electrode protrudes at least partially relative to its fourth sub-surface toward the substrate; the average height of the fourth sub-surface relative to the substrate is higher than the average height of the fifth sub-surface relative to the substrate.

13. The semiconductor device according to claim 12, characterized in that, The heterojunction layer includes an ohmic contact region on the side of its surface away from the substrate. The ohmic contact region includes at least one first ohmic contact region and at least one second ohmic contact region. One first ohmic contact region contacts one of the source electrodes, and one second ohmic contact region contacts one of the drain electrodes. The surface of the same ohmic contact region includes a first ohmic contact sub-surface and a second ohmic contact sub-surface. The second ohmic contact sub-surface is located on at least one side of the first ohmic contact sub-surface. The first ohmic contact sub-surface contacts the fourth sub-surface, and the second ohmic contact sub-surface contacts the fifth sub-surface.

14. The semiconductor device according to claim 13, characterized in that, The first ohmic contact surface includes at least a portion of the surface of the barrier layer on the side away from the substrate, wherein, The second ohmic contact surface includes at least a portion of the barrier layer's surface away from the substrate; and / or, the second ohmic contact surface includes at least a portion of the channel layer's surface away from the substrate.

15. The semiconductor device according to claim 13, characterized in that, The first ohmic contact surface includes at least a portion of the side surface of the channel layer away from the substrate, and the second ohmic contact surface includes at least a portion of the side surface of the channel layer away from the substrate.

16. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes a passivation layer located on the side of the barrier layer away from the channel layer. The passivation layer has at least one first via, and the orthographic projection of the same first via on the substrate overlaps with the orthographic projection of an ohmic contact region on the substrate.

17. The semiconductor device according to claim 12, characterized in that, The heterojunction layer includes an ohmic contact region on its surface away from the substrate. The ohmic contact region includes at least one first ohmic contact region and at least one second ohmic contact region. One first ohmic contact region contacts one of the source electrodes, and one second ohmic contact region contacts one of the drain electrodes. The surface of the same ohmic contact region includes a third ohmic contact sub-surface. The semiconductor device further includes a passivation layer located on the side of the barrier layer away from the channel layer. The passivation layer includes an insulating portion and a first via located on at least one side of the insulating portion. The first via exposes the third ohmic contact sub-surface. The surface of the insulating portion away from the substrate contacts the fourth sub-surface, and the third ohmic contact sub-surface contacts the fifth sub-surface.

18. The semiconductor device according to claim 17, characterized in that, The third ohmic contact surface includes at least a portion of the side surface of the barrier layer away from the substrate; And / or, the third ohmic contact surface includes at least a portion of the side surface of the channel layer away from the substrate.

19. The semiconductor device according to claim 17, characterized in that, In the direction from the channel layer to the barrier layer, the height of the insulating portion is less than the height of the passivation layer excluding the first via and the insulating portion.

20. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes a gate located between the source and the drain, wherein a portion of the fifth sub-surface closer to the gate is closer to the substrate than a portion of the fifth sub-surface farther from the gate.

21. The semiconductor device according to claim 12, characterized in that, At least a portion of the fourth sub-surface is a smooth curved surface; And / or, at least a portion of the fifth sub-surface is a smooth curved surface.

22. The semiconductor device according to claim 12, characterized in that, The fourth sub-surface and the fifth sub-surface are smoothly connected.

23. The semiconductor device according to claim 12, characterized in that, The fifth sub-surface is disposed around the fourth sub-surface.

24. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes a gate, an ohmic electrode including at least one of a source and a drain, the gate being located between the source and the drain, and the ratio of the width of the ohmic electrode to the width of the gate being between 10 and 200 in a direction parallel to the side surface of the barrier layer away from the channel layer.

25. The semiconductor device according to claim 24, characterized in that, The width of the ohmic electrode ranges from 5µm to 100µm in the direction parallel to the side surface of the barrier layer away from the channel layer.

26. The semiconductor device according to claim 24, characterized in that, The width of the gate ranges from 0.1µm to 2µm in the direction parallel to the side surface of the barrier layer away from the channel layer.

27. The semiconductor device according to claim 1, characterized in that, The semiconductor device is a GaN radio frequency device.

28. A method for fabricating a semiconductor device, characterized in that, include: A channel layer and a barrier layer thin film are sequentially formed on the substrate; The barrier layer film is patterned on the side of the barrier layer film away from the channel layer to form a barrier layer. The barrier layer includes a first surface away from the channel layer. The first surface includes an ohmic contact region, which includes at least one first ohmic contact region and at least one second ohmic contact region. The surface of the same ohmic contact region includes a first sub-surface and a second sub-surface, with the second sub-surface located on at least one side of the first sub-surface. In adjacent first and second ohmic contact regions, the second sub-surface of the first ohmic contact region includes at least a first sub-region located on the side of the first sub-surface facing the second ohmic contact region, and the first sub-region of the first ohmic contact region is at least partially recessed relative to its first sub-surface. And / or, in adjacent first and second ohmic contact regions, the second sub-surface of the second ohmic contact region includes at least a second sub-region located on the side of the first sub-surface facing the first ohmic contact region, and the second sub-region of the second ohmic contact region is at least partially recessed relative to its first sub-surface. A source and a drain are formed on the side of the barrier layer away from the channel layer, with the source in contact with the first ohmic contact region and the drain in contact with the second ohmic contact region.

29. The method for fabricating a semiconductor device according to claim 28, characterized in that, The patterning process for the surface of the barrier layer film away from the channel layer includes: A mask layer is formed on the side of the barrier layer film away from the channel layer. The mask layer has mask openings that expose the ohmic contact region of the barrier layer film. The ohmic contact region includes a first patterned region and a second patterned region. The first patterned area is etched with an etching gas having a functional gas ratio of a first proportion to form the first sub-surface, and the second ohmic contact opening area is etched with an etching gas having a functional gas ratio of a second proportion to form the second sub-surface, wherein the first proportion is less than the first proportion. Remove the mask layer.

30. The method for fabricating a semiconductor device according to claim 28, characterized in that, The method for fabricating the semiconductor device further includes: A passivation layer film is formed, and the passivation layer film is patterned to form a first through hole; The step of patterning the passivation layer film and the step of patterning the surface of the passivation layer film away from the channel layer to form a barrier layer are performed by the same patterning process.

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