3D stacked optoelectronic co-packaging structure and its packaging method

Abstract

This invention provides a three-dimensional stacked optoelectronic co-packaging structure and its packaging method. The three-dimensional stacked structure is formed by C2W bonding of optical chips to an adapter wafer, allowing each optical chip to be processed separately before being bonded to the adapter wafer, reducing packaging process complexity and improving packaging reliability. Furthermore, the pads in the pad areas of each optical chip layer are connected to some conductive vias in the electrical interconnect area. The upper optical coupling area is recessed relative to the lower optical coupling area, exposing the first optical coupler in the lower optical coupling area. Thus, along the thickness stacking direction of the optoelectronic adapter structure, the area of ​​the optical chips increases sequentially from bottom to top, forming an inverted pyramid shape. The electrical interconnect structure is distributed on the outer edge of the optical chips, effectively avoiding the fabrication of conductive pillar structures on the optical chips, reducing process complexity. Simultaneously, the optical interconnect structure is also distributed on the outer edge of the optical chips, allowing direct coupling of light from the optical chips to the optoelectronic transmission layer, avoiding excessive efficiency losses caused by too many optical coupling operations.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic packaging technology, and in particular to a three-dimensional stacked optoelectronic co-packaging structure and its packaging method. Background Technology

[0002] With the continuous development of technologies such as communication, high-speed computing, and AI supercomputing, the requirements for chip performance in terms of ultra-low signal loss factor, ultra-high density, ultra-high speed, ultra-low latency, and ultra-multiple interconnects are constantly increasing, making 3D packaging a current focus of industry development. However, electrical interconnects, due to their inherent drawbacks such as small transmission bandwidth, low spatial density, high power consumption, and susceptibility to crosstalk, have gradually reached a bottleneck in development. Compared to the shortcomings of electrical signal transmission, optical interconnects have advantages such as large transmission bandwidth, high spatial density, low power consumption, and less susceptibility to crosstalk, making them a good alternative to electrical interconnects. Therefore, the adoption of optical interconnects to replace electrical interconnects has spurred the development of co-packaged optics (CPO). Simply put, co-packaged optical CPO involves continuously moving the optical module closer to the switching chip, shortening the trace distance between the chip and the module, gradually replacing pluggable optical modules, and ultimately packaging the optical engine and the electrical switching chip into a single chip.

[0003] To further improve chip packaging density and enhance chip performance, 3D packaging is also evolving towards optoelectronic co-packaging. This requires designing more novel structures to increase the integration density of 3D optoelectronic co-packaging structures and ensure low signal loss and high-quality transmission. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a three-dimensional stacked optoelectronic co-packaging structure and its packaging method, so as to solve the problems of low integration density, high signal loss and low signal transmission quality of the three-dimensional optoelectronic co-packaging structure in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a packaging method for a three-dimensional stacked optoelectronic co-packaging structure, the packaging method comprising the following steps:

[0006] S1, providing an adapter wafer; wherein, the adapter wafer includes an optical coupling region and an electrical interconnect region, the electrical interconnect region is located on both outer sides of the optical coupling region in the non-extending direction, and conductive pillars are formed in the electrical interconnect region, the conductive pillars extending inward from the surface of the adapter wafer;

[0007] S2, at least one optoelectronic transition structure is formed on the wafer of the adapter board on the side of the exposed conductive pillar; wherein, each optoelectronic transition structure includes an optoelectronic transmission layer and an optical chip bonded to the optoelectronic transmission layer, and each optoelectronic transmission layer includes an upper optical coupling region correspondingly disposed above the lower optical coupling region and an upper electrical interconnect region correspondingly disposed above the lower electrical interconnect region, each electrical interconnect region having a conductive via penetrating the optoelectronic transmission layer, and the conductive via contacting and connecting with the lower conductive pillar or the lower conductive via, each optical coupling region having two optical waveguides arranged at intervals opposite to each other, each optical waveguide having a first optical coupler for optical signal exchange at one end of its waveguide layer, and the upper optical coupling region being recessed relative to the lower optical coupling region. The first optical coupler in the lower optical coupling region is exposed; each optical chip layer includes a photonic device region and pad regions disposed on both outer sides of the photonic device region. The photonic device region is provided with photonic devices, and each of the two ends of the photonic device has a second optical coupler for optical signal exchange. The pad regions are disposed above a portion of the electrical interconnect region and are provided with pads to provide coupling electrical signals or direct electrical connection electrical signals to the photonic devices. During the bonding process, the photonic devices are bonded above the optical waveguides that are arranged in pairs and spaced apart. The second optical couplers at both ends of the photonic devices at least partially overlap with the horizontal projections of the two first optical couplers of the two spaced optical waveguides. The pads are in contact with the corresponding conductive vias.

[0008] S3, an electrical lead-out structure is formed on the conductive pillar.

[0009] Optionally, the fabrication method of each layer of the optoelectronic transition structure in step S2 includes:

[0010] S20, the photoelectric transmission layer is formed on the obtained structure; wherein, the photoelectric transmission layer includes an optical coupling region and an electrical interconnection region, a conductive via is formed in the electrical interconnection region to penetrate the photoelectric transmission layer, and the conductive via is in contact with the conductive pillar or the conductive via in the lower layer, and optical waveguides are formed in the optical coupling region at intervals, and one end of the waveguide layer of each optical waveguide has a first optical coupler for optical signal exchange;

[0011] S21, a plurality of optical chips are provided; wherein, the optical chip includes the photonic device region and the pad region disposed on both sides of the photonic device region, the photonic device is disposed in the photonic device region, and both ends of the photonic device have a second optical coupler for optical signal exchange, the pad region is disposed above a portion of the electrical interconnect region and is provided with the pad to provide coupled electrical signals or direct electrical connection signals to the photonic device;

[0012] S22, all the optical chips are bonded to the photoelectric transmission layer; during the bonding process, the photonic devices are bonded above the optical waveguides that are arranged in pairs and spaced apart, and the second optical couplers at both ends of the photonic devices at least partially overlap with the horizontal projections of the two first optical couplers of the two spaced optical waveguides, and the pads are in contact with the corresponding conductive vias.

[0013] Furthermore, in step S21, a support layer is provided on the back side of the optical chip; after step S22, a step of peeling off the support layer is also included.

[0014] Optionally, in step S20, the conductive via is connected to the lower conductive pillar or the lower conductive via through a pad, the height of which does not exceed the surface of the photoelectric transmission layer; in step S22, the optical chip and the photoelectric transmission layer are bonded using a hybrid bonding method.

[0015] Optionally, the electrical lead-out structure in step S3 includes a metal pad in contact with the conductive post and a solder ball in contact with the metal pad.

[0016] Optionally, after step S3, the method further includes dicing the obtained structure according to preset requirements to form the three-dimensional stacked optoelectronic co-packaging structure.

[0017] Optionally, the adapter wafer is a silicon adapter wafer.

[0018] Optionally, in step S1, the conductive post extends inward from the surface of the adapter plate wafer but does not penetrate the adapter plate wafer; in step S3, the adapter plate wafer is first thinned to expose the conductive post, and then the electrical lead-out structure is formed on the conductive post.

[0019] The present invention also provides a three-dimensional stacked optoelectronic co-packaging structure, the optoelectronic co-packaging structure comprising: an adapter board chip and at least one optoelectronic adapter structure; wherein,

[0020] The adapter board chip includes an optical coupling region and an electrical interconnection region. The electrical interconnection region is located on both outer sides of the optical coupling region in the non-extending direction. A conductive post is disposed in the electrical interconnection region, and the conductive post penetrates the adapter board chip.

[0021] All the optoelectronic conversion structures are stacked on one side of the adapter board chip, and an electrical lead-out structure is provided on the conductive pillar on the other side.

[0022] Each optoelectronic switching structure includes an optoelectronic transmission layer and an optical chip bonded to the optoelectronic transmission layer. Each optoelectronic transmission layer includes an upper optical coupling region correspondingly disposed above the lower optical coupling region and an upper electrical interconnect region correspondingly disposed above the lower electrical interconnect region. Each electrical interconnect region has a conductive via penetrating the optoelectronic transmission layer, and the conductive via is in contact with the lower conductive pillar or the lower conductive via. Each optical coupling region has two optical waveguides arranged at intervals opposite to each other. One end of the waveguide layer of each optical waveguide has a first optical coupler for optical signal exchange. The upper optical coupling region is recessed relative to the lower optical coupling region to expose the first optical coupler in the lower optical coupling region. Couplers; each layer of the optical chip includes a photonic device region and pad regions disposed on both outer sides of the photonic device region. The photonic device region is provided with photonic devices, and each of the photonic devices has a second optical coupler at both ends for optical signal exchange. The pad regions are disposed above a portion of the electrical interconnect region and are provided with pads to provide coupled electrical signals or direct electrical connection signals to the photonic devices. The photonic devices are bonded above the optical waveguides that are arranged in pairs and spaced apart. The second optical couplers at both ends of the photonic devices at least partially overlap with the horizontal projections of the two first optical couplers of the two spaced-apart optical waveguides. The pads are in contact with the corresponding conductive vias.

[0023] Optionally, the conductive via is connected to the lower conductive pillar or the lower conductive via through a pad, the height of which does not exceed the surface of the photoelectric transmission layer.

[0024] Optionally, the electrical lead-out structure includes a metal pad in contact with the conductive post and solder balls in contact with the metal pad.

[0025] Optionally, the optical waveguide includes the waveguide layer and a cladding layer covering the waveguide layer.

[0026] As described above, the three-dimensional stacked optoelectronic co-packaging structure and packaging method of the present invention form a three-dimensional stacked structure by C2W bonding of optical chips and interposer wafers. This allows each optical chip to be processed separately and then bonded to the interposer wafer, reducing packaging process complexity and improving packaging reliability. In addition, the pads of each optical chip pad area are connected to some conductive vias of the electrical interconnect area, and the upper optical coupling area is set to be recessed relative to the lower optical coupling area to expose the first optical coupler in the lower optical coupling area. Thus, along the thickness stacking direction of the optoelectronic interposer structure, the area of ​​the optical chips increases sequentially from bottom to top, forming an inverted pyramid shape. The electrical interconnect structure is distributed on the outer edge of the optical chip, which can effectively avoid the fabrication of conductive pillar structures on the optical chip and avoid the electrical interconnect structure passing through the optical crystal film of the ridge waveguide, reducing process complexity. At the same time, the optical interconnect structure is also distributed on the outer edge of the optical chip, which can directly couple the light in the optical chip to the optoelectronic transmission layer, avoiding excessive efficiency loss caused by too many optical coupling times. Attached Figure Description

[0027] Figure 1 and Figure 2 The diagram shows a cross-sectional view of the adapter wafer in the packaging method of the three-dimensional stacked optoelectronic co-packaging structure of the present invention.

[0028] Figures 3 to 9 The diagram shows a cross-sectional view of each step in the packaging method of the three-dimensional stacked optoelectronic co-packaging structure of the present invention, which involves forming the first optoelectronic transition structure on the transition plate wafer.

[0029] Figures 10 to 15 The diagram shows a cross-sectional view of each step in the packaging method of the three-dimensional stacked optoelectronic co-packaging structure of the present invention, which involves forming a second optoelectronic transition structure on the transition plate wafer.

[0030] Figures 16 to 21 The diagram shows a cross-sectional view of each step in the packaging method for the three-dimensional stacked optoelectronic co-packaging structure of the present invention, which involves forming a third-layer optoelectronic transition structure on the transition plate wafer.

[0031] Figure 22 and Figure 23 The diagram shows a cross-sectional view of the thinned adapter wafer, exposing the conductive pillars, in the packaging method of the three-dimensional stacked optoelectronic co-packaging structure of the present invention.

[0032] Figure 24 and Figure 25 The diagram shows a cross-sectional view of the electrical lead-out structure formed on the conductive pillars in the packaging method of the three-dimensional stacked optoelectronic co-packaging structure of the present invention.

[0033] Figures 26 to 28This diagram shows a cross-sectional view of the independently stacked optoelectronic co-packaging structure formed by dicing in the packaging method of the three-dimensional stacked optoelectronic co-packaging structure of the present invention.

[0034] Component designation explanation

[0035] 10 Adapter wafer 100 Optical coupling region 101 Electrical interconnection area 102 Conductive pillar 103 Adapter chip 11 Optoelectronic adapter structure 12 Photoelectric transport layer 120 Optical coupling region of optoelectronic transport layer 121 Optoelectronic transport layer electrical interconnect region 122 Conductive via 123 waveguide layer 124 Cladding 125 First optical coupler 13 optical chip 130 Photonic device region 131 solder pad area 132 Photonic devices 133 Second optical coupler 134 solder pads 135 support layer 15 Electrical lead-out structure 150 Metal pads 151 welding balls 16 Dielectric layer Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0038] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0039] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0040] Please see Figures 1 to 28 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0041] Example 1

[0042] This embodiment provides a packaging method for a three-dimensional stacked optoelectronic co-packaging structure, the packaging method comprising the following steps:

[0043] S1, providing an adapter wafer; wherein, the adapter wafer includes an optical coupling region and an electrical interconnect region, the electrical interconnect region is located on both outer sides of the optical coupling region in the non-extending direction, and conductive pillars are formed in the electrical interconnect region, the conductive pillars extending inward from the surface of the adapter wafer;

[0044] S2, at least one optoelectronic transition structure is formed on the wafer of the adapter board on the side of the exposed conductive pillar; wherein, each optoelectronic transition structure includes an optoelectronic transmission layer and an optical chip bonded to the optoelectronic transmission layer, and each optoelectronic transmission layer includes an upper optical coupling region correspondingly disposed above the lower optical coupling region and an upper electrical interconnect region correspondingly disposed above the lower electrical interconnect region, each electrical interconnect region having a conductive via penetrating the optoelectronic transmission layer, and the conductive via contacting and connecting with the lower conductive pillar or the lower conductive via, each optical coupling region having two optical waveguides arranged at intervals opposite to each other, each optical waveguide having a first optical coupler for optical signal exchange at one end of its waveguide layer, and the upper optical coupling region being recessed relative to the lower optical coupling region. The first optical coupler in the lower optical coupling region is exposed; each optical chip layer includes a photonic device region and pad regions disposed on both outer sides of the photonic device region. The photonic device region is provided with photonic devices, and each of the two ends of the photonic device has a second optical coupler for optical signal exchange. The pad regions are disposed above a portion of the electrical interconnect region and are provided with pads to provide coupling electrical signals or direct electrical connection electrical signals to the photonic devices. During the bonding process, the photonic devices are bonded above the optical waveguides that are arranged in pairs and spaced apart. The second optical couplers at both ends of the photonic devices at least partially overlap with the horizontal projections of the two first optical couplers of the two spaced optical waveguides. The pads are in contact with the corresponding conductive vias.

[0045] S3, an electrical lead-out structure is formed on the conductive pillar.

[0046] Different optical crystals have different process requirements. The packaging method of the three-dimensional stacked optoelectronic co-packaging structure in this embodiment forms a three-dimensional stacked structure by C2W bonding of optical chips and interposer wafers. This allows each optical chip to be processed separately and then bonded to the interposer wafer, reducing the complexity of the packaging process and improving the reliability of the packaging. In addition, the pads of each optical chip pad area are connected to some conductive vias of the electrical interconnect area. The upper optical coupling area is set to be recessed relative to the lower optical coupling area to expose the first optical coupler in the lower optical coupling area. Thus, along the thickness stacking direction of the optoelectronic interposer structure, the area of ​​the optical chips increases from bottom to top, forming an inverted pyramid shape. The electrical interconnect structure is distributed on the outer edge of the optical chip, which can effectively avoid the fabrication of conductive pillar structures on the optical chip and avoid the electrical interconnect structure passing through the optical crystal film of the ridge waveguide, reducing the process complexity. At the same time, the optical interconnect structure is also distributed on the outer edge of the optical chip, which can directly couple the light in the optical chip to the optoelectronic transmission layer, avoiding excessive efficiency loss caused by too many optical coupling times.

[0047] The packaging method of the three-dimensional stacked optoelectronic co-packaging structure of this embodiment will be described in detail below with reference to the specific accompanying drawings. In practice, the number of layers of the optoelectronic transition structure package on the transition board wafer is set according to actual needs, and can be one, two, three or more layers, wherein the stacking method of each layer is the same. Here, a three-layer optoelectronic transition structure packaged on the transition board wafer is used as an example for explanation.

[0048] like Figure 1 and Figure 2 As shown, step S1 is performed first, providing an adapter wafer 10; wherein, the adapter wafer 10 includes an optical coupling region 100 (e.g., Figure 1 (as shown) and electrical interconnection area 101 (as shown) Figure 2 As shown), the electrical interconnect region 101 is located on both outer sides of the optical coupling region 100 in the non-extending direction. A conductive pillar 102 is formed in the electrical interconnect region 101, and the conductive pillar 102 extends inward from the surface of the adapter wafer 10.

[0049] The electrical interconnect region 101 is located on both outer sides of the optical coupling region 100 in the non-extending direction, so as to Figure 1 and Figure 2 The following explanation uses the three-dimensional rectangular coordinate system XYZ as an example. Figure 2 It is along Figure 1 Cross-sectional view at point AA. Figure 1 The optical coupling region 100 described herein extends along the X-axis direction on the horizontal plane XOY. The electrical interconnection region 101 is not located on both sides of the X-axis direction of the optical coupling region 100, but is located in the Y-axis direction, which is not X-axis, relative to both sides of the X-axis.

[0050] It should be noted that the dimensions of the optical coupling region 100 on the adapter wafer 10, as well as the dimensions, number, and distribution of the conductive pillars 102 in the electrical interconnect region 101, can be set according to actual needs, and no excessive restrictions are imposed here. Furthermore, all YOZ plane figures are drawn along... Figure 1 A cross-sectional view at point AA in the XOZ plane.

[0051] The adapter board wafer 10 is located at the bottom layer of the entire packaging structure. It is used to improve mechanical strength support, ensure the stability and reliability of the entire packaging structure, and can subsequently enable electrical connection between the entire packaging structure and other components or devices through the adapter board wafer 10.

[0052] As an example, the adapter wafer 10 may be selected as a silicon adapter wafer, but it is not limited to this. Other suitable semiconductor materials or insulating materials may also be used, such as semiconductor materials such as germanium and silicon carbide, or insulating materials such as glass.

[0053] like Figure 20 and Figure 21 As shown, then step S2 is performed to form a three-layer optoelectronic transfer structure 11 on the adapter wafer 10 with the conductive pillar 102 exposed on one side;

[0054] Among them, such as Figure 3 and Figure 4 , Figure 10 and Figure 11 , Figure 16 and Figure 17 As shown, each of the optoelectronic transition structures 11 includes an optoelectronic transmission layer 12 and an optical chip 13 (e.g., [missing information]) bonded to the optoelectronic transmission layer 12. Figure 8 and Figure 9 , Figure 14 and Figure 15 , Figure 20 and Figure 21 As shown), each of the optoelectronic transmission layers 12 includes an upper optoelectronic transmission layer optical coupling region 120 correspondingly disposed above the lower optoelectronic transmission layer optical coupling region 120 and an upper optoelectronic transmission layer electrical interconnection region 121 correspondingly disposed above the lower optoelectronic transmission layer electrical interconnection region 121.

[0055] Each of the photoelectric transmission layer electrical interconnection regions 121 has a conductive via 122 that penetrates the photoelectric transmission layer 12, and the conductive via 122 is connected to the conductive pillar 102 of the lower layer (here referring to...). Figure 4 The conductive via 122 in the first optoelectronic transmission layer 12 is in contact with the conductive pillar 102 in the lower transition plate wafer 10 or the conductive via 122 in the lower layer.

[0056] Each of the optoelectronic transmission layer optical coupling regions 120 has two optical waveguides arranged at intervals. One end of each waveguide layer 123 has a first optical coupler 125 for optical signal exchange. The upper optoelectronic transmission layer optical coupling region 120 is recessed relative to the lower optoelectronic transmission layer optical coupling region 120 to expose the first optical coupler 125 in the lower optoelectronic transmission layer optical coupling region 120 (e.g., ...). Figure 10 and Figure 16 As shown), it can be seen that the photoelectric transmission layer optical coupling region 120 of each photoelectric transmission layer 12 is smaller than that of the previous photoelectric transmission layer 12, and decreases towards the outside. This means that the size of the optical chip 13 in the direction of the photoelectric transmission layer optical coupling region 120 of the later layer will be larger than that of the optical chip 13 in the direction of the photoelectric transmission layer optical coupling region 120 of the previous layer.

[0057] like Figure 7 As shown, each layer of the optical chip 13 includes a photonic device region 130 and pad regions 131 disposed on both outer sides of the photonic device region 130. A photonic device 132 is disposed in the photonic device region 130, and each end of the photonic device 132 has a second optical coupler 133 for optical signal exchange (e.g., ...). Figure 5 As shown), Figure 6 As shown, the pad area 131 is disposed above a portion of the electrical interconnect area 121 of the optoelectronic transmission layer and is provided with pads 134 to provide coupled electrical signals or direct electrical connection signals to the photonic device 132;

[0058] During the bonding process, such as Figure 5 As shown, the photonic device 132 is bonded above the optical waveguides that are arranged in pairs and spaced apart, and the second optical couplers 133 at both ends of the photonic device 132 at least partially overlap with the horizontal projections of the two first optical couplers 125 of the two spaced optical waveguides, and the pad 134 is in contact with the corresponding conductive via 122.

[0059] As an example, the type of the photonic device 132 can be set according to actual needs, such as a laser, photodetector, transducer, modulator, etc. For example, when the photonic device 132 is a waveguide modulator, the photonic device 132 includes a waveguide layer and a cladding layer outside the waveguide layer.

[0060] As an example, the first optical coupler 125 and the second optical coupler 133 mainly carry out optical information exchange. The optical information exchange process involves the transmission of optical information between optical couplers. Therefore, the first optical coupler 125 and the second optical coupler 133 can be selected from any structure suitable for the transmission of optical information between optical couplers, such as grating couplers, evanescent wave couplers, etc. The specific types of the first optical coupler 125 and the second optical coupler 133 are not excessively restricted here, but preferably, the first optical coupler 125 and the second optical coupler 133 on the same optical transmission path are selected from the same type of optical coupler, such as both being grating couplers or both being evanescent wave couplers, etc.

[0061] As a specific example, the fabrication method of each layer of the optoelectronic transition structure 11 includes steps S20 to S22:

[0062] like Figure 3 and Figure 4 , Figure 10 and Figure 11 , Figure 16 and Figure 17 As shown, where Figure 3 and Figure 4 This is the first optoelectronic transmission layer 12. Figure 10 and Figure 11 This is the second photoelectric transmission layer 12. Figure 16 and Figure 17 In step S20, the third photoelectric transmission layer 12 is formed on the obtained structure. The photoelectric transmission layer 12 includes a photoelectric transmission layer optical coupling region 120 and a photoelectric transmission layer electrical interconnection region 121. A conductive via 122 is formed in the photoelectric transmission layer electrical interconnection region 121, penetrating the photoelectric transmission layer 12. The conductive via 122 is connected to the lower conductive pillar 102 (here referring to...). Figure 4 The conductive vias 122 in the first optoelectronic transmission layer 12 are in contact with the conductive pillars 102 in the lower layer interfacing wafer 10 or the lower layer conductive vias 122. Optical waveguides are formed in the optical coupling region 120 of the optoelectronic transmission layer, spaced apart from each other. Each optical waveguide has a first optical coupler 125 at one end of its waveguide layer 123 for optical signal exchange. Each optical waveguide includes not only the waveguide layer 123 but also a cladding layer 124 covering the waveguide layer 123.

[0063] like Figures 5 to 7As shown, in step S21, a plurality of optical chips 13 are provided; wherein, the optical chip 13 includes the photonic device region 130 and the pad region 131 disposed on both outer sides of the photonic device region 130, the photonic device region 130 is provided with the photonic device 132, and both ends of the photonic device 132 have a second optical coupler 133 for optical signal exchange, the pad region 131 is disposed above a portion of the optoelectronic transmission layer electrical interconnect region 121 and is provided with pads 134 to provide coupled electrical signals or direct electrical connection signals to the photonic device 132. Therefore, each layer of optical chip 13 occupies a portion of the optoelectronic transmission layer electrical interconnect region 121 of its layer, reducing the area of ​​the optoelectronic transmission layer electrical interconnect region 121 of the subsequent layer, which means that the size of the subsequent layer of optical chip 13 in the direction of the optoelectronic transmission layer electrical interconnect region 121 will be larger than the size of the preceding layer of optical chip 13 in the direction of the optoelectronic transmission layer electrical interconnect region 121.

[0064] like Figure 8 and Figure 9 , Figure 14 and Figure 15 , Figure 20 and Figure 21 As shown, where, Figure 8 and Figure 9 For the first layer of optical chips, Figure 14 and Figure 15 For the second layer of optical chip, Figure 20 and Figure 21 For the third layer of optical chips, in step S22, all the optical chips 13 are bonded to the photoelectric transmission layer 12. During the bonding process, the photonic devices 132 are bonded above the optical waveguides that are arranged in pairs and spaced apart. The second optical couplers 133 at both ends of the photonic devices 132 at least partially overlap with the horizontal projections of the two first optical couplers 125 of the two spaced optical waveguides. The pads 134 are in contact with the corresponding conductive vias 122.

[0065] like Figure 5 and Figure 6 , Figure 12 and Figure 13 , Figure 18 and Figure 19 As shown, in the actual fabrication process of the optical chip 13, a support layer 135 is required to support the optical chip 13. Therefore, preferably, as shown... Figure 8 and Figure 9 , Figure 14 and Figure 15 , Figure 20 and Figure 21As shown, after the optical chip 13 with the support layer 135 is bonded to the corresponding optoelectronic transmission layer 12, the support layer 135 can be peeled off. By peeling off the support layer 135 after each bonding, leaving only the device layer, ultra-thin three-dimensional stacking of optoelectronic devices can be achieved, allowing more optical chips to be stacked in the vertical direction, which helps to further improve packaging density.

[0066] The support layer 135 primarily serves a load-bearing and supporting function. Any suitable insulating support material can be selected, generally a non-conductive metallic semiconductor material or an insulating material, such as silicon, germanium, silicon carbide, or glass. The support layer 135 is removed using conventional peeling methods in the art, depending on the specific material selected.

[0067] As an example, in this embodiment, the optical chip 13 and the photoelectric transmission layer 12 are bonded using a hybrid bonding method. Therefore, the pads 134 on the optical chip 13 are flush with the surface of the optical chip, and correspondingly, the pads 134 on the conductive vias 122 are flush with the surface of the photoelectric transmission layer 12, thereby achieving hybrid bonding between the two. In addition, the two conductive vias 122 or the conductive vias 122 and the conductive pillars 102 are connected by pads 134. The height of the pads 134 does not exceed the surface of the photoelectric transmission layer 12, so as to improve the contact quality, reduce the alignment accuracy requirements, and reduce the process complexity.

[0068] Finally, proceed to step S3, such as... Figure 24 and Figure 25 As shown, an electrical lead-out structure 15 is formed on the conductive post 102.

[0069] As an example, such as Figure 2 As shown, when the conductive pillar 102 in the adapter wafer 10 provided in step S1 extends inward from the surface of the adapter wafer 10 but does not penetrate the adapter wafer 10, when the electrical lead-out structure 15 is formed in step S3, as... Figure 22 and Figure 23 As shown, the adapter wafer 10 needs to be thinned first to expose the conductive pillars 102, and then the electrical lead-out structure 15 is formed on the conductive pillars 102. The adapter wafer 10 can be thinned by a combination of coarse grinding and fine grinding. During the thinning process, a dielectric layer 16 can be formed on the surface of the adapter wafer 10 for protection.

[0070] As an example, the electrical lead-out structure 15 includes a metal pad 150 in contact with the conductive post 102 and a solder ball 151 in contact with the metal pad 150.

[0071] like Figure 27 and Figure 28As shown, after step S3, the obtained structure is further divided according to preset requirements to form a three-dimensional stacked optoelectronic co-packaging structure with independent packaged chip structure. At this time, the adapter board wafer 10 is cut into independent adapter board chips 103.

[0072] Example 2

[0073] This embodiment provides a three-dimensional stacked optoelectronic co-packaging structure, which can be obtained by the packaging method of Embodiment 1. The beneficial effects it can achieve can be found in the description of Embodiment 1, and will not be repeated below.

[0074] like Figures 26 to 28 As shown, the optoelectronic co-packaging structure includes: an adapter board chip 103 and at least one optoelectronic adapter structure 11; wherein,

[0075] The adapter chip 103 includes an optical coupling region 100 (e.g., ... Figure 1 (as shown) and electrical interconnection area 101 (as shown) Figure 2 As shown), the electrical interconnection region 101 is located on both outer sides of the optical coupling region 100 in the non-extending direction. A conductive post 102 is provided in the electrical interconnection region 101, and the conductive post 102 penetrates the adapter chip 103.

[0076] All the optoelectronic conversion structures 11 are stacked on one side of the adapter board chip 103, and an electrical lead-out structure 15 is provided on the conductive post 102 on the other side.

[0077] like Figure 3 and Figure 4 , Figure 10 and Figure 11 , Figure 16 and Figure 17 As shown, each of the optoelectronic transition structures 11 includes an optoelectronic transmission layer 12 and an optical chip 13 (e.g., [missing information]) bonded to the optoelectronic transmission layer 12. Figure 8 and Figure 9 , Figure 14 and Figure 15 , Figure 20 and Figure 21 As shown), each of the optoelectronic transmission layers 12 includes an upper optoelectronic transmission layer optical coupling region 120 correspondingly disposed above the lower optoelectronic transmission layer optical coupling region 120 and an upper optoelectronic transmission layer electrical interconnection region 121 correspondingly disposed above the lower optoelectronic transmission layer electrical interconnection region 121.

[0078] Each of the photoelectric transmission layer electrical interconnection regions 121 is provided with a conductive via 122 that penetrates the photoelectric transmission layer 12, and the conductive via 122 is connected to the conductive post 102 of the lower layer (here referring to...). Figure 4The conductive via 122 in the first optoelectronic transmission layer 12 is in contact with the conductive pillar 102 in the lower transition plate wafer 10 or the conductive via 122 in the lower layer.

[0079] Each of the optoelectronic transmission layer optical coupling regions 120 is provided with two optical waveguides arranged opposite to each other. One end of the waveguide layer 123 of each optical waveguide has a first optical coupler 125 for optical signal exchange. The upper optoelectronic transmission layer optical coupling region 120 is recessed relative to the lower optoelectronic transmission layer optical coupling region 120 to expose the first optical coupler 125 in the lower optoelectronic transmission layer optical coupling region 120 (e.g., Figure 10 and Figure 16 As shown), it can be seen that the photoelectric transmission layer optical coupling region 120 of each photoelectric transmission layer 12 is smaller than that of the previous photoelectric transmission layer 12, and decreases towards the outside. This means that the size of the optical chip 13 in the direction of the photoelectric transmission layer optical coupling region 120 of the later layer will be larger than that of the optical chip 13 in the direction of the photoelectric transmission layer optical coupling region 120 of the previous layer.

[0080] like Figure 7 As shown, each layer of the optical chip 13 includes a photonic device region 130 and pad regions 131 disposed on both outer sides of the photonic device region 130. A photonic device 132 is disposed in the photonic device region 130, and each end of the photonic device 132 has a second optical coupler 133 for optical signal exchange (e.g., ...). Figure 5 As shown), Figure 6 As shown, the pad area 131 is disposed above a portion of the optoelectronic transmission layer electrical interconnect area 121 and is provided with pads 134 to provide coupled electrical signals or direct electrical connection signals to the photonic device 132; thus, it can be seen that each layer of optical chip 13 occupies a portion of the optoelectronic transmission layer electrical interconnect area 121 of its own layer, thereby reducing the area of ​​the optoelectronic transmission layer electrical interconnect area 121 of the subsequent layer, which means that the size of the subsequent layer of optical chip 13 in the direction of optoelectronic transmission layer electrical interconnect area 121 will be larger than the size of the previous layer of optical chip 13 in the direction of optoelectronic transmission layer electrical interconnect area 121;

[0081] like Figure 5 As shown, the photonic device 132 is bonded above the optical waveguides that are arranged in pairs and spaced apart, and the second optical couplers 133 at both ends of the photonic device 132 at least partially overlap with the horizontal projections of the two first optical couplers 125 of the two spaced optical waveguides, and the pad 134 is in contact with the corresponding conductive via 122.

[0082] In the optoelectronic co-packaging structure of this embodiment, the optoelectronic coupling region 120 of each optoelectronic transmission layer 12 is smaller than that of the previous optoelectronic transmission layer 12, and decreases outward. This means that the size of the subsequent optical chip 13 in the direction of the optoelectronic coupling region 120 is larger than that of the previous optical chip 13 in the direction of the optoelectronic coupling region 120. At the same time, each optical chip 13 occupies part of the optoelectronic transmission layer electrical interconnection region 121 of its own layer, reducing the area of ​​the optoelectronic transmission layer electrical interconnection region 121 of the subsequent layer. This means that the size of the subsequent optical chip 13 in the direction of the optoelectronic transmission layer electrical interconnection region 121 is larger than that of the previous optical chip 13 in the direction of the optoelectronic transmission layer electrical interconnection region 121. Thus, the entire optoelectronic co-packaging structure presents an inverted pyramid shape in both the XOZ and YOZ cross sections, that is, the area of ​​the optical chip 13 increases sequentially along the stacking direction.

[0083] The adapter board chip 103 is located at the bottom layer of the entire packaging structure. It is used to improve mechanical strength support, ensure the stability and reliability of the entire packaging structure, and realize the electrical connection between the entire packaging structure and other components or devices through the adapter board chip 103.

[0084] As an example, the adapter chip 103 may be selected as a silicon adapter wafer, but it is not limited to this. Other suitable semiconductor materials or insulating materials may also be used, such as semiconductor materials such as germanium and silicon carbide, or insulating materials such as glass.

[0085] As an example, the type of the photonic device 132 can be set according to actual needs, such as a laser, photodetector, transducer, modulator, etc. For example, when the photonic device 132 is a waveguide modulator, the photonic device 132 includes a waveguide layer and a cladding layer outside the waveguide layer.

[0086] As an example, the first optical coupler 125 and the second optical coupler 133 mainly carry out optical information exchange. The optical information exchange process involves the transmission of optical information between optical couplers. Therefore, the first optical coupler 125 and the second optical coupler 133 can be selected from any structure suitable for the transmission of optical information between optical couplers, such as grating couplers, evanescent wave couplers, etc. The specific types of the first optical coupler 125 and the second optical coupler 133 are not excessively restricted here, but preferably, the first optical coupler 125 and the second optical coupler 133 on the same optical transmission path are selected from the same type of optical coupler, such as both being grating couplers or both being evanescent wave couplers, etc.

[0087] As an example, the optical chip 13 and the photoelectric transmission layer 12 are bonded using a hybrid bonding method. Therefore, the pads 134 on the optical chip 13 are flush with the surface of the optical chip, and correspondingly, the pads 134 on the conductive vias 122 are flush with the surface of the photoelectric transmission layer 12, thus achieving hybrid bonding between the two. Furthermore, the two conductive vias 122 are connected to each other or to the conductive post 102 via pads 134, the height of which does not exceed the surface of the photoelectric transmission layer 12.

[0088] As an example, the electrical lead-out structure 15 includes a metal pad 150 in contact with the conductive post 102 and a solder ball 151 in contact with the metal pad 150.

[0089] As an example, the optical waveguide in the optoelectronic transmission layer 12 includes the waveguide layer 123 and the cladding layer 124 covering the waveguide layer 123. The materials of the waveguide layer 123 and the cladding layer 124 are not overly restricted, as long as they meet the specific optical waveguide transmission requirements.

[0090] In summary, this invention provides a three-dimensional stacked optoelectronic co-packaging structure and its packaging method. By forming a three-dimensional stacked structure through C2W bonding of optical chips and an adapter wafer, each optical chip can be processed separately before being bonded to the adapter wafer, reducing packaging process complexity and improving packaging reliability. Furthermore, the pads in the bonding pad area of ​​each optical chip layer are connected to some conductive vias in the electrical interconnect area. The upper optical coupling area is recessed relative to the lower optical coupling area, exposing the first optical coupler in the lower optical coupling area. Thus, along the thickness stacking direction of the optoelectronic adapter structure, the area of ​​the optical chips increases sequentially from bottom to top, forming an inverted pyramid shape. The electrical interconnect structure is distributed on the outer edge of the optical chips, effectively avoiding the fabrication of conductive pillar structures on the optical chips and preventing the electrical interconnect structure from passing through the optical crystal film of the ridge waveguide, reducing process complexity. Simultaneously, the optical interconnect structure is also distributed on the outer edge of the optical chips, allowing direct coupling of light from the optical chips to the optoelectronic transmission layer, avoiding excessive efficiency losses caused by excessive optical coupling. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A packaging method for a three-dimensional stacked optoelectronic co-packaging structure, characterized in that, The packaging method includes the following steps: S1, providing an adapter wafer; wherein, the adapter wafer includes an optical coupling region and an electrical interconnect region, the electrical interconnect region is located on both outer sides of the optical coupling region in the non-extending direction, and conductive pillars are formed in the electrical interconnect region, the conductive pillars extending inward from the surface of the adapter wafer; S2, at least one optoelectronic transition structure is formed on the wafer of the adapter board on the side of the exposed conductive pillar; wherein, each optoelectronic transition structure includes an optoelectronic transmission layer and an optical chip bonded to the optoelectronic transmission layer, and each optoelectronic transmission layer includes an upper optical coupling region correspondingly disposed above the lower optical coupling region and an upper electrical interconnect region correspondingly disposed above the lower electrical interconnect region, each electrical interconnect region having a conductive via penetrating the optoelectronic transmission layer, and the conductive via contacting and connecting with the lower conductive pillar or the lower conductive via, each optical coupling region having two optical waveguides arranged at intervals opposite to each other, each optical waveguide having a first optical coupler for optical signal exchange at one end of its waveguide layer, and the upper optical coupling region being recessed relative to the lower optical coupling region. The first optical coupler in the lower optical coupling region is exposed; each optical chip layer includes a photonic device region and pad regions disposed on both outer sides of the photonic device region. The photonic device region is provided with photonic devices, and each of the two ends of the photonic device has a second optical coupler for optical signal exchange. The pad regions are disposed above a portion of the electrical interconnect region and are provided with pads to provide coupling electrical signals or direct electrical connection electrical signals to the photonic devices. During the bonding process, the photonic devices are bonded above the optical waveguides that are arranged in pairs and spaced apart. The second optical couplers at both ends of the photonic devices at least partially overlap with the horizontal projections of the two first optical couplers of the two spaced optical waveguides. The pads are in contact with the corresponding conductive vias. S3, an electrical lead-out structure is formed on the conductive pillar.

2. The packaging method for the three-dimensional stacked optoelectronic co-packaging structure according to claim 1, characterized in that, The fabrication method of each layer of the optoelectronic transition structure in step S2 includes: S20, the photoelectric transmission layer is formed on the obtained structure; wherein, the photoelectric transmission layer includes an optical coupling region and an electrical interconnection region, a conductive via is formed in the electrical interconnection region to penetrate the photoelectric transmission layer, and the conductive via is in contact with the conductive pillar or the conductive via in the lower layer, and optical waveguides are formed in the optical coupling region at intervals, and one end of the waveguide layer of each optical waveguide has a first optical coupler for optical signal exchange; S21, a plurality of optical chips are provided; wherein, the optical chip includes the photonic device region and the pad region disposed on both sides of the photonic device region, the photonic device is disposed in the photonic device region, and both ends of the photonic device have a second optical coupler for optical signal exchange, the pad region is disposed above a portion of the electrical interconnect region and is provided with the pad to provide coupled electrical signals or direct electrical connection signals to the photonic device; S22, all the optical chips are bonded to the photoelectric transmission layer; during the bonding process, the photonic devices are bonded above the optical waveguides that are arranged in pairs and spaced apart, and the second optical couplers at both ends of the photonic devices at least partially overlap with the horizontal projections of the two first optical couplers of the two spaced optical waveguides, and the pads are in contact with the corresponding conductive vias.

3. The packaging method for the three-dimensional stacked optoelectronic co-packaging structure according to claim 2, characterized in that: In step S21, a support layer is provided on the back of the optical chip; after step S22, the step of peeling off the support layer is also included.

4. The packaging method for the three-dimensional stacked optoelectronic co-packaging structure according to claim 2, characterized in that: In step S20, the conductive via is connected to the conductive pillar or the conductive via in the lower layer through a pad, and the height of the pad does not exceed the surface of the photoelectric transmission layer; in step S22, the optical chip and the photoelectric transmission layer are bonded using a hybrid bonding method.

5. The packaging method for the three-dimensional stacked optoelectronic co-packaging structure according to claim 1, characterized in that: The electrical lead-out structure in step S3 includes a metal pad in contact with the conductive post and a solder ball in contact with the metal pad.

6. The packaging method for the three-dimensional stacked optoelectronic co-packaging structure according to claim 1, characterized in that: Step S3 is followed by a step of dicing the obtained structure according to preset requirements to form the three-dimensional stacked optoelectronic co-packaging structure.

7. The packaging method for the three-dimensional stacked optoelectronic co-packaging structure according to claim 1, characterized in that: The adapter wafer is a silicon adapter wafer.

8. The packaging method for the three-dimensional stacked optoelectronic co-packaging structure according to claim 1, characterized in that: In step S1, the conductive pillar extends inward from the surface of the adapter plate wafer but does not penetrate the adapter plate wafer; in step S3, the adapter plate wafer is first thinned to expose the conductive pillar, and then the electrical lead-out structure is formed on the conductive pillar.

9. A three-dimensional stacked optoelectronic co-packaging structure, characterized in that, The optoelectronic co-packaging structure includes: an adapter board chip and at least one optoelectronic adapter structure; wherein... The adapter board chip includes an optical coupling region and an electrical interconnection region. The electrical interconnection region is located on both outer sides of the optical coupling region in the non-extending direction. A conductive post is disposed in the electrical interconnection region, and the conductive post penetrates the adapter board chip. All the optoelectronic conversion structures are stacked on one side of the adapter board chip, and an electrical lead-out structure is provided on the conductive pillar on the other side. Each optoelectronic switching structure includes an optoelectronic transmission layer and an optical chip bonded to the optoelectronic transmission layer. Each optoelectronic transmission layer includes an upper optical coupling region correspondingly disposed above the lower optical coupling region and an upper electrical interconnect region correspondingly disposed above the lower electrical interconnect region. Each electrical interconnect region has a conductive via penetrating the optoelectronic transmission layer, and the conductive via is in contact with the lower conductive pillar or the lower conductive via. Each optical coupling region has two optical waveguides arranged at intervals opposite to each other. One end of the waveguide layer of each optical waveguide has a first optical coupler for optical signal exchange. The upper optical coupling region is recessed relative to the lower optical coupling region to expose the first optical coupler in the lower optical coupling region. Couplers; each layer of the optical chip includes a photonic device region and pad regions disposed on both outer sides of the photonic device region. The photonic device region is provided with photonic devices, and each of the photonic devices has a second optical coupler at both ends for optical signal exchange. The pad regions are disposed above a portion of the electrical interconnect region and are provided with pads to provide coupled electrical signals or direct electrical connection signals to the photonic devices. The photonic devices are bonded above the optical waveguides that are arranged in pairs and spaced apart. The second optical couplers at both ends of the photonic devices at least partially overlap with the horizontal projections of the two first optical couplers of the two spaced-apart optical waveguides. The pads are in contact with the corresponding conductive vias.

10. The three-dimensional stacked optoelectronic co-packaging structure according to claim 9, characterized in that: The conductive via is connected to the conductive pillar or the conductive via in the lower layer via a pad, the height of which does not exceed the surface of the photoelectric transmission layer.

11. The three-dimensional stacked optoelectronic co-packaging structure according to claim 9, characterized in that: The electrical lead-out structure includes a metal pad in contact with the conductive post and solder balls in contact with the metal pad.

12. The three-dimensional stacked optoelectronic co-packaging structure according to claim 9, characterized in that: The optical waveguide includes the waveguide layer and a cladding layer covering the waveguide layer.

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