Simulation methods, devices, software products, and terminals for optical proximity effect correction based on chemical mechanical polishing.

Abstract

This application provides a simulation method, apparatus, program product, and terminal for optical proximity effect correction based on chemical mechanical polishing (CMP). Using CMP process simulation tools, a three-dimensional contour height map of the wafer surface is obtained. An enhanced lithography model is constructed to perceive morphological changes on the wafer surface. Based on the ability of the enhanced lithography model to perceive morphological changes, an optical proximity correction model is used to correct for optical proximity effects and verify lithography simulation. This invention fundamentally solves the systematic errors inherent in traditional OPC models due to neglecting CMP morphology, significantly improving the accuracy of lithography simulation predictions. Furthermore, through multiple design-process collaborative optimization loops during the lithography simulation verification stage, manufacturing defects caused by complex process interactions can be proactively identified and eliminated before wafer fabrication, fundamentally reducing development risks and costs.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a simulation method, apparatus, program product, and terminal for optical proximity effect correction based on chemical mechanical polishing. Background Technology

[0002] In integrated circuit manufacturing, optical proximity correction (OPC) and chemical mechanical polishing (CMP) are two key processes that ensure the accuracy of chip patterns and structural integrity. OPC compensates for the inverse distortion of the mask pattern in advance to offset the imaging errors caused by diffraction and interference during photolithography, thereby ensuring high fidelity of the lithographic pattern. Meanwhile, CMP, as a process that can achieve global planarization of the wafer, does not achieve an absolutely uniform polishing effect. Due to the differences in pattern density and layout in different areas of the wafer surface, specific three-dimensional morphological defects will be formed after polishing, namely, unevenness phenomena such as "dishing" and "erosion".

[0003] Traditional Optical Proximity Correction (OPC) techniques and the lithography models they rely on are typically based on the ideal assumption of an absolutely flat wafer surface. However, the three-dimensional morphologies introduced by Chemical Mechanical Polishing (CMP), such as "disc-shaped depressions" and "etching," overturn this premise. This unevenness caused by CMP results in a difference between the actual focal plane of different regions on the wafer surface and the nominal focal plane of the lithography machine during photolithography exposure. In advanced process nodes with extremely limited depth of focus (DOF), this local defocusing effect can lead to severe non-uniformity in pattern linewidth, causing the OPC correction results based on the assumed ideal plane to fail in actual manufacturing, ultimately affecting chip performance and yield. Therefore, there is an urgent need for a novel OPC correction method that can break through the limitations of traditional models and actively incorporate CMP process effects into modeling and compensation. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a simulation method, device, program product and terminal for optical proximity effect correction based on chemical mechanical polishing, which solves the technical problem that the existing optical proximity effect correction and compensation technology does not consider the three-dimensional morphology changes introduced by the chemical mechanical polishing process, resulting in linewidth deviations in the corrected pattern, which ultimately affects chip performance and yield.

[0005] To achieve the above and other related objectives, this application provides a simulation method for optical proximity effect correction based on chemical mechanical polishing (CMP). The method comprises: obtaining a three-dimensional contour height map of a first wafer surface based on a target design layout using a CMP process simulation tool; wherein the first wafer surface is the surface formed after the previous photolithography layer undergoes a CMP process; integrating the three-dimensional contour height map of the first wafer surface into a photolithography simulation model to construct an enhanced photolithography model; the enhanced photolithography model is used to output topographic sensing data of the first wafer surface; based on the enhanced photolithography model, performing optical proximity effect correction calculations on the current photolithography layer pattern using an optical proximity correction model to generate corrected mask data for the current photolithography layer; and photolithographically etching the mask data of the current photolithography layer onto the first wafer surface for photolithography simulation verification; wherein the mask data of the current photolithography layer, after photolithography on the first wafer surface and undergoing a CMP process, forms a second wafer surface.

[0006] In some embodiments of the first aspect of this application, the process of obtaining a three-dimensional contour height map of the first wafer surface based on a target design layout using a chemical mechanical polishing (CMP) process simulation tool includes: performing hydrodynamic calculation simulation and mechanical wear simulation based on the geometric features of the target design layout and CMP process parameters to obtain a three-dimensional contour height map of the first wafer surface; wherein, the three-dimensional contour height map includes: the set of heights of all points on the first wafer surface from a reference plane.

[0007] In some embodiments of the first aspect of this application, the process of integrating a three-dimensional contour height map of the first wafer surface into a lithography simulation model to construct an enhanced lithography model includes: obtaining an effective focal plane at any point on the first wafer surface, the effective focal plane being obtained based on the three-dimensional contour height map.

[0008] In some embodiments of the first aspect of this application, the effective focal plane at any point on the surface of the first wafer is characterized as: ;in, The effective focal plane represents any point on the surface of the first wafer; H(x, y) represents the standard focal plane; H(x, y) represents the height of any point on the surface of the first wafer from the reference plane; (x, y) represents the coordinates of any point on the surface of the first wafer in the preset coordinate system.

[0009] In some embodiments of the first aspect of this application, the method further includes: setting the reference plane to coincide with the standard focal plane to photolithographically etch the mask data of the current photolithography layer onto the surface of the first wafer.

[0010] In some embodiments of the first aspect of this application, the method further performs a process angle simulation verification step, which includes: adjusting the defocus amount and exposure dose of the process angle within a preset fluctuation range, and using the optical proximity correction model to perform photolithography simulation on the mask data of any photolithography layer, and verifying the key dimensions and edge placement errors of the simulated photolithography layer pattern to determine whether it meets the preset standards.

[0011] In some embodiments of the first aspect of this application, the process of verifying the critical dimensions and edge placement errors of the simulated photolithographic layer pattern to determine whether it meets the preset standard includes: for mask data whose critical dimensions and edge placement errors do not meet the preset standard, adjusting its optical proximity correction operation parameters and reusing the optical proximity correction model to perform photolithographic simulation verification until it meets the preset standard.

[0012] To achieve the above and other related objectives, a second aspect of this application provides an optical proximity effect correction simulation device based on chemical mechanical polishing (CMP), comprising: a three-dimensional contour height prediction module, used to obtain a three-dimensional contour height map of a first wafer surface based on a target design layout using a CMP process simulation tool; wherein the first wafer surface is the surface formed after the previous photolithography layer has undergone a CMP process; an enhanced photolithography module, used to integrate the three-dimensional contour height map of the first wafer surface into a photolithography simulation model to construct an enhanced photolithography model; the enhanced photolithography model is used to output topographic sensing data of the first wafer surface; and an OPC correction and photolithography simulation module, used to perform optical proximity effect correction calculations on the current photolithography layer pattern using an optical proximity correction model based on the enhanced photolithography model to generate corrected mask data of the current photolithography layer; and photolithographically imprint the mask data of the current photolithography layer onto the first wafer surface for photolithography simulation verification; wherein the mask data of the current photolithography layer, after being photolithographically imprinted on the first wafer surface and subjected to a CMP process, forms a second wafer surface.

[0013] To achieve the above and other related objectives, a third aspect of the present invention provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to implement the optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception.

[0014] To achieve the above and other related objectives, a fourth aspect of the present invention provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception.

[0015] As described above, the optical proximity effect correction simulation method, apparatus, program product, and terminal based on chemical mechanical polishing (CMP) of this application have the following beneficial effects: This invention obtains a three-dimensional contour height map of the wafer surface using a CMP process simulation tool, and perceives morphological changes on the wafer surface by constructing an enhanced lithography model. Based on the ability of the enhanced lithography model to perceive morphological changes, optical proximity effect correction and lithography simulation verification are performed using an optical proximity correction model. This invention fundamentally solves the systematic error inherent in traditional OPC models due to neglecting CMP morphology, significantly improving the accuracy of lithography simulation prediction. Furthermore, through multiple design-process collaborative optimization loops during the lithography simulation verification stage, manufacturing defects caused by complex process interaction effects can be proactively identified and eliminated before wafer fabrication, fundamentally reducing development risks and costs. Attached Figure Description

[0016] Figure 1 The diagram shown is a flowchart illustrating a simulation method for optical proximity effect correction based on chemical mechanical polishing according to an embodiment of the present invention.

[0017] Figure 2 The diagram shows a process flow diagram for performing process corner simulation verification on the mask data of the current photolithography layer in one embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram illustrating the process corner simulation verification of the mask data of the front photolithography layer in one embodiment of the present invention.

[0019] Figure 4 The diagram shown is a schematic representation of an optical proximity effect correction device based on chemical mechanical polishing morphology perception in one embodiment of the present invention.

[0020] Figure 5 The diagram shown is an electronic terminal according to an embodiment of the present invention. Detailed Implementation

[0021] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0022] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the present invention. It should be understood that other embodiments may also be used. In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect, without limiting their order. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., are not necessarily different.

[0023] Furthermore, in the embodiments of the present invention, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] Furthermore, in this embodiment of the invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0025] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0026] <1> Optical Proximity Correction (OPC): OPC aims to compensate for various non-ideal effects during the imaging process, such as diffraction, interference, and scattering, by pre-correcting the pattern on the mask, thereby ensuring that the final pattern formed on the wafer surface accurately matches the design requirements.

[0027] <2> Chemical Mechanical Polishing (CMP): In integrated circuit manufacturing, CMP refers to the synergistic effect of chemical etching and mechanical polishing to perform global planarization on the thin film dielectric (such as insulating layer) or metal interconnect layer (such as tungsten, copper, etc.) on the wafer surface, so as to eliminate surface undulations, achieve surface flatness, and lay the foundation for subsequent photolithography and thin film deposition processes.

[0028] <3> Mask Layer: In integrated circuit manufacturing, a mask layer refers to a set of planar geometric patterns on a wafer that define a specific function or structure through one or more associated photolithography and patterning processes. It is a two-dimensional planar mapping of the chip's three-dimensional structure and serves as a bridge connecting the circuit design layout and the physical chip.

[0029] <4> Wafer Surface: In integrated circuit manufacturing, the wafer surface is a dynamically evolving functional interface. Initially, it refers to the plane after planarization of the shallow trench isolation structure; later, it refers to the top-level globally planarized interface after a series of processes such as thin film deposition, photolithography patterning, etching, and chemical mechanical polishing (CMP). It is the physical basis for the construction of all microstructures and the reference plane for each subsequent process.

[0030] <5> Lithography Simulation: Lithography simulation refers to the technology of using lithography simulation software to simulate and predict the entire lithography process by establishing a precise mathematical model. It recreates the entire chain of physical processes—from the light source, mask data, projection lens to the chemical reaction of the photoresist—in a virtual environment, pre-calculating the final pattern contour formed on the wafer surface. The precise mathematical model driving the lithography simulation software to perform calculations and predictions is called the lithography simulation model; it is the core algorithm engine and parameter set of the entire lithography simulation process.

[0031] <6> The best focal plane, in integrated circuit manufacturing, specifically refers to the optimal imaging plane designed for the projection optical system of a lithography machine. On this plane, projected light rays converge to form a light intensity distribution with the smallest size, highest contrast, and closest approximation to the mask design. It serves as the reference plane for focusing operations in the lithography process, and its position is precisely set by the lithography machine's optical system.

[0032] <7> Depth of Focus: Depth of focus refers to the maximum amount of defocus that can be maintained within an acceptable preset standard range for image quality (such as key dimensions and edge placement) near the standard focal plane.

[0033] <8> Amount of Defocus: Amount of defocus refers to the actual position of the wafer surface during exposure, relative to the standard focal plane.

[0034] <9> Defocus: Defocus refers to a state in which the actual position of the wafer surface deviates from the standard focal plane during photolithography exposure.

[0035] <10> Exposure Dose: Exposure dose refers to the total light energy received by a unit area of ​​photoresist during photolithography. It is equal to the product of light intensity and exposure time. It is the most critical control parameter in photolithography besides the standard focal plane, directly determining the extent of chemical reactions within the photoresist and the final pattern size.

[0036] <11> Critical Dimension (CD): CD refers to the width or length of a specific structure in the semiconductor manufacturing process, especially those tiny dimensions that directly affect device performance. CD is a core indicator for evaluating the accuracy and consistency of manufacturing processes.

[0037] <12> Edge Placement Error (EPE): EPE measures the degree of deviation of the edge of a pattern from its position in a photolithography process. EPE is crucial for ensuring proper electrical connections between components in complex integrated circuits.

[0038] This invention provides a simulation method, apparatus, program product, and terminal for optical proximity effect correction based on chemical mechanical polishing (CMP). It obtains a three-dimensional contour height map of the wafer surface using a CMP process simulation tool, and perceives morphological changes on the wafer surface by constructing an enhanced lithography model. Based on the ability of the enhanced lithography model to perceive morphological changes, it performs optical proximity effect correction and lithography simulation verification using an optical proximity correction model. The technical solutions in the embodiments of this invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0039] like Figure 1 The diagram illustrates a flowchart of a simulation method for optical proximity effect correction based on chemical mechanical polishing, as described in an embodiment of the present invention. The simulation method for optical proximity effect correction based on chemical mechanical polishing in this embodiment includes the following steps:

[0040] Step S11: Based on the target design layout, obtain the three-dimensional contour height map of the first wafer surface using a chemical mechanical polishing process simulation tool; wherein, the first wafer surface is the surface formed after the previous photolithography layer has undergone a chemical mechanical polishing process.

[0041] It should be understood that the target design layout is the final target design layout file (e.g., a GDSII file) confirmed during the integrated circuit design phase. This file includes planar geometric data defining all photolithographic layers of the target chip. The first wafer surface is the surface formed after simulating the complete manufacturing process (including photolithography, etching, and chemical mechanical polishing processes) based on the design layout of the previous photolithographic layers.

[0042] In one embodiment of this application, the process of obtaining a three-dimensional contour height map of the first wafer surface based on the target design layout using a chemical mechanical polishing process simulation tool includes:

[0043] Based on the geometric features of the target design layout and the chemical mechanical polishing process parameters, hydrodynamic calculation simulation and mechanical wear simulation are performed to obtain a three-dimensional contour height map of the first wafer surface; wherein, the three-dimensional contour height map includes: the set of heights from any point on the first wafer surface to the reference plane.

[0044] In some alternative implementations, the geometric characteristics of the target design layout include line width, graphic spacing, graphic area and perimeter, graphic density, and layout orientation. To facilitate understanding by those skilled in the art, the impact of graphic density and line width on the chemical mechanical polishing process will be explained in detail below, using graphic density and line width as examples.

[0045] In the simulation of chemical mechanical polishing (CMP) of the design layout of the front photolithography layer, the uniformity of pattern density and line width directly affects the unevenness of the first wafer surface formed after polishing. Pattern density refers to the proportion of the total area of ​​the material corresponding to the design pattern within a specific local area of ​​the target design layout to the total area of ​​that area; it macroscopically describes the density of the target design layout. Line width refers to the physical width of a single design pattern (such as a metal interconnect) in the target design layout, a key microscopic parameter. High-density areas, due to their large total pattern area and strong structural support, have a slower polishing rate; low-density areas, due to their small total pattern area, are more easily over-polished, forming "dish-shaped depressions." At the same time, the line width effect is also significant at the microscopic level: wide lines, due to their inherent structural rigidity, can more effectively resist polishing pressure, thus resulting in less material loss; while narrow lines, especially isolated narrow lines, due to their poor mechanical stability, will be over-removed under the same polishing conditions, leading to a final thickness significantly lower than that of wide lines. This difference in material removal rate, caused by the uneven distribution of density and linewidth, will eventually create unpredictable height fluctuations on the surface of the first wafer.

[0046] In this embodiment, when simulating the chemical mechanical polishing (CMP) process on the design layout of the front photolithography layer, the key process parameters that need to be set and adjusted mainly include polishing pressure, polishing pad characteristics, slurry characteristics, and relative rotation speed. To facilitate understanding by those skilled in the art, the impact of polishing pressure and slurry characteristics on the CMP process will be explained in detail below using these parameters as examples.

[0047] In the simulation of chemical mechanical polishing (CMP) of the design layout of the front photolithography layer, polishing pressure and slurry characteristics jointly determine the material removal behavior of different pattern areas on the design layout. Polishing pressure refers to the force applied by the polishing head, which is the direct source of mechanical abrasion. Slurry characteristics are a comprehensive parameter, mainly including the material, particle size, concentration, and chemical activity of the abrasive particles. The setting of polishing pressure directly determines the intensity of mechanical grinding. Excessive polishing pressure will cause over-polishing of low-density areas and isolated lines on the design layout, exacerbating defects such as "dish-shaped depressions" and "erosion"; while insufficient polishing pressure will lead to incomplete material removal in high-density areas, resulting in residues and surface unevenness. Slurry characteristics regulate the synergistic effect between chemical corrosion and mechanical abrasion: its chemical components are responsible for softening the surface of the metal layer of the design layout, while the abrasive particles are responsible for removing the softened material through mechanical friction. For example, if the particle size of the grinding particles in the slurry is too large, although it can improve the overall removal rate, it is also very easy to cause microscopic scratches on the lines of the design layout; while if the chemical components are too active, they may cause unnecessary corrosion to specific materials.

[0048] It should be understood that, for the convenience of those skilled in the art, the source of the chemical mechanical polishing (CMP) process simulation parameters mentioned above is explained below: When performing CMP process simulation on the preceding photolithography layer, a set of process parameters is set accordingly. After the preceding photolithography layer forms the first wafer surface based on the CMP process simulation using these process parameters, these process parameters are saved in the CMP process simulation tool. When it is necessary to obtain the three-dimensional contour height map of the first wafer surface, the CMP process simulation tool can automatically obtain the saved set of process parameters and automatically extract the design data corresponding to the preceding photolithography layer from the target design layout file. Then, based on the automatically obtained set of process parameters and the corresponding design data of the preceding photolithography layer, it performs simulation calculations to obtain the three-dimensional contour height map of the first wafer surface.

[0049] It should be noted that the first wafer surface in this invention is essentially a predetermined surface morphology formed after the previous photolithography layer has undergone planarization via chemical mechanical polishing (CMP). The three-dimensional morphology features of this surface are directly generated by the coupling effect of the design layout of the previous photolithography layer and the physical mechanism of the CMP process, which is the core constraint basis for performing optical proximity effect correction calculations on the current photolithography layer pattern. The optical proximity effect correction simulation method based on CMP morphology perception proposed in this invention is not limited to the surface of the process layer after CMP processing, but can be flexibly extended to various wafer surface scenarios after planarization, possessing broad process adaptability. For example, when this method is applied to the surface of a bare die (the original wafer that has not undergone multi-layer stacking and CMP processing), the core process parameters used in the formation of the bare die surface (such as the substrate material properties of the original wafer, initial flatness parameters, grinding process conditions during the preparation process, etc.) can be called through the CMP simulation tool to accurately simulate and obtain the three-dimensional contour height map of the bare die surface.

[0050] In one embodiment of this application, the height from any point on the surface of the first wafer to the reference plane is defined as H(x, y), where (x, y) is defined as the coordinates of any point on the surface of the first wafer in a preset coordinate system. The set of heights from all points on the surface of the first wafer to the reference plane constitutes the three-dimensional contour height map of the first wafer surface. The reference plane provides a unified benchmark for measuring the height of the first wafer surface. By calculating the height from any point on the surface of the first wafer to the reference plane, the three-dimensional morphology of the first wafer surface is quantified, providing accurate morphological data support for subsequent construction of enhanced lithography models, optical proximity effect correction calculations, and lithography simulations.

[0051] In one embodiment of this application, a coordinate system is set with the lower left corner of the first wafer surface as the origin. (x, y) represents the coordinates of any point on the first wafer surface relative to the origin, and H(x, y) represents the height of any point on the first wafer surface from the reference plane in the coordinate system.

[0052] In some optional implementations, the reference plane is determined by the lowest point of the first wafer surface. When the lowest point is used as the reference plane, the height from any point on the first wafer surface to the reference plane satisfies H(x,y)≥0. Choosing the lowest point to determine the reference plane avoids negative height values, thus preventing sign ambiguity caused by negative height values ​​in subsequent formula calculations. It also reduces redundancy in data storage (no need for additional symbolic storage), lowers the computational complexity of chemical mechanical polishing process simulation tools, and improves data processing efficiency.

[0053] In some alternative implementations, the reference plane is determined by the average height of the first wafer surface, which serves as a statistical benchmark for the first wafer surface. H(x,y) calculated based on this benchmark exhibits a positive and negative distribution, with H(x,y) being positive (convex) in regions above the average height and negative (recessed) in regions below the average height. This distribution better reflects the overall morphological characteristics of the first wafer surface.

[0054] It should be noted that the above-mentioned setting position of the reference plane is only an exemplary description and is not a limitation on the scope of protection of this invention. In practical applications, its setting position can be flexibly adjusted according to specific scenarios such as wafer structure design, process planarization requirements, and three-dimensional contour detection accuracy requirements. As long as it can achieve accurate perception of chemical mechanical polishing morphology and effective correction of optical proximity effect, it falls within the scope of protection of this invention.

[0055] Step S12: Integrate the three-dimensional contour height map of the first wafer surface into the photolithography simulation model to construct an enhanced photolithography model; the enhanced photolithography model is used to output the topography sensing data of the first wafer surface.

[0056] It should be noted that the lithography simulation model, as a fundamental tool in lithography process simulation, has the core function of simulating the image formation of a mask pattern on a wafer surface by modeling the interaction between the lithography machine's optical system (such as the light source, objective lens, and mask) and the photoresist, based on an ideally flat wafer surface. This results in the output of imaging data, providing simulation support for optical proximity correction. However, the design logic of the lithography simulation model does not consider the non-flat morphology of the wafer surface formed by the chemical mechanical polishing process of the previous lithography layer. It only uses a fixed standard focal plane as the imaging reference, thus failing to capture the in-plane defocus differences caused by morphological undulations. Consequently, the output simulation data lacks the ability to characterize the imaging characteristics of non-flat surfaces, making it difficult to support high-precision optical proximity correction.

[0057] In this embodiment, to address the aforementioned shortcomings of the lithography simulation model, this application does not use the lithography simulation model for direct execution of lithography imaging simulation. Instead, it uses it as the core foundation module of an enhanced lithography model, achieving functional expansion through the integration of key input data. Specifically, the three-dimensional contour height map of the first wafer surface output by the chemical mechanical polishing process simulation tool is used as key input data and integrated into the lithography simulation model. Its imaging logic is optimized and upgraded, ultimately constructing an enhanced lithography model. The output of this enhanced lithography model is a set of topography-aware data. This data establishes a mapping relationship from the three-dimensional contour height map to key lithography simulation parameters (such as the effective focal plane), providing accurate, spatially related conditional inputs for the subsequent optical proximity correction model. This enables optical proximity correction to specifically compensate for imaging errors caused by uneven surfaces, which is an important prerequisite for achieving topography-aware optical proximity correction in this application.

[0058] In some optional implementations, to ensure that the enhanced lithography model can accurately characterize the optical response characteristics of non-planar surfaces, the lithography simulation model, which serves as the basic module, can flexibly select, according to process requirements, either a scalar imaging model based on the Hopkins equation (e.g., suitable for scenarios where the feature size is larger than the illumination wavelength and computational efficiency is required), or a more rigorous vector imaging model (e.g., a rigorous coupled-wave analysis model suitable for subwavelength features, a time-domain finite-difference model that can accurately describe the electromagnetic field distribution, or a hybrid model combining rigorous coupled-wave analysis and finite element methods that balances computational accuracy and efficiency). The core principles, applicable scenarios, and application logic of different types of models in this invention are as follows:

[0059] The scalar imaging model based on the Hopkins equation is suitable for scenarios where the feature size is larger than the illumination wavelength, the process node is relatively flexible (e.g., 28nm and above), the CMP topography fluctuation is small (e.g., ≤50nm), and the computational efficiency requirement is high. It simplifies the calculation by ignoring the polarization characteristics of light. After integrating the three-dimensional contour height map of the wafer surface, it can quickly achieve dynamic adjustment of the effective focal plane, balancing simulation efficiency and basic accuracy requirements.

[0060] A more rigorous vector imaging model: suitable for subwavelength features (such as 7nm and below process nodes), high numerical aperture lithography scenarios, or scenarios with large CMP topographic fluctuations (such as >50nm), specifically including:

[0061] Rigorous Coupled Wave Analysis (RCWA) model: can accurately capture the polarization characteristics and near-field coupling effects of light, and is suitable for optical response simulation of periodic patterns and large topographic fluctuations;

[0062] Finite-difference time-domain (FDTD) models: without assuming periodicity or symmetry of the medium, they can accurately describe the electromagnetic field distribution of non-periodic patterns, irregular morphologies (such as local anomalous bulges / depressions, steep edge features) and complex medium interfaces.

[0063] A hybrid model combining rigorous coupled-wave analysis (RCWA) and finite element method (FEM): This model integrates the computational efficiency of RCWA for periodic regions with the modeling accuracy of the finite element method for irregular regions. Specifically, for regions with regular wafer surface morphology and periodic patterns (such as dense metal wiring areas), the RCWA model is used to quickly calculate the light field distribution; for regions with irregular morphology and non-periodic patterns (such as chip edge patterns and local abrupt morphological changes), the finite element method is used to accurately fit the irregular boundaries.

[0064] It should be noted that all of the above-mentioned lithography simulation models can construct an enhanced lithography model adapted to the first wafer surface by integrating the three-dimensional contour height map of the first wafer surface, so as to output the topographic perception data of the first wafer surface. The selection of the above-mentioned lithography simulation models is only an exemplary description and is not intended to limit the scope of protection of this invention; in practical applications, the models can be flexibly determined according to the actual process node, pattern features, topographic complexity, and simulation efficiency requirements to ensure that the engineering feasibility of the simulation process is taken into account while meeting the requirements for calibration accuracy.

[0065] In one embodiment of this application, the process of integrating the three-dimensional contour height map of the first wafer surface into the photolithography simulation model to construct an enhanced photolithography model includes: obtaining an effective focal plane at any point on the first wafer surface, wherein the effective focal plane is obtained based on the three-dimensional contour height map.

[0066] Specifically, for any point (x, y) on the surface of the first wafer, the effective focal plane for imaging calculation is calculated based on the three-dimensional topographic height H(x, y) of that point.

[0067] In one embodiment of this application, the effective focal plane at any point on the surface of the first wafer is characterized as:

[0068] ;

[0069] in, The effective focal plane represents any point on the surface of the first wafer; H(x, y) represents the standard focal plane; H(x, y) represents the height of any point on the surface of the first wafer from the reference plane; and (x, y) represents the coordinates of any point on the surface of the first wafer in a preset coordinate system.

[0070] It should be understood that the standard focal plane is a reference plane defined by the simulation system, and its position is precisely determined by the lithography-related configuration parameters preset by the simulation system (such as light source wavelength, numerical aperture, coherence factor, photoresist equivalent refractive index, and other optical and process simulation parameters). This standard focal plane is the optimal imaging focal plane under the configuration parameters. In the enhanced lithography model, the effective focal plane of any point (x, y) on the first wafer surface can be obtained by linearly superimposing the height H(x, y) of that point (x, y) with the standard focal plane. This effective focal plane serves as the reference for subsequent OPC correction calculations and precise lithography simulation.

[0071] In this embodiment, the topography perception data output by the enhanced lithography model is based on the effective focal plane data as its core component, and may also include derived data such as topography gradient, local curvature, and topography partitioning identifiers, depending on the simulation accuracy requirements. Among them, the effective focal plane data is a core parameter calculated by correlating the 3D contour height map of the wafer surface output by the chemical mechanical polishing (CMP) process simulation tool with the standard focal plane. It directly maps the local defocusing differences on the wafer surface caused by the CMP process. Specifically, the unevenness and undulation of the first wafer surface caused by the CMP process will cause different positions on the first wafer surface to deviate from the standard focal plane. The effective focal plane directly reflects the degree and direction of deviation between the actual imaging focal plane and the standard focal plane caused by the undulation of the first wafer surface. The remaining derived data are used to further optimize the light field modeling accuracy of the lithography simulation (such as adapting the morphology gradient data to the light field refraction simulation of steep undulation regions, and correcting the light intensity distortion simulation of sharp morphologies with local curvature data). All the data together provide comprehensive and accurate morphology constraints for the subsequent optical proximity effect correction simulation, ensuring that the corrected mask data can specifically compensate for the imaging errors caused by the non-flat surface.

[0072] In some alternative implementations, when constructing the enhanced lithography model, the reference plane defined by the three-dimensional contour height map is set to coincide with the standard focal plane. Therefore, the height H(x, y) of any point (x, y) on the first wafer surface directly characterizes the geometric deviation of that point relative to the standard focal plane, thus giving the aforementioned formula for characterizing the effective focal plane precise physical meaning.

[0073] Step S13: Based on the enhanced lithography model, the optical proximity correction model is used to perform optical proximity effect correction calculation on the current lithography layer pattern to generate the corrected mask data of the current lithography layer; and the mask data of the current lithography layer is photolithographically etched onto the surface of the first wafer for lithography simulation verification; wherein, the mask data of the current lithography layer is photolithographically etched onto the surface of the first wafer and then subjected to chemical mechanical polishing to form the second wafer surface.

[0074] It should be noted that in this step, the optical proximity correction model acts as an integrated correction system, performing a complete process that includes optical proximity effect correction and lithographic simulation.

[0075] The specific process includes:

[0076] 1. Correction calculation stage:

[0077] The optical proximity correction model, based on the topography-sensing data output by the enhanced lithography model, performs optical proximity effect correction calculations on the current lithography layer pattern through multiple iterations of optimization, ultimately generating mask data for the current lithography layer that adapts to the non-planar topography of the first wafer. To facilitate understanding by those skilled in the art, the generation process of the mask data for the current lithography layer is described in detail below, specifically including the following steps:

[0078] Step 1: Data Loading and Spatial Mapping. The optical proximity correction model reads the target design layout data of the current lithography layer (such as the graphic outline, critical dimension (CD) target values, graphic functional partition information, etc. in GDSII format file), and loads the topography-aware data output by the enhanced lithography model (based on the effective focal plane data, including optional topography gradient, partitioning identifiers, and other derived data). This establishes a mapping relationship between the target design layout data and the topography of the first wafer surface, ensuring that subsequent optical proximity correction calculations are accurately correlated with the wafer surface topography.

[0079] Step 2: Initial Mask Pattern Generation. Based on the design rules of the current lithography layer pattern (such as minimum linewidth threshold, minimum pattern spacing constraint, pattern density control requirements, etc.), the target design layout data of the current lithography layer is processed for rule adaptation to generate a mask pattern that matches the design intent. Figure 1 The first step involves obtaining initial mask pattern data (a basic version without optical proximity correction). This initial mask pattern data includes core information such as edge coordinates, pattern hierarchy, and basic dimensions. The third step is topography-aware imaging simulation. The optical proximity correction model performs photolithography simulation imaging on the first wafer surface using the initial mask pattern data. The core principle is based on location-based imaging. The light field propagation path and focusing parameters are dynamically adjusted to accurately calculate the light intensity distribution on the surface of the photoresist layer, the predicted pattern outline after development, and extract the core quality parameters after imaging, including the actual value of the critical dimension (CD), edge placement error (EPE), and pattern distortion features (such as line end shortening and corner rounding radius).

[0080] Step 4: Error Identification and Mask Correction. The simulated imaging parameters are compared with the preset target to identify two main types of core errors: First, inherent errors caused by the proximity effect in traditional optics (such as shortening of isolated line ends, shrinkage of dense line spacing, rounding of corners, and risk of pattern bridging); second, additional errors in the surface topography of the first wafer caused by the CMP process of the previous photolithography layer (such as a larger CD due to defocusing in protruding areas, a smaller CD due to underfocusing in recessed areas, and EPE anomalies caused by steep topographic edges). For areas with excessive errors, the initial mask pattern data is adjusted, specifically including:

[0081] Edge offset correction: Based on the magnitude and direction of the error, nanometer-level displacement adjustment is performed on the edge of the mask pattern (such as offsetting the linewidth direction by 5-20nm, dynamically adapting according to the magnitude of the error), directly compensating for critical size deviations caused by morphology defocusing or optical diffraction.

[0082] Sub-resolution auxiliary pattern (SRAF) addition: In optically sensitive areas such as isolated lines, line ends, and small-pitch patterns, sub-resolution auxiliary patterns that meet the requirements of the photolithography process window are added to optimize the uniformity of local light field distribution and alleviate distortion phenomena such as line end shortening and pattern shrinkage.

[0083] Graphic segmentation and contour reconstruction: For graphics with large areas of wide lines, complex through-hole arrays, or areas with severe topographic undulations, perform segmentation (such as splitting wide lines into multiple narrow line combinations) or contour reconstruction to reduce the non-uniformity of light field propagation on non-flat surfaces and improve imaging consistency.

[0084] Step 5: Iterative convergence verification and mask data output. Repeat steps 3 (topography-aware imaging simulation) and 4 (error identification and mask correction). After each iteration, calculate the error convergence index (such as mean CD deviation, maximum CD deviation, and 3σ value of EPE) until the error meets the preset target (such as critical dimension deviation ≤ ±3% of the preset target value, edge placement error ≤ 5nm). Finally, output the corrected mask data of the current lithography layer.

[0085] 2. Photolithography simulation verification stage:

[0086] In a topography-aware data environment identical to that of the correction calculation stage, the optical proximity correction model uses the same topography-aware data to perform photolithography simulation imaging again on the mask data of the final generated current lithography layer after correction. The core objective of this stage is to evaluate the imaging quality stability and process compatibility of the final corrected mask data under the non-planar topography of the first wafer, ensuring that it meets the preset photolithography process specifications. For example, the following core indicators are extracted for detection:

[0087] Critical Dimension (CD): The actual dimensions of various patterns (such as gate linewidth, via diameter, metal wiring spacing, etc.) after detection imaging. For example, the critical dimension deviation is required to be ≤ ±3% of the preset target value.

[0088] Edge Placement Error (EPE): The offset of the edge of the detected image pattern relative to the designed position in the target design layout. For example, the absolute value of EPE is required to be ≤5nm (which can be reduced to ≤3nm in advanced process nodes), and the 3σ value of EPE is ≤4nm.

[0089] Graphic integrity: Verify that the imaged graphic has no bridging (unintentional adhesion between adjacent graphics), no broken edges (broken main body of the graphic), and no missing key features (such as unimaged through-holes or incomplete line ends), and ensure that the corners, edges, and contours of the graphic conform to the design intent. Figure 1 Consistent, without excessive rounding or distortion;

[0090] Light intensity uniformity: Based on the simulated light intensity distribution data of the photoresist layer surface, calculate the light intensity variation coefficient (CV) inside the pattern and between similar patterns. For example, it is required that CV ≤ 8% (≤ 5% in high-precision pattern areas) to avoid incomplete photoresist development due to uneven light intensity distribution, which may lead to pattern linewidth fluctuations or rough edges.

[0091] This invention integrates calibration calculations and lithography simulation verification into the same optical proximity correction model. Its core advantage lies in achieving consistent reuse of topography-sensing data throughout the calibration and verification process. This avoids evaluation distortion caused by data transmission deviations and inconsistent environmental parameters, ensuring that the verification results can truly reflect the actual imaging effect of the calibrated mask data under non-flat topography. This effectively improves the reliability of calibration accuracy and final lithography imaging quality, providing accurate and reliable simulation basis for mask fabrication in subsequent actual processes.

[0092] In one embodiment of this application, during the process of photolithographically etching the mask data of the current photolithographic layer onto the surface of a first wafer for photolithographic simulation verification, the method further performs a process corner simulation verification step, such as... Figure 2 As shown, it includes:

[0093] Step S21: Preset a fluctuation range for the defocus amount and exposure dose of the process angle, and within the preset range, change the combination of values ​​of the defocus amount and exposure dose multiple times, and use the optical proximity correction model to perform multiple photolithography simulations to verify the mask data of the current photolithography layer.

[0094] Step S22: Verify the key dimensions and edge placement errors of the simulated image of the current lithography layer obtained from each simulation, and determine whether the results under all simulation conditions meet the preset target.

[0095] Step S23: Determine whether the results under all simulation conditions meet the preset target.

[0096] Step S24: If all results meet the preset target, the verification is successful, and the mask data of the current photolithography layer is taken as the final result.

[0097] Step S25: If any result does not meet the preset target, the verification fails, and the optical proximity correction model generates a feedback signal.

[0098] Based on the feedback signal, the optical proximity correction model restarts the optical proximity effect correction operation on the mask data of the current lithography layer. By adjusting the correction operation parameters, the mask data of the current lithography layer is optimized, and the optimized mask data is verified again by process corner simulation until the simulated image meets the preset target under all process corner simulation conditions.

[0099] In one embodiment of this application, if, after a preset number of optical proximity correction operations (e.g., 20 times), the simulated imaging pattern of the current lithography layer still fails to meet the preset standard under all process corner simulation conditions, a design-process co-optimization loop is initiated. In this loop, returning to step S11 above, based on a new target design layout optimized by design rules, the chemical mechanical polishing process simulation of the previous lithography layer is re-executed to generate an updated three-dimensional contour height map. Subsequently, all subsequent processes, including enhanced lithography model construction, optical proximity correction, and lithography simulation verification, are re-executed. This iterative process continues until all simulated imaging pattern indicators converge and meet the preset target.

[0100] It should be understood that if optical proximity correction fails to converge, it indicates an inherent deep conflict between the current design layout and manufacturing process of the current lithography layer, which is difficult to compensate for or eliminate by simply adjusting the mask data (including correction methods such as pattern edge offset correction, auxiliary pattern addition, pattern segmentation and reconstruction). Specifically, the core of this deep conflict stems from the mismatch between the geometric features of the design layout (such as abrupt changes in pattern density, critical dimensions approaching process limits, and irregular topology) and the non-flat wafer surface morphology caused by chemical mechanical polishing. This causes lithography imaging errors (such as dimensional deviations caused by large defocusing and pattern defects caused by light field distortion) to exceed the compensation capability boundary of optical proximity correction, and cannot be fundamentally solved by simply optimizing the mask pattern data. At this point, it is necessary to initiate a design-process co-optimization process, rather than continuing to rely on passive compensation for optical proximity correction. The logic of this co-optimization starts from the source of conflict and optimizes the design layout of the current photolithography layer based on the formation mechanism of the first wafer surface morphology (such as the difference in grinding rate dominated by pattern density, and the stress inhomogeneity caused by the superposition of interlayer patterns). This enables the reverse optimization and adaptation of the current photolithography layer to the surface morphology of the first wafer, thereby creating feasible conditions for subsequent optical proximity correction.

[0101] In one embodiment of this application, during the process of performing photolithography simulation verification on the mask data of the previous photolithography layer, the method further performs a process corner simulation verification step, such as... Figure 3 As shown, it includes:

[0102] Step S31: Preset a fluctuation range for the defocus amount and exposure dose of the process angle, and within the preset range, change the combination of values ​​of the defocus amount and exposure dose multiple times, and use the optical proximity correction model to perform multiple photolithography simulations to verify the mask data of the front photolithography layer.

[0103] Step S32: Verify the key dimensions and edge placement errors of the simulated imaging pattern of the front lithography layer obtained from each simulation, and determine whether the results under all simulation conditions meet the preset target.

[0104] Step S33: Determine whether the results under all simulation conditions meet the preset target.

[0105] Step S34: If all results meet the preset target, the verification is successful, and the mask data of the previous photolithography layer is taken as the final result;

[0106] Step S35: If any result does not meet the preset target, the verification fails, and the optical proximity correction model generates a feedback signal.

[0107] Based on the feedback signal, the optical proximity correction model restarts the optical proximity effect correction operation on the mask data of the previous lithography layer. The mask data of the previous lithography layer is optimized by adjusting the correction operation parameters, and the optimized mask data is verified by process corner simulation again until the simulated imaging pattern meets the preset target under all process corner simulation conditions.

[0108] like Figure 4 The diagram illustrates a structural schematic of an optical proximity effect correction simulation device based on chemical mechanical polishing according to an embodiment of the present invention. The optical proximity effect correction simulation device 400 in this embodiment includes: a three-dimensional contour height prediction module 401, an enhanced lithography module 402, and an OPC correction and lithography simulation module 403.

[0109] The three-dimensional contour height prediction module 401 is used to obtain a three-dimensional contour height map of the first wafer surface based on the target design layout and through a chemical mechanical polishing process simulation tool; wherein, the first wafer surface is the surface formed after the previous photolithography layer has undergone a chemical mechanical polishing process.

[0110] The enhanced lithography module 402 is used to integrate the three-dimensional contour height map of the first wafer surface into the lithography simulation model to construct an enhanced lithography model; the enhanced lithography model is used to output the topography sensing data of the first wafer surface;

[0111] The OPC correction and lithography simulation module 403 is used to perform optical proximity effect correction calculations on the current lithography layer pattern using an optical proximity correction model based on the enhanced lithography model, so as to generate the corrected mask data of the current lithography layer; and to photolithographically ...

[0112] It should be noted that the implementation principle and process of the optical proximity effect correction simulation device based on chemical mechanical polishing provided in this embodiment of the invention are similar to those of the optical proximity effect correction simulation method based on chemical mechanical polishing described above, and will not be repeated here. The specific process of each module performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0113] It should also be understood that the module division in the embodiments of the present invention is illustrative and only represents one logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of the present invention can be integrated into a single processor, exist as separate physical entities, or two or more modules can be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0114] like Figure 5 The diagram shown is a schematic of an electronic terminal provided in an embodiment of this application. The electronic terminal includes at least one processor 501, a memory 502, at least one network interface 503, and a user interface 505. The various components in the device are coupled together via a bus system 504. It is understood that the bus system 504 is used to implement communication between these components. In addition to a data bus, the bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for clarity, ... Figure 5 The general will label all buses as bus systems.

[0115] The user interface 505 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0116] It is understood that memory 502 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0117] In this embodiment of the invention, the memory 502 is used to store various types of data to support the operation of the electronic terminal 500. Examples of this data include: any executable program for operation on the electronic terminal 500, such as the operating system 5021 and application program 5022; the operating system 5021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 5022 may contain various applications, such as media players, browsers, etc., for implementing various application services. The method for testing the lateral positioning accuracy of agricultural machinery provided in this embodiment of the invention can be included in the application program 5022.

[0118] The methods disclosed in the above embodiments of the present invention can be applied to processor 501, or implemented by processor 501. Processor 501 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 501 or by instructions in the form of software. The processor 501 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 501 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 501 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0119] In an exemplary embodiment, the electronic terminal 500 may be used to execute the aforementioned method by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0120] According to the method provided in the embodiments of the present invention, the present invention also provides a computer program product, the computer program product comprising: computer program code, which, when executed on a computer, causes the computer to perform... Figure 1The simulation method for optical proximity effect correction based on chemical mechanical polishing morphology perception in any of the embodiments shown.

[0121] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0122] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0123] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0124] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0125] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0126] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0127] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs, etc.).

[0128] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0129] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0130] In summary, the optical proximity effect correction simulation method, apparatus, program product, and terminal based on chemical mechanical polishing (CMP) provided by this invention obtain a three-dimensional contour height map of the wafer surface through CMP process simulation tools. It then constructs an enhanced lithography model to perceive morphological changes on the wafer surface. Based on the enhanced lithography model's ability to perceive morphological changes, it performs optical proximity effect correction and lithography simulation verification through an optical proximity correction model. This invention fundamentally solves the systematic errors inherent in traditional OPC models due to neglecting CMP morphology, significantly improving the accuracy of lithography simulation predictions. Furthermore, through multiple design-process collaborative optimization loops during the lithography simulation verification stage, it proactively identifies and eliminates manufacturing defects caused by complex process interaction effects before wafer fabrication, fundamentally reducing development risks and costs.

[0131] Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0132] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A simulation method for optical proximity effect correction based on chemical mechanical polishing morphology perception, characterized in that, include: Based on the target design layout, a three-dimensional contour height map of the first wafer surface is obtained using a chemical mechanical polishing (CMP) process simulation tool; wherein, the first wafer surface is the surface formed after the previous photolithography layer undergoes a CMP process; wherein, the three-dimensional contour height map includes: the set of heights of all points on the first wafer surface from the reference plane. The three-dimensional contour height map of the first wafer surface is integrated into the photolithography simulation model to construct an enhanced photolithography model; the enhanced photolithography model is used to output the topography sensing data of the first wafer surface. The process of integrating the three-dimensional contour height map of the first wafer surface into the lithography simulation model to construct an enhanced lithography model includes: obtaining an effective focal plane at any point on the first wafer surface, wherein the effective focal plane is obtained based on the three-dimensional contour height map; Based on the topography-sensing data output by the enhanced lithography model, an optical proximity correction model is used to perform optical proximity effect correction calculations on the current lithography layer pattern to generate corrected mask data for the current lithography layer; and the mask data for the current lithography layer is photolithographically etched onto the surface of the first wafer for lithography simulation verification; wherein, the mask data for the current lithography layer is photolithographically etched onto the surface of the first wafer and then subjected to a chemical mechanical polishing process to form the surface of the second wafer.

2. The optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception according to claim 1, characterized in that, The process of obtaining a three-dimensional contour height map of the first wafer surface based on the target design layout and using a chemical mechanical polishing process simulation tool includes: Based on the geometric features of the target design layout and the chemical mechanical polishing process parameters, fluid dynamics calculation simulation and mechanical wear simulation are performed to obtain a three-dimensional contour height map of the first wafer surface.

3. The optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception according to claim 1, characterized in that, The effective focal plane at any point on the surface of the first wafer is characterized as: in, The effective focal plane represents any point on the surface of the first wafer; H(x, y) represents the standard focal plane; H(x, y) represents the height of any point on the surface of the first wafer from the reference plane; (x, y) represents the coordinates of any point on the surface of the first wafer in the preset coordinate system.

4. The optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception as described in claim 3, characterized in that, The method further includes: setting the reference plane to coincide with the standard focal plane so as to photolithographically print the mask data of the current photolithography layer onto the surface of the first wafer.

5. The optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception according to claim 1, characterized in that, In the process of photolithographically etching the mask data of any photolithographic layer onto the wafer surface for photolithographic simulation verification, the method also performs a process corner simulation verification step, which includes: The defocusing amount and exposure dose of the process angle are adjusted within the preset fluctuation range, and the optical proximity correction model is used to perform photolithography simulation on the mask data of any photolithography layer. The key dimensions and edge placement errors of the simulated photolithography layer pattern are verified to determine whether they meet the preset standards.

6. The optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception according to claim 5, characterized in that, The process of verifying the key dimensions and edge placement errors of the simulated photolithographic layer pattern to determine whether it meets the preset standards includes: For mask data whose critical dimensions and edge placement errors do not meet the preset standards, adjust its optical proximity correction operation parameters and re-use the optical proximity correction model for photolithography simulation verification until it meets the preset standards.

7. An optical proximity effect correction device based on chemical mechanical polishing morphology perception, characterized in that, include: A 3D contour height prediction module is used to obtain a 3D contour height map of the first wafer surface based on the target design layout and through a chemical mechanical polishing process simulation tool; wherein, the first wafer surface is the surface formed after the previous photolithography layer has undergone a chemical mechanical polishing process; wherein, the 3D contour height map includes: the set of heights of all points on the first wafer surface from the reference plane. An enhanced lithography module is used to integrate the three-dimensional contour height map of the first wafer surface into the lithography simulation model to construct an enhanced lithography model; the enhanced lithography model is used to output the topography sensing data of the first wafer surface; The process of integrating the three-dimensional contour height map of the first wafer surface into the lithography simulation model to construct an enhanced lithography model includes: obtaining an effective focal plane at any point on the first wafer surface, wherein the effective focal plane is obtained based on the three-dimensional contour height map; The OPC correction and lithography simulation module is used to perform optical proximity effect correction calculations on the current lithography layer pattern using an optical proximity correction model based on the topography sensing data output by the enhanced lithography model, so as to generate the corrected mask data of the current lithography layer; and to photolithographically ...

8. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, enables the computer to implement the optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception as described in any one of claims 1 to 6.

9. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the optical proximity effect correction simulation method based on chemical mechanical polishing morphology perception as described in any one of claims 1 to 6.

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