MCU upgrading method and device, equipment and storage medium

Abstract

The invention provides an MCU upgrading method and device, equipment and a storage medium, and belongs to the field of computers. The method comprises the steps that an MCU receives a data writing instruction, the data writing instruction is an assembly language instruction and is used for indicating that a frame of first target data is written into a flash memory, the frame of first target data comprises N bytes of data, and N is an integer larger than 1; receiving the frame of first target data according to the data writing instruction, and storing the frame of first target data to a cache; and writing the frame of first target data into a flash memory of the MCU from the cache so as to upgrade the MCU. The method is beneficial to improving the upgrading efficiency of the MCU.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of computers, and in particular, to an MCU upgrading method, device, equipment and storage medium. BACKGROUND

[0002] After the MCU (Microcontroller Unit) is shipped, the software program in the MCU is often updated and iterated, and therefore, the software program in the MCU needs to be upgraded.

[0003] In the related art, when the software program in the MCU is upgraded, an upgrading program is generally installed in the MCU, and after the MCU receives an upgrading data packet, the upgrading program upgrades the software program according to the upgrading data packet.

[0004] However, the storage space of the ROM (Read Only Memory) in some low-cost MCUs is small, and the upgrading program is often programmed in a high-level language such as C language, which causes the storage space of the ROM in the MCU to be largely occupied by the upgrading program; and in the upgrading process, once the upgrading program in the high-level language is run, the RAM (Random Access Memory) of the MCU is largely occupied, which makes the upgrading efficiency of the MCU low. SUMMARY

[0005] The present disclosure provides an MCU upgrading method, device, equipment and storage medium, which can reduce the size of the upgrading packet when the MCU is upgraded. The technical solution at least includes the following solutions.

[0006] In a first aspect, an MCU upgrading method is provided, which includes: an MCU receiving a write data instruction, the write data instruction being an assembly language instruction and being used to instruct to write a frame of first target data into a flash memory, the frame of first target data including N bytes of data, N being an integer greater than 1; according to the write data instruction, receiving the frame of first target data and storing the frame of first target data into a cache of the MCU; and writing the frame of first target data from the cache into the flash memory of the MCU to upgrade the MCU.

[0007] Optionally, the receiving the frame of first target data and storing the frame of first target data into the cache includes: receiving the N bytes of data in the frame of first target data in units of bytes in sequence; and storing the received data into the cache every time one byte of data is received, until the frame of first target data is all stored into the cache.

[0008] Optionally, the method further comprises: receiving a write address setting instruction, the write address setting instruction being an assembly language instruction, the write address setting instruction being used to set a first flash memory address, the first flash memory address being used to indicate an address in the flash memory for storing the first target data; and receiving write address data according to the write address setting instruction, the write address data being used to indicate the first flash memory address.

[0009] Optionally, before receiving the write data instruction, the method further comprises: receiving an erase instruction, the erase instruction being used to instruct to erase a first sector corresponding to the first flash memory address; and erasing data in the first sector according to the erase instruction.

[0010] Optionally, the method further comprises: receiving a read data instruction, the read data instruction being an assembly language instruction, the read data instruction being used to read a second target data, the second target data including N bytes of data; and sending the N bytes of data in the second target data according to the read data instruction.

[0011] Optionally, the method further comprises: receiving a read address setting instruction, the read address setting instruction being an assembly language instruction, the read address setting instruction being used to set a second flash memory address, the second flash memory address being used to indicate a storage address of the second target data in the flash memory; and receiving read address data according to the read address setting instruction, the read address data being used to indicate the second flash memory address.

[0012] Optionally, N is equal to a size of a sector in the flash memory.

[0013] The second aspect further provides an MCU upgrading apparatus, which comprises: a receiving module, configured to receive a write data instruction, the write data instruction being an assembly language instruction and being used to instruct to write a first target data into a flash memory, the first target data including N bytes of data, N being an integer greater than 1; a first storage module, configured to receive the first target data according to the write data instruction and store the first target data into a cache; and a second storage module, configured to write the first target data from the cache into the flash memory of the MCU to upgrade the MCU.

[0014] The third aspect further provides a computer device, which comprises: a memory and a processor, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor, so as to execute any one of the MCU upgrading methods.

[0015] In a fourth aspect, a computer readable storage medium is provided, wherein the computer readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by a processor, so as to execute any of the MCU upgrading methods.

[0016] In a fifth aspect, a computer program product is provided, comprising computer programs / instructions, and the computer programs / instructions are executed by a processor to implement any of the MCU upgrading methods.

[0017] The technical scheme provided by the embodiments of the present disclosure has at least the following beneficial effects:

[0018] In the embodiments of the present disclosure, the write data instruction adopted by the host computer is an assembly language instruction, and the assembly language instruction occupies less computing resources of the MCU. The MCU can process the assembly language instruction by using less computing resources, which is beneficial to speed up the processing efficiency of the MCU on the write data instruction, thereby improving the upgrading efficiency of the MCU. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical schemes in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0020] Figure 1 is a schematic diagram of an MCU upgrading system provided by the embodiments of the present disclosure;

[0021] Figure 2 is a flowchart of an MCU upgrading method provided by the embodiments of the present disclosure;

[0022] Figure 3 is a flowchart of another MCU upgrading method provided by the embodiments of the present disclosure;

[0023] Figure 4 is an instruction interaction diagram between the host computer and the MCU in the MCU upgrading method provided by the embodiments of the present disclosure;

[0024] Figure 5 is a flowchart of reading data from the MCU provided by the embodiments of the present disclosure;

[0025] Figure 6 is an instruction interaction diagram between the host computer and the MCU in the process of reading a software program from the MCU provided by the embodiments of the present disclosure;

[0026] Figure 7is a process of reading software version information and chip version information from the MCU provided by the embodiment of the disclosure, and the instruction interaction diagram between the host computer and the MCU;

[0027] Figure 8 and Figure 9 is a flowchart of another MCU upgrading method provided by the embodiment of the disclosure;

[0028] Figure 10 is a variation process schematic diagram of the state machine in the MCU provided by the embodiment of the disclosure;

[0029] Figure 11 is a structural schematic diagram of an MCU upgrading device provided by the embodiment of the disclosure;

[0030] Figure 12 is a structural schematic diagram of a computer device provided by the embodiment of the disclosure. DETAILED DESCRIPTION

[0031] Unless otherwise defined, technical terms or scientific terms used herein should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs. The use of "first", "second", "third" and similar words in the specification and claims of the present disclosure do not indicate any order, number or importance, but are only used to distinguish different components. Similarly, "one" or "a" and similar words do not indicate a quantity limitation, but indicate the presence of at least one. "Include" or "contain" and similar words mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects.

[0032] In order to make the purpose, technical scheme and advantages of the disclosure clearer, the embodiments of the disclosure will be further described in detail below with reference to the drawings.

[0033] The embodiment of the disclosure provides an MCU upgrading method, which is especially suitable for upgrading low-cost and / or small-memory MCUs, such as 8051 MCU.

[0034] In order to facilitate understanding of the embodiments of the disclosure, the 8051 MCU will be briefly introduced as follows.

[0035] The 8051 MCU is an 8-bit single-chip microcontroller, which generally includes a CPU (Central Processing Unit), a memory and a serial communication interface structure. The CPU, the memory and the serial communication structure are connected through a bus.

[0036] The CPU can send a control signal to the memory through the bus to read data from the memory or write data into the memory.

[0037] The memory includes a ROM and a RAM. The ROM generally uses a Flash Memory (Flash for short). The Flash is used to store an application program in the 8051 MCU. The size of the Flash is generally 4 KB (Kilobyte) to 64 KB. For a low-cost MCU, the size of the Flash is generally small, about 4 KB.

[0038] The most basic storage unit of the Flash is a transistor with a floating gate. The floating gate can store electric charges, thereby changing the control gate switching threshold value Vth of the unit. When there are positive electric charges in the floating gate, it represents "1", and when there are negative electric charges / electrons in the floating gate, it represents "0", so one storage unit can store one bit of data. In the Flash, a plurality of storage units are arranged in an array. The word line of each row of storage units is connected. Generally, one row of storage units includes 8 storage units, that is, one row of storage units can store 8 bits of data (i.e., one byte of data). A plurality of rows of storage units form a sector. The size of the sector is generally in bytes, which can be 128 bytes, 256 bytes, or 512 bytes, etc. In the Flash, data is read and written in bytes, and data is erased in sectors.

[0039] The RAM includes an on-chip RAM and an off-chip RAM. It is generally used to store data generated by the application program in the Flash during running, or to temporarily store data received from an external device, that is, to be used as a cache. According to different functions, the RAM of the 8051 MCU can be divided into a working register area, a bit addressing area, a user RAM area, and a special function register area. The special function register area is mainly used to manage various functional components (such as a serial communication interface) in the 8051 MCU. By programming to set the values of some special function registers, the corresponding functional components can be brought into the set working state.

[0040] The serial communication interface is used for serial communication with an external device (such as a host computer). In serial communication, the 8051 MCU can receive or send data bit by bit. The received or sent data is temporarily stored in the SBUF (Serial data Buffer) in the special function register area of the RAM. When receiving data through the serial communication interface, the received data is first temporarily stored in the SBUF, and then stored in other areas of the memory. When sending data through the serial communication interface, the data to be sent is first temporarily stored in the SBUF, and then sent out through the serial communication interface.

[0041] Figure 1A schematic diagram of an MCU upgrading system provided by one example embodiment of the present disclosure is shown. As shown in Figure 1 The MCU upgrading system includes a host computer (or host) and an MCU. The host computer and the MCU can be connected through a wired manner (such as a serial port connection, etc.) or through a wireless manner (such as a Bluetooth connection, a WiFi connection, etc.). In the embodiments of the present disclosure, the host computer can be various computer devices, such as a desktop computer or a mobile terminal (such as a notebook computer or a tablet computer, etc.).

[0042] The host computer is configured to obtain an upgrading package of the MCU, the upgrading package including at least one frame of upgrading data, and then send the at least one frame of upgrading data to the MCU in sequence. The MCU is configured to receive the at least one frame of upgrading data, and write the received upgrading data into a flash memory of the MCU, so as to realize upgrading of the MCU. Here, the at least one frame of data is sent to the MCU in sequence, that is, the data is sent to the MCU frame by frame according to the order of the multiple frames of data in the data package.

[0043] Optionally, the host computer can obtain the upgrading package of the MCU from a server, or obtain the upgrading package of the MCU pre-stored locally.

[0044] Figure 2 A flowchart of an MCU upgrading method provided by one example embodiment of the present disclosure is shown, referring to Figure 2 The method includes:

[0045] In step 201, the MCU receives a write data instruction.

[0046] The write data instruction is an assembly language instruction, and is configured to instruct to write a frame of first target data into the flash memory, the frame of first target data including N bytes of data, N being an integer greater than 1.

[0047] Optionally, the length of each frame of first target data is equal to a target length, and the target length is the size of a sector in the flash memory of the MCU.

[0048] In some embodiments, the size of the sector of the MCU can be 128 bytes, that is, the length of each frame of first target data is 128 bytes. In other embodiments, the size of the sector of the MCU can be 256 bytes, 512 bytes or other sizes, and at this time, the length of each frame of first target data will also change accordingly.

[0049] In some embodiments, the upgrade package obtained by the host computer includes N frames of upgrade data, where N is a positive integer. If the data length in the upgrade package is an integer multiple of the target length, the length of each frame of upgrade data is equal to the target length, and the upgrade data in the upgrade package can be sent to the MCU frame by frame. If the data length in the upgrade package is not an integer multiple of the target length, the length of the first N-1 frames of upgrade data is equal to the target length, and the length of the last 1 frame of upgrade data is less than the target length, and the last 1 frame of upgrade data needs to be supplemented to the target length (for example, invalid data is filled in the last 1 frame of data) before being sent to the MCU. Here, each frame of upgrade data is a frame of first target data.

[0050] In step 202, according to the write data instruction, a frame of first target data is received, and the frame of first target data is stored to the cache of the MCU.

[0051] In step 203, the frame of first target data is written from the cache to the flash memory of the MCU to upgrade the MCU.

[0052] In the embodiments of the present disclosure, since the write data instruction used by the host computer is an assembly language instruction, the assembly language instruction occupies less computing resources of the MCU, and the MCU can process the assembly language instruction using less computing resources, which is beneficial to speed up the processing efficiency of the MCU on the write data instruction, thereby further improving the upgrade efficiency of the MCU.

[0053] In addition, in the embodiments of the present disclosure, N bytes of data in a frame of first target data are first written into the cache of the MCU according to the write data instruction, and then N bytes of data in the frame of first target data in the cache are written into the flash memory. In this way, multiple bytes of data can be written into the flash memory of the MCU by one write data instruction. In the related art, one write data instruction usually indicates that one byte of data is written into the flash memory of the MCU. Therefore, the embodiments of the present disclosure can effectively reduce the number of write data instructions sent by the host computer to the MCU in one upgrade process, and improve the upgrade efficiency of the MCU.

[0054] The following will be described in detail in combination with Figure 3 The process of receiving data by the MCU and writing data into the flash memory will be described in detail. In the following, the MCU will be taken as an 8051 MCU, and the assembly language instruction will be taken as an 8051 assembly language instruction.

[0055] Figure 3 A flowchart of an upgrade method of an MCU provided by an example embodiment of the present disclosure is shown, see Figure 3 The method includes:

[0056] In step 301, the MCU receives a write address setting instruction sent by the host computer.

[0057] Before the step 301, the method further includes: the host computer obtaining an upgrade package of the MCU. Details of the host computer obtaining the upgrade package of the MCU can refer to the foregoing step 201, and details are not described herein again.

[0058] Optionally, the write address setting instruction is an assembly language instruction, and the write address setting instruction is used to set a first flash memory address, the first flash memory address being used to indicate an address in the flash memory for storing the one frame of first target data. Here, the first flash memory address is set, that is, the first flash memory address is set as a target flash memory address, and the target flash memory address is an address to be operated by the MCU, and the operation includes at least one of reading data, storing data, or erasing data.

[0059] In the embodiment of the present disclosure, the length of the first flash memory address is 2 bytes.

[0060] In step 302, the MCU receives write address data according to the write address setting instruction.

[0061] The write address data is used to indicate the first flash memory address.

[0062] Through the step 302, the MCU can take the first flash memory address corresponding to the write address setting instruction as the target flash memory address.

[0063] Exemplarily, the step 302 includes: after receiving the write address setting instruction, the MCU receives two bytes of address data sent by the host computer in sequence, and stores the two bytes of address data into an address register; and stores the address data in the address register into a flash memory address register, so as to set the first flash memory address as the target flash memory address.

[0064] Optionally, the method further includes: after storing the address data into the address register, the MCU sends, to the host computer, reception completion indication information, the reception completion indication information being used to indicate that the address data has been received completely.

[0065] The implementation manner of the steps 301-302 will be exemplarily described below in combination with codes. In the part of codes, SET_ADDRESS_CMD represents an address setting instruction, and when the address setting instruction is sent before a write data instruction, it is a write address setting instruction.

[0066] WAIT_UART_DATA:

[0067] JNB (0x98.0), WAIT_UART_DATA; wherein 0x98.0 is the address of the RI (Receive Interrupt) of the serial communication interface, when the serial communication interface receives data, 0x98.0 is set to 1, that is, the RI is set to 1, indicating that the data is received at this time, and the next line of code is executed; when the serial communication interface does not receive data, 0x98.0 is set to 0, that is, the RI is set to 0, at this time, continue to wait for the host computer to send data. Here, the data can be a numerical value corresponding to an assembly language instruction, address data or upgrade data in an upgrade package.

[0068] CLR (0x98.0); clear the receive interrupt flag RI so that the next time the serial communication interface receives data, it can continue to generate a receive interrupt.

[0069] MOV A, 0x99; 0x99 is the address of SBUF, the data received from the serial communication interface is temporarily stored in SBUF. This line of code is used to copy the data in SBUF to register A (register A is accumulator ACC).

[0070] CJNE R0, #NONE_CMD, CURRENT_CMD_PROC; wherein NONE_CMD is 0H, that is, 0 in hexadecimal. When R0 is equal to 0, it means that there is no instruction being executed at the moment, and the next line of code is executed in order; when R0 is not equal to 0, it means that there is an instruction being executed at the moment, and the serial communication interface receives a numerical value that is not corresponding to an instruction, and CURRENT_CMD_PROC is executed.

[0071] MOV FLASH_IAP_ADDL_REG, DPL

[0072] MOV FLASH_IAP_ADDH_REG, DPH; wherein DPL and DPH are address registers, DPL is used to store the low address, and DPH is used to store the high address.

[0073] FLASH_IAP_ADDL_REG and FLASH_IAP_ADDH_REG are flash address registers, used to store the target flash address. This line of code is used to set the address in the address register to the target flash address. It should be noted that at this time, since the address data corresponding to the write address instruction has not been received, this line of code has not written the first flash address into the flash address register, that is, the first flash address has not been set as the target flash address. In the following, when the address data corresponding to the write address instruction is received and written into the flash address register, the first flash address can be set as the target flash address.

[0074] CMD_SET_ADDR:

[0075] CJNE A, #SET_ADDRESS_CMD, CMD_WRITE; if the data in register A is the value corresponding to the address setting instruction, execute the next line of code in sequence; if the data in register A is not the value corresponding to the address setting instruction, execute CMD_WRITE.

[0076] MOV R1, #0x02; where R1 is a register used to count the length of the received data, since the length of the address data is two bytes, R1 is assigned a value of 2 at this time.

[0077] SJMP CMD_END

[0078] CMD_END:

[0079] MOV R0, A; register R0 is used to store the instruction currently being executed, this line of code is used to indicate that the instruction in register A is the instruction currently being executed.

[0080] JMP WAIT_UART_DATA

[0081] CURRENT_CMD_PROC:

[0082] CJNE R0, #SET_ADDRESS_CMD, DATA_WRITE; when the data stored in R0 is the value corresponding to SET_ADDRESS_CMD, it indicates that the instruction currently being executed is the address setting instruction, and the next line of code is executed in sequence.

[0083] DEC R1; R1 is decremented.

[0084] CJNE R1, #0x0, ADR_HIGH; if R1 is not equal to 0, it means that the address data has not been received, i.e. the current received is the first byte of address data (i.e. the low 8-bit address) in the two bytes of address data, then execute ADR_HIGH. If R1 is equal to 0, it means that the address data has been received, then the next line of code is executed in sequence.

[0085] MOV DPH, A; store the second byte of address data to address register DPH.

[0086] MOV 0x99, R0; store the data in R0 to SBUF, the data in SBUF will be returned to the upper computer later. Here, the data is the value corresponding to SET_ADDRESS_CMD, which is used to indicate that the address data has been received.

[0087] MOV R0, #0x0

[0088] SJMP WAIT_UART_DATA

[0089] ADR_HIGH:

[0090] MOV DPL, A; put the first byte of data into address register DPL.

[0091] JMP WAIT_UART_DATA

[0092] In step 303, the MCU receives the erasing instruction sent by the host computer.

[0093] The erasing instruction is an assembly language instruction, and the erasing instruction is used to instruct to erase the first sector corresponding to the first flash memory address.

[0094] In step 304, the MCU erases the data in the first sector according to the erasing instruction.

[0095] In the embodiment of the present disclosure, the first flash memory address is the starting address of the first sector. For the 8051 MCU, before writing data into the flash memory, the data in the address to be written into the data needs to be erased first. Since the erasing is in units of sectors, in the process of erasing in the flash memory, sector alignment needs to be performed first, that is, before executing the erasing instruction, the starting address of a sector needs to be set as the target flash memory address.

[0096] When erasing the data in the first sector, the target flash memory address does not change, that is, after erasing the data in the first sector, the target flash memory address is still the first flash memory address, and the write command can be continued to write a frame of first target data into the flash memory. Since the length of a frame of first target data is equal to the sector size, after the data in the first sector is erased, a frame of first target data can be written from the first flash memory address. In this way, a frame of first target data can fill the first sector, effectively improving the utilization rate of the flash memory space.

[0097] Optionally, the method further includes: after erasing the data in the first sector, the MCU sends erasing completion indication information to the host computer, and the erasing completion indication information is used to indicate that the erasing instruction has been executed.

[0098] The specific implementation manner of steps 303 and 304 will be exemplarily described below in combination with the code. In the code, SECTOR_ERASE_CMD represents the erasing instruction;

[0099] FLASH_SECTOR_ERASE represents an erase command. In the following, the instruction word alone refers to the assembly language instruction sent by the host computer to the MCU, while the command refers to the assembly language instruction inside the MCU. In addition, the following will not repeat the comments on the code statements that have appeared in the previous text.

[0100] WAIT_UART_DATA:

[0101] JNB (0x98.0), WAIT_UART_DATA;

[0102] CLR (0x98.0)

[0103] MOV A, 0x99

[0104] CJNE R0, #NONE_CMD, CURRENT_CMD_PROC

[0105] MOV FLASH_IAP_ADDL_REG, DPL

[0106] MOV FLASH_IAP_ADDH_REG, DPH

[0107] CJNE A, #SECTOR_ERASE_CMD, CMD_READ; if the data in the current register A is an erase command, the next code is executed in sequence. If the data in the current register A is not an erase command, CMD_READ is executed.

[0108] MOV FLASH_IAP_CMD_REG, #FLASH_SECTOR_ERASE; FLASH_IAP_CMD_REG is a flash command register, used to store operation commands for flash, and the MCU will perform corresponding operations on the flash according to the operation commands stored in FLASH_IAP_CMD_REG, which includes erase commands or programming commands. Here, since FLASH_SECTOR_ERASE is an erase command, the MCU will erase the data in the sector corresponding to the target flash address.

[0109] MOV 0x99, A; store the data in register A to SBUF, so that the data in SBUF can be returned to the host computer later, and here the data is the value corresponding to SECTOR_ERASE_CMD, indicating that the erase command has been executed.

[0110] SJMP WAIT_UART_DATA

[0111] In step 305, the MCU receives the write data command sent by the host computer.

[0112] The details of the write data instruction are described in the foregoing step 201, and thus are omitted here.

[0113] In step 306, the MCU receives a frame of first target data according to the write data instruction.

[0114] The details of the frame of first target data are described in the foregoing step 201 and step 202, and thus are omitted here.

[0115] In step 307, the MCU stores the received frame of first target data into a buffer of the MCU.

[0116] Optionally, the buffer can be located in idata or xdata. The idata is an addressable in-chip RAM with a size of 256 bytes, and the xdata is an addressable off-chip RAM with a size of 128 bytes. When the length of the frame of first target data is equal to 128 bytes, the xdata or the idata is sufficient to store the frame of data as the buffer.

[0117] The receiving and storing of the frame of first target data by the MCU includes: after receiving the write data instruction, repeatedly performing the following steps until the frame of first target data is stored in the buffer: receiving one byte of data sent by the host computer, and storing the received data in a first register; and writing the data in the first register into the buffer.

[0118] The steps 305 to 307 are exemplarily described below by taking the buffer located in the xdata as an example and in combination with codes. In the codes in this part, WRITE_CMD represents the write data instruction.

[0119] WAIT_UART_DATA:

[0120] JNB (0x98.0), WAIT_UART_DATA;

[0121] CLR (0x98.0)

[0122] MOV A, 0x99

[0123] CJNE R0, #NONE_CMD, CURRENT_CMD_PROC

[0124] MOV FLASH_IAP_ADDL_REG, DPL

[0125] MOV FLASH_IAP_ADDH_REG, DPH

[0126] CMD_WRITE:

[0127] CJNE A, #WRITE_CMD, WAIT_UART_DATA

[0128] MOV R1, #READ_WRITE_LENGTH; Here, READ_WRITE_LENGTH is used to indicate the length of the first target data in a frame, i.e. the aforementioned target length. For example, READ_WRITE_LENGTH can be 80H, i.e. 128.

[0129] CMD_END:

[0130] MOV R0, A

[0131] JMP WAIT_UART_DATA

[0132] CURRENT_CMD_PROC:

[0133] CJNE R0, #SET_ADDRESS_CMD, DATA_WRITE;

[0134] DATA_WRITE:

[0135] CJNE R0, #WRITE_CMD, WAIT_UART_DATA; When R0 is the value corresponding to the write data instruction, it indicates that the write data instruction is received, and the next line of code is executed in sequence; when R0 is not the value corresponding to the write data instruction, it indicates that the received data is not a valid instruction, and the data is continued to be received.

[0136] CJNE R1, #READ_WRITE_LENGTH, WRITE_NEXT; When R1 is equal to 128, the next line of code is executed in sequence; when R1 is not equal to 128, WRITE_NEXT is executed.

[0137] MOV DPL, #0x0

[0138] MOV DPH, #0x0; In addition to being used as an address register, DPL and DPH can also be used as a DPTR register when they are combined. The DPTR register can be used as a pointer to access the cache located in xdata, so DPL and DPH are cleared to prepare for subsequent use of the DPTR register to access the cache.

[0139] WRITE_NEXT:

[0140] MOVX @DPTR, A; Store the one-byte data received in register A in the cache pointed to by the DPTR register. When storing for the first time, DPTR is 0, i.e. store one byte of data in 00H of xdata.

[0141] DEC R1

[0142] INC DPTR; After each byte of data is stored in the buffer, the DPTR register is incremented by 1, and the corresponding DPTR register points to the next address in the buffer, thus enabling a frame of data to be stored in the buffer byte by byte.

[0143] CJNE R1, #0x0, WAIT_UART_DATA; When R1 equals 0, it means that the data stored in the buffer has reached the target length; when R1 is not equal to 0, it means that the data stored in the buffer has not yet reached the target length, and data needs to be received.

[0144] In the example above, xdata in RAM is used as a buffer to temporarily store data from the serial port. Therefore, the DPTR register used to access the off-chip RAM is used as a pointer to store the data in xdata.

[0145] In other examples, idata is used as a buffer to temporarily store data from the serial port. In this case, the Rx registers (such as R0 to R7 registers, etc.) used to access the on-chip RAM can be used as pointers to store the data in idata.

[0146] In step 308, the MCU writes a frame of first target data from the cache to the flash memory.

[0147] Step 308 includes writing a frame of data from the cache to the flash memory using byte programming.

[0148] In this embodiment of the disclosure, since the erase instructions in steps 303 and 304 do not change the target flash memory address, the target flash memory address in step 308 is the aforementioned first flash memory address.

[0149] For example, the MCU writes a frame of data from the cache to the flash memory by: writing the first byte of data from the cache to the target flash memory address, incrementing the target flash memory address by 1; then writing the second byte of data to the incremented target flash memory address, and repeating this process until a frame of data is completely written to the flash memory, and then sending a write completion indication message to the host computer. This write completion indication message is used to indicate that the write data instruction has been executed.

[0150] The following example illustrates step 308 with reference to the code. In this part of the code, FLASH_BYTE_PROGRAM represents the programming command.

[0151] WRITE_PROG:

[0152] MOV DPL, #0x0

[0153] MOV DPH, #0x0

[0154] MOV R1, #READ_WRITE_LENGTH

[0155] PROG_LOOP:

[0156] DEC R1

[0157] CJNE R1, #0x0, PROG_CONT; When R1 is equal to 0, it indicates that the current frame data is written completely, and the next line of code is executed in sequence; when R1 is not equal to 0, it indicates that the current frame data is not written completely, and then PROG_CONT is executed to write data into the flash memory.

[0158] MOV 0x99, R0; The data in R0 is stored in SBUF to return the data in SBUF to the host computer. Here, the data is the value corresponding to WRITE_CMD, which is used to indicate that the write data instruction is executed.

[0159] MOV R0, #0x0

[0160] JMP WAIT_UART_DATA

[0161] PROG_CONT:

[0162] MOVX A, @DPTR; When this line of code is executed for the first time, since DPL and DPH are both cleared in the previous step, the value in the DPTR register is 0 at this time, that is, the data at address 00H in xdata is transferred to register A, and the data at address 00H in xdata is the data of the first byte in the received frame data.

[0163] MOV FLASH_IAP_DAT_REG, A; FLASH_IAP_DAT_REG is used to store the data to be programmed into the flash memory.

[0164] MOV FLASH_IAP_CMD_REG, #FLASH_BYTE_PROGRAM; Here, since FLASH_BYTE_PROGRAM is a programming command, the MCU will perform byte programming to write the data in FLASH_IAP_DAT_REG into the current target flash memory address.

[0165] INC DPTR; DPTR is incremented by 1, so that the data of the next byte to be written can be obtained.

[0166] INC FLASH_IAP_ADDL_REG; target flash address self plus 1, so that the next byte of data can be written to the next target flash address, realizing continuous writing of data into flash.

[0167] SJMP PROG_LOOP

[0168] END

[0169] For the subsequent MCU upgrade package of multiple frame data, only need to repeat the steps 301-307 for each frame data, that is, the MCU can write all data in the upgrade package into the flash of MCU.

[0170] It should be noted that in the embodiments of the present disclosure, each assembly language instruction needs to be assigned in advance, for example, each assembly language instruction is assigned by using an EQU assignment command, so as to realize the foregoing code. Illustratively, each assembly language instruction can be assigned in the following manner:

[0171] SECTOR_ERASE_CMD EQU 45H

[0172] SET_ADDRESS_CMD EQU 41H

[0173] READ_CMD EQU 48H

[0174] WRITE_CMD EQU 57H

[0175] FLASH_SECTOR_ERASE EQU 04H

[0176] FLASH_BYTE_PROGRAM EQU 02H

[0177] FLASH_IAP_CMD_REG EQU 0F9H

[0178] FLASH_IAP_DAT_REG EQU 0FAH

[0179] FLASH_IAP_ADDL_REG EQU 0FBH

[0180] FLASH_IAP_ADDH_REG EQU 0FCH

[0181] NONE_CMD EQU 0H

[0182] READ_WRITE_LENGTH EQU 80H

[0183] The values corresponding to SECTOR_ERASE_CMD, SET_ADDRESS_CMD, READ_CMD, WRITE_CMD, FLASH_SECTOR_ERASE or FLASH_BYTE_PROGRAM can also be the addresses of other unused addressable storage units in the RAM, and the embodiments of the present disclosure do not limit this. The values corresponding to FLASH_IAP_CMD_REG, FLASH_IAP_DAT_REG, FLASH_IAP_ADDL_REG or FLASH_IAP_ADDH_REG can also be replaced by other addresses in 0F8H-0FFH in the special function register, as long as the addresses corresponding to the four instructions are different.

[0184] When the upgrade package includes multiple frames of upgrade data, the host computer and the MCU repeatedly execute the flow in Figure 3 In this case, the instruction interaction flow between the host computer and the MCU is as shown in Figure 4

[0185] As shown in Figure 4 , for the first frame of data in the multiple frames of data:

[0186] The host computer sends a write address setting instruction (SET_ADDRESS_CMD) to the MCU, which is used to indicate that the first flash memory addresses addl0 and addh0 are set as the target flash memory addresses; the MCU sends a receiving completion indication information (SET_ADDRESS_CMD) to the host computer, which is used to indicate that the address data corresponding to the first flash memory address has been received. The host computer sends an erase instruction (ERASE_CMD) to the MCU, which is used to indicate that the data in the sector corresponding to the first flash memory address is erased; the MCU sends an erase completion indication information (ERASE_CMD) to the host computer, which is used to indicate that the data in the sector corresponding to the first flash memory address has been erased. The host computer sends a write data instruction (WRITE_CMD) and a frame of data (CODE0-CODE127) to the MCU, so as to write a frame of data into the sector corresponding to the first flash memory address; the MCU sends a write completion indication information (WRITE_CMD) to the host computer, which is used to indicate that the write data instruction is executed. In succession……

[0187] For the last frame of data in the multiple frames of data:

[0188] ​The host computer sends a write address setting instruction (SET_ADDRESS_CMD) to the MCU, where the write address setting instruction is used to indicate that the first flash memory address addln and addhn are set as the target flash memory address; the MCU sends the host computer with a receiving completion indication information. The host computer sends an erase instruction (ERASE_CMD) to the MCU; the MCU sends the host computer with an erase completion indication information (ERASE_CMD). The host computer sends a write data instruction (WRITE_CMD) and a frame of data (CODEn-CODEn+127) to the MCU; the MCU sends the host computer with a write completion indication information.

[0189] In the embodiment of the present disclosure, the write data instruction adopted by the host computer is an assembly language instruction, and the assembly language instruction occupies less computing resources of the MCU. The MCU can process the assembly language instruction by using less computing resources, which is beneficial to speed up the processing efficiency of the MCU on the write data instruction, thereby further improving the upgrading efficiency of the MCU.

[0190] In addition, in the embodiment of the present disclosure, the N bytes of data in a frame of first target data are written into the cache of the MCU according to the write data instruction, and then the N bytes of data in the frame of first target data in the cache are written into the flash memory. In this way, multiple bytes of data can be written into the flash memory of the MCU by using one write data instruction. In the related art, one write data instruction is usually used to indicate that one byte of data is written into the flash memory of the MCU. Therefore, the embodiment of the present disclosure can effectively reduce the number of write data instructions sent by the host computer to the MCU in one upgrading process, thereby improving the upgrading efficiency of the MCU.

[0191] Moreover, in the embodiment of the present disclosure, the write data instruction, the erase instruction, the address setting instruction and the read data instruction all adopt assembly language instructions, so the corresponding upgrading program code in the MCU is also written in assembly language. When the upgrading program is written in assembly language and the types of instructions issued by the host computer are only four, the data amount of the software program is very small, which can be less than 128 bytes, thereby the occupation of the flash memory storage space of the MCU can be reduced to the greatest extent.

[0192] Optionally, the host computer can also read data from the MCU, and the reading data can be performed before the MCU starts upgrading or after the upgrading is completed, which is not limited in the present disclosure. The reading process is described below. Figure 5 A flowchart of reading data from the MCU is shown in an example embodiment of the present disclosure, which is shown in FIG. 5. Figure 5 As shown in the figure, the reading data process includes the following steps.

[0193] In step 501, the MCU receives a read address setting instruction.

[0194] The read address setting instruction is an assembly language instruction, and the read address setting instruction is used to set the second flash address, and the second flash address is used to indicate a storage address of a frame of second target data in the flash memory.

[0195] Optionally, the frame of second target data includes N bytes of data, for example, the length of the frame of second target data is equal to the target length.

[0196] In step 502, the MCU receives the read address data according to the read address setting instruction.

[0197] The read address data is used to indicate the second flash address.

[0198] In step 503, the MCU receives the read data instruction.

[0199] The read data instruction is an assembly language instruction, and the read data instruction is used to read a frame of second target data.

[0200] In step 504, the MCU sends N bytes of data in the frame of second target data to the host computer according to the read data instruction.

[0201] In the embodiment of the present disclosure, the MCU sends N bytes of data in the frame of second target data to the host computer, including: the MCU obtains one byte of data from the target flash address (i.e. the second flash address) and sends it to the host computer; then, the target flash address becomes the next address of the second flash address, and the MCU sends one byte of data in the target flash address at this time to the host computer; repeat the above process of sending one byte of data to the host computer until N bytes of data are sent to the host computer, and stop sending data.

[0202] Since the read address setting instruction and the write address setting instruction are essentially the same, and the actions performed by the MCU are also the same, only steps 503 and 504 will be exemplarily described in combination with the code below. In this part of the code, READ_CMD represents the read data instruction.

[0203] WAIT_UART_DATA:

[0204] JNB (0x98.0), WAIT_UART_DATA

[0205] CLR (0x98.0)

[0206] MOV A, 0x99

[0207] CJNE R0, #NONE_CMD, CURRENT_CMD_PROC

[0208] MOV FLASH_IAP_ADDL_REG, DPL

[0209] MOV FLASH_IAP_ADDH_REG, DPH

[0210] CMD_READ:

[0211] CJNE A, #READ_CMD, CMD_SET_ADDR; When the current instruction is a read data instruction, execute the next line of code in sequence.

[0212] MOV R1, #READ_WRITE_LENGTH;

[0213] DATA_READ_CONT:

[0214] CLR (0x98.1); where 0x98.1 is the address of the TI (Transmit Interrupt) of the serial communication interface. When TI is 0, it means that there is no data to be sent at this time; when TI is 1, it means that the data transmission is complete. This line of code is used to clear TI, so that the next time the serial communication interface sends data, it can continue to generate a transmit interrupt.

[0215] MOV 0x99, A; After the data in register A is stored in SBUF, the data will be sent from the serial communication interface to the host computer. After sending one byte of data, 0x98.1 will be set to 1. When the data in SBUF is the value corresponding to READ_CMD, it is used to indicate that the MCU is about to start sending data.

[0216] UART_SEND:

[0217] JNB (0x98.1), UART_SEND;

[0218] CLR A; Clear register A.

[0219] MOVC A, @A+DPTR; Store the data stored in the address corresponding to A+DPTR in register A. Since register A has been cleared, it is actually storing the data in the address indicated by the DPTR register in register A. When sending data for the first time, the address indicated by the DPTR register is the second flash address mentioned above.

[0220] INC DPTR

[0221] DEC R1

[0222] CJNE R1, #0x0, DATA_READ_CONT; When R1 is equal to 0, execute the next line of code; when R1 is not equal to 0, execute DATA_READ_CONT, which means continue sending data.

[0223] AJMP WAIT_UART_DATA

[0224] It can be seen that when the data sent from the MCU to the host computer reaches 128 bytes, the address indicated by the DPTR register is the next flash memory address after the flash memory address where the 128th byte of data is located.

[0225] Optionally, the second target data may include at least one of the following: the current software program stored in the MCU, software version information, or read chip version information.

[0226] In some embodiments, if the second target data is the current software program stored in the MCU, then the second flash memory address corresponding to the read address setting instruction is the entry address of the current software program.

[0227] As mentioned earlier, after executing a read data instruction, the target flash memory address will become the next flash memory address after the flash memory address where the last data corresponding to the read data instruction is located. Since the software program in the MCU is stored continuously in the flash memory, when the host computer reads the current software program from the MCU, it only needs to send an address setting instruction once and then repeatedly send the read data instruction to obtain the entire software program.

[0228] like Figure 6 As shown, the second flash memory address corresponding to the read address setting instruction is the starting address x0 and x1 of the current software program, and the data CODE0 to CODEn+127 sent by the MCU to the host computer is all the data of the current software program.

[0229] In other embodiments, the second target data is software version information and / or chip version information, thereby enabling verification of whether the upgrade package version matches the software program in the MCU.

[0230] In one possible implementation, the software version information and chip version information in the MCU are stored at non-contiguous flash memory addresses in the MCU's flash memory. In this case, the MCU's software version information and chip version information can be obtained separately. Figure 7 As shown, when sending chip version information to the host computer, the second flash memory address corresponding to the read address setting instruction is the starting address x0x1 of the chip version information, and the current software program data sent by the MCU to the host computer is the chip version information data INF0~INFn+127.

[0231] When sending software version information to the host computer, such as Figure 7 As shown, the second flash memory address corresponding to the read address setting instruction is the starting address y0y1 of the software version information, and the current software program data sent by the MCU to the host computer is the software version information VER0~VERn+127.

[0232] After the MCU sends the chip version information and the sending software version information to the host computer, the host computer can realize the functions of software version control and software verification through the chip version information and the sending software version information.

[0233] It should be noted that in the embodiments of the present disclosure, the read address setting instruction and the write address setting instruction are the same instructions, which are distinguished according to different uses.

[0234] Figure 8 And Figure 9 A flowchart of the upgrading method of the MCU provided by the embodiments of the present disclosure is shown, referring to Figure 8 And Figure 9 The method comprises the following steps:

[0235] In step 801, it is judged whether the data receiving port receives data.

[0236] That is, the MCU waits for the host computer to send data.

[0237] If the data receiving port receives data, step 802 is executed; if the data receiving port does not receive data, step 801 is returned.

[0238] In step 802, the received data is stored in the register A.

[0239] In step 803, it is judged whether the received data is a new instruction.

[0240] If the received data is a new instruction, step 804 is executed; if the received data is not a new instruction, it is indicated that there is an instruction being executed at present, and the data receiving port receives data other than the instruction (for example, address data or data of an upgrading package), and step 813 is executed.

[0241] Here, whether the received data is a new instruction can be judged according to the value of the register R0, when the value of R0 is 0, it is indicated that the received data is a new instruction; when the value of R0 is not 0, it is indicated that the received data is not a new instruction.

[0242] Here, the new instruction can be the aforementioned write data instruction, read data instruction, address setting instruction or erase instruction.

[0243] In step 804, the address in the address register is set as a target flash memory address.

[0244] That is, the address data in the address register is copied to the flash memory address register.

[0245] In step 805, it is judged whether the data in the register A is an erase instruction.

[0246] If the data in the register A is an erase instruction, steps 806a and 806b are executed; if the data in the register A is not an erase instruction, step 807 is executed.

[0247] In step 806a, the erase instruction is executed.

[0248] The details of the execution of the erase instruction are described above in step 304, and are not repeated here.

[0249] In step 806b, the erase completion indication information is sent to the host computer.

[0250] After step 806b is executed, the MCU returns to the idle state and returns to step 801.

[0251] In step 807, it is determined whether the data in the register A is a read data instruction.

[0252] If the data in the register A is a read data instruction, step 808 is executed; if the received assembly language instruction is not a read data instruction, step 809 is executed.

[0253] In step 808, a frame of second target data is sent to the host computer according to the read data instruction, starting from the target flash memory address.

[0254] Optionally, step 808 includes steps 808a to 808d:

[0255] In step 808a, the length of the read data pointer is set.

[0256] The length of the read data pointer is the length of a frame of second target data.

[0257] In step 808b, data sending indication information is sent to the host computer.

[0258] In step 808c, one byte of data corresponding to the target flash memory address is sent to the host computer, and the read data pointer is decremented by 1 and the target flash memory address is incremented by 1.

[0259] In step 808d, it is determined whether the read data pointer is 0.

[0260] If the read data pointer is 0, the MCU returns to the idle state and returns to step 801; if the read data pointer is not 0, it means that a frame of second target data has not been read, and the process jumps to step 808c to continue sending the next byte of data to the host computer.

[0261] The details of the implementation of steps 808a-808d are described above in steps 503 and 504, and are not repeated here.

[0262] In step 809, it is determined whether the data in the register A is a write data instruction.

[0263] If the data in the register A is a write data instruction, steps 810a and 810b are executed, and if the data in the register A is not a write data instruction, step 811 is executed.

[0264] In step 810a, the length of the write data pointer is set.

[0265] In the embodiment of the present disclosure, the length of the write data pointer is the aforementioned target length.

[0266] In step 810b, the write data instruction is set as the instruction currently being executed.

[0267] The register R0 is used to store the instruction currently being executed, and thus setting the write data instruction as the instruction currently being executed means storing the value corresponding to the write data instruction into the register R0.

[0268] After step 810b is executed, step 801 is returned to, and the host computer is waited for to send data.

[0269] In step 811, it is judged whether the data in the register A is an address setting instruction.

[0270] If the data in the register A is an address setting instruction, steps 812a and 812b are executed, and if the data in the register A is not an address setting instruction, step 801 is returned. If it is not an address setting instruction, it means that the data received by the current data receiving port can be an invalid instruction, and in this case, the MCU does not need to make any processing, and directly returns to the idle state.

[0271] In step 812a, the length of the address length pointer is set.

[0272] In the embodiment of the present disclosure, the length of the address data is 2 bytes, and thus the length of the address length pointer is 2.

[0273] In step 812b, the address setting instruction is set as the instruction currently being executed.

[0274] After step 812b is executed, step 801 is returned to, and the host computer is waited for to send address data.

[0275] In step 813, it is judged whether the instruction currently being executed is an address setting instruction.

[0276] If the instruction currently being executed is an address setting instruction, step 814 is executed, and if the instruction currently being executed is not an address setting instruction, it means that the instruction currently being executed is a write data instruction, and step 815 is executed.

[0277] The address setting instruction in step 813 is actually the aforementioned write address instruction.

[0278] In step 814, the flash address indicated by the address setting instruction is set as the target flash address.

[0279] Optionally, step 814 includes steps 814a to 814e:

[0280] Step 814a, the address length pointer is decremented by 1.

[0281] Step 814b, it is judged whether the address length pointer is 0.

[0282] If the address length pointer is 0, it indicates that the address data of the second byte is received at this time, and then step 814d is executed; if the address length pointer is not 0, it indicates that the address data of the first byte is received at this time, and then step 814c is executed.

[0283] Step 814c, the received one-byte address data is stored to the DPL.

[0284] In the embodiment of the present disclosure, when the host sends the two-byte address data to the MCU, the host sends the one-byte low address data first, and then sends the one-byte high address data. Therefore, if the address length pointer is not 0, it indicates that the first byte of the address, that is, the low address data, is received, and thus the received one-byte address data is stored to the DPL.

[0285] Step 814d, the received one-byte address data is stored to the DPH.

[0286] It should be noted that, in the embodiment of the present disclosure, the low address register and the high address register are both address registers, and the two registers are continuously present on the storage unit of the RAM. Therefore, storing the two-byte address data to the low address register and the high address register respectively will not affect the continuity of the two-byte address data.

[0287] Step 814e, the receiving completion indication information is sent to the host.

[0288] After step 814e is executed, return to step 801 to wait for the host to send data.

[0289] In step 815, the data in the register A is stored to the cache until the data in the cache reaches the target length.

[0290] Optionally, step 815 includes steps 815a to 815e:

[0291] Step 815a, it is judged whether the length of the write data pointer is the target length.

[0292] When the length of the write data pointer is the target length, it indicates that the current received data is the first byte of a frame of data, and step 815b can be executed. When the length of the write data pointer is not the length of a frame of data, it indicates that the received byte of data is not the first byte of a frame of data, and step 815c is executed.

[0293] Here, the write data pointer is register Rl. It is determined whether the length of the write data pointer is the target length, i.e., whether the value of register Rl is equal to the target length.

[0294] Step 815b, the length of the write address pointer is set.

[0295] The write address pointer is used to indicate the address in the buffer, and thus when the received data is the first byte of data, the length of the write address pointer is set to 0, indicating that the first byte of data is stored in the first address in the buffer.

[0296] Here, the write address pointer is register DPTR.

[0297] Step 815c, the data in register A is stored in the address in the buffer corresponding to the write address pointer.

[0298] Step 815d, the write data pointer is decremented by 1, and the write address pointer is incremented by 1.

[0299] Step 815e, it is determined whether the write data pointer is 0.

[0300] If the write data pointer is 0, it indicates that the data in the buffer has reached the target length, and step 816 is executed. If the write data pointer is not 0, it indicates that the data in the buffer has not reached the target length, and the process returns to step 801 to wait for the next byte of data to be sent by the host computer.

[0301] The detailed implementation of steps 815a to 815e is described above in step 307, and thus is not described in detail here.

[0302] In step 816, a frame of data is written from the buffer to the flash memory.

[0303] Optionally, step 816 includes steps 816a to 816e:

[0304] Step 816a, the length of the write address pointer and the length of the write data pointer are set.

[0305] Optionally, the length of the write address pointer is 0, corresponding to the address in the buffer where the first byte of data in a frame of data is written. The length of the write data pointer is the target length.

[0306] Step 816b, it is determined whether the write data pointer is 0.

[0307] If the write data pointer is 0, it indicates that one frame of data has been written from the cache to the flash memory at this time, and step 816e is executed; if the write data pointer is not 0, it indicates that one frame of data has not been completely written from the cache to the flash memory at this time, and data needs to be continuously written from the cache to the flash memory, and step 816c is executed.

[0308] Step 816c: data of one byte corresponding to the write address pointer is written to the target flash memory address.

[0309] Step 816d: the write data pointer is decremented by 1, the write address pointer is incremented by 1, and the target flash memory address is incremented by 1.

[0310] After step 816d is executed, step 816b is executed, so that one frame of data in the cache can be written to the flash memory.

[0311] Step 816e: write completion indication information is sent to the upper computer.

[0312] Optionally, after step 816e is executed, step 801 is returned to.

[0313] The specific implementation of steps 816a to 816e is described above in the foregoing step 308, and detailed description is omitted here.

[0314] In the embodiments of the present disclosure, steps 805-806b are used to determine whether the data in the register A is an erase instruction, and to erase the data in the sector corresponding to the target flash memory address in the flash memory when the data in the register A is the erase instruction.

[0315] Steps 807-808 are used to determine whether the data in the register A is a read data instruction, and to send one frame of second target data to the upper computer when the data in the register A is the read data instruction.

[0316] Steps 809-810b are used to determine whether the data in the register A is a write data instruction, and to set the write data instruction as the instruction currently being executed when the data in the register A is the write data instruction.

[0317] Steps 811-812b are used to determine whether the data in the register A is an address setting instruction, and to set the address setting instruction as the instruction currently being executed when the data in the register A is the address setting instruction.

[0318] It should be noted that the order between the steps 805-806b, the steps 807-808, the steps 809-810b and the steps 811-812b can be changed, for example, it can be first determined whether the data in the register A is an erase instruction, then it can be determined whether the data in the register A is a read data instruction, then it can be determined whether the data in the register A is an address setting instruction, and finally it can be determined whether the data in the register A is a write data instruction. The embodiment of the present disclosure does not limit the specific order between the steps 805-806b, the steps 807-808, the steps 809-810b and the steps 811-812b.

[0319] Figure 10 The variation process schematic diagram of the state machine of the MCU upgrading method provided by the embodiment of the present disclosure is shown. Referring to Figure 10 , the MCU is in an idle state 901 (that is, corresponding to the foregoing step 801), if an address setting instruction is received, the MCU enters an address receiving state 902 (that is, corresponding to the foregoing step 814a); if an erase instruction is received, the MCU enters an erase state 903 (that is, corresponding to the foregoing step 806a); if a read data instruction is received, the MCU enters a read data state 904 (that is, corresponding to the foregoing step 808a); if a write data instruction is received, the MCU enters a data receiving state 905 (that is, corresponding to the foregoing step 815a) and a flash programming state 906 (that is, corresponding to the foregoing step 816a) in sequence. After the corresponding instruction is executed, the MCU returns to the idle state 901.

[0320] Before entering the idle state 901, the MCU will first perform communication interface hardware initialization.

[0321] Figure 11 is a structural schematic diagram of an MCU upgrading apparatus provided by the embodiment of the present disclosure. As shown in Figure 11 , the apparatus includes a receiving module 1001, a first storage module 1002 and a second storage module 1003.

[0322] The receiving module 1001 is configured to receive a write data instruction, the write data instruction being an assembly language instruction and being used to instruct to write a frame of first target data into a flash memory, the frame of first target data including N bytes of data, N being an integer greater than 1; the first storage module 1002 is configured to receive the frame of first target data according to the write data instruction and store the frame of first target data into a cache; and the second storage module 1003 is configured to write the frame of first target data from the cache into the flash memory of the MCU to upgrade the MCU.

[0323] Optionally, the receiving module 1001 is further configured to receive a write address setting instruction, the write address setting instruction being an assembly language instruction, the write address setting instruction being used to set a first flash memory address, the first flash memory address being used to indicate an address in the flash memory for storing the first target data; and receive write address data according to the write address setting instruction, the write address data being used to indicate the first flash memory address.

[0324] Optionally, the receiving module 1001 is further configured to receive an erase instruction, the erase instruction being used to instruct to erase a first sector corresponding to the first flash memory address. The apparatus further includes an erasing module 1004, which is configured to erase data in the first sector according to the erase instruction.

[0325] Optionally, the receiving module 1001 is further configured to receive a read data instruction, the read data instruction being an assembly language instruction, the read data instruction being used to read a second target data, the second target data including N bytes of data. The apparatus further includes a sending module 1005, which is configured to send the N bytes of data in the second target data according to the read data instruction.

[0326] Optionally, the receiving module 1001 is further configured to receive a read address setting instruction, the read address setting instruction being an assembly language instruction, the read address setting instruction being used to set a second flash memory address, the second flash memory address being used to indicate a storage address of the second target data in the flash memory.

[0327] Optionally, the receiving module 1001 is further configured to receive a read address setting instruction, the read address setting instruction being an assembly language instruction, the read address setting instruction being used to set a second flash memory address, the second flash memory address being used to indicate a storage address of the second target data in the flash memory.

[0328] It should be noted that the MCU upgrading apparatus provided in the above embodiments is used to upgrade the MCU, and only the division of the above functional modules is used as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the apparatus is divided into different functional modules to complete all or part of the functions described above. In addition, the MCU upgrading apparatus and the MCU upgrading method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be described here.

[0329] The division of the modules in the embodiments of the present disclosure is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, each functional module in each embodiment of the present disclosure can be integrated in one processor, or can be physically separated, or two or more modules can be integrated into one module. The above integrated module can be realized in the form of hardware or in the form of a software functional module.

[0330] The integrated module, if implemented in the form of a software function module and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such an understanding, the technical solutions of the present disclosure, essentially or in part, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for making a terminal device (which can be a personal computer, a mobile phone, or a communication device, etc.) or a processor execute all or part of the steps of the methods according to the embodiments of the present disclosure. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various other media that can store program codes.

[0331] Figure 12 is a structural schematic diagram of a computer device provided by an embodiment of the present disclosure. The computer device is the aforementioned MCU. As shown in the figure, the computer device 1100 includes a processor 1101 and a memory 1102. Figure 12

[0332] The processor 1101 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1101 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 1101 can also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU. The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 1101 can be integrated with a GPU (Graphics Processing Unit). The GPU is responsible for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 1101 can also include an AI (Artificial Intelligence) processor. The AI processor is used to process machine learning related computing operations.

[0333] The memory 1102 can include one or more computer readable storage media that can be non-transitory. The memory 1102 can also include a high-speed random access memory, and a non-volatile memory such as one or more disk storage devices, flash storage devices.

[0334] ​In some embodiments, the non-transitory computer-readable storage medium in the memory 1102 is configured to store at least one instruction for being executed by the processor 1101 to implement the MCU upgrading method provided in the embodiments of the present disclosure.

[0335] Those skilled in the art can understand that the structure shown in the figure is not a limitation on the computer device 1000, and the computer device 1000 can include more or fewer components than those shown in the figure, or combine certain components, or adopt a different arrangement of components. Figure 11

[0336] The embodiments of the present disclosure further provide a non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of a computer device, the computer device is enabled to perform the MCU upgrading method provided in the embodiments of the present disclosure.

[0337] The embodiments of the present disclosure further provide a computer program product, including computer programs / instructions, when the computer programs / instructions are executed by a processor, the MCU upgrading method provided in the embodiments of the present disclosure is implemented.

[0338] The above only describes optional embodiments of the present disclosure, and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.​

Claims

1. A method for upgrading an MCU, the method comprising: The method comprises: The MCU receives a write data instruction, the write data instruction is an assembly language instruction, and is used to instruct writing a frame of first target data into a flash memory, the frame of first target data comprises N bytes of data, N is an integer greater than 1; According to the write data instruction, the frame of first target data is received and stored into a cache of the MCU; The frame of first target data is written from the cache into the flash memory of the MCU to upgrade the MCU.

2. The method of claim 1, wherein, The receiving the frame of first target data and storing the frame of first target data into the cache comprises: The N bytes of data in the frame of first target data are received in sequence in byte units; After receiving one byte of data, the received data is stored into the cache until the frame of first target data is stored into the cache.

3. The method according to claim 1 or 2, characterized in that, The method further comprises: A write address setting instruction is received, the write address setting instruction is an assembly language instruction, the write address setting instruction is used to set a first flash memory address, and the first flash memory address is used to indicate an address in the flash memory for storing the frame of first target data; According to the write address setting instruction, write address data is received, and the write address data is used to indicate the first flash memory address.

4. The method of claim 3, wherein, Before receiving the write data instruction, the method further comprises: An erase instruction is received, the erase instruction is used to instruct erasing a first sector corresponding to the first flash memory address; According to the erase instruction, data in the first sector is erased.

5. The method according to any one of claims 1 to 2 and 4, characterized in that, The method further comprises: A read data instruction is received, the read data instruction is an assembly language instruction, and the read data instruction is used to read a frame of second target data, the frame of second target data comprises N bytes of data; According to the read data instruction, N bytes of data in the frame of second target data are sent.

6. The method of claim 5, wherein, The method further comprises: A read address setting instruction is received, the read address setting instruction is an assembly language instruction, and the read address setting instruction is used to set a second flash memory address, the second flash memory address is used to indicate a storage address of the frame of second target data in the flash memory; According to the read address setting instruction, read address data is received, and the read address data is used to indicate the second flash memory address.

7. The method according to any one of claims 1 to 2, 4 and 6, characterized in that, N is equal to a size of a sector in the flash memory.

8. An MCU upgrade apparatus, characterized by The apparatus comprises: A receiving module is configured to receive a write data instruction, the write data instruction is an assembly language instruction, and is used to instruct writing a frame of first target data into a flash memory, the frame of first target data comprises N bytes of data, N is an integer greater than 1; A first storage module is configured to receive the frame of first target data according to the write data instruction, and store the frame of first target data into a cache; A second storage module is configured to write the frame of first target data from the cache into the flash memory of the MCU to upgrade the MCU.

9. A computer device, comprising: The computer device comprises a memory and a processor, the memory stores at least one computer program, the at least one computer program is loaded and executed by the processor to implement the method in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the method in any one of claims 1 to 7.

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