A sample-and-hold circuit with signal division

Abstract

The application provides a sample-and-hold circuit with signal voltage division, comprising a sample-and-hold module and a control module; the sample-and-hold module comprises a plurality of capacitor units for storing charges and a switch unit connected with the capacitor units, and the switch unit is also connected with the control module; the control module is configured to output corresponding control signals in different working stages to control the conduction or turn-off of the switch unit, thereby changing the connection state of the capacitor units, so that the sample-and-hold module has at least a reset state, a sampling state and a holding voltage division state; in the sampling state, the capacitor units are connected with an input voltage to sample the input voltage and store charges; in the holding voltage division state, the connection relationship between the capacitor units is changed, so that the charges stored by the capacitor units in the sampling state are redistributed according to a preset proportion, thereby outputting a holding voltage proportional to the input voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more particularly to a sample-and-hold circuit with signal voltage divider. Background Technology

[0002] As integrated circuit manufacturing processes continue to advance towards deeper submicron levels, chip operating voltages are constantly decreasing, leading to the widespread application of high-speed, low-voltage signal processing circuits in various systems. However, in practical applications, systems often need to sample and process analog signals with high amplitudes, such as voltage signals from high-voltage detection nodes, power stage feedback nodes, or other high-level signal sources. The amplitude of such signals typically exceeds the input range that low-voltage chips can directly withstand.

[0003] To address the challenge of processing high-voltage signals in low-voltage chips, existing technologies typically employ resistor voltage dividers or operational amplifiers to attenuate the input signal before sampling. However, resistor voltage dividers are limited by resistor matching accuracy and temperature drift, making it difficult to achieve stable and reliable voltage division results in high-precision applications. Furthermore, resistor voltage dividers are susceptible to load effects during sampling, further reducing sampling accuracy. While operational amplifiers can improve accuracy, they significantly increase circuit area and power consumption, introduce additional bandwidth limitations and stability design issues, hindering the implementation of high-speed sampling systems and increasing system design complexity and cost. Summary of the Invention

[0004] The purpose of this invention is to provide a sample-and-hold circuit with signal voltage divider to solve the problems of insufficient accuracy and high circuit complexity faced by low-voltage sampling systems when sampling and holding high-voltage input signals.

[0005] This invention provides a sample-and-hold circuit with signal voltage division, including a sample-and-hold module and a control module;

[0006] The sample-and-hold module includes multiple capacitor units for storing charge and a switching unit connected to the capacitor units. The switching unit is also connected to the control module.

[0007] The control module is configured to output corresponding control signals at different working stages to control the switching unit to turn on or off, thereby changing the connection state of the capacitor unit, so that the sample-and-hold module has at least a reset state, a sampling state, and a holding voltage divider state.

[0008] In the sampling state, the capacitor unit is connected to the input voltage and is used to sample the input voltage and store charge.

[0009] In the holding voltage divider state, the connection relationship between the capacitor units changes, causing the charge stored in the capacitor units in the sampling state to be redistributed according to a preset ratio, thereby outputting a holding voltage proportional to the input voltage.

[0010] Optionally, it also includes:

[0011] A common-mode voltage generation module, connected to the switching unit, is used to provide a common-mode voltage to the capacitor unit in the holding voltage divider state and the reset state.

[0012] Optionally, during the process of switching from the sampling state to the holding voltage divider state, the end time of the sampling state is earlier than the start time of the holding voltage divider state, and there is a time interval between the end of the sampling state and the start of the holding voltage divider state, so as to reduce the error introduced by the switching unit during the state switching process.

[0013] Optionally, the plurality of capacitor units for storing charge include a first capacitor unit C1, a second capacitor unit C2, a third capacitor unit C3, and a fourth capacitor unit C4.

[0014] The first end of the first capacitor unit C1 is connected to the voltage input terminal through the switching unit, the second end of the first capacitor unit C1 is connected to the first end of the second capacitor unit C2, and the second end of the second capacitor unit C2 is connected to the voltage output terminal.

[0015] The first end of the third capacitor unit C3 is connected to the voltage input terminal through the switching unit, the second end of the third capacitor unit C3 is connected to the first end of the fourth capacitor unit C4, and the second end of the fourth capacitor unit C4 is connected to the voltage output terminal.

[0016] Optionally, the capacitance values ​​of the first capacitor unit C1 and the third capacitor unit C3 are equal, the capacitance values ​​of the second capacitor unit C2 and the fourth capacitor unit C4 are equal, and the capacitance value of the second capacitor unit C2 is k times the capacitance value of the first capacitor unit C1.

[0017] Optionally, the switching unit includes a first switch K1, a second switch K2, and a third switch K3;

[0018] The first switch K1 is disposed between the first capacitor unit C1 and the voltage input terminal, and the second switch K2 is disposed between the third capacitor unit C3 and the voltage input terminal;

[0019] One end of the third switch K3 is connected to the second end of the second capacitor unit C2, and the other end of the third switch K3 is connected to the second end of the fourth capacitor unit C4.

[0020] Optionally, the switching unit further includes:

[0021] The fourth switch K4 has one end connected to the first terminal of the first capacitor unit C1 and the other end connected to the common-mode voltage generating module.

[0022] The fifth switch K5 has one end connected to the second terminal of the second capacitor unit C2 and the other end connected to the common-mode voltage generating module;

[0023] The sixth switch K6 has one end connected to the first end of the third capacitor unit C3 and the other end connected to the common mode voltage generating module.

[0024] The seventh switch K7 has one end connected to the second terminal of the fourth capacitor unit C4 and the other end connected to the common-mode voltage generating module.

[0025] The eighth switch K8 has one end connected between the first capacitor unit C1 and the second capacitor unit C2, and the other end connected to the common-mode voltage generating module.

[0026] The ninth switch K9 has one end connected between the third capacitor unit C3 and the fourth capacitor unit C4, and the other end connected to the common-mode voltage generating module.

[0027] Optionally, the control module includes a first inverter A1, a second inverter A2, a third inverter A3, a first NAND gate NAND1, a second NAND gate NAND2, and a first delay unit;

[0028] The input terminal of the first inverter A1 is connected to the clock signal clk_in, the output terminal of the first inverter A1 is connected to the input terminal of the second inverter A2, and the output terminal of the first inverter A1 is also connected to the first input terminal of the second NAND gate NAND2.

[0029] The first input terminal of the first NAND gate NAND1 is connected to the output terminal of the second inverter A2, the second input terminal of the first NAND gate NAND1 is connected to the output terminal of the second NAND gate NAND2, and the output terminal of the first NAND gate NAND1 is connected to the input terminal of the first delay unit.

[0030] The output terminal of the first delay unit is connected to the input terminal of the third inverter A3, and the output terminal of the third inverter A3 outputs the first control signal S1;

[0031] The output of the first delay unit is also connected to the second input of the second NAND gate NAND2.

[0032] Optionally, the control module further includes a fourth inverter A4, a fifth inverter A5, a first NOR gate NOR1, a D flip-flop, a second delay unit, and a third delay unit;

[0033] The output of the second NAND gate NAND2 is connected to the input of the fourth inverter A4 through the second delay unit, and the output of the fourth inverter A4 is connected to the first input of the first NOR gate NOR1.

[0034] The second input terminal of the first NOR gate NOR1 is connected to the initial signal Rst, and the output terminal of the first NOR gate NOR1 outputs the second control signal S2 through the fifth inverter A5.

[0035] The clock terminal of the D flip-flop is connected to the output terminal of the first NAND gate NAND1, and the output terminal outputs the third control signal S3 through the third delay unit.

[0036] Optionally, the first control signal S1 is used to control the on / off state of the first switch K1 and the second switch K2, the second control signal S2 is used to control the on / off state of the eighth switch K8 and the ninth switch K9, the third control signal S3 is used to control the on / off state of the third switch K3, and the initial signal Rst is used to control the fourth switch K4, the fifth switch K5, the sixth switch K6 and the seventh switch K7.

[0037] The delay duration of the third delay unit is less than the delay duration of the first delay unit.

[0038] According to the present invention, by introducing a reconfigurable capacitor cell connection method in the sample-and-hold module, after the input voltage sampling is completed, the capacitor cells redistribute the stored charge according to a preset ratio during the hold phase, thereby directly outputting a hold voltage proportional to the input voltage in the hold state. By completing the sampling and voltage division processes within the same capacitor network, the additional error accumulation caused by relying on independent voltage divider or amplifier circuits in traditional solutions is avoided, which is beneficial for achieving stable and controllable sample-and-hold and signal voltage division functions with a relatively simple structure.

[0039] Furthermore, by introducing a common-mode voltage into the capacitor cell during both the holding voltage divider state and the reset state, the operating potential of each capacitor node is kept within a controlled range, effectively reducing the nonlinear error caused by node potential drift during charge redistribution. Simultaneously, introducing a clear time interval between the sampling state and the holding voltage divider state isolates the switching actions corresponding to different states in time, thereby reducing the impact of overlapping switching and transient coupling on sampling accuracy and contributing to improved consistency and repeatability of the holding voltage.

[0040] Furthermore, by rationally configuring the number of capacitor units, their capacitance ratios, and the connection methods of the switching units, the voltage division ratio is directly determined by the capacitor parameters. This avoids dependence on high-precision resistors or analog amplifier gains, enhancing the circuit's adaptability to process deviations and temperature changes. Combined with a control module featuring delay and logic control relationships, each switch operates according to a predetermined sequence at different operating stages. This ensures orderly switching between sampling, resetting, and holding the voltage division process, further suppressing dynamic errors introduced by state switching, and overall improving the accuracy and stability of the sample-and-hold circuit.

[0041] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below. Attached Figure Description

[0042] Figure 1 The voltage divider circuit of the inventor's preliminary scheme is shown in this application;

[0043] Figure 2 This application illustrates a voltage divider circuit for another preliminary design by the inventors.

[0044] Figure 3 A block diagram of a sample-and-hold circuit according to an embodiment of the present invention is shown;

[0045] Figure 4 A circuit topology diagram of a sample-and-hold module according to an embodiment of the present invention is shown;

[0046] Figure 5 A circuit topology diagram of a control module according to an embodiment of the present invention is shown;

[0047] Figure 6 Waveform diagrams of various signals according to an embodiment of the present invention are shown. Detailed Implementation

[0048] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0049] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0050] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0051] In the process of researching the aforementioned background technical problems, the inventors did not directly form the technical solution adopted in this application. Instead, they first followed the conventional thinking of those skilled in the art and made various attempts and verifications on existing voltage division and amplification methods.

[0052] Specifically, Figure 1 The voltage divider circuit of the inventor's preliminary scheme is shown. For example... Figure 1 As shown, the inventors first attempted to achieve signal processing by combining a resistor voltage divider network with an operational amplifier. In this scheme, the input voltage Vin is connected to ground through a voltage divider network formed by two resistors. The non-inverting input of the operational amplifier is connected between the two resistors, and the output of the operational amplifier is fed back to its inverting input to form a voltage follower structure. This scheme can achieve voltage division and buffering of the input signal to a certain extent, reducing the impact of the subsequent load on the voltage divider node, and improving the output driving capability compared to the pure resistor voltage divider method. However, this scheme still reveals obvious limitations in practical applications. On the one hand, the voltage division ratio depends entirely on the accuracy and matching characteristics of the resistors, and factors such as process deviations and temperature drift can easily introduce proportional errors. On the other hand, the operational amplifier's own offset voltage, input bias current, and noise, among other non-ideal factors, will be further amplified or superimposed in the divided signal, making it difficult to meet the error control requirements of high-precision sample-and-hold scenarios.

[0053] Building on this, the inventors further experimented with, for example... Figure 2The second approach, shown, uses an instrumentation amplifier structure to process the input signal. This approach, through a symmetrical structure of multiple amplifiers and resistor networks, can suppress common-mode interference to some extent and improve the impedance characteristics at the input, theoretically leading to better voltage division accuracy and signal consistency. Compared to the previous approach, this approach does achieve some improvement in anti-interference capability and input adaptability. However, this approach also introduces new problems: its circuit structure is complex and highly dependent on the matching relationship of multiple sets of resistors; any parameter deviation can disrupt the overall gain and voltage division ratio. Furthermore, the multi-stage amplification structure inevitably introduces additional power consumption and area overhead, and the cascading relationship between amplifiers makes system stability and dynamic response design more difficult. These problems are particularly prominent in high-integration, low-power, or high-speed sample-and-hold applications.

[0054] Building upon the aforementioned research, it can be seen that, in response to the technical problems raised in the background section, those skilled in the art, under the influence of conventional thinking, typically continue to optimize within the technical path of "resistor voltage divider—amplification buffer—high-precision amplifier structure." For example, they might attempt to combine the resistor voltage divider scheme with the instrumentation amplifier scheme, hoping to further improve the driving capability and anti-interference performance while maintaining the stability of the voltage division ratio. This approach essentially still revolves around the resistor network and amplifier structure, representing the performance superposition and parameter optimization of existing technical means. It is a relatively natural and intuitive direction for improvement for those skilled in the art when facing related problems.

[0055] However, after repeatedly verifying the above technical paths, the inventors realized that whether using a resistor-based voltage divider combined with an operational amplifier or employing a more complex instrumentation amplifier structure, the core remains the same: achieving voltage division through continuous-time analog amplification and resistor ratios. This makes it difficult to fundamentally escape the dependence on high-precision analog devices and parameter matching. Against this backdrop, the inventors broke free from the conventional thinking and did not continue with the resistor-based amplifier approach of superimposed optimization. Instead, they proposed a completely different design approach: utilizing the charge storage and redistribution characteristics of capacitors to complete the sampling and voltage division process at different time sequences using the same sample-and-hold module 20. This application's solution eliminates the need for an additional independent voltage divider module and does not rely on a continuous-time amplifier to amplify and correct the voltage division result. Instead, it uses a capacitor network to reconstruct the proportionality of the sampled charge during the hold phase, fundamentally changing the technical mechanism for achieving signal voltage division.

[0056] Because the solution in this application is not a simple combination or equivalent replacement of the two conventional solutions mentioned above, but rather adopts a design concept of integrated capacitor voltage division and sampling and holding that is not easily thought of under the background technology, it is fundamentally different from the aforementioned solutions based on resistors and amplifiers in terms of implementation method, error source and system structure.

[0057] Figure 3 A block diagram of a sample-and-hold circuit according to an embodiment of the present invention is shown. Figure 3 As shown, the sample-and-hold circuit includes a sample-and-hold module 20 and a control module 10. The sample-and-hold module 20 includes multiple capacitor units for storing charge and a switching unit 21 connected to the capacitor units. The switching unit 21 is also connected to the control module 10. The control module 10 is configured to output corresponding control signals at different operating stages to control the switching unit 21 to turn on or off, thereby changing the connection state of the capacitor units. This ensures that the sample-and-hold module 20 has at least a reset state, a sampling state, and a holding voltage divider state. In the sampling state, the capacitor units are connected to the input voltage to sample the input voltage and store charge. In the holding voltage divider state, the connection relationship between the capacitor units changes, causing the charge stored in the capacitor units in the sampling state to be redistributed according to a preset ratio, thereby outputting a holding voltage proportional to the input voltage.

[0058] According to the above embodiment, by introducing a reconfigurable capacitor unit connection method in the sample-and-hold module 20, after completing the input voltage sampling, the capacitor unit redistributes the stored charge according to a preset ratio during the hold phase, thereby directly outputting a hold voltage proportional to the input voltage in the hold state. By completing the sampling and voltage division processes within the same capacitor network, the additional error accumulation caused by relying on independent voltage divider circuits or amplifier circuits in traditional solutions is avoided, which is beneficial to achieving stable and controllable sample-and-hold and signal voltage division functions with a relatively simple structure.

[0059] In one embodiment, reference Figure 3 The sample-and-hold circuit also includes a common-mode voltage generation module. This module is connected to the switching unit 21 and is used to provide a common-mode voltage Vcm to the capacitor unit in both the holding voltage divider state and the reset state.

[0060] In this embodiment, by setting a common-mode voltage generation module and introducing the common-mode voltage Vcm to the capacitor cell when the circuit is in the hold-and-hold voltage divider state and the reset state, the capacitor cell can switch states around a stable reference potential in different operating stages, thereby avoiding floating or uncertain potentials at the capacitor node during switching. This structure helps to unify the potential starting point of the capacitor cell in the reset and hold-and-hold voltage divider stages, reduces transient disturbances introduced by potential transitions, and provides stable reference conditions for the subsequent charge redistribution process, thus helping to improve the consistency and stability of the sample-and-hold circuit in multiple operating cycles.

[0061] In one embodiment, during the transition from the sampling state to the holding voltage divider state, the end time of the sampling state is earlier than the start time of the holding voltage divider state, and there is a time interval between the end of the sampling state and the start of the holding voltage divider state, so as to reduce the error introduced by the switching unit 21 during the state transition.

[0062] In this embodiment, by introducing an independent transition time between the sampling state and the holding voltage divider state, the sampling action and the voltage divider action are separated in time, thereby avoiding the simultaneous participation of different switches in capacitor node reconstruction at the moment of state switching. This timing arrangement allows the charge redistribution process between capacitors to be initiated only after the sampling path related to the input voltage is completely disconnected, reducing transient errors caused by overlapping switch conduction, charge injection, and parasitic coupling, which is beneficial to improving the stability and repeatability of the output voltage during the holding voltage divider stage.

[0063] In one embodiment, the time when the input voltage is disconnected from the sample-and-hold module 20 is between the end of the sampling state and the start of the holding voltage divider state, that is, the time when the input voltage is disconnected is later than the end of the sampling state and earlier than the start of the holding voltage divider state.

[0064] In this embodiment, by setting the input voltage disconnection time after the sampling state ends and before the holding voltage divider begins, the input path disconnection process is not directly superimposed on the capacitor charge redistribution process, thus reserving buffer time for the complete release of the sampling path. This timing arrangement helps reduce the impact of input parasitic capacitance, charge injection, and switching coupling on the subsequent voltage divider process, allowing the capacitor unit to be in a more stable initial condition before entering the holding voltage divider stage, thereby improving the accuracy and consistency of the output holding voltage.

[0065] Figure 4 A circuit topology diagram of a sample-and-hold module 20 according to an embodiment of the present invention is shown. Figure 4 As shown, the multiple capacitor units for storing charge include a first capacitor unit C1, a second capacitor unit C2, a third capacitor unit C3, and a fourth capacitor unit C4. The first terminal of the first capacitor unit C1 is connected to a voltage input terminal via a switching unit 21, and the second terminal of the first capacitor unit C1 is connected to the first terminal of the second capacitor unit C2. The second terminal of the second capacitor unit C2 is connected to a voltage output terminal. The first terminal of the third capacitor unit C3 is connected to the voltage input terminal via the switching unit 21, and the second terminal of the third capacitor unit C3 is connected to the first terminal of the fourth capacitor unit C4. The second terminal of the fourth capacitor unit C4 is connected to a voltage output terminal.

[0066] In this embodiment, the sample-and-hold module 20 adopts a symmetrically configured capacitor structure, consisting of two sets of identical capacitor units arranged in parallel. This allows the input voltage signal to be input to the corresponding capacitor paths during the sampling phase, and a stable output voltage to be formed through charge redistribution between the capacitors during the holding voltage division phase. This topology facilitates balanced processing of the input voltage signal while ensuring controllable voltage division ratios, and provides a structural basis for subsequent differential spread or common-mode rejection, thereby improving the stability and consistency of the sample-and-hold process.

[0067] In one embodiment, the capacitance values ​​of the first capacitor unit C1 and the third capacitor unit C3 are equal, the capacitance values ​​of the second capacitor unit C2 and the fourth capacitor unit C4 are equal, and the capacitance value of the second capacitor unit C2 is k times the capacitance value of the first capacitor unit C1.

[0068] In this embodiment, by proportionally configuring the capacitance values ​​of different capacitor units, the charge stored during the sampling phase can be redistributed according to a predetermined ratio during the voltage division phase. This directly determines the proportional relationship between the output voltage and the input voltage at the structural level, i.e., output voltage = input voltage. 1 / (k+1). This method does not require the introduction of additional voltage divider components or amplifier circuits. It can achieve a stable and controllable voltage divider effect through the capacitor parameters themselves, which is beneficial to improving voltage divider accuracy and reducing the impact of device mismatch on overall performance.

[0069] In one embodiment, reference Figure 4 The switching unit 21 includes a first switch K1, a second switch K2, and a third switch K3. The first switch K1 is disposed between the first capacitor unit C1 and the voltage input terminal, and the second switch K2 is disposed between the third capacitor unit C3 and the voltage input terminal. One end of the third switch K3 is connected to the second terminal of the second capacitor unit C2, and the other end of the third switch K3 is connected to the second terminal of the fourth capacitor unit C4.

[0070] In this embodiment, the first switch K1 and the second switch K2 are used to control the connection between the first capacitor unit C1 and the third capacitor unit C3 and the voltage input terminal, respectively, so that the input voltage is introduced into the corresponding capacitor unit only during the sampling phase. The third switch K3 is located between the output sides of the second capacitor unit C2 and the fourth capacitor unit C4, and is used to establish the connection relationship between the two capacitor output terminals during the sampling phase or at the end of the sampling process. As the sampling phase ends, the third switch K3 is turned off, and the direct connection between the output capacitors is released, thereby maintaining the predetermined capacitor connection state during the subsequent voltage division phase, so that the voltage division process is determined only by the charge redistribution relationship between the capacitors, without introducing additional switching disturbances.

[0071] In one embodiment, reference Figure 4The switching unit 21 also includes a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, and a ninth switch K9. One end of the fourth switch K4 is connected to the first terminal of the first capacitor unit C1, and the other end is connected to the common-mode voltage generation module. One end of the fifth switch K5 is connected to the second terminal of the second capacitor unit C2, and the other end is connected to the common-mode voltage generation module. One end of the sixth switch K6 is connected to the first terminal of the third capacitor unit C3, and the other end is connected to the common-mode voltage generation module. One end of the seventh switch K7 is connected to the second terminal of the fourth capacitor unit C4, and the other end is connected to the common-mode voltage generation module. One end of the eighth switch K8 is connected between the first capacitor unit C1 and the second capacitor unit C2, and the other end is connected to the common-mode voltage generation module. One end of the ninth switch K9 is connected between the third capacitor unit C3 and the fourth capacitor unit C4, and the other end is connected to the common-mode voltage generation module.

[0072] In this embodiment, switches K4 to K7 are respectively located at the input or output terminals of each capacitor unit. These switches are used to force the endpoints of each capacitor unit to switch to the common-mode voltage in the reset state, ensuring that the capacitor units are at a consistent initial potential before entering the sampling state. Switches K8 and K9 are located at intermediate nodes between adjacent capacitor units. These switches are used to pull the intermediate nodes to the common-mode voltage in the voltage divider holding state, thereby defining the reference potential relationship between the capacitors and allowing the capacitor units to redistribute charge. Through the division of labor among these switches at different nodes, the capacitor units have clear potential control paths during the reset, sampling, and voltage divider holding stages, preventing residual charge or floating nodes from affecting the voltage divider results.

[0073] In some embodiments, the first switch K1, the second switch K2, the fourth switch K4, and the sixth switch K6, which are directly connected to the input voltage or high-potential node, are all high-voltage resistant switching devices, enabling them to operate reliably even when the input voltage is higher than the internal operating voltage of the sample-and-hold circuit. By selecting high-voltage resistant devices on critical high-voltage paths, the risk of breakdown or leakage due to insufficient device withstand voltage during sampling or reset can be avoided, thereby ensuring the safety and stability of the sample-and-hold circuit when processing high-amplitude input signals.

[0074] Figure 5 A circuit topology diagram of a control module 10 according to an embodiment of the present invention is shown. Figure 5As shown, the control module 10 includes a first inverter A1, a second inverter A2, a third inverter A3, a first NAND gate NAND1, a second NAND gate NAND2, and a first delay unit 11. The input of the first inverter A1 is connected to the clock signal clk_in. The output of the first inverter A1 is connected to the input of the second inverter A2, and the output of the first inverter A1 is also connected to the first input of the second NAND gate NAND2. The first input of the first NAND gate NAND1 is connected to the output of the second inverter A2, the second input of the first NAND gate NAND1 is connected to the output of the second NAND gate NAND2, and the output of the first NAND gate NAND1 is connected to the input of the first delay unit 11. The output of the first delay unit 11 is connected to the input of the third inverter A3, and the output of the third inverter A3 outputs a first control signal S1. The output of the first delay unit 11 is also connected to the second input of the second NAND gate NAND2.

[0075] In this embodiment, the control module 10 generates a first control signal S1 based on the clock signal clk_in through inversion, logic combination, and delayed feedback. The clock signal clk_in is first output after passing through the first inverter A1. One path is sent to the second inverter A2 to form an inverted signal, and the other path is directly sent to the second NAND gate NAND2, so that the control logic simultaneously obtains the clock information and its inverted signal at the same moment. At the same time, the output of the first NAND gate NAND1 is sent to the third inverter A3 after passing through the first delay unit 11. On the one hand, it is sent to the third inverter A3 to generate the first control signal S1, and on the other hand, it is fed back to the second input terminal of the second NAND gate NAND2, thereby forming a time-delay-based closed-loop control relationship between the first NAND gate NAND1 and the second NAND gate NAND2. Therefore, when the clock signal flips, the first NAND gate NAND1 generates a valid output only within a predetermined time window under the effect of delay feedback. Its output is then converted into the first control signal S1 by the third inverter A3, so that the first control signal S1 has a clear start time and end time, and avoids the introduction of uncertain control state due to clock edge jitter or logic competition.

[0076] In one embodiment, the clock signal clk_in is a periodic clock signal with a fixed frequency, ideally a square wave with a duty cycle of approximately 50%, used to provide a stable timing reference for the control module 10. Driven by the clock signal clk_in, each control signal is derived through logic and delay units to form a predetermined timing relationship, thereby ensuring that the sampling, reset, and voltage divider operation stages are performed in an orderly manner within each clock cycle.

[0077] In one embodiment, reference Figure 5The control module 10 also includes a fourth inverter A4, a fifth inverter A5, a first NOR gate NOR1, a D flip-flop, a second delay unit 12, and a third delay unit 13. The output of the second NAND gate NAND2 is connected to the input of the fourth inverter A4 through the second delay unit 12, and the output of the fourth inverter A4 is connected to the first input of the first NOR gate NOR1. The second input of the first NOR gate NOR1 is connected to the initial signal Rst, and the output of the first NOR gate NOR1 outputs the second control signal S2 through the fifth inverter A5. The clock input of the D flip-flop is connected to the output of the first NAND gate NAND1, the data input is connected to the power supply vdda, and the output output is the third control signal S3 through the third delay unit 13.

[0078] In this embodiment, based on the generation of the first control signal S1, the control module 10 further uses logic gates, flip-flops, and delay units to derive the timing of the remaining control signals. Specifically, the output of the second NAND gate NAND2 is used as one of the input signals of the first NOR gate NOR1 after passing through the second delay unit 12 and the fourth inverter A4, and is logically combined with the initial signal Rst, so that the second control signal S2 is only allowed to be effective after the reset state is released, thereby avoiding the accidental entry into the holding voltage divider state during the reset phase. At the same time, the output of the first NAND gate NAND1 is used as the clock signal of the D flip-flop, so that the state change of the third control signal S3 is strictly controlled by the edge of the sampling control signal, and its output time is delayed by the third delay unit 13. Through the above structure, the second control signal S2 and the third control signal S3 are constrained in time by the reset condition and the sampling end time, respectively, thereby forming a stable and repeatable timing relationship between the sampling, reset, and holding voltage divider stages.

[0079] In one embodiment, the first control signal S1 is used to control the on / off state of the first switch K1 and the second switch K2, the second control signal S2 is used to control the on / off state of the eighth switch K8 and the ninth switch K9, the third control signal S3 is used to control the on / off state of the third switch K3, and the initial signal Rst is used to control the fourth switch K4, the fifth switch K5, the sixth switch K6, and the seventh switch K7. The delay duration of the third delay unit 13 is less than the delay duration of the first delay unit 11.

[0080] In this embodiment, each control signal corresponds to a switch group with a different function, thus clearly distinguishing the sampling, reset, and holding voltage division processes at the structural level. Specifically, the first control signal S1 controls the switch connected to the input terminal, ensuring that the input voltage is introduced to the capacitor unit only during the sampling phase. The third control signal S3 controls the connection between the output-side capacitors, and its level change directly determines the end time of the sampling process. The second control signal S2 controls the connection between the intermediate node and the common-mode voltage, establishing a stable reference potential during the holding voltage division phase. By introducing different time delays for the different control signals, the third control signal S3 only passes through the third delay unit 13, and its delay duration is shorter than the delay duration of the first delay unit 11 through which the first control signal S1 passes, causing the level switching of the third control signal S3 to occur before that of the first control signal. Simultaneously, the second control signal S2 must pass through the first delay unit 11 and the second delay unit 12 sequentially, resulting in its level switching time being the latest. This creates a clear time sequence between the end of sampling and the start of holding voltage division, ensuring that the sampling action ends first, then the input path is disconnected, and finally the holding voltage division state is entered, thereby reducing the disturbance to the stored charge of the capacitor caused by the simultaneous switching of multiple switches.

[0081] Figure 6 A timing waveform diagram of various control signals according to an embodiment of the present invention is shown. Figure 6 As shown, when the initial signal Rst is high, the circuit is in a reset state. At this time, the first control signal S1 is low, keeping the switch connected to the input terminal open to prevent the input signal from entering the sampling path. The second control signal S2 and the third control signal S3 are high, switching each capacitor node to the common-mode voltage Vcm, thereby uniformly resetting the capacitor units and eliminating the residual charge from the previous working cycle.

[0082] As the initial signal Rst switches from high to low, the circuit exits the reset state and enters the sampling phase. The first control signal S1 goes high, allowing the input voltage to be introduced into the capacitor cell for sampling. During the sampling process, the control signals do not switch simultaneously but change in a strict sequence. The falling edge 'a' of the third control signal S3 arrives first, used to disconnect the capacitors on the output side in advance, thus clearly defining the sampling end time. Subsequently, the first control signal S1 falls, disconnecting the input terminal from the capacitor cell and preventing the input signal from continuing to inject charge into the capacitor in subsequent stages. Finally, the second control signal S2 rises, switching the relevant capacitor nodes to the common-mode voltage Vcm, and the circuit officially enters the hold-and-divide state. Through the above timing arrangement, the sampling end, input disconnection, and voltage division establishment unfold sequentially in time, forming an effective buffer between sampling and hold-and-divide, thereby reducing the charge injection and coupling errors introduced by multiple simultaneous switching, and improving the stability and consistency of the hold-and-divide results.

[0083] In practical applications, the control module 10 described above is only one specific implementation of the technical solution of this application, and its circuit structure is not uniquely limited. Depending on different application requirements, the specific circuit configuration of the control module 10 can be adjusted accordingly. As long as the falling edge a of the third control signal S3 is earlier than the falling edge b of the first control signal S1, and earlier than the rising edge c of the second control signal S2, the control effect required by this application can be achieved. The relevant implementation methods will not be elaborated upon here.

[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A sample-and-hold circuit with signal voltage divider, characterized in that, Includes a sample-and-hold module and a control module; The sample-and-hold module includes multiple capacitor units for storing charge and a switching unit connected to the capacitor units. The switching unit is also connected to the control module. The control module is configured to output corresponding control signals at different working stages to control the switching unit to turn on or off, thereby changing the connection state of the capacitor unit, so that the sample-and-hold module has at least a reset state, a sampling state, and a holding voltage divider state. In the sampling state, the capacitor unit is connected to the input voltage and is used to sample the input voltage and store charge; In the holding voltage division state, the connection relationship between the capacitor units changes, so that the charge stored in the capacitor units in the sampling state is redistributed according to a preset ratio, thereby outputting a holding voltage that is proportional to the input voltage; The control module includes a first inverter A1, a second inverter A2, a third inverter A3, a first NAND gate NAND1, a second NAND gate NAND2, and a first delay unit; The input terminal of the first inverter A1 is connected to the clock signal clk_in, the output terminal of the first inverter A1 is connected to the input terminal of the second inverter A2, and the output terminal of the first inverter A1 is also connected to the first input terminal of the second NAND gate NAND2. The first input terminal of the first NAND gate NAND1 is connected to the output terminal of the second inverter A2, the second input terminal of the first NAND gate NAND1 is connected to the output terminal of the second NAND gate NAND2, and the output terminal of the first NAND gate NAND1 is connected to the input terminal of the first delay unit. The output terminal of the first delay unit is connected to the input terminal of the third inverter A3, and the output terminal of the third inverter A3 outputs the first control signal S1; The output of the first delay unit is also connected to the second input of the second NAND gate NAND2; The control module also includes a fourth inverter A4, a fifth inverter A5, a first NOR gate NOR1, a D flip-flop, a second delay unit, and a third delay unit; The output of the second NAND gate NAND2 is connected to the input of the fourth inverter A4 through the second delay unit, and the output of the fourth inverter A4 is connected to the first input of the first NOR gate NOR1. The second input terminal of the first NOR gate NOR1 is connected to the initial signal Rst, and the output terminal of the first NOR gate NOR1 outputs the second control signal S2 through the fifth inverter A5. The clock terminal of the D flip-flop is connected to the output terminal of the first NAND gate NAND1, and the output terminal outputs the third control signal S3 through the third delay unit.

2. The sample-and-hold circuit according to claim 1, characterized in that, Also includes: A common-mode voltage generation module, connected to the switching unit, is used to provide a common-mode voltage to the capacitor unit in the holding voltage divider state and the reset state.

3. The sample-and-hold circuit according to claim 2, characterized in that, During the transition from the sampling state to the holding voltage divider state, the end time of the sampling state is earlier than the start time of the holding voltage divider state, and there is a time interval between the end of the sampling state and the start of the holding voltage divider state, so as to reduce the error introduced by the switching unit during the state transition.

4. The sample-and-hold circuit according to claim 2, characterized in that, The plurality of capacitor units for storing charge include a first capacitor unit C1, a second capacitor unit C2, a third capacitor unit C3, and a fourth capacitor unit C4. The first end of the first capacitor unit C1 is connected to the voltage input terminal through the switching unit, the second end of the first capacitor unit C1 is connected to the first end of the second capacitor unit C2, and the second end of the second capacitor unit C2 is connected to the voltage output terminal. The first end of the third capacitor unit C3 is connected to the voltage input terminal through the switching unit, the second end of the third capacitor unit C3 is connected to the first end of the fourth capacitor unit C4, and the second end of the fourth capacitor unit C4 is connected to the voltage output terminal.

5. The sample-and-hold circuit according to claim 4, characterized in that, The capacitance values ​​of the first capacitor unit C1 and the third capacitor unit C3 are equal, the capacitance values ​​of the second capacitor unit C2 and the fourth capacitor unit C4 are equal, and the capacitance value of the second capacitor unit C2 is k times the capacitance value of the first capacitor unit C1.

6. The sample-and-hold circuit according to claim 4, characterized in that, The switching unit includes a first switch K1, a second switch K2, and a third switch K3; The first switch K1 is disposed between the first capacitor unit C1 and the voltage input terminal, and the second switch K2 is disposed between the third capacitor unit C3 and the voltage input terminal; One end of the third switch K3 is connected to the second end of the second capacitor unit C2, and the other end of the third switch K3 is connected to the second end of the fourth capacitor unit C4.

7. The sample-and-hold circuit according to claim 6, characterized in that, The switching unit further includes: The fourth switch K4 has one end connected to the first terminal of the first capacitor unit C1 and the other end connected to the common-mode voltage generating module. The fifth switch K5 has one end connected to the second terminal of the second capacitor unit C2 and the other end connected to the common-mode voltage generating module; The sixth switch K6 has one end connected to the first end of the third capacitor unit C3 and the other end connected to the common mode voltage generating module. The seventh switch K7 has one end connected to the second terminal of the fourth capacitor unit C4 and the other end connected to the common-mode voltage generating module. The eighth switch K8 has one end connected between the first capacitor unit C1 and the second capacitor unit C2, and the other end connected to the common-mode voltage generating module. The ninth switch K9 has one end connected between the third capacitor unit C3 and the fourth capacitor unit C4, and the other end connected to the common-mode voltage generating module.

8. The sample-and-hold circuit according to claim 7, characterized in that, The first control signal S1 is used to control the on / off state of the first switch K1 and the second switch K2, the second control signal S2 is used to control the on / off state of the eighth switch K8 and the ninth switch K9, the third control signal S3 is used to control the on / off state of the third switch K3, and the initial signal Rst is used to control the fourth switch K4, the fifth switch K5, the sixth switch K6 and the seventh switch K7. The delay duration of the third delay unit is less than the delay duration of the first delay unit.

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