A method for enhancing resistance to quantum computing attacks

Abstract

The application provides an anti-quantum computing attack ability enhancement method, which comprises the following steps: obtaining computing power data, a security level identifier and a network delay value of a communication initiator, and receiving corresponding parameters sent by a communication responder; sending an encryption mode enabling instruction to the communication initiator and the communication responder according to a comparison result of the computing power data, a matching state of the security level identifier and a sum of the network delay values; controlling the communication initiator and the communication responder to generate a lattice-based public key parameter group and an elliptic curve temporary public key in parallel, inputting the public key parameter group into a key derivation function to generate a session key; and after writing an identification bit in a protocol header of the session key, when the encryption mode enabling instruction indicates a hybrid mode or a pure anti-quantum mode, optimizing an algorithm structure and hardware resources in cooperation, and enabling different encryption modes to combine the optimization of the algorithm and the hardware, so that the efficiency of anti-quantum computing can be ensured in the case of limited resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of information security, and in particular to an anti-quantum computing attack ability enhancement method. BACKGROUND

[0002] The current mainstream public key cryptography (such as RSA, ECC) is seriously threatened by quantum computing attacks (such as Shor algorithm), and traditional encryption methods may fail after the practicalization of quantum computers. Although anti-quantum cryptographic algorithms (such as lattice-based LWE, hash-based signature) have been proposed, the current anti-quantum cryptographic algorithms (such as lattice-based LWE algorithm) have a fundamental contradiction between computational efficiency and security strength in resource-constrained devices. Security requirement level: the development of quantum computers threatens traditional public key cryptography (such as RSA, ECC), and NIST standardized anti-quantum algorithms need to maintain high-dimensional parameters to ensure security strength; efficiency defect level: high-dimensional parameters lead to a sharp increase in algorithm computational complexity, resulting in delay exceeding the limit and power consumption exceeding the limit on low-power devices such as Internet of Things terminals.

[0003] Therefore, how to improve the computational efficiency of anti-quantum algorithms in resource-constrained devices while maintaining anti-quantum security strength has become a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0004] The present application provides an anti-quantum computing attack ability enhancement method to solve the defects of the prior art that cannot balance computational efficiency and security strength in resource-constrained devices.

[0005] In a first aspect, the present application provides an anti-quantum computing attack ability enhancement method, comprising:

[0006] Obtaining the computing power data, security level identifier and network delay value of the communication initiator, and receiving the corresponding parameters sent by the communication responder;

[0007] According to the comparison result of the computing power data, the matching state of the security level identifier and the sum of the network delay value, an encryption mode enabling instruction is sent to the communication initiator and the communication responder;

[0008] Controlling the communication initiator and the communication responder to generate a lattice-based public key parameter group and an elliptic curve temporary public key in parallel, and inputting the public key parameter group into a key derivation function to generate a session key;

[0009] After writing an identification bit in the protocol header of the session key, when the encryption mode enabling instruction indicates a hybrid mode or a pure anti-quantum mode, the algorithm structure and hardware resources are optimized in coordination;

[0010] Monitoring the cooperative optimized session data transmission volume and duration, triggering key update when exceeding the preset threshold, and injecting randomization instruction mask during key operation.

[0011] According to the anti-quantum computing attack ability enhancement method provided by the application, after receiving the corresponding parameters sent by the communication response party, the following steps are further included:

[0012] Calculating the difference between the communication initiator computing power data and the communication responder computing power data, and determining whether the difference exceeds a predefined computing power threshold;

[0013] Verifying whether the communication initiator security level identifier and the communication responder security level identifier belong to the same security category;

[0014] Adding the communication initiator network delay value and the communication responder network delay value to obtain the sum of the delay values.

[0015] According to the anti-quantum computing attack ability enhancement method provided by the application, the encryption mode enabling instruction is sent to the communication initiator and the communication responder, including:

[0016] When the difference does not exceed the computing power threshold and the security level identifiers of both parties are the preset high security category, or the sum of the delay values does not exceed the maximum delay threshold and the security level identifier of any one party is the preset high security category, send the instruction to enable the pure anti-quantum mode;

[0017] When the difference is within the predefined computing power interval, the security level identifiers of both parties belong to the same preset medium security category, and the sum of the delay values is within the predefined delay interval, send the instruction to enable the mixed mode;

[0018] When the difference exceeds the computing power threshold and the security level identifiers of both parties are the preset low security category, send the instruction to enable the pure traditional mode.

[0019] According to the anti-quantum computing attack ability enhancement method provided by the application, the instruction to enable the pure anti-quantum mode includes:

[0020] Performing lattice-based key exchange protocol in the key negotiation phase;

[0021] Using the highest security level LWE parameter set in the data transmission phase;

[0022] In the signature verification phase, SPHINCS and anti-quantum signature are used exclusively;

[0023] In the scheduling of all available hardware acceleration resources, anti-quantum operation tasks are preferentially processed.

[0024] According to the anti-quantum computing attack ability enhancement method provided by the application, the instruction enabling the mixed mode comprises:

[0025] The lattice-based key exchange and the traditional elliptic curve key exchange are executed in parallel in the key negotiation phase;

[0026] The lightweight LWE encryption algorithm is used in the data transmission phase;

[0027] The SPHINCS and the anti-quantum signature and the ECC signature are generated simultaneously in the signature verification phase.

[0028] According to the anti-quantum computing attack ability enhancement method provided by the application, the public key parameter group is input into the key derivation function to generate a session key, comprising:

[0029] The communication initiator calculates a first shared component based on the LWE private key vector and the received LWE public key parameter group of the responder;

[0030] The communication responder calculates a second shared component based on the LWE private key vector and the received LWE public key parameter group of the initiator;

[0031] The communication parties calculate a shared component based on the temporary public key through the elliptic curve protocol;

[0032] The first shared component or the second shared component is spliced with the elliptic curve shared component to obtain input data;

[0033] The input data is output through the key derivation function, and the first 128 bits are used as a session key, and the last 256 bits are used as a side channel protection mask.

[0034] According to the anti-quantum computing attack ability enhancement method provided by the application, the algorithm structure and the hardware resource are cooperatively optimized, comprising:

[0035] Parameter optimization and calculation simplification operations are performed in the algorithm structure layer;

[0036] Instruction acceleration and heterogeneous task allocation operations are performed in the hardware resource layer.

[0037] According to the anti-quantum computing attack ability enhancement method provided by the application, the parameter optimization and calculation simplification operations are performed in the algorithm structure layer, comprising:

[0038] The parameter matrix dimension of the lattice algorithm is reduced to a predefined lightweight range;

[0039] The standard deviation of the noise distribution is expanded to a predefined safety margin range;

[0040] A pre-stored constant matrix library is called to perform matrix multiplication operation;

[0041] Eliminate redundant modulo reduction calculation steps in the encryption process.

[0042] According to the anti-quantum computing attack ability enhancement method provided by the application, the instruction acceleration and heterogeneous task allocation operation are performed at the hardware resource layer, and the method comprises the following steps of:

[0043] sending a special instruction to the central processor to perform a lattice basis multiplication operation;

[0044] sending a special instruction to the central processor to perform a number theory transform operation;

[0045] when it is detected that the matrix operation amount exceeds the graphics processor acceleration threshold, sending a matrix block calculation task to the graphics processor;

[0046] when it is detected that the modulus operation amount exceeds the programmable gate array acceleration threshold, sending a modulus reduction pipeline task to the programmable gate array.

[0047] In a second aspect, the application provides an anti-quantum computing attack ability enhancement system, comprising:

[0048] The acquisition module is used to acquire the computing power data, the security level identifier and the network delay value of the communication initiator, and receive the corresponding parameters sent by the communication responder;

[0049] The selection module is used to send an encryption mode enabling instruction to the communication initiator and the communication responder according to the comparison result of the computing power data, the matching state of the security level identifier and the sum of the network delay values;

[0050] The generation module is used to control the communication initiator and the communication responder to generate a lattice-based public key parameter group and an elliptic curve temporary public key in parallel, and input the public key parameter group into a key derivation function to generate a session key;

[0051] The optimization module is used to write an identification bit in the protocol header of the session key, and when the encryption mode enabling instruction indicates a hybrid mode or a pure anti-quantum mode, the optimization module is used to optimize the algorithm structure and the hardware resources in cooperation;

[0052] The update module is used to monitor the session data transmission amount and the duration after the cooperation and optimization, trigger key update when the preset threshold is exceeded, and inject a randomization instruction mask during key operation.

[0053] In a third aspect, the application further provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the anti-quantum computing attack ability enhancement method according to any one of the above aspects when executing the program.

[0054] In a fourth aspect, the present application also provides a non-transitory computer-readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the anti-quantum-computing-attack-enhanced method according to any one of the above aspects.

[0055] In a fifth aspect, the present application also provides a computer program product comprising a computer program, which, when executed by a processor, implements the anti-quantum-computing-attack-enhanced method according to any one of the above aspects.

[0056] The anti-quantum-computing-attack-enhanced method provided by the present application comprises the following steps: obtaining computing power data, a security level identifier and a network delay value of a communication initiator, and receiving corresponding parameters sent by a communication responder; sending an encryption mode enabling instruction to the communication initiator and the communication responder according to a comparison result of the computing power data, a matching state of the security level identifier and a sum of the network delay values; controlling the communication initiator and the communication responder to generate a lattice-based public key parameter group and an elliptic curve temporary public key in parallel, inputting the public key parameter group into a key derivation function to generate a session key; after writing an identification bit in a protocol header of the session key, when the encryption mode enabling instruction indicates a hybrid mode or a pure anti-quantum mode, optimizing the algorithm structure and the hardware resources in coordination; monitoring the session data transmission volume and the duration after the coordination and optimization, triggering a key update when a preset threshold is exceeded, and injecting a randomization instruction mask during the key operation, so that the efficiency of anti-quantum computing can be ensured even in the case of limited resources by enabling different encryption modes in combination with the optimization of algorithms and hardware. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0058] Figure 1 is a flowchart of the anti-quantum-computing-attack-enhanced method provided by the present embodiment;

[0059] Figure 2 is a structural diagram of the anti-quantum-computing-attack-enhanced system provided by the present embodiment;

[0060] Figure 3 is a structural diagram of the electronic device provided by the present embodiment. DETAILED DESCRIPTION

[0061] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in conjunction with the drawings in the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0062] Figure 1 FIG. 1 is a flowchart of the anti-quantum computing attack ability enhancement method provided by the present embodiment.

[0063] As shown in FIG. 1, the anti-quantum computing attack ability enhancement method provided by the present embodiment mainly includes the following steps: Figure 1

[0064] 101, obtaining computing power data, security level identifier and network delay value of a communication initiator, and receiving corresponding parameters sent by a communication responder.

[0065] In a specific implementation process, the communication initiator collects core data reflecting computing power by calling the underlying interface of its own system, including but not limited to the real-time computing power of the processor (CPU / GPU), the memory resource occupation situation and the state of the hardware acceleration resources (such as special encryption chips) available for cryptographic operation. This process does not require human intervention and automatically completes data aggregation through system native instructions, ensuring that the obtained computing power data truly reflects the current processing capacity of the device, providing a hardware performance basis for subsequent algorithm mode selection, and avoiding efficiency bottlenecks when deploying anti-quantum algorithms due to limited device resources.

[0066] The security level identifier is generated by the communication initiator according to a preset rule or user configuration. The identifier corresponds to the security requirements of the communication scenario (such as military level, civilian level, etc.), directly reflecting the requirement for encryption strength. The identifier is obtained through system internal configuration file reading or special security module calling, ensuring the accuracy and tamper resistance of the security level, providing a security requirement benchmark for the dynamic selection engine, and ensuring that the selected algorithm matches the security strength and application scenario.

[0067] The communication initiator records the difference between the data packet sending time and the response receiving time by sending a preset format of probe data packet to the communication responder, and obtains the network delay value through simple calculation. The probe process supports multiple sampling and averaging to reduce the influence of network fluctuations on delay measurement, ensuring that the obtained network delay data can truly reflect the current communication link status, providing a network environment basis for selecting an algorithm mode that takes into account real-time performance, and avoiding communication lag due to excessively high network delay.

[0068] ​The communication initiator encapsulates the obtained computing power data, security level identifier, and network delay value into a standard parameter message, and sends it to the communication responder through an initial handshake channel; at the same time, the communication initiator opens a receiving channel to receive the computing power data, security level identifier, and network delay value of the responder sent in the same format. The parameter interaction process adopts a lightweight verification mechanism (such as simple hash verification) to ensure data integrity and avoid parameter transmission errors affecting subsequent decisions. Through the mutual transmission of parameters by both parties, the dynamic selection engine can make algorithm mode decisions based on the device performance, security requirements, and network conditions of both parties, ensuring the consistency of algorithm selection by both parties, reducing negotiation conflicts, and improving the compatibility and dynamic adaptability of the communication protocol.

[0069] Through the comprehensive and accurate acquisition of key environmental parameters by both parties, the dynamic selection engine provides complete input, realizes intelligent adaptation of algorithm modes, ensures the security of anti-quantum attacks, takes into account the communication efficiency in different devices and network environments, and improves the dynamic adaptability and compatibility of the cryptographic system.

[0070] 102. According to the comparison result of the computing power data, the matching state of the security level identifier, and the sum of the network delay values, an encryption mode enabling instruction is sent to the communication initiator and the communication responder.

[0071] Specifically, the dynamic selection engine first receives the computing power data, security level identifier, and network delay value of both parties, calculates the difference of the computing power data (such as the absolute difference of the computing power of the initiator and the responder), sums the network delay values (the sum of the delay from the initiator to the responder and the reverse delay), and extracts the category information of the security level identifier of both parties (high, medium, and low security categories). This process is automatically completed by a preset numerical processing module without human intervention, ensuring the accuracy of parameter calculation, providing standardized data for subsequent threshold comparison, and improving decision-making efficiency.

[0072] The dynamic selection engine first checks whether the computing power difference exceeds the preset computing power threshold, and whether the security level identifiers of both parties belong to the preset high security category. If the conditions are met, it means that the device performance of both parties is sufficient to support high-complexity anti-quantum algorithms, and the security requirements match. At this time, the instruction to enable pure anti-quantum mode is sent to ensure that the communication security reaches the highest level, while avoiding the efficiency loss caused by insufficient computing power. If the above conditions are not met, the sum of the network delays is checked to see if it exceeds the maximum delay threshold, and whether the security level identifier of either party is the preset high security category: if the conditions are met, it means that even if one party has high security requirements and the network link can support the real-time performance of anti-quantum algorithms, sending the pure anti-quantum mode instruction can ensure the security requirements of the key party while reducing the time overhead of algorithm execution by taking advantage of the low delay characteristics of the network.

[0073] When the computing power difference is in the predefined computing power interval (neither meets the low difference requirement of the pure quantum resistance mode nor reaches the high difference standard of the pure traditional mode), the security level identifiers of both parties belong to the same preset medium security category, and the sum of the delay values is in the predefined delay interval (neither meets the low delay requirement of the pure quantum resistance mode nor exceeds the acceptable delay range of the mixed mode), the dynamic selection engine determines that the performance, security requirements and network conditions of the devices of both parties are in a balanced state, and sends an instruction to enable the mixed mode. In this mode, the quantum resistance algorithm and the traditional algorithm run in parallel, which can meet the medium security requirements through the quantum resistance layer and improve the efficiency through the traditional layer, adapt to the resource limitations of medium computing power devices, and at the same time avoid affecting the communication experience due to high delay.

[0074] If the computing power difference exceeds the preset computing power threshold, and the security level identifiers of both parties are the preset low security category, it means that the performance gap between the devices of both parties is large (such as one is a low computing power terminal and the other is a high performance server), and the security requirement is low. At this time, an instruction to enable the pure traditional mode is sent, which can fully utilize the high efficiency of the traditional algorithm, reduce the resource occupation of the high complexity quantum resistance algorithm to the low computing power device, reduce the communication delay, and at the same time ensure the compatibility of both parties through the unified traditional encryption mechanism, avoiding the failure of negotiation due to the mismatch of algorithm complexity.

[0075] The encryption mode enabling instruction is transmitted through the algorithm identifier bit reserved by the protocol layer, ensuring that both parties receive and analyze the instruction at the same time, avoiding communication interruption caused by asynchronous mode switching. After the execution of the instruction, the devices of both parties automatically load the algorithm modules of the corresponding mode (such as loading lattice algorithm for pure quantum resistance mode, and loading lattice and traditional algorithms for mixed mode), and confirm the success of mode enabling through a short feedback message. This synchronization mechanism guarantees the consistency of the encryption modes of both parties, improves the dynamic adaptability of the protocol, seamlessly connects the algorithm switching process, and reduces the risk of connection failure caused by mode conflict.

[0076] The dynamic selection engine can accurately match the optimal encryption mode according to the comprehensive judgment of device performance, security requirements and network conditions, maximize the use of device resources, optimize communication efficiency, and achieve the balance between quantum resistance security and system compatibility while meeting the security requirements of different scenarios.

[0077] The instruction to enable the pure quantum resistance mode includes: executing lattice-based key exchange protocol in the key negotiation phase; using the highest security level LWE parameter set in the data transmission phase; exclusively using SPHINCS and quantum resistance signature in the signature verification phase; and preferentially processing quantum resistance operation tasks by scheduling all available hardware acceleration resources.

[0078] Specifically, the key negotiation phase implements a lattice-based key exchange protocol: in a pure quantum-resistant mode, the communication parties abandon traditional key exchange algorithms and only use a lattice-based quantum-resistant key exchange protocol (such as an LWE-related protocol) to complete key negotiation. Each party generates a public key and a private key pair that meets the lattice-based cryptography standard, exchanges the public key through a preset protocol process, calculates a shared key material based on the public key of the other party and the private key of itself, and finally generates a session key through a key derivation function (KDF). This process only relies on quantum-resistant algorithms, avoids the security risks of traditional algorithms under quantum computing attacks, ensures that the key calculation logic of both parties is consistent through the format constraints of the protocol layer, guarantees the security and uniqueness of key negotiation, and lays a quantum-resistant security foundation for subsequent data transmission.

[0079] The data transmission phase uses the highest security level LWE parameter set: after entering the data transmission phase, the encryption module automatically loads the highest security level LWE parameter set (such as optimized high-dimensional, high-noise tolerance parameters) for encryption operations on plaintext data. This parameter set improves resistance to quantum algorithms (such as Shor's algorithm and lattice reduction algorithms) by increasing problem size and noise complexity, ensuring that encrypted data is difficult to be cracked by quantum computing in the long term. At the same time, the pre-computed random matrix in the parameter set can reduce real-time computational load, balance security and transmission real-time performance, and reduce efficiency loss caused by parameter complexity under the premise of ensuring the highest security level.

[0080] The signature verification phase exclusively uses SPHINCS and quantum-resistant signatures: in the signature and verification stage (such as certificate verification in TLS handshake) of the communication process, the system closes the calling interface of traditional signature algorithms (such as ECC) and only enables SPHINCS+ quantum-resistant signature algorithm. The sender signs the data digest using its private key, and the receiver verifies the validity of the signature using the sender's quantum-resistant public key. This exclusive mechanism avoids the risk of traditional signature being cracked by quantum attacks, ensures the quantum-resistant security of identity authentication and data integrity verification, and at the same time, the hash chain structure design of SPHINCS+ can improve the efficiency of signature verification and reduce the verification delay in pure quantum-resistant mode.

[0081] Scheduling all available hardware acceleration resources to prioritize anti-quantum operation tasks: After receiving the pure anti-quantum mode instruction, the hardware resource scheduling module automatically scans and aggregates all available hardware acceleration resources in the current device (such as FPGA encryption cores supporting lattice operations, RISC-V CPUs integrating NTT instructions, and special ASIC signature chips), and marks anti-quantum operation tasks (such as LWE matrix multiplication and SPHINCS+ hash calculation) as the highest priority. The scheduler dynamically allocates operation tasks according to the adaptability of the task type (such as encryption and signature) and the hardware resource (such as FPGA's good at parallel matrix operations), ensuring that hardware resources are tilted towards anti-quantum operations. This mechanism fully utilizes the acceleration capabilities of special hardware, reduces the delay caused by the high computational complexity of anti-quantum algorithms, improves the overall communication efficiency in pure anti-quantum mode, and makes the execution performance of high-security level encryption on resource-rich devices close to that of traditional algorithms.

[0082] The pure anti-quantum mode can achieve anti-quantum attack protection in the whole process of key agreement, data transmission, and identity verification, while balancing security and efficiency with parameter optimization and hardware acceleration to ensure that the communication system can resist quantum computing threats and maintain stable operation performance in high-security demand scenarios such as military communication and sensitive data transmission.

[0083] Among them, the instructions for enabling the mixed mode include: performing lattice-based key exchange and traditional elliptic curve key exchange in parallel in the key agreement phase; using lightweight LWE encryption algorithm in the data transmission phase; generating SPHINCS and anti-quantum signature and ECC signature in the signature verification phase.

[0084] Specifically, the key agreement phase performs lattice-based key exchange and traditional elliptic curve key exchange in parallel: In the mixed mode, the key agreement module simultaneously starts two independent key generation links, one based on lattice-based anti-quantum key exchange protocol (such as LWE-related protocol), and the other based on traditional elliptic curve (ECC) key exchange protocol. Both parties generate a lattice public / private key pair and exchange public keys, and derive shared key material through lattice operations. The other party generates an ECC public / private key pair and completes elliptic curve point exchange, calculating the ECC shared key material. The two links are executed in parallel and do not interfere with each other, and finally the two key materials are fused by a unified key derivation function (KDF) to generate a unique session key. This parallel mechanism not only preserves the long-term security of anti-quantum algorithms, but also improves the key agreement speed with the help of ECC's efficiency, while the KDF fusion process ensures the key consistency when the two algorithms are executed in parallel, avoiding agreement conflicts and adapting to the performance requirements of medium-power devices.

[0085] The data transmission stage adopts a lightweight LWE encryption algorithm: during data transmission, the encryption module automatically loads an optimized lightweight LWE algorithm: by compressing the parameter dimension (such as reducing the matrix size), precomputing commonly used random matrices, and removing redundant modulo operation steps, the calculation amount is reduced while the quantum-resistant strength is maintained by increasing the noise tolerance. The lightweight design significantly reduces the running delay of LWE encryption on low-power devices (such as Internet of Things terminals), while retaining the core ability to resist quantum attacks, achieving a balance between "security not downgrading and efficiency acceptable". Compared with the pure quantum-resistant mode, this algorithm can reduce device resource occupation and avoid transmission lag caused by insufficient computing power, adapting to scenarios with large fluctuations in network environment.

[0086] The signature verification stage simultaneously generates SPHINCS and quantum-resistant signatures and ECC signatures: in the signature link, the sender's signature module simultaneously calls two types of signature algorithms: using SPHINCS and quantum-resistant private keys to generate quantum-resistant signatures for data digest, and using ECC private keys to generate traditional signatures, and the two types of signatures are packaged and sent with the data. When the receiver verifies, the corresponding verification interface is enabled simultaneously, and the validity of the two types of signatures is verified through the SPHINCS+ public key and the ECC public key, respectively. As long as one type of signature verification passes (or according to the double verification pass condition set by the security level requirement), the data integrity and the legitimacy of the sender's identity are confirmed. This double signature mechanism not only resists quantum attacks through SPHINCS, but also guarantees compatibility and verification efficiency in traditional environments through ECC, avoiding the limitations of a single signature algorithm in mixed scenarios, and improving the flexibility and security of the signature verification link.

[0087] The mixed mode retains the core ability of quantum-resistant security while taking advantage of the efficiency and compatibility of traditional algorithms to reduce the requirements for device computing power and network environment, achieving a dynamic balance between security and efficiency, and being suitable for cross-device communication scenarios from servers to lightweight terminals, providing a feasible path for the smooth transition of quantum-resistant cryptographic systems.

[0088] 103. Controlling a communication initiator and a communication responder to generate a lattice-based public key parameter set and an elliptic curve temporary public key in parallel, and inputting the public key parameter set into a key derivation function to generate a session key.

[0089] Specifically, when the dynamic selection engine determines to enable the hybrid mode, a parallel generation instruction is sent to the key generation modules of the communication initiator and the responder. After receiving the instruction, the key generation modules of the devices of the two parties automatically divide independent computing resources (such as CPU cores, memory areas) to be respectively used for lattice-based public key parameter group generation and elliptic curve (ECC) temporary public key generation, so as to ensure that the two types of key generation processes do not occupy resources at the hardware level and avoid operation conflicts. The resource isolation mechanism guarantees the efficiency of parallel processing, greatly shortens the total key generation time compared with the serial generation mode, and improves the real-time performance of key agreement in the hybrid mode.

[0090] In the allocated dedicated resources, the devices of the two parties generate a public key parameter group according to a preset lattice-based cryptography standard (such as LWE related specifications): a random matrix is first generated as a basic parameter, and a public key component is calculated by combining a private key (a random vector) and a noise vector, and finally a complete lattice-based public key parameter group (including a matrix and a corresponding public key value) is formed. During the generation process, the real-time operation amount is reduced by calling a precomputed random matrix library, and the matrix multiplication step is optimized by using a hardware acceleration instruction (such as lwe_mul), so as to improve the generation efficiency on the premise of ensuring quantum resistance, and ensure that the lattice-based public key parameter group can resist quantum attacks and be quickly generated.

[0091] In another set of independent resources, the devices of the two parties generate a temporary key pair based on a preset elliptic curve parameter (such as a curve type and a base point): a private key (an integer) is randomly selected, and a public key (a point on the curve) is obtained by elliptic curve point multiplication operation (multiplication of the private key and the base point), that is, an elliptic curve temporary public key. During the generation process, the operation is quickly completed by virtue of the lightweight characteristics (low computational complexity) of the ECC algorithm, and the generation time is further shortened by using the native support of the hardware for the elliptic curve operation (such as a special instruction set). The short-term validity design of the temporary public key (only used for the current session) reduces the long-term exposure risk, and the efficiency and security of the traditional algorithm are taken into account.

[0092] After the generation of the two types of public keys is completed, the devices of the two parties respectively perform format verification (such as verifying the matrix dimension and the legality of the curve point) on the lattice-based public key parameter group and the elliptic curve temporary public key, to ensure that the parameters meet the protocol specifications. After the verification is passed, the two types of public keys are packaged into a parameter message in a unified format, and are synchronously sent to the other party through the communication link. The parallel generation mechanism enables the two parties to complete the preparation of the two types of key materials at the same time, avoids the agreement blockage caused by the generation delay of a single algorithm, and simultaneously provides complete input for subsequent key fusion (through KDF) by synchronously outputting the two public keys, guarantees the key consistency in the hybrid mode, and improves the protocol compatibility.

[0093] The communication initiator generates an LWE public key parameter group based on its own LWE private key vector and the received LWE public key parameter group of the responder , ), the first shared component is calculated as formula (1):

[0094] (1)

[0095] The communication responder calculates the second shared component based on its LWE private key vector and the received initiator LWE public key parameter set , ), the second shared component is calculated as formula (2):

[0096] (2)

[0097] and both represent noise vectors, which are random small error terms, and are the core elements to ensure the provable security of the scheme.

[0098] The communication parties calculate the shared component based on the temporary public keys Q_A and Q_B through the elliptic curve Diffie-Hellman protocol, as formula (3):

[0099] K_ECC=ECDH(Q_A,Q_B) (3)

[0100] ECDH (Elliptic Curve Diffie-Hellman) is an elliptic curve Diffie-Hellman key exchange protocol, and the calculation process thereof will not be described.

[0101] The first shared component or the second shared component is spliced with the elliptic curve shared component to obtain input data, as formula (4):

[0102] Input data=K_LWE||K_ECC (4)

[0103] The input data is subjected to one-way hash transformation by a key derivation function using the SHA-3 algorithm; the HKDF expansion process is performed to generate key material of a specified length. The first 128 bits are output as the session key K_session, and the last 256 bits are output as the side channel protection mask.

[0104] 104、After writing the identification bit in the protocol header of the session key, when the encryption mode enabling instruction indicates the hybrid mode or the pure quantum-resistant mode, the algorithm structure and hardware resources are optimized in cooperation.

[0105] Specifically, after the session key is generated, the protocol layer automatically writes a 1-bit algorithm identification bit in the header thereof, which is used to mark the current enabled encryption mode (hybrid mode or pure quantum-resistant mode). The identification bit serves as a hidden control signal within the protocol, is transmitted together with the session key, and is parsed by the communication parties, ensuring that the communication parties reach a consensus on the current encryption mode, providing a unified trigger basis for the subsequent algorithm layer and hardware layer collaborative operation, avoiding processing conflicts caused by inconsistent mode identification, and improving the continuity of protocol execution.

[0106] When the encryption mode enabling instruction indicates the hybrid mode or the pure quantum-resistant mode, parameter optimization and calculation simplification operations are performed at the algorithm structure layer, including: reducing the dimension of the parameter matrix based on the lattice algorithm to a predefined lightweight range; extending the standard deviation of the noise distribution to a predefined safety margin range; calling a pre-stored constant matrix library to perform matrix multiplication operations; eliminating redundant modulo reduction calculation steps in the encryption process.

[0107] Specifically, the dimension of the parameter matrix based on the lattice algorithm is reduced to a predefined lightweight range: after receiving the hybrid mode or pure quantum-resistant mode instruction, the algorithm structure layer first calls the parameter adjustment module to reduce the dimension of the core parameter matrix based on the lattice algorithm (such as LWE) to a predefined lightweight range. This range is determined through a large number of security verifications, which can reduce the complexity of matrix operations (reduce the number of elements and multiplication times), and will not cause the quantum-resistant security strength to decrease due to excessive reduction of the dimension. The reduction of the dimension directly reduces the occupation of computing resources, reduces the running delay of the quantum-resistant algorithm on low-power devices (such as Internet of Things terminals), while maintaining the basic resistance ability to quantum attacks, balancing the lightweight demand and the security bottom line.

[0108] Extending the standard deviation of the noise distribution to a predefined safety margin range: while reducing the dimension of the matrix, the algorithm structure layer extends the standard deviation of the noise distribution through the noise adjustment module, so that it falls within the predefined safety margin range. This operation increases the randomness and complexity of the noise, makes up for the possible security loss caused by the reduction of the dimension of the matrix, ensures that the difficulty of solving the lattice problem (a core indicator of quantum-resistant algorithms) does not decrease. The noise expansion mechanism does not need to increase the amount of calculation, but can maintain or even improve the quantum-resistant security level on the premise of parameter lightweight, solves the contradiction between dimension reduction and security strength, and makes the optimized parameters efficient and secure.

[0109] Calling a pre-stored constant matrix library to perform matrix multiplication operation: For the frequently occurring matrix multiplication operation in the lattice algorithm, the algorithm structure layer no longer generates random matrices in real time, but directly calls matrices that meet the current parameter requirements from the pre-stored constant matrix library. The matrices in the constant matrix library are pre-computed and security-verified, and cover multiple dimensions and noise configurations, which can directly adapt to the operation requirements in different modes. This mechanism saves the time overhead of generating random matrices in real time, reduces the dynamic memory occupation, significantly improves the execution efficiency of matrix multiplication, and at the same time avoids the operation deviation caused by the randomness fluctuation in the real-time generation process, and guarantees the calculation stability.

[0110] Eliminate redundant modulo reduction calculation steps in the encryption process: The algorithm structure layer identifies redundant or unnecessary modulo reduction steps (such as continuously performing modulo operations on the same value) in the encryption process through the process analysis module, and automatically removes the redundant operations. Modulo reduction is a basic operation in lattice-based encryption, but excessive execution will increase the calculation delay. After eliminating redundant steps, only necessary modulo reductions that guarantee the correctness of the operation are retained, which reduces the CPU operation load without affecting the accuracy of the encryption result, making the encryption process more concise and efficient, especially in mixed mode, which can form synergy with the high efficiency of traditional algorithms, further improving the overall communication speed.

[0111] When the encryption mode enables instruction indicates a mixed mode or a pure quantum-resistant mode, the hardware resource layer performs instruction acceleration and heterogeneous task allocation operations, including: sending a special instruction to the central processor to perform lattice multiplication operation; sending a special instruction to the central processor to perform number-theoretic transform operation; when detecting that the matrix operation amount exceeds the graphics processor acceleration threshold, sending a matrix block calculation task to the graphics processor; when detecting that the modulo operation amount exceeds the programmable gate array acceleration threshold, sending a modulo reduction pipeline task to the programmable gate array.

[0112] Specifically, sending a special instruction to the central processor to perform lattice multiplication operation: After recognizing the mixed mode or pure quantum-resistant mode instruction, the hardware resource layer automatically sends an extended special instruction (such as lwe_mul) to the central processor (CPU) for the core lattice multiplication operation in the lattice-based algorithm (such as LWE). The instruction is realized through the instruction set extension of RISC-V architecture, which converts the lattice multiplication operation that needs to be simulated by multiple steps of software into a single-cycle hardware native operation, reducing the instruction execution period and memory interaction frequency. The direct call of the special instruction avoids the redundant overhead of software implementation, significantly improves the processing speed of lattice multiplication, and at the same time ensures the stability of the operation process, providing bottom-layer hardware support for the efficient execution of quantum-resistant algorithms.

[0113] Send special instruction to central processor to perform number theory transform operation: for the polynomial operation involved in the anti-quantum algorithm (such as polynomial multiplication in the lattice-based cryptography), the hardware resource layer sends the number theory transform (NTT) special instruction to the CPU. The instruction optimizes the butterfly operation flow of the number theory transform through hardware circuit, improves the conversion efficiency of the polynomial between time domain and frequency domain, and reduces the calculation complexity of large integer multiplication. Compared with the NTT implemented by software, the special instruction can avoid the additional loss of data type conversion and loop iteration, greatly reduce the time consumption of the number theory transform operation, and adapt to the efficiency requirements of parallel processing of traditional algorithms and anti-quantum algorithms in mixed mode.

[0114] When it is detected that the matrix operation amount exceeds the graphics processor acceleration threshold, send the matrix block calculation task to the graphics processor: the hardware resource layer monitors the matrix operation amount (such as matrix dimension and operation times) in the anti-quantum algorithm in real time, and when it is detected that it exceeds the preset graphics processor (GPU) acceleration threshold, the task scheduler automatically decomposes the matrix operation into several independent sub-block tasks and assigns them to the GPU for execution. The multi-thread parallel architecture of the GPU is good at processing high-parallel matrix block operations, and can simultaneously process the multiplication and accumulation operations of multiple sub-blocks through the cooperative scheduling of thread blocks and thread bundles. This allocation mechanism fully utilizes the parallel computing advantage of the GPU, avoids the performance bottleneck of the CPU in large-scale matrix operation, and improves the throughput of high-load matrix operation in the anti-quantum algorithm.

[0115] When it is detected that the modulus operation amount exceeds the programmable gate array acceleration threshold, send the modulus reduction pipeline task to the programmable gate array: for the modulus reduction operation frequently appeared in the anti-quantum algorithm (such as the modulus operation in lattice-based encryption), the hardware resource layer monitors its operation amount in real time, and when it exceeds the programmable gate array (FPGA) acceleration threshold, the modulus reduction task is packaged as a pipeline processing unit and assigned to the FPGA for execution. The FPGA can simultaneously process multiple modulus reduction operations through the parallel pipeline design of hardware logic circuit without the intervention of CPU in data flow. The allocation of pipeline tasks makes the modulus reduction operation free from the serial restriction of software loop, reduces the operation delay, and at the same time, the configurable characteristics of the FPGA can adapt to the operation requirements of different modulus lengths, improving the adaptability of hardware resources and anti-quantum algorithms.

[0116] 105、Monitor the session data transmission amount and duration after cooperative optimization, trigger key update when the preset threshold is exceeded, and inject randomization instruction mask during key operation.

[0117] Specifically, the monitoring module is started after the session is established, and the total amount of session data transmission (the cumulative amount of encrypted data received and sent) after collaborative optimization (such as algorithm parameter optimization, hardware acceleration processing) is counted in real time, and the session duration (the time length from key generation to the present) is recorded. The monitoring module obtains the transmission amount data through the data stream interface of the hook communication protocol in a low-overhead manner to avoid performance interference on normal communication; the duration is updated by the system clock timing to ensure the accuracy of time statistics. The monitoring mechanism provides a quantitative basis for key update, avoids the accumulation of quantum attack risks caused by long-term use of the same key, and adapts to the communication intensity difference in different scenarios (such as a high-frequency transmission scenario requiring a more sensitive threshold trigger).

[0118] The monitoring module compares the real-time collected transmission amount and duration with the preset threshold (set according to the security level, such as a lower threshold in a high-security scenario) respectively. When any indicator exceeds the corresponding threshold, the key update protocol is triggered immediately. During the update process, the communication parties automatically re-execute the key agreement process in the hybrid mode or the pure quantum-resistant mode (such as generating lattice public keys and ECC temporary public keys in parallel, and fusing keys through KDF), generate a new session key to replace the old key, and ensure the consistency of key switching of both parties through the protocol layer synchronization mechanism. This "transmission amount-time" double-condition triggering mechanism not only avoids the efficiency loss caused by frequent key updates, but also actively terminates the life cycle of the old key when the key exposure risk increases (such as the large amount of transmission data may increase the side channel leakage probability), thereby reducing the key cracking risk under quantum attack to the minimum.

[0119] During the operation process of new key generation, storage, encryption / decryption calling, etc., the hardware resource layer automatically injects randomization instruction masking. Specifically, when the CPU executes key-related instructions (such as key derivation, modular operation), a random delay signal is dynamically generated through a special hardware circuit (such as a random number generator integrated in the CPU) and superimposed into the instruction execution period; at the same time, a random address offset is introduced in the memory access link (such as reading key materials) to disrupt the access timing of key data. These masking operations do not affect the correctness of key operations, but can disturb the correlation between side channel information (such as power consumption, electromagnetic radiation) and key content, making it difficult for attackers to restore the key by analyzing the side channel characteristics. Compared with the masking scheme at the pure software level, the hardware-level randomization instruction masking has stronger concealment and can significantly reduce the success rate of side channel attacks, thereby improving the physical security of key operations.

[0120] Based on the same overall inventive concept, the present application also protects an anti-quantum computing attack capability enhancement system. The anti-quantum computing attack capability enhancement system described below can be mutually corresponding and referred to the anti-quantum computing attack capability enhancement method described above.

[0121] Figure 2is a structural schematic diagram of the anti-quantum computing attack ability enhancement system provided by the embodiment.

[0122] As shown in Figure 2 The anti-quantum computing attack ability enhancement system provided by the embodiment includes:

[0123] The acquisition module 201 is configured to acquire the computing power data, the security level identifier, and the network delay value of the communication initiator, and receive the corresponding parameters sent by the communication responder.

[0124] The selection module 202 is configured to send the encryption mode enabling instruction to the communication initiator and the communication responder according to the comparison result of the computing power data, the matching state of the security level identifier, and the sum of the network delay values.

[0125] The generation module 203 is configured to control the communication initiator and the communication responder to generate a lattice-based public key parameter group and an elliptic curve temporary public key in parallel, and input the public key parameter group into a key derivation function to generate a session key.

[0126] The optimization module 204 is configured to, after writing an identification bit in the protocol header of the session key, when the encryption mode enabling instruction indicates a hybrid mode or a pure anti-quantum mode, optimize the algorithm structure and the hardware resources in cooperation.

[0127] The update module 205 is configured to monitor the session data transmission amount and the duration after the cooperation and optimization, trigger key update when a preset threshold is exceeded, and inject a randomization instruction mask during key operation.

[0128] Figure 3 is a structural schematic diagram of the electronic device provided by the embodiment.

[0129] As shown in Figure 3 The electronic device can include a processor 310, a communications interface 320, a memory 330, and a communications bus 340, wherein the processor 310, the communications interface 320, and the memory 330 can communicate with each other through the communications bus 340. The processor 310 can invoke the logical instructions in the memory 330 to execute the anti-quantum computing attack ability enhancement method.

[0130] In addition, the logic instructions in the memory 330 described above can be realized in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0131] In another aspect, the present application also provides a computer program product, which comprises a computer program, the computer program can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the anti-quantum computing attack ability enhancement method provided by the above-mentioned methods.

[0132] In another aspect, the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the anti-quantum computing attack ability enhancement method provided by the above-mentioned methods.

[0133] The device embodiments described above are only schematic, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment. Those skilled in the art can understand and implement without creative labor.

[0134] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software and the necessary general hardware platform, and of course, can also be realized by hardware. Based on such understanding, the above technical solutions essentially or the parts that make contributions to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0135] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features therein can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for enhancing resistance to quantum computing attacks, the method comprising: The method comprises the following steps: Obtain the computing power data, security level identifier and network delay value of the communication initiator, and receive the corresponding parameters sent by the communication responder; According to the comparison result of the computing power data, the matching state of the security level identifier and the sum of the network delay value, send the encryption mode enabling instruction to the communication initiator and the communication responder; Control the communication initiator and the communication responder to generate a lattice-based public key parameter group and an elliptic curve temporary public key in parallel, and input the public key parameter group into a key derivation function to generate a session key; After writing an identification bit in the protocol header of the session key, when the encryption mode enabling instruction indicates a hybrid mode or a pure quantum-resistant mode, optimize the algorithm structure and hardware resources in coordination; Monitor the session data transmission volume and duration after the coordination optimization, trigger key update when the preset threshold is exceeded, and inject a randomization instruction mask during key operation.

2. The quantum computing attack resistant capability enhancement method of claim 1, wherein, After receiving the corresponding parameters sent by the communication responder, the method further comprises the following steps: Calculate the difference between the computing power data of the communication initiator and the computing power data of the communication responder, and determine whether the difference exceeds a predefined computing power threshold; Verify whether the security level identifier of the communication initiator and the security level identifier of the communication responder belong to the same security category; Add the network delay value of the communication initiator and the network delay value of the communication responder to obtain the sum of the delay values.

3. The method of claim 2, wherein, The step of sending the encryption mode enabling instruction to the communication initiator and the communication responder comprises the following steps: When the difference does not exceed the computing power threshold and the security level identifiers of both parties are the preset high security category, or the sum of the delay values does not exceed the maximum delay threshold and the security level identifier of any party is the preset high security category, send the instruction to enable the pure quantum-resistant mode; When the difference is within the predefined computing power interval, the security level identifiers of both parties belong to the same preset medium security category, and the sum of the delay values is within the predefined delay interval, send the instruction to enable the hybrid mode; When the difference exceeds the computing power threshold and the security level identifiers of both parties are the preset low security category, send the instruction to enable the pure traditional mode.

4. The method of claim 3, wherein, The instruction to enable the pure quantum-resistant mode comprises the following steps: Perform lattice-based key exchange protocol in the key negotiation phase; Use the highest security level LWE parameter set in the data transmission phase; Exclusively use SPHINCS and quantum-resistant signature in the signature verification phase; Schedule all available hardware acceleration resources to preferentially process quantum-resistant operation tasks.

5. The quantum computing attack resistant capability enhancement method of claim 3, wherein, The instruction to enable the hybrid mode comprises the following steps: Perform lattice-based key exchange and traditional elliptic curve key exchange in parallel in the key negotiation phase; Use the lightweight LWE encryption algorithm in the data transmission phase; Generate SPHINCS and quantum-resistant signature and ECC signature in the signature verification phase.

6. The quantum computing attack resistant capability enhancement method of claim 1, wherein, The step of inputting the public key parameter group into the key derivation function to generate the session key comprises the following steps: The communication initiator calculates a first shared component based on the received responder LWE public key parameter group and the LWE private key vector of itself; The communication responder calculates a second shared component based on the received initiator LWE public key parameter group and the LWE private key vector of itself; The two communication parties calculate a shared component based on a temporary public key through an elliptic curve protocol; The first shared component or the second shared component is spliced with the elliptic curve shared component to obtain input data; The input data is output through a key derivation function, and the first 128 bits are used as a session key, and the last 256 bits are used as a side channel protection mask.

7. The quantum computing attack resistant capability enhancement method of claim 1, wherein, The collaborative optimization algorithm structure and hardware resources include: Parameter optimization and calculation simplification operations are performed at the algorithm structure layer; Instruction acceleration and heterogeneous task allocation operations are performed at the hardware resource layer.

8. The quantum computing attack resistant capability enhancement method of claim 7, wherein, The parameter optimization and calculation simplification operations performed at the algorithm structure layer include: Reducing the dimension of a parameter matrix based on a lattice algorithm to a predefined lightweight range; Extending the standard deviation of a noise distribution to a predefined safety margin range; Calling a pre-stored constant matrix library to perform matrix multiplication operations; Eliminating redundant modulo reduction calculation steps in the encryption process.

9. The quantum computing attack resistant capability enhancement method of claim 7, wherein, The instruction acceleration and heterogeneous task allocation operations performed at the hardware resource layer include: Sending a special instruction to a central processing unit to perform lattice basis multiplication operations; Sending a special instruction to a central processing unit to perform number theoretic transform operations; When it is detected that the matrix operation amount exceeds a graphics processing unit acceleration threshold, sending a matrix block calculation task to a graphics processing unit; When it is detected that the modulo operation amount exceeds a programmable gate array acceleration threshold, sending a modulo reduction pipeline task to a programmable gate array.

10. A quantum computing attack resistance capability enhancement system, comprising: It includes: An acquisition module is configured to acquire computing power data, a security level identifier, and a network delay value of a communication initiator, and receive corresponding parameters sent by a communication responder; A selection module is configured to send an encryption mode enabling instruction to the communication initiator and the communication responder according to a comparison result of the computing power data, a matching state of the security level identifier, and a sum of the network delay values; A generation module is configured to control the communication initiator and the communication responder to generate a lattice-based public key parameter group and an elliptic curve temporary public key in parallel, and input the public key parameter group into a key derivation function to generate a session key; An optimization module is configured to, after an identification bit is written in a protocol header of the session key, when the encryption mode enabling instruction indicates a hybrid mode or a pure quantum-resistant mode, collaboratively optimize an algorithm structure and hardware resources; An update module is configured to monitor a session data transmission amount and a duration after the collaborative optimization, trigger a key update when a preset threshold is exceeded, and inject a randomization instruction mask during key operations.

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