Coarse frequency offset estimation method and device

Abstract

The invention provides a coarse frequency offset estimation method and device, and relates to the technical field of wireless communication and coherent light communication. The method comprises the following steps: performing Fourier transform on a time domain signal to obtain a frequency domain signal, calculating a power spectrum, and performing multi-group average processing to obtain an average power spectrum; based on the average power spectrum, a frequency offset value is determined by iteratively adjusting a frequency shift amount. The method is characterized in that cyclic shift in an iteration process is logic cyclic shift and is realized by updating a reading initial address of a memory storing an average power spectrum, and physical write-back of data is avoided. And finally, performing phase compensation on the time domain signal according to the determined frequency offset value. The device comprises corresponding modules for realizing the method. Physical shift is replaced by logic shift, hardware resources are remarkably saved, power consumption is reduced, time sequence performance is improved, a blind frequency offset estimation algorithm is easier to realize by hardware, and estimation precision is averagely improved through a power spectrum.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication and coherent optical communication, in particular to a coarse frequency offset estimation method and device. BACKGROUND

[0002] In a wireless communication or coherent optical communication system, due to the frequency difference between the local oscillators of the transmitter and the receiver, and the Doppler effect that may occur when the signal is transmitted in the channel, the carrier frequency of the received signal will be offset from the original transmitted frequency, i.e. frequency offset. If the frequency offset is not corrected effectively, the constellation points of the demodulated signal will rotate continuously, and in severe cases, the data cannot be correctly judged, resulting in communication interruption.

[0003] In order to solve this problem, a blind frequency offset estimation algorithm without pilot or training sequence is proposed in the prior art. The basic idea of this algorithm is to use the symmetry of the power spectrum of the modulated signal. Specifically, this algorithm first performs a fast Fourier transform on the received digital signal, converting it from the time domain to the frequency domain, and then calculates its power spectrum. In the ideal case of no frequency offset, the power spectrum of the signal should be symmetric about zero frequency. When there is a frequency offset, the entire power spectrum will be shifted accordingly, thus destroying its symmetry about zero frequency. Therefore, this algorithm sets symmetric detection windows on both sides of the power spectrum peak, compares the total energy in the two windows, and based on the energy difference, iteratively performs a circular shift on the entire power spectrum data until the energy of the two windows reaches a balance. At this time, the total amount of shift accumulated during the entire iteration process is considered as the estimated value of the frequency offset. However, this algorithm faces serious challenges when implemented in hardware. The circular shift operation in the iteration process requires large-scale data reading, shifting and writing of the memory that stores the entire power spectrum data (usually containing thousands of data points). This physical shift operation on the memory content not only consumes a lot of hardware logic resources and power consumption, but also due to the long time-consuming operation, it is easy to cause timing convergence difficulties in high-speed systems, which greatly reduces the practicality of this algorithm in chip design. SUMMARY

[0004] In view of the defects in the prior art, the purpose of the present application is to provide a coarse frequency offset estimation method and device.

[0005] According to the coarse frequency offset estimation method provided by the present application, the method comprises: performing Fourier transform on the received time domain digital signal to obtain a frequency domain signal; calculating the power spectrum of the frequency domain signal; averaging the power spectrum from multiple groups of time domain signals to obtain an average power spectrum; determining a frequency offset value by iteratively adjusting a frequency shift amount based on the average power spectrum, the iteratively adjusting the frequency shift amount comprising performing a logical circular shift operation on the average power spectrum, wherein the logical circular shift operation is implemented by updating a read start address for accessing a memory in which the average power spectrum is stored; phase compensating the time domain digital signal according to the determined frequency offset value.

[0006] Preferably, the iteratively adjusting the frequency shift amount further comprises: setting a first detection window and a second detection window on the average power spectrum; calculating power accumulation values in the first detection window and the second detection window respectively; and determining whether to continue adjusting the frequency shift amount based on a difference between the two power accumulation values.

[0007] Preferably, when reading data from the memory according to the updated read start address, if a required data block crosses a physical storage word boundary in the memory, the method further comprises: performing a data splicing operation on data portions read from different physical storage words to form a logically continuous data block.

[0008] Preferably, the calculating power accumulation values in the two detection windows comprises: performing a continuous reading operation on data in the first detection window and the second detection window which are logically located at two ends of the average power spectrum by utilizing an address wraparound feature of the memory.

[0009] Preferably, widths of the first detection window and the second detection window are adaptively determined according to a bandwidth of the average power spectrum.

[0010] According to the present application, a coarse frequency offset estimation device is provided, comprising: a Fourier transform module configured to perform Fourier transform on a received time domain digital signal to obtain a frequency domain signal; a power spectrum calculation module configured to calculate a power spectrum of the frequency domain signal; a power spectrum averaging module configured to average the power spectrum from a plurality of groups of time domain signals to obtain an average power spectrum; a frequency offset determination module configured to determine a frequency offset value by iteratively adjusting a frequency shift amount based on the average power spectrum; a frequency offset compensation module configured to phase compensate the time domain digital signal according to the determined frequency offset value; wherein the frequency offset determination module comprises: a memory for storing the average power spectrum; and control logic configured to perform a logical circular shift on the average power spectrum by updating a read start address of the memory to iteratively determine the frequency offset value.

[0011] Preferably, the frequency offset determination module is further configured to set a first detection window and a second detection window on the average power spectrum, and calculate power accumulation values within the first detection window and the second detection window respectively. Moreover, the control logic is further configured to determine whether the frequency offset value needs to be further adjusted based on a difference between the two power accumulation values.

[0012] Preferably, the control logic is further configured to generate a continuous read address sequence by utilizing an address wraparound feature of the memory to extract data of the first detection window and the second detection window located logically at both ends of the average power spectrum at one time.

[0013] Preferably, the control logic is further configured to perform a data splicing operation to reconstruct logically continuous data blocks when reading data according to the updated read start address, if a required data block spans a physical storage word boundary in the memory.

[0014] Preferably, the memory is a ring buffer and is organized as a structure with a depth of 64 and a bit width of 16 power spectrum data points.

[0015] Compared with the prior art, the present application has the following beneficial effects: 1. The present application completely avoids the physical data shift and write-back operations with huge resource and power consumption overhead in the traditional implementation by using an innovative logical shift scheme, i.e. updating the read start address of the memory and assisting with a data splicing operation to equivalently implement the circular shift of the power spectrum data, thereby greatly saving the chip area, reducing the power consumption, and significantly improving the timing performance, so that the frequency offset estimation algorithm based on the power spectrum symmetry becomes efficient, low-cost and easy to implement in hardware.

[0016] 2. The present application improves the estimation accuracy by accumulating and averaging the power spectra from multiple groups of continuous time-domain signals, effectively suppresses the noise interference, and obtains a smoother and more reliable power spectrum shape, thereby improving the accuracy of the frequency offset estimation in a low signal-to-noise ratio environment.

[0017] 3. The present application implements blind estimation without any pilot or training sequence, and can directly process the initial received signal, thereby having wide applicability and robustness. BRIEF DESCRIPTION OF DRAWINGS

[0018] Other features, objects, and advantages of the application will become more apparent from the following detailed description when read in conjunction with the accompanying drawings: Figure 1 A flowchart of a coarse frequency offset estimation method based on logical shift provided for an embodiment of the present application; Figure 2 A structural diagram of a coarse frequency offset estimation device provided for an embodiment of the present application; Figure 3 A principle diagram of 16-point base-4 fast Fourier transform provided for an embodiment of the present application; Figure 4 A principle diagram of base-4 butterfly operation provided for an embodiment of the present application; Figure 5 A flowchart of power spectrum average calculation provided for an embodiment of the present application; Figure 6 A diagram of power spectrum shape and edge detection window provided for an embodiment of the present application; Figure 7 A flowchart of peak detection algorithm provided for an embodiment of the present application; Figure 8 A diagram of high-efficiency RAM reading strategy provided for an embodiment of the present application; Figure 9 A diagram of data offset and splicing provided for an embodiment of the present application.

[0019] Explanation of reference signs: DETAILED DESCRIPTION

[0020] The application will be described in detail below with specific embodiments. The following embodiments will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the application. These are within the scope of protection of the application.

[0021] Embodiment 1 The present application discloses a coarse frequency offset estimation method and device. It can be understood that the present application aims to solve the problems of large hardware resource consumption, high power consumption and complex implementation caused by repeatedly physically shifting power spectrum data in the frequency offset estimation process based on power spectrum symmetry in the prior art.

[0022] The application firstly performs 1024-point fast Fourier transform (FFT) on the received training sequence to convert from time domain to frequency domain. Secondly, the complex data output by the FFT is squared to obtain the power spectrum of the signal. The FFT power spectrum is superimposed and averaged for multiple rounds to amplify and highlight the frequency components with concentrated energy, making the frequency offset more obvious and facilitating edge detection. Finally, edge detection is performed on the power spectrum to align the waveform on both sides and obtain the frequency-frequency data.

[0023] The coarse frequency offset estimation method disclosed in the embodiments of the application is as follows: Step S1: cache the upstream receiving module and perform address mapping (note: base-4 address mapping is to flip by 2 bits, for example, if the current write address is 4'b0001, it is flipped by 2 bits to obtain 4'b0100; in this way, it is sequentially written to the following address control X(0), X(4), X(8),..., X(11), X(15), and written to the mapped address cache. When a 1024-point is cached, fast Fourier transform (FFT) of 1024 points based on base-4 is performed.

[0024] Please refer to Figure 3 , which is a data flow diagram of 16-point FFT based on base-4. The FFT of 1024 points based on base-4 is based on a similar flow diagram.

[0025] Please refer to Figure 4 In the design of the embodiments of the application, 32 base-4 butterfly operations are calculated in parallel based on 1024 points. Thus, one round of 1024-point calculation requires 8 clock time units, and a total of 5 rounds of butterfly operations are required to complete the FFT calculation, finally requiring 8 clock*5=40 clock, achieving a full-rate performance with an input parallel degree of 16.

[0026] Step S2: square the FFT output value obtained in step S1 to obtain the power spectrum. Please refer to Figure 5 For subsequent power spectrum peak detection, in the embodiments of the application, multiple sets of FFT power spectrum data are cached, and finally the average value is sent to the next module. For example, 128 sets of FFT are performed. After each set of FFT output, the square value is calculated. If it is the first set of FFT, the square value is stored in the RAM. If not, the cached value in the RAM and the FFT power spectrum value calculated at present are added until 128 sets of data are completed. Finally, the FFT power spectrum cumulative value in the RAM is read, divided by the number of FFT, such as 128 times, to obtain the average power spectrum value sent to the frequency offset detection module.

[0027] Step S3: according to the average power spectrum obtained in the previous step, its shape should be as shown in Figure 6 A detection window is set on both sides to detect the frequency offset by accumulating the size of the window.

[0028] The detection method is shown in the following table Figure 7 , specifically: according to the following table Figure 6 , the minus window cumulative value and the pluse window cumulative value are obtained (the window size can be configured), and by comparing , whether the absolute value of the difference exceeds the comparison threshold value is determined, if yes, if , it indicates that the right window is too large, and a certain amount of data needs to be circularly shifted to the left, and the number of each movement is accumulated to y, and then the data is sent into the interception window, the data is extracted, and the next round of comparison is performed. If , it indicates that the left window is too large, and a certain amount of data needs to be circularly shifted to the right. If , the absolute value of the difference is less than the threshold value, it is considered that the current moving data point cumulative value y is the carrier frequency offset (y / 1024* sampling frequency).

[0029] In chip design, in order to reduce the area and power consumption, RAM cache is used for 1024 power spectrum points, and spectrum point shifting is completed. Here, the specific innovation is described, assuming that the window size is set to 64 points, and the parallelism of the upstream module input data is 16. The RAM cache depth is 64, and the bit width is 16 points, so that the complete 1024 points are stored. In edge detection, the general method is to detect the cumulative value of the left window (32 points) , then read the right window (32 points) , and compare and shift, and then re-detect according to the shifted data. In the embodiment of the present application, referring to Figure 8 , the cumulative value of the right window (32 points) is detected first, and then the cumulative value of the left window (32 points) is detected. By using the address continuity of the RAM (as shown in the following figure, the starting address 60 is continuously read for 4 rows, and then the window data is read again , and the address 64 overflows back to the 0 address), it can be found that the right window to the left window is continuous, which facilitates reading and shifting.

[0030] The data read from the window above is as follows Figure 9 , because the data read from the starting address after shifting may not be 16 points all valid, it needs to be spliced with the data of the next address to form a complete 16 points. Because the read address is continuous, it will be much easier to control the spliced data. According to the spliced data and , the peak detection and offset are completed, and the offset x is accumulated into the total offset y, until the window data on both sides is less than the configured threshold value, the detection is completed. This method does not need to write the data back to the RAM after shifting, only the starting address and the number of valid points in the address need to be updated in real time.

[0031] Step S4: Perform frequency offset correction (rotation angle) based on the frequency offset y obtained in the previous step. This involves multiplying the received data by the offset / 1024 * sampling frequency. The rotated data is then sent to the next module for processing.

[0032] Example 2 As a more specific implementation method, this invention provides a coarse frequency offset estimation method, such as... Figure 1 As shown, the method first performs a Fourier transform step (S101) on the received continuous time-domain digital signal to obtain a frequency-domain signal, and then performs a power spectrum calculation step (S102) and a power spectrum accumulation and averaging step (S103) to improve the signal-to-noise ratio. The crucial edge detection step (S104) determines the frequency offset value through an iterative process based on logical cyclic shifting. Finally, based on the determined frequency offset value, a frequency offset compensation step (S105) is performed, and the corrected signal is output.

[0033] Figure 2 The schematic diagram illustrates the structure of the coarse frequency offset estimation device for implementing the above method. As an optional implementation, this device can be integrated into the front end of a wireless communication or coherent optical communication receiver. The device includes a Fast Fourier Transform module 10, a power spectrum calculation module 20, a power spectrum averaging module 30, an edge detection module 40, and a frequency offset compensation module 50 connected in sequence. Among them, the edge detection module 40 is a key part for implementing the core technology of this application, and it internally contains a ring memory 41 and corresponding control logic 42.

[0034] The following will combine Figures 1 to 9 The functions of each module in the device and their collaborative working process are described in detail.

[0035] In a specific application scenario, the analog-to-digital converter at the receiver front end converts the received analog signal into a time-domain digital signal sequence, which serves as the input of this device.

[0036] Specifically, the time-domain digital signal is fed into the Fast Fourier Transform module 10 to perform... Figure 1 The Fourier transform step (S101) is described. In this embodiment, the Fast Fourier Transform module 10 is configured to perform a 1024-point Fourier transform. To achieve high-speed processing in hardware, a radix-4 Fast Fourier Transform algorithm is preferably used. Figure 3 The diagram illustrates the data flow of a 16-point radix-4 Fast Fourier Transform, serving as a principle example for a 1024-point transform. A 1024-point radix-4 transform can be decomposed into three levels of butterfly operations. Figure 4The basic operation unit of the transform, i.e. the radix-4 butterfly operation, is shown. In hardware implementation, the FFT module 10 can contain 32 parallel radix-4 butterfly operation units, so that a 1024-point transform can be completed in, for example, 40 clock cycles, satisfying the real-time requirement of high-speed communication systems. The input of the module is 1024 time-domain complex samples, and the output is 1024 frequency-domain complex data points, representing the amplitude and phase of the signal at different frequency components.

[0037] Subsequently, the 1024 frequency-domain complex data points output by the FFT module 10 are sent to the power spectrum calculation module 20 to perform the calculation power spectrum step (S102) in Figure 1 For each input frequency-domain complex point X(k) = I(k) + jQ(k), where k is the frequency index and I(k) and Q(k) are the in-phase component and quadrature component respectively, the power spectrum calculation module 20 calculates the square of its modulus, i.e. the power spectrum value P(k) = I(k)^2 + Q(k)^2. After this step, a set of 1024 frequency-domain complex points is converted into a set of 1024 real values, i.e. the power spectrum corresponding to the set of time-domain signals.

[0038] Thereafter, the power spectrum data is sent to the power spectrum average module 30 to perform the cumulative average step (S103) in Figure 1 In a wireless communication environment, the signal is often disturbed by noise, and the power spectrum calculated in a single time may have large random fluctuations, which is not conducive to accurate frequency offset estimation. In order to obtain a smoother and higher SNR power spectrum, the embodiment adopts the method of cumulative averaging of multiple sets of power spectrum. The calculation process of power spectrum averaging can refer to Figure 5 The power spectrum average module 30 internally contains a memory for storing the cumulative sum (represented by the loop of accumulator Σ and buffer Buffer in Figure 5 ) and a counter. Each time a new set of 1024-point power spectrum data is received from the power spectrum calculation module 20, the module will add it to the existing cumulative value in the memory point by point and update it. At the same time, the counter is incremented by one. In the present embodiment, the preset average group number is 128. When the counter reaches 128, it means that the cumulative of 128 sets of power spectrum has been completed. At this time, the module divides each point of the 128 set sum in the memory by 128 (in hardware, it is usually implemented as right shift by 7 bits), thereby obtaining the average power spectrum. The noise of the average power spectrum is effectively suppressed, and the spectral shape characteristics (such as peak and edge slope) of the signal are thus more prominent. After completing the average calculation, the average power spectrum is output to the edge detection module 40, and the accumulator and counter are cleared to prepare for the next round of 128-group average.

[0039] The edge detection module 40 is used to performFigure 1 The edge detection step (S104) is a key module used in this application to determine the frequency offset value. This module receives 1024-point averaged power spectrum data from the power spectrum averaging module 30. Figure 2 As shown, it mainly consists of a ring memory 41 and control logic 42.

[0040] In this embodiment, the ring memory 41 is a random access memory, specifically organized with a depth of 64 and a bit width of 16 data points, for a total capacity of exactly 64 * 16 = 1024 data points. The 1024 points of average power spectrum data are sequentially written into this memory. It is understood that this storage structure is optimized for efficient subsequent data retrieval and logical shift operations.

[0041] Control logic 42 is responsible for implementing the iterative search algorithm based on power spectrum symmetry. For detailed flowcharts, please refer to [link / reference needed]. Figure 7 The specific working process is as follows: 1. Initialization: Control logic 42 clears an internal frequency offset accumulator register y to zero, and sets a read start address pointer for accessing the ring memory 41, which initially points to a logical zero.

[0042] 2. Set up the detection window: such as Figure 6 As shown, the algorithm works by symmetrically placing two detection windows on either side of the peak of the average power spectrum: a first detection window (e.g., the Minus window in the figure) and a second detection window (e.g., the Plust window in the figure), and comparing the total energy within the two windows. In this embodiment, the widths of the two windows are fixed; for example, each window contains 32 consecutive power spectrum data points, and the windows are positioned symmetrically relative to the predicted spectrum center.

[0043] 3. Efficient Data Reading: To acquire data from both windows, control logic 42 utilizes the address wraparound characteristic of the ring memory 41 to implement an efficient reading strategy, such as... Figure 8 As shown. Assume the Plus window is located at the high end of the spectrum logic, while the Minus window is located at the low end. For example, the data in the Plus window might be stored at physical addresses 60 to 61, while the data in the Minus window might be stored at physical addresses 0 to 1. Control logic 42 can initiate a continuous read operation starting from address 60. After reading address 63, the memory address counter automatically wraps back to 0. In this way, the controller can read the data in the Plus window first, and then seamlessly read the data in the Minus window within a single continuous read cycle, without initiating two separate read operations, thus greatly improving data access efficiency.

[0044] 4. Power and comparison: Control logic 42 accumulates the data read from the two windows separately to get the first power sum Pm (from the Minus window) and the second power sum Pp (from the Pluse window). Then, it calculates the absolute value of the difference |Pp-Pm| and compares it with a pre-set threshold TH.

[0045] 5. Iterative decision and logical shift: If |Pp-Pm| < TH, it indicates that the power spectrum is approximately symmetric at this position, and the iteration process ends. The value stored in the frequency offset accumulation register y is the final frequency offset estimate. If |Pp-Pm| >= TH, the power spectrum needs to be shifted to continue searching for the symmetric point. At this time, control logic 42 determines the shift direction according to the size relationship between Pp and Pm: if Pp > Pm, it means that the power spectrum energy is biased to the right, and a logical left circular shift is needed; if Pm > Pp, a logical right circular shift is needed. The step size of the shift can be a fixed value, for example, 4 data points.

[0046] It should be noted that a key feature of the present application is the implementation of "logical circular shift". Compared with the huge overhead of physically reading out the entire 1024-point data, shifting, and then writing back to the memory in the traditional method, the control logic 42 in the present application does not perform any data write-back operation, but only updates the read start address for accessing the ring memory 41 in the next iteration. For example, if a left logical shift of 4 points is needed, the control logic 42 only needs to add 4 to the internal read start address pointer, and at the same time, add the shift amount (with sign) to the frequency offset accumulation register y.

[0047] 6. Data splicing: Since the shift step size (4) is not an integer multiple of the memory bit width (16), in the next read after updating the start address, the logically continuous data block (for example, a 16-point processing block) may span two physically adjacent memory words in the ring memory 41. At this time, data splicing operation is necessary for correctly reconstructing the logically continuous data block. As shown in Figure 9 to construct a logically shifted "effective data block", the control logic 42 reads data from the physical row (for example, address N) where the new start address is located and the next row (address N+1) respectively. Then, its internal data splicing logic will cut the latter half (for example, the last 12 points) from the data read from address N and splice it with the former half (for example, the first 4 points) cut from the data read from address N+1, thus perfectly reconstructing the continuous data block after circular shift in logic. This process is completely completed on the read and processing path, without the need to modify the memory content.

[0048] 7. Cycle: After one logical shift is completed, the control logic 42 returns to step 3, uses the new read start address and concatenation logic to fetch the window data at the new position, and repeats the above comparison and adjustment process until the termination condition is met.

[0049] Finally, when the edge detection module 40 completes the iteration and outputs the final frequency offset estimation value y, the value is sent to the frequency offset compensation module 50 to perform the frequency offset compensation step (S105) in Figure 1 The frequency offset compensation module 50 receives the original, unprocessed time domain digital signal y(n) at the same time. It performs a complex multiplication operation on each time domain sampling point y(n) according to the estimation value y to correct its phase. The compensation formula is: z(n) = y(n) * e^(-j*2*π*y*ts*n / N) where z(n) is the compensated time domain signal, ts is the sampling period, N is the number of points of Fourier transform (1024 in this example), and n is the time index of the sampling point. The formula is essentially multiplying the original signal by a rotation factor with the same size and opposite direction of the estimated frequency offset, thereby canceling the phase rotation caused by the frequency offset. The output signal z(n) is the frequency offset corrected signal, which can be sent to the subsequent synchronization and demodulation module for processing.

[0050] In the above manner, the scheme of the embodiment efficiently implements the frequency offset estimation algorithm based on the symmetry of the power spectrum by using the logical shift mechanism of updating the read start address and data concatenation, avoids large-scale data write-back, and thus significantly saves hardware resources, reduces power consumption, and improves timing performance.

[0051] The specific embodiments of the application are described above. It should be understood that the application is not limited to the specific implementation described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essential content of the application. In the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A coarse frequency offset estimation method, characterized in that, comprising: performing Fourier transform on the received time-domain digital signal to obtain a frequency-domain signal; calculating power spectrum of the frequency-domain signal; averaging the power spectrum from multiple sets of time-domain signals to obtain an averaged power spectrum; determining a frequency offset value by iteratively adjusting a frequency shift based on the averaged power spectrum, the iteratively adjusting the frequency shift comprising performing a logical circular shift operation on the averaged power spectrum by updating a read start address for accessing a memory storing the averaged power spectrum; performing phase compensation on the time-domain digital signal according to the determined frequency offset value.

2. The coarse frequency offset estimation method of claim 1, wherein, the iteratively adjusting the frequency shift further comprises: setting a first detection window and a second detection window on the averaged power spectrum; calculating power accumulation values within the first detection window and the second detection window respectively; and determining whether to continue adjusting the frequency shift based on a difference between the two power accumulation values.

3. The coarse frequency offset estimation method of claim 1 or 2, characterized in that, when reading data from the memory according to the updated read start address, if a required data block spans a physical memory word boundary in the memory, the method further comprises: performing data splicing operation on data portions read from different physical memory words to form a logically continuous data block.

4. The coarse frequency offset estimation method of claim 2, wherein, the calculating power accumulation values within the two detection windows comprises: performing a continuous reading operation on data of the first detection window and the second detection window which are logically located at two ends of the averaged power spectrum by utilizing an address wrap-around feature of the memory.

5. The coarse frequency offset estimation method of claim 2, wherein widths of the first detection window and the second detection window are adaptively determined according to a bandwidth of the averaged power spectrum.

6. A coarse frequency offset estimation apparatus characterized by comprising: comprising: a Fourier transform module configured to perform Fourier transform on the received time-domain digital signal to obtain a frequency-domain signal; a power spectrum calculation module configured to calculate power spectrum of the frequency-domain signal; a power spectrum averaging module configured to average the power spectrum from multiple sets of time-domain signals to obtain an averaged power spectrum; a frequency offset determination module configured to determine a frequency offset value by iteratively adjusting a frequency shift based on the averaged power spectrum; a frequency offset compensation module configured to perform phase compensation on the time-domain digital signal according to the determined frequency offset value. wherein the frequency offset determination module comprises: a memory configured to store the averaged power spectrum; and control logic configured to perform a logical circular shift on the averaged power spectrum by updating a read start address of the memory to iteratively determine the frequency offset value.

7. The coarse frequency offset estimation apparatus of claim 6, wherein the frequency offset determination module is further configured to set a first detection window and a second detection window on the averaged power spectrum and to calculate power accumulation values within the first detection window and the second detection window respectively; and the control logic is further configured to determine whether to continue adjusting the frequency shift based on a difference between the two power accumulation values.

8. The coarse frequency offset estimation apparatus of claim 7, wherein the control logic is further configured to generate a sequence of consecutive read addresses using wrap-around property of the memory to fetch data of the first and second detection windows located logically at two ends of the averaged power spectrum in one shot.

9. The coarse frequency offset estimation apparatus of claim 6, wherein the control logic is further configured to perform data stitching operation to reconstruct logically consecutive data blocks when reading data according to the updated read start address, if a required data block spans a physical storage word boundary in the memory.

10. The coarse frequency offset estimation apparatus of claim 6, wherein the memory is a ring buffer and is organized as a structure with a depth of 64 and a bit width of 16 power spectrum data points. ​ ​ ​

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