A heterogeneous device integration package structure and method

Abstract

The application discloses a heterogeneous device integrated packaging structure and method. The packaging method comprises the following steps: providing a carrier, the surface of the carrier being provided with an initial metal layer; attaching at least one active device and at least one passive device on the initial metal layer; using plastic sealing material to perform plastic sealing, forming a plastic sealing body for covering the active device and the passive device and combining with the initial metal layer; removing the carrier, and then selectively removing the initial metal layer to at least reserve and form an independent metal connecting block electrically connected with the terminal of the passive device; exposing the bonding pad of the active device; and manufacturing redistribution lines on the surface of the plastic sealing body based on the independent metal connecting block and the exposed bonding pad, so as to realize the electrical interconnection between the active device and the passive device. The application sets an initial metal layer as a process interface, bypasses the fundamental difficulty that the heterogeneous surfaces cannot directly co-manufacture lines, and realizes high-density heterogeneous integration without customizing a substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a heterogeneous device integrated packaging structure and method. Background Technology

[0002] With the continuous development of integrated circuit technology, the requirements for product computing power, performance, size, power consumption, and cost are increasing. As Moore's Law approaches its physical limits, improving performance from a chip manufacturing process perspective is becoming increasingly difficult, leading the integrated circuit industry to focus more on advanced packaging technologies. Heterogeneous integration of active devices (such as logic chips and memory) and passive devices (such as capacitors, resistors, and inductors) in three-dimensional space can effectively reduce product size, shorten interconnect lengths, and lower signal delay and power consumption. This is a key path to achieving system miniaturization, functional modularization, and high performance.

[0003] However, this technological approach faces a significant bottleneck in process compatibility. Currently, the electrode terminals of mainstream low-cost, standardized surface-mount passive devices are typically made of tin (Sn) or tin alloys. While tin terminals offer good solderability, they possess inherent characteristics such as a low melting point, susceptibility to oxidation, and poor adhesion to advanced wiring processes. In contrast, the input / output pads of active devices are generally made of aluminum (Al) or copper (Cu). This heterogeneity in surface materials makes it impossible to directly fabricate high-density, high-reliability interconnects on both using the same set of standard redistribution line (RDL) processes (such as seed layer deposition and electroplating). Tin may melt or undergo electrochemical migration during subsequent high-temperature processes, severely impacting the feasibility of achieving high-density heterogeneous integration using advanced board-level packaging processes such as fan-out.

[0004] To circumvent this problem, the current mainstream solution in the industry is to use customized packaging substrates. This solution mounts active and passive devices separately on a customized substrate with pre-fabricated multilayer interconnect lines, achieving interconnection through internal traces within the substrate. However, this solution has significant drawbacks: First, it has a long development cycle, with each new product requiring a lengthy process of substrate design, manufacturing, and verification, making it unsuitable for rapidly iterating market demands; second, it is costly, as the customized substrate itself is expensive, and it adds additional component and assembly costs; third, it limits integration density, as the substrate linewidth and spacing are typically much larger than wafer-level or board-level RDL processes, making it difficult to meet higher-performance interconnect requirements.

[0005] Therefore, the industry urgently needs an innovative packaging method that can overcome the process limitations of heterogeneous surface materials and directly build high-density interconnects on top of devices, thereby getting rid of dependence on custom substrates and achieving heterogeneous integration of active and passive devices with short development cycles, low costs, and high integration density. Summary of the Invention

[0006] To address the aforementioned technical problems, the present invention aims to provide a heterogeneous device integrated packaging structure and method. By setting a unified initial metal layer as the process interface, the present invention circumvents the fundamental difficulty of directly co-fabricating circuits on heterogeneous surfaces, achieving high-density heterogeneous integration without the need for a custom substrate.

[0007] To achieve the above-mentioned technical objectives and effects, the present invention is implemented through the following technical solution: This invention provides a method for integrating and packaging heterogeneous devices, comprising the following steps: A carrier is provided, the surface of which has an initial metal layer; At least one active device and at least one passive device are mounted on the initial metal layer; Molding compound is used to form a molded body that encapsulates the active and passive devices and bonds them to the initial metal layer; After removing the carrier, the initial metal layer is selectively removed to at least retain and form an independent metal connection block that is electrically connected to the terminals of the passive device; Expose the pads of the active device; On the surface of the molding compound, redistribution lines are fabricated based on the independent metal connectors and exposed pads to achieve electrical interconnection between the active and passive devices.

[0008] Furthermore, the carrier is a copper-clad laminate with a separable copper foil, and the initial metal layer is the separable copper foil.

[0009] Furthermore, before mounting the active and passive devices, the method includes a step of forming a temporary positioning structure on the initial metal layer, wherein the active and passive devices are mounted within an area defined by the temporary positioning structure; the temporary positioning structure is removed before molding.

[0010] Furthermore, the temporary positioning structure is made of photoresist or photolithographic dry film through a photolithography process.

[0011] Furthermore, the passive devices are mounted onto the initial metal layer by printing solder paste and using surface mount technology; the active devices are mounted onto the initial metal layer by bonding adhesive or bonding film.

[0012] Furthermore, the step of selectively removing the initial metal layer includes: using photolithography and etching processes to ensure that the initial metal layer is retained only in the region corresponding to the terminal of the passive device, thereby forming the independent metal interconnect block.

[0013] Furthermore, the step of exposing the active device pads includes removing the bonding adhesive or bonding film on the pads by laser drilling at the locations corresponding to the pads.

[0014] Furthermore, the heterogeneous device integration packaging method further includes: after the redistribution circuit is fabricated, the molding compound is thinned and ground to expose the back side of the active device.

[0015] Furthermore, the terminal surface of the passive device is made of tin or a tin alloy.

[0016] Another aspect of the present invention provides a heterogeneous device integrated packaging structure, which is obtained by the above packaging method and includes: A plastic encapsulation having at least one active device and at least one passive device embedded therein; The redistribution circuit is disposed on one surface of the molding compound and is used to realize the electrical interconnection between the active device and the passive device; The redistribution line includes a metal connection portion that directly contacts the terminals of the passive device, and an interconnection line portion that connects to the pads of the active device.

[0017] The beneficial effects of this invention are as follows: This invention innovatively constructs a unified metal process interface on the surface of heterogeneous devices by providing an initial metal layer, thereby transforming the complex problem of "heterogeneous material surface compatibility" into the problem of "homogeneous metal layer patterning". Subsequently, through the step of "selective removal of the initial metal layer", the "in-situ functional conversion" of the initial metal layer material is achieved. That is, the precisely preserved metal layer portion is directly formed into an independent metal connector block that is integrally connected with the passive device terminals. This serves as the preset substrate for redistribution circuitry and completes the structural reuse from the initial process interface to the permanent circuit. Based on the above interface reconstruction and structural conversion, the method of this invention can directly fabricate high-density redistribution circuitry on the molding compound, which not only achieves better electrical performance (high density, short delay) but also eliminates the dependence on high-cost, long-cycle custom packaging substrates. At the same time, it allows the direct use of low-cost standardized tin-terminal passive devices and enables interconnections with finer linewidths and spacings and higher wiring freedom, significantly improving integration density and electrical performance.

[0018] In summary, this invention effectively solves the core challenges currently faced in the heterogeneous integration of active and passive devices, enabling advanced board-level packaging with high performance, high density, low cost, and short cycle time. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure obtained in step S1 of the packaging method of the present invention.

[0020] Figure 2This is a schematic diagram of the structure obtained in step S2 of the packaging method of the present invention.

[0021] Figure 3 This is a schematic diagram of the structure obtained in step S3 of the packaging method of the present invention.

[0022] Figure 4 This is a schematic diagram of the structure obtained in step S4 of the packaging method of the present invention.

[0023] Figure 5 This is a schematic diagram of the structure obtained in step S5 of the packaging method of the present invention.

[0024] Figure 6 This is a schematic diagram of the structure obtained in step S6 of the packaging method of the present invention.

[0025] Figure 7 This is a schematic diagram of the structure obtained in step S7 of the packaging method of the present invention.

[0026] In the figure, 10: carrier; 20: initial metal layer; 201: independent metal connector block; 30: temporary positioning structure; 40: passive device; 50: active device; 60: encapsulation; 70: temporary bonding board; 80: redistribution line; 90: insulating dielectric layer; 100: external conductive structure. Detailed Implementation

[0027] The technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] This invention provides a method for integrating and packaging heterogeneous devices, comprising the following steps: Step 1, refer to Figure 1 A carrier 10 is provided, the surface of which has an initial metal layer 20; Preferably, the carrier 10 is a copper-clad laminate with a separable copper foil, and the initial metal layer 20 is the separable copper foil. The separable copper foil has excellent surface flatness, conductivity, and adhesion to the molding compound. At the same time, its "separable" characteristic ensures that the carrier can be cleanly removed after molding, allowing the initial metal layer 20 to be retained and become the substrate for subsequent processes.

[0029] Step two, refer to Figure 2A photoresist or photolithographic dry film is applied to the initial metal layer 20, and a temporary positioning structure 30 is formed by photolithography. At least one passive device 40 is mounted onto the area defined by the temporary positioning structure 30 on the initial metal layer 20 by printing solder paste and using surface mount technology. At least one active device 50 is mounted onto the area defined by the temporary positioning structure 30 on the initial metal layer 20 by bonding adhesive or bonding film. The active surface (the side with the pads) of the active device 50 faces the initial metal layer 20. The terminal surface of the passive device 40 is made of tin or tin alloy. The temporary positioning structure 30 can precisely define the placement position of each device before packaging, ensuring the accuracy of the spatial layout of active and passive devices, which is a prerequisite for achieving high-density interconnection, and also avoids the displacement of devices during the molding process.

[0030] Step 3, refer to Figure 3 The temporary positioning structure 30 is removed, and molding compound is used to form a molding compound 60 that encapsulates the active device 50 and the passive device 40 and bonds them to the initial metal layer 20.

[0031] Step 4, refer to Figure 4 and Figure 5 The carrier 10 is removed, and a temporary bonding plate 70 is bonded to the side of the molding compound 60 away from the initial metal layer 20. Then, the initial metal layer 20 is selectively removed by photolithography and etching processes to at least retain the metal layer area corresponding to the terminal of the passive device 40, forming an independent metal connection block 201 electrically connected to the terminal of the passive device 40.

[0032] Step 5, refer to Figure 5 Holes are made in the bonding adhesive or bonding film of the corresponding active device 50 through laser drilling process to expose the bonding pads of the active device 50.

[0033] Step Six, refer to Figure 6 On the surface of the molding compound 60, a redistribution circuit 80 is fabricated based on independent metal connectors 201 and exposed pads. The independent metal connectors 201 become part of the redistribution circuit 80, realizing electrical interconnection between active devices 50 and passive devices 40. Furthermore, the redistribution circuit 80 has one or more layers, each layer of redistribution circuit 80 being covered with an insulating dielectric layer 90. Additionally, on the outermost insulating dielectric layer 90, an opening is formed, and an external conductive structure 100, such as a solder ball, is formed at the opening. This external conductive structure 100 is electrically connected to the redistribution circuit 80.

[0034] Step 7, refer to Figure 7Removing the temporary bonding plate 70 and thinning and grinding the molding compound 60 to expose the back of the active device 50 can improve the heat dissipation capacity of the package structure, thereby enhancing the reliability and performance potential of the product.

[0035] like Figure 7 As shown, the heterogeneous device integrated packaging structure obtained by the above packaging method includes: The encapsulation 60 has at least one active device 50 and at least one passive device 40 embedded therein; A redistribution line 80 is disposed on one surface of the encapsulation 60 to realize the electrical interconnection between the active device 50 and the passive device 40; The redistribution line 80 includes a metal connection portion that directly contacts the terminals of the passive device 40 (formed by continuing to fabricate the redistribution line 80 on the basis of the independent metal connection block 201), and an interconnection line portion that is connected to the pads of the active device 50. The redistribution line 80 has one or more layers, and each layer of redistribution line 80 is covered with an insulating dielectric layer 90. The outermost insulating dielectric layer 90 has a window, and an external conductive structure 100 is formed at the window. The external conductive structure 100 is electrically connected to the redistribution line 80.

[0036] Example This embodiment provides a specific heterogeneous device integration packaging method for integrating a system-on-a-chip (SoC, as an active device 50) and a multilayer ceramic capacitor (MLCC, as a passive device 40) into a package.

[0037] S1. Preparing the carrier and initial metal layer like Figure 1 As shown, a copper-clad laminate is provided as a carrier 10. On one side surface of the copper-clad laminate, a removable copper foil is temporarily bonded by heat-release adhesive, which serves as the initial metal layer 20.

[0038] S2. Form a temporary positioning structure and mount the components. A layer of positive photoresist is spin-coated onto the initial metal layer 20, and then a temporary positioning structure 30 is formed by photolithography (including exposure and development). The temporary positioning structure 30 includes a positioning frame area for placing an active device 50 (SoC chip) and a positioning frame area for placing a passive device 40 (MLCC); Mounting active device 50: Apply bonding adhesive to the positioning frame area of ​​active device 50, then precisely mount the active device 50 with the active side (the side with the pads) facing down in the corresponding positioning frame area. The chip is then fixed by curing. Mounting passive component 40: Solder paste is printed on a stencil in the positioning frame area of ​​passive component 40. Then, a high-precision pick-and-place machine is used to mount the passive component 40 (with Sn terminal surface) onto the solder paste in the corresponding positioning frame area. After completion, reflow soldering is performed to melt the solder paste and form a reliable metallurgical bond with the solder terminals of passive component 40 and the underlying initial metal layer 20. The structure obtained in step S2 is as follows Figure 2 As shown.

[0039] S3. Remove the temporary positioning structure and seal it. The photoresist serving as the temporary positioning structure 30 is completely removed by immersion in acetone solution and ultrasonic cleaning. Then, the entire structure is placed in a mold and molded using an encapsulating compound (EMC, composed of epoxy resin and silica filler) to form a molded body 60. The molded body 60 encapsulates the active device 50 and the passive device 40 and firmly bonds them to the initial metal layer 20, achieving the desired result. Figure 3 The structure shown.

[0040] S4. Remove carrier The structure obtained in step S3 is placed on a hot plate and heated to cause the heat-release adhesive to lose its stickiness, thereby removing the carrier 10 while the initial metal layer 20 (separable copper foil) remains intact on the surface of the molding compound 60. Then, a temporary bonding plate 70 (glass carrier) is bonded to the back of the molding compound 60 (the side without separable copper foil) to provide support, resulting in the structure shown in the image. Figure 4 The structure shown.

[0041] S5. Graphicalize the initial metal layer and expose the active device pads. A photoresist is coated on the surface of the initial metal layer 20. After exposure and development, a patterned mask is formed. The pattern of this mask only exposes the copper foil area that needs to be removed, while protecting the copper foil area corresponding to the terminals of the passive device 40. Then, a wet etching process is used to completely remove the unprotected copper foil. After etching, only a copper foil area matching the shape and size of the terminals is retained at each of the two tin terminals of each passive device 40, which is the independent metal connection block 201. The copper foil area above the active device 50 is completely etched away.

[0042] For the pads of the active device 50, an ultraviolet laser drilling machine is used to create laser holes in the bonding adhesive above them. Laser parameter settings ensure precise removal of the bonding adhesive without damaging the pads below. After drilling, the pads of the active device 50 are exposed, obtaining... Figure 5 The structure shown.

[0043] S6. Create redistribution lines like Figure 6As shown, a first layer of redistribution circuitry 80 is fabricated on the entire surface of the structure (including the surface of the molding compound 60, the pads of the exposed active device 50, and the independent metal interconnects 201 on the passive device 40). This layer of circuitry is formed through standard processes such as seed layer deposition, photolithography, electroplating, and patterning. The redistribution circuitry 80 is electrically connected to the pads of the active device 50, and the independent metal interconnects 201 become part of the redistribution circuitry 80. Subsequently, a layer of silicon dioxide is deposited as the first insulating dielectric layer 90 on the completed first layer of redistribution circuitry 80 and the surface of the structure. Vias are then created on the insulating dielectric layer 90 using photolithography and etching processes to expose the areas of the circuitry that need to be interconnected. By repeating the above steps of "fabricating redistribution circuitry - depositing insulating dielectric layer - creating vias", a multilayer redistribution circuitry 80 can be constructed. In this embodiment, two layers of redistribution circuitry 80 are fabricated. Finally, windows are created on the uppermost insulating dielectric layer 90, and solder balls are formed as external conductive structures 100.

[0044] S7, Post-processing like Figure 7 As shown, the temporary bonding board 70 on the back is removed. The package structure is placed on a grinder and its back side (i.e., the side where the active device 50 is located) is thinned and ground to remove the molding compound, exposing the back side of the active device 50 (SoC chip) to enhance heat dissipation.

[0045] Through the above steps, a high-density, highly integrated heterogeneous device integrated packaging structure is obtained, such as... Figure 7 As shown. The packaging structure of this embodiment includes: The encapsulation 60 has an active device 50 and a passive device 40 embedded therein; A redistribution line 80 is disposed on one surface of the encapsulation 60 to realize the electrical interconnection between the active device 50 and the passive device 40; The redistribution line 80 includes a metal connection portion that directly contacts the terminals of the passive device 40 (formed by continuing to fabricate the redistribution line 80 on the basis of the independent metal connection block 201), and an interconnection line portion that is connected to the pads of the active device 50.

[0046] In this embodiment, the redistribution line 80 has a two-layer structure, with each layer of redistribution line 80 covered by an insulating dielectric layer 90. The outermost insulating dielectric layer 90 has a window, and an external conductive structure 100 is formed at the window. The external conductive structure 100 is electrically connected to the redistribution line 80. In this embodiment, the external conductive structure 100 is a solder ball.

[0047] This invention bypasses the fundamental problem that heterogeneous surfaces cannot be directly co-fabricated with circuits by setting a unified initial metal layer as the process interface, and realizes high-density heterogeneous integration without the need for a custom substrate.

[0048] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0049] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for integrating and packaging heterogeneous devices, characterized in that, Includes the following steps: A carrier is provided, the surface of which has an initial metal layer; At least one active device and at least one passive device are mounted on the initial metal layer; the passive device is mounted onto the initial metal layer by printing solder paste and using surface mount technology. Molding compound is used to form a molded body that encapsulates the active and passive devices and bonds them to the initial metal layer; After removing the carrier, the initial metal layer is selectively removed to at least retain and form an independent metal connection block that is electrically connected to the terminals of the passive device; Expose the pads of the active device; On the surface of the molding compound, redistribution lines are fabricated based on the independent metal connectors and exposed pads to achieve electrical interconnection between the active and passive devices.

2. The heterogeneous device integration and packaging method according to claim 1, characterized in that, The carrier is a copper-clad laminate with a separable copper foil, and the initial metal layer is the separable copper foil.

3. The heterogeneous device integration and packaging method according to claim 1, characterized in that, Before mounting the active and passive devices, the process includes forming a temporary positioning structure on the initial metal layer, wherein the active and passive devices are mounted within an area defined by the temporary positioning structure; the temporary positioning structure is removed before molding.

4. The heterogeneous device integration and packaging method according to claim 3, characterized in that, The temporary positioning structure is made of photoresist or photolithographic dry film through a photolithography process.

5. The heterogeneous device integration and packaging method according to claim 1, characterized in that, The active device is attached to the initial metal layer by bonding adhesive or bonding film.

6. The heterogeneous device integration and packaging method according to claim 1, characterized in that, The step of selectively removing the initial metal layer includes: using photolithography and etching processes to ensure that the initial metal layer is retained only in the region corresponding to the terminal of the passive device, thereby forming the independent metal interconnect block.

7. The heterogeneous device integration and packaging method according to claim 5, characterized in that, The step of exposing the pads of the active device includes removing the bonding adhesive or bonding film thereon by laser drilling at the location corresponding to the pad.

8. The heterogeneous device integration and packaging method according to claim 1, characterized in that, Also includes: After the redistribution circuitry is fabricated, the encapsulation is thinned and ground to expose the back side of the active device.

9. The heterogeneous device integration and packaging method according to claim 1, characterized in that, The terminal surface of the passive device is made of tin or tin alloy.

10. A heterogeneous device integrated packaging structure, characterized in that, It is prepared by the method of any one of claims 1 to 9, comprising: A plastic encapsulation having at least one active device and at least one passive device embedded therein; The redistribution circuit is disposed on one surface of the molding compound and is used to realize the electrical interconnection between the active device and the passive device; The redistribution line includes a metal connection portion that directly contacts the terminals of the passive device, and an interconnection line portion that connects to the pads of the active device.

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