A photoelectric co-encapsulation structure and its preparation method

Abstract

This invention provides a photoelectric co-packaged structure and its fabrication method. The method involves a silicon photonic wafer where the device layer includes at least one device region with an optical port and a first pad. First, a lead-out post is formed penetrating the device region, and a first interconnect layer electrically connected to the first pad and the lead-out post is formed on the side of the device layer facing away from the substrate. Then, an electrical chip is bonded to the side of the first interconnect layer facing away from the device region, and the exposed second pad of the electrical chip is electrically connected to the first interconnect layer. The substrate layer is removed to expose the lead-out post, and a second interconnect layer is electrically connected through the lead-out post. The silicon photonic wafer is then diced to obtain a chip structure including a single device region with an optical port exposed on the sidewall. After electrically connecting the side of the second interconnect layer facing away from the device region to the substrate, an optical fiber array is optically interconnected with the optical port. The resulting photoelectric co-packaged structure not only has high interconnect density, low interconnect loss, small size, and high reliability, but also improves production efficiency and effectively reduces production costs.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology and relates to an optoelectronic co-encapsulation structure and its preparation method. Background Technology

[0002] With the development of technologies such as data centers, high-performance computers, and AI, the importance of optical communication technology is becoming increasingly prominent. Optical communication uses light waves as an information carrier to achieve high-speed, high-capacity, and low-loss data transmission, providing solid support for modern communication networks. To ensure stable connection and efficient communication between optical and electrical chips, the packaging technology of optical and electrical chips needs to achieve higher integration. Currently, 2D planar packaging, 2.5D packaging, and 3D stacked packaging processes are commonly used to package optical and electrical chips. While 2D planar packaging is technically simple and easy to implement, the high-speed signal interconnects between optical and electrical chips are relatively long and occupy a large area, severely limiting the number of I / O (input / output) ports on the chip. Although 2.5D packaging achieves a higher number of I / O ports and lower interconnection losses, the optical and electrical chips are still interconnected through silicon interposers, which cannot minimize losses and prevent the optical and electrical chips from being laid flat on the same plane, hindering further area reduction. Although 3D stacked packaging achieves the integration of optical and electrical chips, conductive bumps are required to connect the optical and electrical chips, preventing further reduction in interconnection density. This results in a large package size and limited reliability. Furthermore, due to the use of wire bonding technology, there are still significant interconnection losses between the optical and electrical chips and the substrate, leading to low production efficiency and high manufacturing costs.

[0003] Against this backdrop, in order to improve production efficiency, reduce manufacturing costs, and obtain optoelectronic chips with high interconnect density, low interconnect loss, small size, and high reliability, it is particularly urgent to develop a new fabrication method. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an optoelectronic co-encapsulation structure and its preparation method, so as to solve the problems of low interconnection density, high interconnection loss, large package size, low reliability, low production efficiency and high manufacturing cost of the prior art optoelectronic co-encapsulation structure.

[0005] To achieve the above and other related objectives, the present invention provides a method for preparing a photoelectric co-encapsulation structure, comprising the following steps:

[0006] A silicon photonics wafer including a substrate layer and a device layer is provided, wherein the device layer includes at least a device region, the device region having an optical port and a first pad exposing the upper surface of the device region;

[0007] A via is formed that penetrates the device region and exposes the surface of the substrate layer; a post is formed that fills the via; and a first interconnect layer is formed on the side of the device layer facing away from the substrate layer that is electrically connected to the first pad and the post.

[0008] Provide at least one electrical chip with a second pad exposed, the electrical chip is bonded to the side of the first interconnect layer opposite to the device region, and the second pad is electrically connected to the first interconnect layer;

[0009] A support substrate is formed on one side of the bonding electrode in the first interconnect layer, and the substrate layer is removed to expose the lead-out post;

[0010] A second interconnect layer electrically connected to the lead-out post is formed on the side of the device layer opposite to the first interconnect layer, and the silicon photonics wafer is divided to obtain a chip structure including a single device region and the optical port is exposed on the sidewalls;

[0011] A substrate is provided, the substrate is electrically connected to the side of the second interconnect layer opposite to the device region, and an optical fiber array is optically interconnected with the optical port.

[0012] Optionally, the electrical chip is bonded to the first interconnect layer via hybrid bonding.

[0013] Optionally, after bonding the electrical chip to the side of the first interconnect layer away from the device region, the method further includes the step of forming an insulating layer that encloses the sidewalls of the electrical chip.

[0014] Optionally, after forming the insulating layer that encloses the sidewalls of the electrical chip, the process further includes thinning the insulating layer.

[0015] Optionally, the method for removing the substrate layer includes chemical mechanical polishing, dry etching, and wet etching.

[0016] Optionally, the method for dividing the silicon photonic wafer includes dry etching, wet etching, and dicing.

[0017] Optionally, after forming the second interconnect layer electrically connected to the lead-out post and before dicing the silicon photonics wafer, the method further includes forming conductive bumps electrically connected to the second interconnect layer, wherein the substrate is electrically connected to the second interconnect layer through the conductive bumps.

[0018] Optionally, after the substrate is electrically connected to the second interconnect layer via the conductive bumps, the method further includes the step of forming a filler layer to fill the gap between the second interconnect layer and the substrate.

[0019] Optionally, after optically interconnecting the fiber array with the optical port, the method further includes the step of forming a fixing layer to fix the fiber array and the substrate.

[0020] The present invention also provides a photoelectric co-encapsulation structure, the photoelectric co-encapsulation structure comprising:

[0021] A chip structure includes a device layer, lead-out posts, a first interconnect layer, an electrical chip, and a second interconnect layer. The device layer has an optical port and a first pad, and the optical port is exposed on the sidewall of the chip structure. The lead-out posts penetrate the device layer. The first interconnect layer is electrically connected to the lead-out posts and the first pad. The electrical chip is bonded to the side of the first interconnect layer opposite to the device layer, and the second pad exposed by the electrical chip is electrically connected to the first interconnect layer. The second interconnect layer is located on the side of the device layer opposite to the first interconnect layer, and the second interconnect layer is electrically connected to the lead-out posts.

[0022] The substrate is electrically connected to the side of the second interconnect layer that is opposite to the device layer;

[0023] An optical fiber array is optically interconnected with the optical port.

[0024] As described above, the optoelectronic co-packaged structure and its fabrication method provided by this invention, by fabricating lead-out conductive pillars that penetrate the device layer and serve as electrical connections between the chip structure and the substrate before bonding the electronic chip to the device region, and then bonding the device layer and the electronic chip together using a hybrid bonding process, avoids the need to fabricate microbumps for interconnection between the optical chip and the electronic chip. Simultaneously, by extending the lead-out pillars of the chip structure from the side of the optical chip away from the electronic chip, the interconnection density is increased, interconnection loss is reduced, and the reliability of the optoelectronic co-packaged structure is improved. The optical port of the optical chip is exposed on the sidewall of the chip structure, facilitating optical interconnection of the optical chip. After the optical chip and the electronic chip are bonded, the volume of the chip structure is reduced by removing the substrate layer, further minimizing the volume of the optoelectronic co-packaged structure. Furthermore, the use of wafer-level processes not only improves production efficiency but also effectively reduces production costs. Attached Figure Description

[0025] Figure 1 The diagram shown is a flowchart illustrating a method for preparing a photoelectric co-encapsulation structure according to the present invention.

[0026] Figure 2 The diagram shows a cross-sectional view of a silicon photonic wafer provided by a method for fabricating a photoelectric co-sealing structure according to the present invention.

[0027] Figure 3 The diagram shown is a cross-sectional view of the photoelectric co-sealing structure after the formation of the lead-out hole, which is a method for preparing a photoelectric co-sealing structure according to the present invention.

[0028] Figure 4The diagram shown is a cross-sectional view of the photoelectric co-encapsulation structure after the formation of the lead-out pillars and the first interconnect layer, according to a method for fabricating a photoelectric co-encapsulation structure of the present invention.

[0029] Figure 5 The diagram shown is a cross-sectional view of the bonding electrode chip after the fabrication method of the optoelectronic co-sealing structure of the present invention.

[0030] Figure 6 The diagram shown is a cross-sectional view of the photoelectric co-sealing structure after the insulating layer is formed, according to a method for preparing a photoelectric co-sealing structure of the present invention.

[0031] Figure 7 The diagram shown is a cross-sectional view of the support substrate formed according to the method for fabricating an optoelectronic co-sealing structure of the present invention.

[0032] Figure 8 The diagram shows a cross-sectional structure after removing the substrate layer, which is a method for preparing an optoelectronic co-encapsulation structure according to the present invention.

[0033] Figure 9 The diagram shown is a cross-sectional view of the second interconnect layer after the fabrication method of the optoelectronic co-encapsulation structure of the present invention.

[0034] Figure 10 The diagram shown is a cross-sectional view of the conductive bumps formed in the preparation method of the optoelectronic co-sealing structure of the present invention.

[0035] Figure 11 The diagram shown is a cross-sectional view of a silicon photonic wafer after it has been sliced, illustrating a method for fabricating a photoelectric co-sealing structure according to the present invention.

[0036] Figure 12 The diagram shown is a cross-sectional view of a photoelectric co-encapsulation structure fabricated using a method for preparing a photoelectric co-encapsulation structure according to the present invention.

[0037] Reference numerals: 1-Silicon photonic wafer; 11-Substrate layer; 12-Device layer; 13-Device area; 14-Optical port; 15-First pad; 16-Lead-out via; 17-Lead-out post; 2-First interconnect layer; 21-First dielectric layer; 22-First metal wiring layer; 23-Third pad; 3-Electrical chip; 31-Second pad; 32-Insulating layer; 33-Supporting substrate; 4-Second interconnect layer; 41-Second dielectric layer; 42-Second metal wiring layer; 43-Fourth pad; 44-Conductive bump; 5-Substrate; 51-Fill layer; 6-Fiber array; 61-Fixing layer. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] Example 1

[0041] This invention provides a method for preparing a photoelectric co-encapsulation structure. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic flowchart of a method for preparing a photoelectric co-encapsulation structure according to the present invention; wherein the method includes the following steps:

[0042] Step S1: Provide a silicon photonics wafer 1 including a substrate layer 11 and a device layer 12. The device layer 12 includes at least a device region 13. The device region 13 has an optical port 14 and a first pad 15 exposed on the upper surface of the device region 13. A cross-sectional structural schematic diagram of the silicon photonics wafer 1 can be found in [reference needed]. Figure 2 As shown.

[0043] Specifically, the thickness and planar dimensions of the silicon photonics wafer 1 can be selected according to actual needs. The substrate layer 11 and the device layer 12 are stacked sequentially. The thickness and planar dimensions of the substrate layer 11 and the device layer 12 can be selected according to actual needs. The number and planar dimensions of the device regions 13 can be selected according to actual needs. It should be noted that the present invention does not specifically limit the type of optical chip in each device region 13. The number and size of the optical ports 14 and the number and size of the first pads 15 can be selected according to actual needs. It should be noted that the optical ports 14 are located in the edge region of the device layer 12 corresponding to the device region 13.

[0044] Step S2: A via 16 is formed that penetrates the device region 13 and exposes the surface of the substrate layer 11; a post 17 is formed that fills the via 16; and a first interconnect layer 2 is formed on the side of the device layer 12 facing away from the substrate layer 11, which is electrically connected to the first pad 15 and the post 17. Figure 3 To form a schematic diagram of the cross-sectional structure after the lead-out hole 16 is formed. Figure 4A schematic diagram of the cross-sectional structure after the formation of the lead-out pillars and the first interconnect layer 2.

[0045] Specifically, the methods for fabricating the lead-out holes 16 include dry etching, wet etching, or other suitable fabrication methods. The number and size of the lead-out holes 16 can be selected according to actual needs. The methods for fabricating the lead-out posts 17 include magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or other suitable methods.

[0046] Specifically, the first interconnect layer 2 includes a third pad 23 and alternating layers of a first dielectric layer 21 and a first metal wiring layer 22. The first metal wiring layer 22 is used to realize wiring and interconnection between wiring layers. The number of alternating layers of the first dielectric layer 21 and the first metal wiring layer 22 can be selected according to actual needs while ensuring device performance. The fabrication of the first dielectric layer 21 includes spin coating, atomic layer deposition, chemical vapor deposition, physical vapor deposition, or other suitable methods. The fabrication of the first metal wiring layer 22 includes magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or other suitable methods. The fabrication of the third pad 23 includes magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or other suitable methods. The third pad 23 exposes the surface of the first dielectric layer 21 and is electrically connected to the first metal wiring layer 22.

[0047] See Figure 5 As shown, step S3 is performed: at least one electrical chip 3 exposing the second pad 31 is provided, the electrical chip 3 is bonded to the side of the first interconnect layer 2 facing away from the device region 13, and the second pad 31 is electrically connected to the first interconnect layer 2, wherein, Figure 5 This is a schematic diagram of the cross-sectional structure of the bonded electrical chip 3.

[0048] Specifically, the number and size of the second pad 31 can be selected according to actual needs, and the size, number and type of the electrical chip 3 can be selected according to actual needs. It should be noted that the electrical chip 3 and the device area 13 correspond one-to-one, and the bonding method between the electrical chip 3 and the first interconnect layer 2 can be selected according to actual needs.

[0049] Specifically, the device layer 12 and the electrical chip 3 are mechanically fixed and electrically connected through the lead-out post 17 and the first interconnect layer 2, eliminating the need for bump interconnects and completely avoiding the through-silicon via (TSV) structure. This not only improves production efficiency and effectively reduces production costs, but also increases the upper limit of interconnect density, greatly shortens the interconnect path, avoids the use of gaps and fillers, and eliminates the reliability issues caused by the TSV structure itself, while reducing the thickness of the chip structure.

[0050] In one exemplary embodiment, the electrical chip 3 is bonded to the first interconnect layer 2 via hybrid bonding.

[0051] Specifically, the electrical chip 3 is bonded to the surface of the first interconnect layer 2 by a hybrid bonding method, eliminating the need to fabricate microbumps to interconnect the electrical chip 3 and the first interconnect layer 2, thereby reducing the size of the chip structure subsequently fabricated.

[0052] In one exemplary embodiment, after bonding the electrical chip 3 to the side of the first interconnect layer 2 facing away from the device region 13, the method further includes forming an insulating layer 32 that surrounds the sidewalls of the electrical chip 3, specifically as follows: Figure 6 As shown, Figure 6 This is a schematic diagram of the cross-sectional structure after the insulation layer 32.

[0053] Specifically, the insulating layer 32 is made of materials including polybenzoxazole, benzocyclobutene, epoxy resin, polyimide or other suitable materials. The method of making the insulating layer 32 includes molding, vacuum lamination, spin coating or other suitable methods. It should be noted that while the insulating layer 32 wraps the sidewall of the electrical chip 3, the insulating layer 32 also fills the gaps between multiple electrical chips 3.

[0054] In one exemplary embodiment, after forming the insulating layer 32 that encloses the sidewalls of the electrical chip 3, a thinning process for the insulating layer 32 is further included.

[0055] Specifically, thinning methods include chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0056] Specifically, by thinning the insulating layer 32 to expose the back side of the electrical chip 3 (the back side of the electrical chip 3 is the side of the electrical chip 3 that faces away from the first interconnect layer 2), the heat dissipation of the electrical chip 3 is facilitated, and the heat dissipation capacity of the packaging structure is improved.

[0057] Please see Figure 7 and 8 Step S4: A support substrate 33 is formed on one side of the first interconnect layer 2 where the bonding electrode 3 is located, and the substrate layer 11 is removed to expose the lead-out post 17, wherein, Figure 7 This is a schematic diagram of the cross-sectional structure after the support substrate 33 is formed. Figure 8 This is a schematic diagram of the cross-sectional structure after removing the substrate layer 11.

[0058] Specifically, the material of the support substrate 33 includes silicon wafers, glass plates, sapphire plates, or other suitable substrates, and the thickness and planar dimensions of the support substrate 33 can be selected according to actual needs. This invention does not specifically limit the method of forming the support substrate 33. For example, the support substrate 33 is formed by bonding it to the side of the electrical chip 3 facing away from the first interconnect layer 2.

[0059] Specifically, by completely removing the substrate layer 11, the thickness of the optoelectronic co-encapsulation structure can be significantly reduced, which is more conducive to the miniaturization of the packaging structure.

[0060] In another exemplary embodiment, after the insulating layer 32 is thinned, a support substrate 33 is formed on the side of the insulating layer 32 and the electrical chip 3 facing away from the first interconnect layer 2.

[0061] Specifically, the support substrate 33 and the insulating layer 32 are bonded or adhered to the side opposite to the first interconnect layer 2, and the electrical chip 3 is bonded or adhered to the side opposite to the first interconnect layer 2.

[0062] In one exemplary embodiment, the method for removing the substrate layer 11 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0063] Specifically, the method for removing the substrate layer 11 can be one or a combination of the above methods, and the specific process parameters can also be set according to actual needs.

[0064] Please see Figure 9-11 Step S5: A second interconnect layer 4 electrically connected to the lead-out post 17 is formed on the side of the device layer 12 opposite to the first interconnect layer 2, and the silicon photonics wafer 1 is divided to obtain a chip structure including a single device region 13 and with the sidewalls exposing the light port 14. The cross-sectional structure of the chip structure is as follows: Figure 11 As shown.

[0065] Specifically, the second interconnect layer 4 includes a fourth pad 43 and alternating layers of a second dielectric layer 41 and a second metal wiring layer 42. The second metal wiring layer 42 is used to implement wiring and interconnection between wiring layers. The number of alternating layers of the second dielectric layer 41 and the second metal wiring layer 42 can be selected according to actual needs while ensuring device performance. The fabrication of the second dielectric layer 41 includes spin coating, atomic layer deposition, chemical vapor deposition, physical vapor deposition, or other suitable methods. The fabrication of the second metal wiring layer 42 includes magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or other suitable methods. The fabrication of the fourth pad 43 includes magnetron sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or other suitable methods. The fourth pad 43 exposes the surface of the second dielectric layer 41 and is electrically connected to the second metal wiring layer 42.

[0066] Specifically, the silicon photonic wafer 1 (which at this time includes at least a device layer 12, lead-out pillars 17, a first interconnect layer 2, an electrical chip 3, and a second interconnect layer 4) is divided along the edge of the device region 13 to obtain a chip structure that includes a single device region 13 and has a light port 14 exposed on the sidewall. In other words, the sidewall of the chip structure exposes the light port 14. More specifically, in the chip structure, the sidewall of the device layer 12 corresponding to the device region 13 exposes the light port 14.

[0067] In one exemplary embodiment, after forming the second interconnect layer 4 electrically connected to the lead-out post 17 and before dicing the silicon photonics wafer 1, the step of forming conductive bumps 44 electrically connected to the second interconnect layer 4 is further included.

[0068] Specifically, the conductive bump 44 can be made of materials such as tin, copper, aluminum, silver, gold, nickel, titanium, indium, or other conductive materials. The size and quantity of the conductive bump 44 can be selected according to actual needs. The methods for manufacturing the conductive bump 44 include reflow soldering, ball bonding, or other suitable methods, as detailed below. Figure 10 As shown, Figure 10 This is a schematic diagram of the cross-sectional structure after the conductive bump 44 is formed.

[0069] In one exemplary embodiment, the method for dicing the silicon photonics wafer 1 includes dry etching, wet etching, dicing, or other suitable methods.

[0070] Specifically, the cutting methods include wire cutting and knife cutting. The specific process parameters for wire cutting or knife cutting can be selected according to actual needs.

[0071] Step S6: Provide a substrate 5, electrically connect the substrate 5 to the side of the second interconnect layer 4 facing away from the device region 13, and optically interconnect the fiber array 6 with the optical port 14 to obtain an optoelectronic co-encapsulation structure as shown below. Figure 12 As shown, Figure 12 This is a cross-sectional schematic diagram of a photoelectric co-sealing structure.

[0072] Specifically, while ensuring device performance, the size and thickness of the substrate 5 can be selected according to actual needs, the size of the fiber array 6 can be selected according to actual needs, and the fiber arrangement in the fiber array 6 can be selected according to actual needs.

[0073] In one exemplary embodiment, the substrate 5 is electrically connected to the second interconnect layer 4 via conductive bumps 44.

[0074] Specifically, the conductive bump 44 is electrically connected to the second interconnect layer 4 by reflow soldering or other suitable methods.

[0075] In one exemplary embodiment, after the substrate 5 is electrically connected to the second interconnect layer 4 via conductive bumps 44, the step further includes forming a filling layer 51 to fill the gap between the second interconnect layer 4 and the substrate 5.

[0076] Specifically, the filling layer 51 is made of epoxy resin, polyimide, polybenzoxazole, benzocyclobutene or other suitable dielectric filling materials, forming a filling layer 51 between the second interconnect layer 4 and the substrate 5, so as to ensure the electrical contact performance between the conductive bump 44 and the second interconnect layer 4 and the substrate 5, and improve the reliability of the optoelectronic co-encapsulation structure.

[0077] In one exemplary embodiment, after optically interconnecting the fiber array 6 with the optical port 14, the method further includes forming a fixing layer 61 that fixes the fiber array 6 and the substrate 5.

[0078] Specifically, bottom filler adhesive is usually used as the material of the fixing layer 61. Under the premise of ensuring the stability of the fiber array 6 and the substrate 5, it can completely fill the gap between the fiber array 6 and the substrate 5, or partially fill the gap between the fiber array 6 and the substrate 5.

[0079] In another exemplary embodiment, after forming the fixing layer 61 that fixes the fiber array 6 and the substrate 5, the step of removing the support substrate 33 is also included.

[0080] Specifically, the methods for removing the support substrate 33 include dry etching, wet etching, or other suitable methods.

[0081] Example 2

[0082] This invention also provides a photoelectric co-packaging structure, which is obtained by any of the photoelectric co-packaging structure preparation methods provided in Example 1. The photoelectric co-packaging structure includes at least: a chip structure, a substrate 5, and an optical fiber array 6. The chip structure includes at least a device layer 12, lead-out posts 17, a first interconnect layer 2, an electrical chip 3, and a second interconnect layer 4. The device layer 12 has an optical port 14 and a first pad 15, and the optical port 14 is exposed on the sidewall of the chip structure. The lead-out posts 17 penetrate the device layer 12. The first interconnect layer 2 is electrically connected to the lead-out posts 17 and the first pad 15. The electrical chip 3 is bonded to the side of the first interconnect layer 2 opposite to the device layer 12, and the second pad 31 exposed by the electrical chip 3 is electrically connected to the first interconnect layer 2. The second interconnect layer 4 is located on the side of the device layer 12 opposite to the first interconnect layer 2, and the second interconnect layer 4 is electrically connected to the lead-out posts 17. The substrate 5 is electrically connected to the side of the second interconnect layer 4 opposite to the device layer 12. The optical fiber array 6 is optically interconnected with the optical port 14.

[0083] Specifically, the device layer 12 in the chip structure is the device layer 12 corresponding to the device region 13 obtained by dividing the silicon photonic wafer along the edge of the device region 13, and the device layer 12 in the chip structure is an optical chip structure.

[0084] Specifically, the material of the lead-out post 17 includes copper, nickel, silver, gold, palladium, tin, aluminum, tantalum, titanium, tungsten, or other suitable conductive materials. The lead-out post 17 is usually a conductive lead-out post for interconnecting the chip structure with the external circuit. The lead-out post 17 is electrically connected to the substrate 5 through the second interconnect layer 4.

[0085] Specifically, optical port 14 is an optical coupling end face, which is optically interconnected with the internal structure of device layer 12.

[0086] Specifically, the second pad 31 is electrically connected to the internal structure of the electrical chip 3. The second pad 31 is located on the front side of the electrical chip 3, and the height of the exposed surface of the second pad 31 relative to the back side of the electrical chip 3 is not higher than the height of the front side of the electrical chip 3 relative to the back side of the electrical chip 3.

[0087] Specifically, the third pad 23 exposes the surface of the first interconnect layer 2, and the surface of the metal pad does not protrude from the surface of the first interconnect layer 2. The electrical chip 3 is fully bonded to the first interconnect layer 2, and the second pad 31 is fully bonded to the third pad 23 to achieve electrical connection. The material of the third pad 23 includes copper, nickel, silver, gold, palladium, tin, aluminum, tantalum, titanium, tungsten, or other suitable conductive materials. The material of the first metal wiring layer 22 includes copper, nickel, silver, gold, palladium, tin, aluminum, tantalum, titanium, tungsten, or other suitable conductive materials. The material of the first dielectric layer 21 includes polybenzoxazole, benzocyclobutene, epoxy resin, polyimide, phosphosilicate glass, fluorinated glass, silicon oxide, or other suitable dielectric materials. For example, a redistribution layer is used as the first interconnect layer 2.

[0088] Specifically, the material of the fourth pad 43 includes copper, nickel, silver, gold, palladium, tin, aluminum, tantalum, titanium, tungsten, or other suitable conductive materials; the material of the second metal wiring layer 42 includes copper, nickel, silver, gold, palladium, tin, aluminum, tantalum, titanium, tungsten, or other suitable conductive materials; and the material of the second dielectric layer 41 includes polybenzoxazole, benzocyclobutene, epoxy resin, polyimide, phosphosilicate glass, fluorinated glass, silicon oxide, or other suitable dielectric materials. For example, a redistribution layer is used as the second interconnect layer 4.

[0089] Specifically, the present invention provides a method for fabricating a photoelectric co-encapsulated structure. This method employs wafer-level processes to fabricate multiple photoelectric co-encapsulated structures in a single process, improving production efficiency. By fabricating lead-out pillars 17 penetrating the device layer 12, the first interconnect layer 2 is electrically connected to the electrical chip 3. Simultaneously, the lead-out pillars 17 also serve as conductive leads in the chip structure formed by the device layer 12 and the electrical chip 3, connecting to the substrate 5 via the second interconnect layer 4. Mechanical fixation and electrical connection between the device layer 12 and the electrical chip 3 can be achieved without the need for bump interconnects, completely avoiding through-silicon via (TSV) structures. This not only improves production efficiency and effectively reduces production costs but also increases the upper limit of interconnect density, significantly shortens the interconnect path, avoids the use of gaps and fillers, and eliminates reliability issues inherent in TSV structures. It also reduces the thickness of the chip structure. By completely removing the photoelectric chip substrate structure (referring to substrate layer 11), the thickness of the photoelectric co-encapsulated structure can be significantly reduced, making miniaturization more feasible.

[0090] In summary, the present invention provides an optoelectronic co-packaged structure and its fabrication method. This method involves fabricating conductive posts that penetrate the device layer and serve as electrical connections between the chip structure and the substrate before bonding the electronic chip to the device region. The device layer and the electronic chip are then bonded together using a hybrid bonding process. This avoids the need for fabricating microbumps for interconnecting the optical and electronic chips. Furthermore, by extending the conductive posts from the side of the optical chip away from the electronic chip, interconnect density is increased, interconnect loss is reduced, and the reliability of the optoelectronic co-packaged structure is improved. The optical port of the optical chip is exposed on the sidewall of the chip structure, facilitating optical interconnection. After bonding the optical and electronic chips, the volume of the chip structure is reduced by removing the substrate layer, further minimizing the overall size of the optoelectronic co-packaged structure. In addition, the use of wafer-level processes not only improves production efficiency but also effectively reduces production costs.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a photoelectric co-encapsulation structure, characterized in that, Includes the following steps: A silicon photonics wafer including a substrate layer and a device layer is provided, wherein the device layer includes at least a device region, the device region having an optical port and a first pad exposing the upper surface of the device region; A via is formed that penetrates the device region and exposes the surface of the substrate layer. A lead-out post is formed that fills the via. A first interconnect layer is formed on the side of the device layer facing away from the substrate layer that is electrically connected to the first pad and the lead-out post. A redistribution layer is used as the first interconnect layer. Provide at least one electrical chip with a second pad exposed, bond the electrical chip to a side of the first interconnect layer away from the device region, and electrically connect the second pad to the first interconnect layer, wherein the electrical chip is bonded to the first interconnect layer in a manner including hybrid bonding; A support substrate is formed on one side of the bonding electrode in the first interconnect layer, and the substrate layer is removed to expose the lead-out post; A second interconnect layer electrically connected to the lead-out post is formed on the side of the device layer opposite to the first interconnect layer, and the silicon photonics wafer is divided to obtain a chip structure including a single device region and the optical port is exposed on the sidewall. A redistribution layer is used as the second interconnect layer. A substrate is provided, the substrate is electrically connected to the side of the second interconnect layer opposite to the device region, and an optical fiber array is optically interconnected with the optical port.

2. The method for preparing the optoelectronic co-encapsulation structure according to claim 1, characterized in that: After bonding the electrical chip to the side of the first interconnect layer away from the device region, the process further includes forming an insulating layer that wraps around the sidewalls of the electrical chip.

3. The method for preparing the optoelectronic co-encapsulation structure according to claim 2, characterized in that: After forming the insulating layer that encloses the sidewalls of the electrical chip, the process further includes thinning the insulating layer.

4. The method for preparing the optoelectronic co-encapsulation structure according to claim 1, characterized in that: Methods for removing the substrate layer include chemical mechanical polishing, dry etching, and wet etching.

5. The method for preparing the optoelectronic co-encapsulation structure according to claim 1, characterized in that: Methods for dividing the silicon photonics wafer include dry etching, wet etching, and dicing.

6. The method for preparing the optoelectronic co-encapsulation structure according to claim 1, characterized in that: After forming the second interconnect layer electrically connected to the lead-out post, and before dicing the silicon photonics wafer, the method further includes forming conductive bumps electrically connected to the second interconnect layer, wherein the substrate is electrically connected to the second interconnect layer through the conductive bumps.

7. The method for preparing the optoelectronic co-encapsulation structure according to claim 6, characterized in that: After the substrate is electrically connected to the second interconnect layer via the conductive bumps, the method further includes the step of forming a fill layer to fill the gap between the second interconnect layer and the substrate.

8. The method for preparing the optoelectronic co-encapsulation structure according to claim 1, characterized in that: After optically interconnecting the fiber array with the optical port, the process further includes the step of forming a fixing layer to fix the fiber array and the substrate.

9. A photoelectric co-encapsulation structure, characterized in that, The optoelectronic co-sealment structure includes: A chip structure includes a device layer, lead-out pillars, a first interconnect layer, an electrical chip, and a second interconnect layer. The device layer has an optical port and a first pad, and the optical port is exposed on the sidewall of the chip structure. The lead-out pillars penetrate the device layer. The first interconnect layer is electrically connected to the lead-out pillars and the first pad. The electrical chip is bonded to the side of the first interconnect layer opposite to the device layer, and the second pad exposed by the electrical chip is electrically connected to the first interconnect layer. The second interconnect layer is located on the side of the device layer opposite to the first interconnect layer and is electrically connected to the lead-out pillars. A redistribution layer is used as the first interconnect layer, and a redistribution layer is used as the second interconnect layer. The substrate is electrically connected to the side of the second interconnect layer that is opposite to the device layer; An optical fiber array is optically interconnected with the optical port.

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