Method and computer program product for generating vertex auxiliary graphics

Abstract

The application discloses a method and a computer program product for generating vertex auxiliary patterns. The method comprises: obtaining a chip design layout and geometric parameters thereof, wherein the chip design layout comprises sparse patterns and dense patterns, and the geometric parameters comprise minimum spacing of the dense patterns, side length of the sparse patterns, and coordinates of vertices of vertex auxiliary patterns to be configured for the sparse patterns; determining a placement track according to the geometric parameters, wherein the placement track is a circular track or a plurality of concentric circular tracks; and generating at least one vertex auxiliary pattern arranged on the placement track. The application can avoid missing vertex auxiliary patterns.

Description

Technical Field

[0001] This application belongs to the field of semiconductor integrated circuits, and in particular relates to a method for generating vertex-assisted graphics and a computer program product. Background Technology

[0002] In semiconductor integrated circuit manufacturing, sub-resolution auxiliary patterns are used to correct image distortion caused by light diffraction and interference effects during photolithography, thereby improving imaging quality and process window size.

[0003] Currently, auxiliary graphics are divided into those based on the edges of the main graphic and those based on the vertices of the main graphic. When placing edge-based auxiliary graphics, their position can be determined by the area they can be placed in, their linewidth, and the distance between them and the edges of the main graphic. However, when placing vertex-based auxiliary graphics, the coordinates of the vertex auxiliary graphics can only be roughly estimated based on the location of the edge auxiliary graphics. This placement method requires engineers to calculate specific coordinates, which is very inefficient and can easily lead to problems such as missing auxiliary graphics, preventing the process window size from being increased.

[0004] In summary, the current method of placing vertex-based auxiliary graphics suffers from low efficiency and the tendency to miss some elements. Summary of the Invention

[0005] This application provides a method and computer program product for generating vertex auxiliary graphics, which can generate vertex auxiliary graphics efficiently and accurately, and avoid missing vertex auxiliary graphics.

[0006] On one hand, embodiments of this application provide a method for generating vertex-assisted graphics, the method comprising:

[0007] Obtain the chip design layout and its geometric parameters. The chip design layout includes sparse and dense patterns. The geometric parameters include the minimum spacing of the dense patterns, the side length of the sparse patterns, and the coordinates of the target vertex of the auxiliary pattern to be configured in the sparse patterns.

[0008] Based on the geometric parameters, the placement trajectory is determined, which is a circular trajectory or multiple concentric circle trajectories;

[0009] Generate at least one vertex auxiliary graph arranged on the placement trajectory.

[0010] On the other hand, embodiments of this application provide an apparatus for generating vertex-assisted graphics, the apparatus comprising:

[0011] The acquisition module is used to acquire the chip design layout and its geometric parameters. The chip design layout includes sparse patterns and dense patterns. The geometric parameters include the minimum spacing of the dense patterns, the side length of the sparse patterns, and the coordinates of the target vertex of the auxiliary pattern to be configured in the sparse patterns.

[0012] The determining module is used to determine the placement trajectory based on the geometric parameters, wherein the placement trajectory is a circular trajectory or multiple concentric circle trajectories;

[0013] A generation module is used to generate at least one vertex auxiliary graph arranged on the placement trajectory.

[0014] In another aspect, embodiments of this application provide an electronic device, which includes a processor and a memory storing computer program instructions. When the processor executes the computer program instructions, it implements the method for generating vertex-assisted graphics as described in the above aspect.

[0015] In another aspect, embodiments of this application provide a computer-readable storage medium storing a program or instructions that, when executed by a processor, implement the method for generating vertex-assisted graphics as described in the above aspect.

[0016] In another aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method for generating vertex-assisted graphics as described above.

[0017] The method for generating vertex auxiliary graphics in this application embodiment obtains the chip design layout and its geometric parameters, determines the placement trajectory based on the geometric parameters, and generates at least one vertex auxiliary graphic arranged on the placement trajectory. For the problem of narrow process window caused by the lack of optical interaction between neighboring graphics in sparse graphics, it can generate auxiliary graphics for the vertices of sparse graphics, avoid missing auxiliary graphics, thereby improving the light field distribution near the vertices of sparse graphics, improving imaging quality and expanding the process window. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 It is a schematic diagram of auxiliary graphs based on the edges of sparse graphs and auxiliary graphs based on the vertices of sparse graphs;

[0020] Figure 2 This is a flowchart illustrating a method for generating vertex-assisted graphics according to an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the placement coordinates calculated in another embodiment of this application;

[0022] Figure 4 This is a schematic diagram of a chip design layout that generates the vertex auxiliary graphics, provided in another embodiment of this application;

[0023] Figure 5 This is a schematic diagram of the line segment direction in yet another embodiment of this application;

[0024] Figure 6 This is a flowchart illustrating a method for generating vertex-assisted graphics according to another embodiment of this application;

[0025] Figure 7 This is a schematic diagram showing the placement of vertex auxiliary graphics provided in another embodiment of this application;

[0026] Figure 8 This is a schematic diagram of the structure of an apparatus for generating vertex auxiliary graphics according to another embodiment of this application;

[0027] Figure 9 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0028] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0030] First, let me introduce the technical terms used in this application.

[0031] A process node, also known as a technology node or process node, is a generational marker used to measure the advancement of integrated circuit manufacturing processes. Generally, a smaller process node number means that more transistors can be integrated into a unit area, thereby achieving higher computing performance, lower power consumption, and a smaller chip area.

[0032] Minimum linewidth refers to the smallest pattern feature size that can be stably and reliably transferred onto a silicon wafer through processes such as photolithography and etching under a specific integrated circuit manufacturing process.

[0033] In photolithography, the process window refers to the range of allowed variations in process parameters that ensure the critical dimensions of the manufactured pattern meet design requirements. A larger process window allows for greater tolerance in the manufacturing process, resulting in higher chip yield.

[0034] Optical proximity correction is a computational lithography technique used in chip design and manufacturing. It compensates for distortions caused by light diffraction and proximity effects during the lithography process by pre-correcting the design pattern on the mask.

[0035] The background technology involved in this application is described below.

[0036] Photolithography is one of the core technologies for manufacturing very large-scale integrated circuits. Photolithography involves a system that uses a light source to illuminate a photomask, and then projects the integrated circuit layout from the photomask onto a photoresist plate using a projection lens. Computational lithography uses computers to simulate and model these optical and chemical processes, theoretically exploring ways to increase lithographic resolution and the process window (PW), and guiding the optimization of process parameters.

[0037] As process nodes shrink from micrometers to nanometers, the minimum critical dimension (CD) on devices begins to fall below the exposure wavelength of lithography machines, making the lithography imaging quality and process window increasingly susceptible to the effects of light diffraction. At advanced technology nodes below 28nm, traditional optical proximity correction (OPC) relying solely on master pattern correction is insufficient to meet the accuracy requirements of lithography imaging. Both theory and experiments demonstrate that when the pattern size is smaller than or close to the lithography wavelength, light diffraction and interference effects will cause image distortion, specifically manifested as significant differences in the actual imaging between sparse and dense patterns, shortened pattern line ends, and rounded pattern corners. Sparse patterns refer to those in the chip design layout where the pattern spacing is much greater than the minimum critical dimension (CD), the pattern distribution is scattered, and the line density is extremely low. Examples include patterns where a single pattern (such as an isolated line or isolated via) has no adjacent patterns or the spacing between adjacent patterns far exceeds the resolution threshold of the lithography system. These are patterns in the chip design layout that require auxiliary pattern optimization. Dense patterns refer to patterns in a photolithography layout that have a spacing close to or less than the minimum linewidth (CD), a compact pattern arrangement, and a high linewidth density. They do not require auxiliary pattern optimization in chip design layouts.

[0038] Furthermore, as process nodes continue to shrink, the lithography process window shrinks dramatically. The process window for sparse patterns is much smaller than that for dense patterns, resulting in a significant decrease in the common process window.

[0039] To improve imaging accuracy and expand the process window, the semiconductor manufacturing industry has introduced sub-resolution assistant feature (SRAF) or scattering bar (SBAR) techniques. These techniques involve adding tiny auxiliary features around sparse patterns in the integrated circuit chip design layout to adjust the light intensity distribution during exposure, making the optical environment of the sparse features during imaging similar to that of the dense features. These auxiliary features are smaller than the resolution of the lithography machine. During exposure, these features only scatter light and do not themselves image onto the photoresist, thereby improving imaging contrast and effectively expanding the process window, ultimately increasing chip manufacturing yield.

[0040] Currently, the generation of auxiliary graphics is mostly based on rules summarized from experience, followed by cleaning and adjustment. The placed auxiliary graphics include those based on the edges of the main graphic and those based on the vertices of the main graphic.

[0041] Currently, the rules for edge-based auxiliary graphics are relatively mature. The position of an edge-based auxiliary graphic can be determined by the range in which it is placed, its line width, and the distance between the auxiliary graphic and the edge of the main graphic. However, vertex-based auxiliary graphics offer greater freedom, but can only be placed by roughly estimating the coordinates of the vertex auxiliary graphics based on the location area of ​​the edge auxiliary graphics.

[0042] Figure 1 This is a schematic diagram of auxiliary graphs based on the edges and vertices of a sparse graph. For example... Figure 1 As shown, sparse pattern 11 is a sparse pattern at the process node of its chip design layout. In order to make the optical environment of sparse pattern 11 during imaging similar to that of dense pattern in its chip design layout, edge auxiliary pattern 12 is placed based on the edges of sparse pattern 11, and vertex auxiliary pattern 13 is placed based on the vertices of sparse pattern 11. When placing edge auxiliary pattern 12, the position of edge auxiliary pattern 12 can be determined by setting the placement range of auxiliary pattern, the line width of auxiliary pattern, and the distance between the edge of auxiliary pattern and the edge of sparse pattern. However, when placing vertex auxiliary pattern 13, the coordinate position of vertex auxiliary pattern can only be roughly estimated based on the position area of ​​edge auxiliary pattern.

[0043] Therefore, currently, when placing vertex-based auxiliary graphics, engineers need to waste time and effort to calculate specific coordinate positions, which is very inefficient. At the same time, it is easy to miss placing auxiliary graphics, ultimately failing to achieve the effect of improving the process window.

[0044] To address the problems of the prior art, this application provides a method for generating vertex auxiliary graphics. The execution entity of this method can be a device for generating vertex auxiliary graphics. The method for generating vertex auxiliary graphics provided in this application is described below.

[0045] Figure 2 This is a flowchart illustrating a method for generating vertex-assisted graphics according to another embodiment of this application. Figure 2 As shown, an embodiment of this application provides a method for generating vertex-assisted graphics, which includes steps 201 to 203.

[0046] Step 201: Obtain the chip design layout and its geometric parameters. The chip design layout includes sparse and dense patterns. The geometric parameters include the minimum spacing of the dense patterns, the side length of the sparse patterns, and the coordinates of the vertices of the auxiliary patterns to be configured in the sparse patterns.

[0047] Step 202: Determine the placement trajectory based on the geometric parameters. The placement trajectory can be a circular trajectory or multiple concentric circle trajectories.

[0048] Step 203: Generate at least one vertex auxiliary graph arranged on the placement trajectory.

[0049] In some embodiments, a chip design layout refers to a layout diagram in integrated circuit design. A chip design layout consists of multiple polygons, which represent the circuit structures on the chip. The file format of the chip design layout can be the first or second version of the Graphic Data System (GDS) format, i.e., GDS I or GDS II format, or the Open Artwork System Interchange Standard (OASIS) format.

[0050] Chip design layouts consist of multiple main patterns, each including at least one sparse pattern and at least one dense pattern. Sparse patterns are those in the chip design layout where the pattern spacing is much greater than the minimum linewidth (CD), the pattern distribution is scattered, and the linewidth density is extremely low. Examples include patterns where a single pattern (such as an isolated line or via) has no adjacent patterns or the spacing between adjacent patterns far exceeds the resolution threshold of the lithography system. Dense patterns are those in the lithography layout where the pattern spacing is close to or less than the minimum linewidth (CD), the pattern arrangement is compact, and the linewidth density is high.

[0051] In photolithography, sparse patterns have a much smaller process window than dense patterns due to the lack of optical interaction between them and their neighboring patterns. Therefore, sparse patterns need to be optimized by auxiliary patterns in the chip design layout, while dense patterns do not need to be optimized by auxiliary patterns in the chip design layout.

[0052] Those skilled in the art will know that sparse and dense patterns in a chip design layout should be distinguished based on the resolution threshold of the lithography system and the process window requirements at a specific process node for each chip design layout, which will not be elaborated here.

[0053] The minimum spacing between dense patterns refers to the actual minimum distance between the edges of adjacent patterns in a chip design layout. It represents the characteristic scale of the most compactly distributed and spatially constrained area on the chip design layout. The minimum spacing between dense patterns is greater than or equal to the minimum design spacing specified by the chip manufacturer for the process node.

[0054] Sparse shapes can be squares, rectangles, L-shapes, or other polygons. When a sparse shape is a square, its side length is the same as the side length of a square. When a sparse shape is a rectangle, its side length is the shorter side length of the rectangle. When a sparse shape is an L-shape or other polygon, its side length can be the shortest side length of the polygon or the minimum linewidth (CD), etc.

[0055] Vertex auxiliary patterns refer to sub-resolution patterns with a width smaller than the resolution of the lithography machine. Vertex auxiliary patterns do not form images on the silicon wafer, but they can alter the light intensity distribution at locations adjacent to the main pattern through scattering or diffraction.

[0056] The coordinates of the vertices of the auxiliary graphic to be configured in the sparse graphic are the coordinates of the vertices of the auxiliary graphic to be configured in the sparse graphic on the chip design layout.

[0057] From an optical imaging perspective, the imaging quality of sparse patterns, due to their open perimeter, is primarily limited by their linewidth control precision and the logarithmic slope of the image. The theoretical process window for sparse patterns in an isolated state may be relatively large. However, integrated circuit manufacturing requires all patterns within the same exposure field, regardless of density, to share identical core process conditions such as exposure wavelength, focal length, and dosage. Therefore, the practically effective common process window for the system must be the intersection of the process windows of the dense and sparse regions. Since the spatial frequency of dense patterns is the highest, and optical interference and diffraction effects are the most complex, the minimum spacing between dense patterns directly affects the exposure process conditions required to achieve clear imaging of dense areas in photolithography—that is, the theoretical upper limit of the process window.

[0058] Therefore, the optimization goal of sparse patterns, which is determined to meet the imaging requirements of dense areas (such as optimal focal length and exposure dose), is not to infinitely expand its isolated window, but to improve its imaging robustness and tolerance under the given baseline conditions, thereby bringing the process window curve of sparse patterns closer to the common conditions, and ultimately effectively expanding the common process window.

[0059] Based on the above principles, this application determines the placement trajectory according to the geometric parameters of the chip design layout and generates vertex auxiliary graphics arranged on the placement trajectory. This not only enables the generation position of the auxiliary graphics to be compatible with the imaging conditions of dense areas, but also avoids missing auxiliary graphics, thereby improving the performance of sparse graphics under a unified process benchmark and expanding the common process window of the entire chip design layout.

[0060] In some embodiments, a computer program can read a standard format chip design layout data file and identify sparse and dense patterns in the chip design layout based on a preset pattern spacing or density threshold. Specifically, the chip layout can be scanned, and for each pattern, the shortest edge distance between it and its surrounding adjacent patterns can be calculated. If the distance is less than or equal to the preset pattern spacing or density threshold, the pattern and its local area are marked as dense patterns. Similarly, if the distance is greater than the preset pattern spacing or density threshold, the pattern and its local area are marked as sparse patterns.

[0061] For each sparse pattern, its side length can be measured to obtain the side length of the sparse pattern. Furthermore, the target vertex of the auxiliary vertex to be configured can be selected from the sparse pattern, and the coordinates of the target vertex can be obtained from the data attributes of the sparse pattern in the chip design layout.

[0062] After identifying the dense graphic region, the minimum distance between the edges of all graphics within that region can be calculated to obtain the minimum spacing of the dense graphics. Specifically, this can be achieved by calculating the edge-to-edge distance between each pair of adjacent graphics within the dense graphic region. Then, from all these distance values, the minimum distance value is found, and this minimum distance value is the minimum spacing of the dense graphics.

[0063] In some embodiments, to improve the placement efficiency of vertex auxiliary graphics, avoid missing placement of vertex auxiliary graphics, ensure compensation for insufficient light intensity at the target vertex, and suppress corner rounding, a placement trajectory is constructed based on the principle that the effective range of vertex auxiliary graphics at the sparse graph vertex is closely related to the size of the sparse graph itself and the minimum spacing density of the dense graphs in the design layout. This is done by placing the vertex auxiliary graphics on the trajectory, which not only determines the position of the auxiliary graphics and improves the placement efficiency but also prevents missing placement. To ensure that the auxiliary graphics are arranged within a specific distance range around the target vertex, the placement trajectory can be a circular trajectory or a concentric circle trajectory.

[0064] At least one vertex auxiliary graphic is generated on the placement trajectory. Specifically, at least one specific placement coordinate on the placement trajectory is first calculated, and then the placement coordinate is used as a preset reference point for the vertex auxiliary graphic to generate a vertex auxiliary graphic with a preset shape and preset size. The vertex auxiliary graphic is then added to the layout data of the chip design layout. The at least one specific placement coordinate on the placement trajectory can be distributed at equal angular intervals along the placement trajectory. The preset shape can be a square, and the preset reference point can be the geometric center of the square or a vertex.

[0065] The method for generating vertex auxiliary graphics provided in this application obtains the chip design layout and its geometric parameters, determines the placement trajectory based on the geometric parameters, and generates at least one vertex auxiliary graphic arranged on the placement trajectory. For the problem of narrow process window caused by the lack of optical interaction between neighboring graphics in sparse graphics, it can generate auxiliary graphics for the vertices of sparse graphics, avoid missing auxiliary graphics, thereby improving the light field distribution near the vertices of sparse graphics, improving imaging quality and expanding the process window.

[0066] In some embodiments, step 202 is further refined to include steps 301 to 302.

[0067] Step 301: Determine the center of the placement trajectory based on the coordinates of the target vertex, the side length of the sparse graph, and the preset side length of the vertex auxiliary graph.

[0068] Step 302: Determine the radius of the placement trajectory based on the side length of the sparse shape and the minimum spacing of the dense shape.

[0069] In photolithography, dense patterns, due to their tight periodic arrangement, exhibit significant optical proximity effects, and their imaging contrast and process window are typically in a predictable and relatively stable state. The performance degradation of sparse patterns, however, is essentially due to the difference in local effective pattern density compared to dense regions, leading to variations in light intensity distribution. Therefore, the fundamental idea behind patterning techniques is to add sub-resolution patterns around sparse patterns to increase their local effective pattern density, thus making their imaging behavior more robust and similar to that of dense patterns.

[0070] Meanwhile, optical simulations and experience show that the size of a sparse pattern directly determines its inherent light intensity distribution gradient near its vertices. A larger sparse pattern typically has a larger characteristic scale of the light field attenuation region at its vertices. To effectively modulate this light field, the center of the auxiliary pattern's effective region also needs to be shifted by a correspondingly larger amount to match its effective range with the optical characteristic size of the main pattern. Furthermore, the auxiliary pattern is also a pattern with physical dimensions, and its own size also affects the range and intensity of its scattering effect. When placing the auxiliary pattern, the position of its edge or center relative to the vertices of the main pattern must also be considered.

[0071] The fundamental purpose of placing vertex auxiliary patterns is to compensate for the light intensity loss due to diffraction at the vertices of sparse patterns through their scattering effect, thereby improving corner imaging. This compensation effect is not strongest directly above the vertex, but needs to occur within a ring-shaped region at a certain distance from the vertex. Therefore, by constructing a Cartesian coordinate system with the sparse pattern vertex as the origin, determining the center of the placement trajectory based on the side length of the sparse pattern and the preset side length of the vertex auxiliary pattern, and determining the radius of the placement trajectory based on the side length of the sparse pattern and the minimum spacing of the dense pattern, we can ensure that the placement trajectory is within the effective range of optical correction, i.e., close to the optically weak region of the sparse pattern. This allows the generated vertex auxiliary patterns to form an equivalent optical microstructure around the target vertex, similar to the dense pattern environment with a spacing equal to the minimum spacing of the dense pattern. This allows the optical performance of the sparse pattern during imaging to be as close as possible to that of the dense pattern, thereby expanding the common process window. Furthermore, it enables the placement trajectory to be applicable to different chip design layouts and different process nodes for sparse patterns of different sizes and vertex auxiliary patterns of different dimensions.

[0072] When generating vertex auxiliary graphics, if the vertex auxiliary graphics are squares and the geometric center of the vertex auxiliary graphics falls on the placement trajectory, then it is only necessary to ensure that the vertex auxiliary graphics satisfy the Manhattan geometric layout, that is, the edges of the vertex auxiliary graphics are aligned with the wafer coordinate system axis.

[0073] Based on the thickness and spacing of the main graphic line segments in the chip design layout, each line segment that makes up the polygon in the chip design layout has a direction. For a clockwise polygon, this application defines the right side of a line segment as the interior of the polygon, which is the direction of the width, and the left side of the line segment as the exterior of the polygon, which is the direction of the spacing.

[0074] When generating vertex auxiliary graphics, if the vertex auxiliary graphics are squares and the vertices of the vertex auxiliary graphics fall on the placement trajectory, then the vertex auxiliary graphics can be generated in the outer direction of the placement trajectory, i.e., the sapce direction.

[0075] In some embodiments, the x and y coordinates of the center can be obtained by linearly combining or weighting the preset side lengths of the sparse graph and the vertex auxiliary graph. x 0 and the vertical axis y The value of 0. For example... x 0= k 1 L + k 2 Q , y 0= k 1 L + k 2 Q ,in, x 0 and y 0 is the coordinate of the center of the circle. L Let be the side length of the sparse graph. Q The preset side length for the vertex auxiliary shape. k 1 and k 2 is the preset coefficient.

[0076] k 1 and k 2 can be determined based on optical experience or simulation results, for example, k 1 can be a number less than 0 and greater than -1. k 2 can be a number that is less than 0 and greater than -1. k 1 can be -1 / 3, -2 / 3, -5 / 6, etc. k 2 can be -1 / 3, -2 / 3, -5 / 6, etc.

[0077] In some embodiments, the radius of the placement trajectory can be calculated based on the side lengths of the sparse graphs and the minimum spacing of the dense graphs. For example, the radius of a circular trajectory can be calculated by weighted summation of the side lengths of the sparse graphs and the minimum spacing, such as... r = m 1 L + m 2 S ,in, r For radius, L Let be the side length of the sparse graph. S The minimum spacing for dense graphics. m 1 and m 2 is the preset coefficient. m 1 and m 2 can be determined based on optical experience or simulation results, for example, m 1 can be a number greater than 0 and less than 1. m 2 can be a number greater than 1, specifically, m 1 can be 1 / 3, 2 / 3, 5 / 6, etc. m 2 can be 3 / 2, 4 / 3, 2, 5 / 2, 3, etc.

[0078] The method for generating vertex auxiliary graphics provided in this application obtains the radius by linearly combining or weighted summing the side lengths of sparse graphics and the minimum spacing of dense graphics. This ensures a linear relationship between the radius of the placement trajectory and the side lengths of the sparse graphics and the minimum spacing of the dense graphics, thereby ensuring that the vertex auxiliary graphics can be placed in areas with significant optical proximity effects. This simulates the light intensity distribution of the dense graphics and improves the imaging quality of the sparse graphics. Furthermore, placing all vertex auxiliary graphics on a circular trajectory ensures that the vertex auxiliary graphics are evenly distributed along the circular trajectory, avoiding imaging distortion caused by local uneven light intensity or diffraction effects.

[0079] In some embodiments, k 1 can be with k 2 are equal. k 1 Can be with m 1 is the opposite number.

[0080] In some embodiments, the order of the vertex auxiliary graph of the sparse graph can be the same as the order of the edge auxiliary graph of the sparse graph, that is, the number of order auxiliary graphs based on the edges of the sparse graph is equal to the number of order auxiliary graphs based on the vertices of the sparse graph.

[0081] The order refers to the classification of auxiliary patterns placed around a sparse pattern, arranged from closest to furthest. Typically, first-order auxiliary patterns are closest to the sparse pattern, and their position and size have the most direct impact on the optical performance of the sparse pattern. Second-, third-, and higher-order auxiliary patterns are arranged outwards in sequence, forming multi-layered enclosing or extending structures. Each order of auxiliary pattern has its specific placement rules and objectives.

[0082] By calculating the radius of the circular trajectory through a weighted summation of the side length and minimum spacing of the sparse graphic, it is possible to support the placement of vertex auxiliary graphics at multiple levels, such as first-order, second-order, and third-order. The placement radius of each level can be adjusted by adjusting the weight coefficients to adapt to different auxiliary graphic density requirements, thereby expanding the process window.

[0083] In some embodiments, after determining the placement trajectory, a series of placement coordinates for the vertex auxiliary graphics can be generated mathematically based on a preset number of vertex auxiliary graphics and the calculated center and radius of the circle. These placement coordinates can be the vertex coordinates or geometric center coordinates of the vertex auxiliary graphics.

[0084] In some embodiments, the preset number of vertex auxiliary graphics determines the spacing of the placement coordinates on the placement trajectory. A higher preset number of vertex auxiliary graphics results in smaller spacing between placement coordinates and a denser arrangement of the placed vertex auxiliary graphics; conversely, a lower preset number of auxiliary graphics results in larger spacing between placement coordinates and a sparser arrangement of the placed vertex auxiliary graphics. Furthermore, when facing different optical characteristic requirements for different process layers, the coverage density of the auxiliary graphics can be flexibly adjusted by using the preset number, balancing the process window as much as possible and avoiding overly dense graphics.

[0085] In some embodiments, the placement coordinates can fall uniformly on a circular trajectory.

[0086] In some embodiments, when the placement coordinates are the geometric center coordinates of the vertex auxiliary graphic, a specific vertex auxiliary graphic can be generated at the determined placement coordinate point according to a preset graphic shape, such as a square, and a size, such as a preset side length. For example, the coordinates of the target vertex of the sparse graphic can be added to the placement coordinates to obtain the absolute coordinates of the vertex auxiliary graphic in the global chip design layout. The vertex auxiliary graphic is then generated using these absolute coordinates as the geometric center or a vertex of the square.

[0087] Figure 3 This is a schematic diagram of the placement coordinates calculated in another embodiment of this application. For example... Figure 3As shown, with vertex A of sparse graphic 31 as the origin of the coordinate system, the center coordinates B of the circular trajectory are calculated based on the side length of the sparse graphic and the preset side length of the vertex auxiliary graphic. The radius of the circular trajectory is calculated based on the side length of the sparse graphic and the minimum spacing of the dense graphic. The circular trajectory C is drawn based on the center coordinates B and the radius. The placement coordinates D1, D2, D3 and D4 of the vertex auxiliary graphic are determined based on the center coordinates, radius and preset number of vertex auxiliary graphics.

[0088] The method for generating vertex auxiliary graphics provided in this application obtains the chip design layout and its geometric parameters, determines the placement trajectory based on the geometric parameters, and generates at least one vertex auxiliary graphic arranged on the placement trajectory. This method can place vertex auxiliary graphics on the placement trajectory and avoid missing vertex auxiliary graphics.

[0089] In some embodiments, the chip design layout also includes edge auxiliary graphics of the sparse graphics. To avoid conflicts between vertex auxiliary graphics and edge auxiliary graphics, step 203 refines the following:

[0090] Step 501: For each vertex auxiliary graph generated, perform a mask rule check on the vertex auxiliary graph to determine whether there is a mask rule conflict between the vertex auxiliary graph and dense graphs, sparse graphs or edge auxiliary graphs.

[0091] Step 502: If a mask rule conflict is determined, the side length of the vertex auxiliary graph is adjusted until there is no mask rule conflict between the vertex auxiliary graph and all dense graphs, all sparse graphs and all edge auxiliary graphs.

[0092] In some embodiments, placing a sufficient number of vertex auxiliary patterns, provided that the mask rule check (MRC) is satisfied, can effectively improve imaging quality and process window. Therefore, the preset number of vertex auxiliary patterns can be relatively large, for example, 20 or more, such as 20, 25, or 30. Meanwhile, to ensure the mask layout of the chip design can be manufactured, the vertex auxiliary patterns need to meet mask rules. In chip manufacturing, edge auxiliary patterns are fundamental to ensuring the imaging quality of sparse pattern edges; their positions and shapes are usually optimized and fixed. Therefore, edge auxiliary patterns have a higher priority than vertex auxiliary patterns. When the generated vertex auxiliary pattern does not meet the mask rules, the vertex auxiliary pattern should be adjusted. For example, when generating a vertex auxiliary pattern, if the vertex auxiliary pattern conflicts with any dense pattern, any sparse pattern, or any edge auxiliary pattern in terms of mask rules, the generation of that vertex auxiliary pattern can be abandoned.

[0093] In some embodiments, the side length of vertex auxiliary graphs that have mask rule conflicts can be adjusted, for example, by reducing the side length. Specifically, the side length of the vertex auxiliary graph can be reduced according to the mask rule violation length of the vertex auxiliary graph, and a mask rule check can be performed again after the side length is reduced. For example, when generating a vertex auxiliary graph, if the vertex auxiliary graph has a mask rule conflict with any dense graph, any sparse graph, or any edge auxiliary graph, the side length of the vertex auxiliary graph can be reduced according to the mask rule violation length of the vertex auxiliary graph, and a mask rule check can be performed again after the side length is reduced.

[0094] In some embodiments, if a mask rule conflict still exists when the side length of the vertex auxiliary graphic is reduced to a preset minimum allowable value, the auxiliary graphic can be deleted, because an excessively small graphic may have lost its optical assistance function, and keeping it would violate the rules.

[0095] Figure 4 This is a schematic diagram of a chip design layout that generates vertex-assisted graphics, provided in another embodiment of this application. For example... Figure 4 As shown, the chip design layout includes a sparse pattern 41, an edge auxiliary pattern 42 of the sparse pattern, and a vertex auxiliary pattern 43 of the sparse pattern generated using the method of this application. The vertical spacing between the vertex auxiliary pattern 43 and the edge auxiliary pattern 42 is 25nm. The mask rule requires that the minimum spacing between the auxiliary patterns is 28nm. After the mask rule check, it is determined that there is a mask rule conflict between the vertex auxiliary pattern 43 and the edge auxiliary pattern 42, with a violation length of 3nm. Therefore, the vertex auxiliary pattern 43 can be reduced by 3nm in the vertical direction to satisfy the mask rule.

[0096] The method for generating vertex auxiliary graphics provided in this application adjusts the side length of vertex auxiliary graphics that conflict with mask rules to satisfy the mask rules. This ensures that the position of the vertex auxiliary graphics remains basically unchanged and that the vertex auxiliary graphics satisfy the mask rules. As a result, more vertex auxiliary graphics can be retained as much as possible while satisfying the mask rules, thereby maximizing the improvement of the process window.

[0097] In some embodiments, in order to accurately generate vertex auxiliary graphics based on placement coordinates, step 203 refinement includes:

[0098] Step 901: Using the placement coordinates as the vertex coordinates of the vertex auxiliary graphic, generate the vertex auxiliary graphic outside the placement trajectory.

[0099] In some embodiments, the placement coordinates can be coordinates with the sparse graphic vertices as the origin of the coordinate system, or they can be the absolute position of the vertex auxiliary graphic on the chip design layout. The placement coordinates can be the vertex coordinates of the vertex auxiliary graphic. For example, the absolute position of the vertex auxiliary graphic on the chip design layout can be calculated based on the absolute coordinates of the sparse graphic vertices in the global chip design layout and the relative coordinates of the vertex auxiliary graphic in the coordinate system with the sparse graphic vertices as the origin, such as... x final = x 0+ x vertex , y final = y 0+ y vertex ,in, x vertex This represents the x-coordinate of the auxiliary graph at the vertex in a coordinate system with the vertices of the sparse graph as the origin. y vertex This represents the ordinate value of the auxiliary graph at the vertex in the coordinate system with the vertices of the sparse graph as the origin. x 0 represents the x-coordinate of the absolute coordinates of the sparse graph vertex in the global chip design layout. y 0 represents the ordinate value of the absolute coordinates of the sparse graph vertex in the global chip design layout. x final This represents the x-coordinate of the absolute position of the vertex auxiliary graphic within the chip design layout. y final This represents the ordinate value of the absolute position of the vertex auxiliary graphic in the chip design layout.

[0100] Figure 5 This is a schematic diagram of the line segment direction in yet another embodiment of this application. For example... Figure 5 As shown, since each line segment that makes up a polygon in a chip design layout has a direction, for a clockwise polygon, the right side of the line segment is predefined as the polygon's interior (width), and the left side is the polygon's exterior (space). Similarly, for a counter-clockwise polygon, the left side of the line segment is predefined as the polygon's interior (width), and the right side is the polygon's exterior (space). The width direction points inwards, while the space direction points outwards.

[0101] In some embodiments, after calculating the placement coordinates, the placement coordinates can be the vertex coordinates of the vertex auxiliary graphic. A vertex auxiliary graphic with a preset side length is generated outside the placement trajectory, i.e., in the direction outside the polygon, such as a side length of... Q A square. This square can be a Manhattan geometry, with its four sides parallel to the horizontal and vertical coordinate axes of the chip design layout.

[0102] The method for generating vertex auxiliary graphics provided in this application generates vertex auxiliary graphics outside the placement trajectory by using the placement coordinates as the vertex coordinates of the vertex auxiliary graphics. This method can generate vertex auxiliary graphics quickly and accurately, and can eliminate directional errors and omissions caused by human placement of vertex auxiliary graphics, ensuring that each auxiliary graphic is accurately placed in the theoretically calculated optimal position.

[0103] Figure 6 This is a flowchart illustrating a method for generating vertex-assisted graphics according to another embodiment of this application. Figure 6 As shown, the method for generating vertex-assisted graphics provided in this application embodiment includes:

[0104] Step 401: Obtain the chip design layout and its geometric parameters. The chip design layout includes sparse and dense patterns. The geometric parameters include the minimum spacing of the dense patterns, the side length of the sparse patterns, and the coordinates of the target vertex of the auxiliary pattern to be configured in the sparse patterns.

[0105] Step 402: Determine the center of the placement trajectory based on the coordinates of the target vertex, the side length of the sparse graph, and the preset side length of the vertex auxiliary graph.

[0106] Step 403: Determine the radius of the placement trajectory based on the side length of the sparse shape and the minimum spacing of the dense shape;

[0107] Step 404: For each vertex auxiliary graph generated, perform a mask rule check on the vertex auxiliary graph to determine whether there is a mask rule conflict between the vertex auxiliary graph and dense graphs, sparse graphs or edge auxiliary graphs.

[0108] Step 405: If a mask rule conflict is determined, the side length of the vertex auxiliary graph is adjusted until there is no mask rule conflict between the vertex auxiliary graph and all dense graphs, all sparse graphs and all edge auxiliary graphs.

[0109] The implementation methods for steps 401 to 405 can be found in the descriptions in the above embodiments, and will not be repeated here.

[0110] In some embodiments, in order to make the vertex auxiliary graphics uniformly distributed around the vertices of the sparse graphics, step 301 refinement includes:

[0111] The coordinates of the center of the circle are calculated using the following formula:

[0112] x 0= k 1 L + k 2 Q , y 0= k 1 L + k 2 Q (1)

[0113] in, x 0 and y 0 is the coordinate of the center of the circle. L Let be the side length of the sparse graph. Q The preset side length for the vertex auxiliary shape. k 1 and k 2 is the preset coefficient.

[0114] In some embodiments, based on the principle of optical proximity (OPE), in order to effectively modulate the light intensity distribution at the vertices of the sparse pattern to improve imaging, such as reducing corner rounding, the auxiliary pattern needs to be placed within a ring-shaped region surrounding the vertices at a suitable distance. The theoretical center of this region, i.e., the center of the circle, is intrinsically related to the size of both the sparse pattern and the auxiliary pattern itself, relative to the vertices. This is achieved by establishing the center coordinates as... L and Q A specific function, such as a linear combination relationship, can ensure that the circular trajectory is positioned near a theoretically optimal region that effectively utilizes optical modulation while conforming to general design rules, such as avoiding excessive proximity to the sparse graphic body. Preset coefficients k 1 and k 2. It contains empirical knowledge verified through optical simulation or experimentation. For example, k 1 can be -1 / 3, -2 / 3, -5 / 6, etc. k 2 can be -1 / 3, -2 / 3, -5 / 6, etc.

[0115] Since the vertices of the sparse graph are where the graph orientation changes, in order to cover the optically sensitive points in each direction and effectively compensate for the optical proximity effect, the vertex auxiliary graph should be placed near the intersection of the extensions of the first and second directions of the auxiliary graph based on the sparse graph edge. The first and second directions are perpendicular to each other. By using formula (1) to calculate the center coordinates of the circular trajectory, it can be ensured that the circular trajectory can just cover the intersection of the extensions of the first and second directions of the auxiliary graph based on the sparse graph edge.

[0116] The method for generating vertex auxiliary graphics provided in this application embodiment adopts... x 0=k 1 L + k 2 Q , y 0= k 1 L + k 2 Q Calculate the coordinates of the center of the circular trajectory so that the circular trajectory can just cover the vicinity of the intersection of the extensions of the mutually perpendicular first and second directions of the auxiliary graphic based on the sparse graphic edges. This will allow the subsequently generated vertex auxiliary graphic to fall near the intersection of the extensions of the mutually perpendicular first and second directions of the auxiliary graphic based on the sparse graphic edges.

[0117] In some embodiments, step 302 is further refined to include:

[0118] The radius is calculated using the following formula:

[0119] r = m 1 L + m 2 S ,

[0120] in, r For radius, L Let be the side length of the sparse graph. S The minimum spacing for dense graphics. m 1 and m 2 is the preset coefficient.

[0121] In some embodiments, the side length of the sparse pattern affects its optical properties, while the minimum spacing of the dense pattern affects the required density at the location of the sparse pattern. Therefore, different methods are used. m 1 and m By weighting the side length of sparse patterns and the minimum spacing of dense patterns, the complex optical interactions in the photolithography process can be simulated more precisely and accurately.

[0122] m 1 and m 2 can be determined based on optical experience or simulation results, for example, m 1 can be a number greater than 0 and less than 1. m 2 can be a number greater than 1, specifically, m 1 can be 1 / 3, 2 / 3, 5 / 6, etc. m 2 can be 3 / 2, 4 / 3, 2, 5 / 2, 3, etc.

[0123] m A value greater than 0 ensures that the radius of the circular trajectory increases with the side length of the sparse graph. Meanwhile, mA value less than 1 ensures that the radius of the circular trajectory does not grow synchronously with the side length of the sparse pattern. This allows the vertex auxiliary pattern to both compensate for the optical differences in the sparse region caused by the spacing and prevent the vertex auxiliary pattern from entering the optically insensitive region or causing interference due to being placed too far away from the vertex.

[0124] In photolithography, the proximity effect between patterns is one of the factors affecting image quality. m A value greater than 1 (2) allows the radius of the circular trajectory to vary with the minimum spacing of the dense pattern, enabling the generated vertex auxiliary pattern to effectively improve the imaging quality of the sparse pattern. m 1 is greater than 0 and less than 1. m A value greater than 1 (2) enables the generated vertex auxiliary graph to effectively improve the imaging quality of sparse graphs.

[0125] The method for generating vertex auxiliary graphics provided in this application embodiment, through... r = m 1 L + m 2 S Calculating the radius of the placement trajectory allows for a more refined and accurate simulation of the complex optical interactions during the photolithography process. This enables the vertex-assisted patterns on the placement trajectory to improve the robustness and tolerance of the imaging of sparse patterns.

[0126] In some embodiments, to generate vertex auxiliary graphics more accurately, when the placement trajectory is multiple concentric circle trajectories, step 203 is further refined to include:

[0127] Starting from the center of multiple concentric circle trajectories, generate vertex auxiliary graphics arranged on each concentric circle trajectory in order from the inner circle to the outer circle.

[0128] When a sparse pattern has multiple layers of auxiliary patterns arranged outwards, the auxiliary patterns closer to the sparse pattern have a more direct impact on the optical performance of the sparse pattern. Therefore, when the placement trajectory is multiple concentric circle trajectories, the vertex auxiliary patterns arranged on each concentric circle trajectory can be generated starting from the center of the multiple concentric circle trajectories and in order from the inner circle to the outer circle. This ensures that the vertex auxiliary patterns closer to the sparse pattern can be generated and retained first, thereby maximizing the process window of the sparse pattern.

[0129] In some embodiments, while generating vertex auxiliary graphics arranged on each concentric circle trajectory, a mask rule check can be performed on each vertex auxiliary graphic generated to determine whether there is a mask rule conflict between the vertex auxiliary graphic and dense graphics, sparse graphics, or edge auxiliary graphics. If a mask rule conflict is determined, the side length of the vertex auxiliary graphic is adjusted until there is no mask rule conflict between the vertex auxiliary graphic and all dense graphics, all sparse graphics, and all edge auxiliary graphics, so as to ensure that the generated vertex auxiliary graphics can satisfy the mask rules.

[0130] The method for generating vertex auxiliary graphics provided in this application, when the placement trajectory is multiple concentric circle trajectories, generates vertex auxiliary graphics arranged on each concentric circle trajectory starting from the center of the multiple concentric circle trajectories and in order from the inner circle to the outer circle. This method can prioritize retaining vertex auxiliary graphics that have a more direct impact on the optical performance of sparse graphics, thus ensuring the optimization effect on sparse graphics.

[0131] In some embodiments, to improve the optimization effect on sparse graphics, when the placement trajectory is multiple concentric circle trajectories, step 201 further includes:

[0132] Based on the order of the auxiliary graphics of the sparse graphics in the chip design layout, determine the number of concentric circle trajectories and the order of the auxiliary graphics corresponding to each concentric circle trajectory.

[0133] Step 202 is further refined by: determining the weighting coefficient of the minimum spacing of dense graphics based on the order of the auxiliary graphics corresponding to the concentric circle trajectory, wherein the weighting coefficient is positively correlated with the order of the auxiliary graphics corresponding to the concentric circle trajectory;

[0134] The radius is determined based on the side length and weight coefficient of the sparse graph, and the radius is positively correlated with the weight coefficient.

[0135] Step 203 is further refined to include:

[0136] For each concentric circle trajectory, generate at least one vertex auxiliary graph.

[0137] When the placement trajectory consists of multiple concentric circular trajectories, the vertex auxiliary graphics include at least one order. Multiple-order vertex auxiliary graphics are used to adjust light intensity in different regions from the target vertex, from near to far. As the order increases, the optical region that the auxiliary graphics need to influence extends further, and the boundary of this region is mainly determined by the spatial environment between the graphics, i.e., the minimum spacing between the dense graphics. Therefore, in order to push the auxiliary graphics to a more distant region, the radius of the placement trajectory needs to increase with the order of the auxiliary graphics when placing different-order auxiliary graphics. Thus, the weighting coefficient of the minimum spacing between the dense graphics is positively correlated with the order of the vertex auxiliary graphics to ensure that the radii of the circular trajectories of vertex auxiliary graphics of different orders are different during placement.

[0138] In some embodiments, the number of concentric circle trajectories can be the same as the order of the auxiliary edge graphic of the sparse graph. For example, different concentric circle trajectories correspond to different orders of auxiliary graphics. That is, each auxiliary edge graphic of a first-order sparse graph can have a corresponding concentric circle trajectory.

[0139] For each concentric circle trajectory, in order to make the auxiliary graphics with higher order further away from the sparse graphics, the radius of the concentric circle trajectory is positively correlated with the order of its corresponding auxiliary graphics. Therefore, when determining the radius of the placement trajectory, the weight coefficient of the minimum spacing of the dense graphics can be determined according to the order of the auxiliary graphics corresponding to the concentric circle trajectory, and the radius can be determined according to the side length of the sparse graphics and the weight coefficient. The radius is positively correlated with the weight coefficient, and the weight coefficient is positively correlated with the order of the auxiliary graphics corresponding to the concentric circle trajectory.

[0140] For example, the weighting coefficients for the minimum spacing of the dense graphs corresponding to first-order, second-order, and third-order vertex auxiliary graphs can be 2, 4, and 6, respectively. Then, when the sparse graph is a square with a side length of... L The minimum spacing of dense graphics is S When, the radius of the circular trajectory of the first-order vertex auxiliary figure of the sparse figure is placed. r 1 can be r 1= m 1 L +2 S The radius of the circular trajectory of a second-order auxiliary figure used to place the sparse figure. r 2 can be r 2= m 1 L +4 S The radius of the circular trajectory of a third-order auxiliary figure used to place a sparse figure. r 3 can be r 3= m 1 L +6 S .

[0141] For example, for the mid-path lithography layer at a 28nm node, the side length of the sparse pattern L It is 70nm, the minimum spacing between sparse patterns. S It is 45nm, the radius of the circular trajectory of the first-order vertices of the sparse pattern auxiliary pattern. r 1 can be 120nm, the radius of the circular trajectory of the second-order auxiliary pattern for placing the sparse pattern. r 2 can be 200nm, the radius of the circular trajectory of the third-order auxiliary pattern for placing sparse patterns. r 3 can be 300nm.

[0142] In some embodiments, after determining the concentric circle trajectories with different orders of assistance, at least one vertex assistance graphic is generated for each concentric circle trajectory, and vertex assistance graphics arranged on each concentric circle trajectory can be generated starting from the center of the circle of the multiple concentric circle trajectories and in order from the inner circle to the outer circle.

[0143] The method for generating vertex auxiliary graphics provided in this application embodiment has a positive correlation between the weight coefficient and the order of the auxiliary graphics corresponding to the concentric circle trajectory, and a positive correlation between the radius and the weight coefficient. This method can generate vertex auxiliary graphics of different orders for sparse graphics in chip design layout.

[0144] In some embodiments, step 203 is further refined to include:

[0145] Using the coordinates of the target vertex as the origin of the coordinate system, the placement coordinates of the auxiliary graphics arranging the vertices on the placement trajectory are calculated using the following formula:

[0146] ,

[0147] in, n For the first one arranged on the placement trajectory n A vertex auxiliary graph, x n To place the x-coordinate value of the coordinate system. y n The ordinate value is used to place the coordinates. x 0 and y 0 Let the coordinates be the center of the circle. r For radius, N The preset number of auxiliary graphs for vertices.

[0148] In some embodiments, when the placement trajectory is multiple concentric circle trajectories, for each concentric circle trajectory, the placement coordinates of the vertex auxiliary graphics arranged on the concentric circle trajectory are calculated using the following formula:

[0149] ,in, m Let be the order of the vertex auxiliary graph. Where, N The preset number of vertex auxiliary graphics is specified, and the preset number of vertex auxiliary graphics on each concentric circle trajectory can be different.

[0150] The method for generating vertex auxiliary graphics provided in this application embodiment, through... n Traverse from 1 to NIt can calculate the placement of vertex auxiliary graphics without any omissions, and all placement positions are calculated by deterministic mathematical formulas, exhibiting extremely high repeatability and accuracy. It does not rely on the operator's experience and avoids the randomness and risk of omissions inherent in manual estimation. Furthermore, based on the trigonometric function-based angle division, it ensures that the vertex auxiliary graphics are evenly distributed on the target arc, thus providing a symmetrical and balanced modulation effect optically. A preset number of [items / items] is available. N It can control the generation density of auxiliary graphics, and thus select different preset quantities according to different design layouts, balancing imaging performance and mask graphic complexity.

[0151] In one embodiment of this application, the method for generating vertex-assisted graphics provided in this application includes:

[0152] Step 701: Obtain the chip design layout with auxiliary graphics placed on it. This chip design layout contains both dense and sparse graphics. The sparse graphics need to be supplemented with auxiliary graphics to improve the process window. The sparse graphics in this chip design layout are squares.

[0153] Step 702: Measure the side length L of the sparse pattern and the minimum spacing S among all sparse patterns.

[0154] Step 703: Obtain the preset side length of the vertex auxiliary graphic to be generated. Q The auxiliary shape of the vertex is a square.

[0155] Step 704: Based on the side length L and spacing S of the sparse pattern, calculate the placement period of the first-order auxiliary pattern: P1 = m1L + 2 × m2S; the placement period of the second-order auxiliary pattern: P2 = m1L + 4 × m2S; and the placement period of the third-order auxiliary pattern: P3 = m1L + 6 × m2S. For example, for a mid-path lithography layer at a 28nm node, the side length L of the sparse pattern is 70nm, and the minimum spacing S between the sparse patterns is 45nm. Therefore, the first-order placement period P1 can be calculated to be 120nm, the second-order placement period P2 to be 200nm, and the third-order placement period P3 to be 300nm. Here, the placement period is the radius of the circular trajectory.

[0156] Step 705: Obtain the preset number N1, N2, N3 of auxiliary graphics corresponding to placement periods P1, P2, P3.

[0157] Step 706, iterate through the number of auxiliary figures N1, for each auxiliary figure n ( ) Calculate the coordinates x of the auxiliary graph of each vertex of the sparse graph using trigonometric functions. n and y n Positive coordinate value x n y n Represents the space direction of a vertex in an auxiliary graph; negative coordinate value x.n y n This represents the width direction of a vertex in the auxiliary graph. As you can see, the x-coordinate... n and y n The trajectory is based on ( k 1 L + k 2 Q , k 1 L + k 2 Q A circle with center P1 and radius P1; N1 is the number of equal divisions of this circle starting from an angle of 0 degrees. By setting N1, not only can the number of auxiliary graphics be controlled, but the spacing between the auxiliary graphics can also be flexibly adjusted.

[0158] For example, Figure 7 This is a schematic diagram showing the placement of vertex auxiliary graphics according to another embodiment of this application. For example... Figure 7 As shown, for the 28nm node, the side length of the auxiliary pattern... Q =30nm. Therefore, for vertex 71 of the sparse pattern, construct a Cartesian coordinate system with it as the origin. The coordinates of its center 72 are (-50, -50), and its radius is 125nm. If the number of auxiliary patterns N1 can be set to 20, then there will be an average of 5 auxiliary patterns in each of the 4 coordinate quadrants. Figure 7 The image only shows the placement positions of the vertex auxiliary graphics (x1, y1), (x2, y2), (x3, y3), and (x... n ,y n ).

[0159] Step 707, for each auxiliary figure n ( ), calculated in step 706 (x n ,y n The coordinates are the vertices of the auxiliary graphic, and the generated side length is... Q A square auxiliary figure. Continuing from the previous example, Figure 7 The diagram shows the generation of a side with a length of [value] at the calculated (x1, y1) coordinates. Q 73. Square auxiliary graphic.

[0160] Step 708, for each auxiliary figure n ( ), calculate the current (x) n ,y n The edge-to-edge distance and vertex-to-vertex space distance between the auxiliary graph and the sparse graph at the given position (x) and the current position (x) n ,y nThe distance between the vertex auxiliary graphic at the placement position and other already placed edge-based auxiliary graphics and vertex auxiliary graphics is calculated as the edge-to-edge and vertex-to-vertex space distance. The code checks whether the mask rule check (MRC) set by the chip manufacturer is satisfied. If satisfied, the complete vertex auxiliary graphic is retained. If not satisfied, the edge length of the vertex auxiliary graphic is reduced according to the size of the MRC violation to meet the requirements of the mask rule MRC.

[0161] Step 709: Iterate through the number of auxiliary graphics N1 to complete the generation of auxiliary graphics related to the placement period P1.

[0162] Step 710: Repeat steps 705 to 708 to complete the generation of vertex auxiliary graphics for the second-order placement period P2 and the third-order placement period P3. In practice, the number of orders of the edge-based auxiliary graphics generally corresponds to the number of orders of the vertex auxiliary graphics. The number of orders of the vertex auxiliary graphics to be generated can be adjusted based on the actual order of the edge auxiliary graphics.

[0163] Based on the above method for generating vertex-assisted graphics, this application also provides specific embodiments of an apparatus for generating vertex-assisted graphics.

[0164] Figure 8 This is a schematic diagram of the structure of an apparatus for generating vertex-assisted graphics according to another embodiment of this application. Figure 8 As shown, the apparatus 80 for generating vertex auxiliary graphics provided in this application embodiment includes an acquisition module 81, a determination module 82, and a generation module 83.

[0165] The acquisition module 81 is used to acquire the chip design layout and its geometric parameters. The chip design layout includes sparse patterns and dense patterns. The geometric parameters include the minimum spacing of the dense patterns, the side length of the sparse patterns, and the coordinates of the target vertex of the auxiliary pattern to be configured in the sparse patterns.

[0166] The determination module 82 is used to determine the placement trajectory based on geometric parameters. The placement trajectory can be a circular trajectory or multiple concentric circle trajectories.

[0167] Generation module 83 is used to generate at least one vertex auxiliary graph arranged on the placement trajectory.

[0168] As an optional implementation, the determining module is specifically used for:

[0169] Determine the center of the placement trajectory based on the coordinates of the target vertex, the side length of the sparse graph, and the preset side length of the vertex auxiliary graph.

[0170] The radius of the placement trajectory is determined based on the side length of the sparse graph and the minimum spacing of the dense graph.

[0171] As an optional implementation, the determining module is further used for:

[0172] Using the coordinates of the target vertex as the origin of the coordinate system, the coordinates of the center of the circle are calculated using the following formula:

[0173] x 0= k 1 L + k 2 Q , y 0= k 1 L + k 2 Q ;

[0174] in, x 0 and y 0 is the coordinate of the center of the circle. L Let be the side length of the sparse graph. Q The preset side length for the vertex auxiliary shape. k 1 and k 2 is the preset coefficient.

[0175] As an optional implementation, the determining module is further used for:

[0176] The radius is calculated using the following formula:

[0177] r = m 1 L + m 2 S ,

[0178] in, r For radius, L Let be the side length of the sparse graph. S The minimum spacing for dense graphics. These are preset coefficients.

[0179] As an optional implementation, the chip design layout also includes edge auxiliary graphics for sparse graphics, and the generation module is specifically used for:

[0180] For each vertex auxiliary graph generated, a mask rule check is performed on the vertex auxiliary graph to determine whether there is a mask rule conflict between the vertex auxiliary graph and dense graphs, sparse graphs, or edge auxiliary graphs.

[0181] If a mask rule conflict is determined, the side length of the vertex auxiliary graph is adjusted until there is no mask rule conflict between the vertex auxiliary graph and all dense graphs, all sparse graphs, and all edge auxiliary graphs.

[0182] As an optional implementation, when the placement trajectory is multiple concentric circle trajectories, the generation module is further used for:

[0183] Starting from the center of multiple concentric circle trajectories, generate vertex auxiliary graphics arranged on each concentric circle trajectory in order from the inner circle to the outer circle.

[0184] As an optional implementation, when the placement trajectory is multiple concentric circle trajectories, the apparatus for generating vertex auxiliary graphics further includes:

[0185] The second determining module is used to determine the number of concentric circle trajectories based on the order of the auxiliary graphics of the sparse graphics in the chip design layout, and to determine the order of the auxiliary graphics corresponding to each concentric circle trajectory.

[0186] The module is specifically used for:

[0187] The weighting coefficient for the minimum spacing of dense graphics is determined based on the order of the auxiliary graphics corresponding to the concentric circle trajectory. The weighting coefficient is positively correlated with the order of the auxiliary graphics corresponding to the concentric circle trajectory.

[0188] The radius is determined based on the side length and weight coefficient of the sparse graph, and the radius is positively correlated with the weight coefficient.

[0189] The generation module is specifically used for:

[0190] For each concentric circle trajectory, generate at least one vertex auxiliary graph.

[0191] As an optional implementation, the generation module is specifically used for:

[0192] Using the coordinates of the target vertex as the origin of the coordinate system, the placement coordinates of the auxiliary graphics arranging the vertices on the placement trajectory are calculated using the following formula:

[0193] ,

[0194] in, n For the first one arranged on the placement trajectory n A vertex auxiliary graph, x n To place the x-coordinate value of the coordinate system. y n The ordinate value is used to place the coordinates. x 0 and y 0 Let the coordinates be the center of the circle. r For radius, N The preset number of auxiliary graphs for vertices.

[0195] As an optional implementation, the generation module is further used for:

[0196] Using the placement coordinates as the vertex coordinates of the auxiliary vertex graphic, generate the auxiliary vertex graphic outside the placement trajectory.

[0197] Figure 9 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. For example... Figure 9 As shown, the electronic device may include a processor 91 and a memory 92 storing computer program instructions.

[0198] Specifically, the processor 91 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0199] Memory 92 may include mass storage for data or instructions. For example, and not limitingly, memory 92 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 92 may include removable or non-removable (or fixed) media. Where appropriate, memory 92 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 92 is non-volatile solid-state memory.

[0200] The processor 91 implements any of the methods for generating vertex-assisted graphics in the above embodiments by reading and executing computer program instructions stored in the memory 92.

[0201] In one example, the electronic device may also include a communication interface 93 and a bus 94. Wherein, as... Figure 9 As shown, the processor 91, memory 92, and communication interface 93 are connected via bus 94 and communicate with each other.

[0202] Communication interface 93 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0203] Bus 94 includes hardware, software, or both, that couples the components of the electronic device together. For example, and not limitingly, the bus may include Accelerated Graphics Port (AGP) or other graphics buses, Enhanced Industry Standard Architecture (EISA) buses, Front Side Bus (FSB), HyperTransport (HT) interconnects, Industry Standard Architecture (ISA) buses, Infinite Bandwidth Interconnects, Low Pin Count (LSI) interconnects, etc. LThe bus may be a PC bus, memory bus, Microchannel Architecture (MCA) bus, Peripheral Component Interconnect (PCI) bus, PCI-Express (PCI-X) bus, Serial Advanced Technology Attachment (SATA) bus, Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 94 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0204] Furthermore, in conjunction with the methods for generating vertex-assisted graphics in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. This computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the methods for generating vertex-assisted graphics in the above embodiments.

[0205] This application also provides a computer program product, including a computer program that, when executed by a processor, implements any of the methods for generating vertex-assisted graphics described in the above embodiments.

[0206] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0207] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0208] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0209] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0210] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for generating vertex-assisted graphics, characterized in that, include: Obtain the chip design layout and its geometric parameters. The chip design layout includes sparse and dense patterns. The geometric parameters include the minimum spacing of the dense patterns, the side length of the sparse patterns, and the coordinates of the target vertex of the auxiliary pattern to be configured in the sparse patterns. Based on the geometric parameters, the placement trajectory is determined, which is a circular trajectory or multiple concentric circle trajectories; Generate at least one vertex auxiliary pattern arranged on the placement trajectory, such that the effective range of the vertex auxiliary pattern matches the optical feature size of the sparse pattern; Determining the placement trajectory based on the geometric parameters includes: The center of the placement trajectory is determined based on the coordinates of the target vertex, the side length of the sparse graph, and the preset side length of the vertex auxiliary graph. The radius of the placement trajectory is determined based on the side length of the sparse pattern and the minimum spacing of the dense pattern; Determining the center of the placement trajectory based on the side length of the sparse graph and the preset side length of the vertex auxiliary graph includes: Using the coordinates of the target vertex as the origin of the coordinate system, the coordinates of the center of the circle are calculated using the following formula: x 0= k 1 L + k 2 Q ， y 0= k 1 L + k 2 Q ； in, x 0 and y 0 is the coordinate of the center of the circle. L Let be the side length of the sparse graph. Q The preset side length of the vertex auxiliary shape. k 1 and k 2 is the preset coefficient; The radius of the placement trajectory is determined based on the side length of the sparse pattern and the minimum spacing of the dense pattern, including: The radius is calculated using the following formula: r = m 1 L + m 2 S ， in, r The radius is... L Let be the side length of the sparse graph. S The minimum spacing of the dense pattern. These are preset coefficients.

2. The method according to claim 1, characterized in that, The chip design layout also includes edge auxiliary graphics of the sparse graphics, and generating at least one vertex auxiliary graphic arranged on the placement trajectory includes: For each vertex auxiliary graph generated, a mask rule check is performed on the vertex auxiliary graph to determine whether there is a mask rule conflict between the vertex auxiliary graph and the dense graph, the sparse graph, or the edge auxiliary graph. If a mask rule conflict is determined, the side length of the vertex auxiliary graph is adjusted until there is no mask rule conflict between the vertex auxiliary graph and all the dense graphs, all the sparse graphs and all the edge auxiliary graphs.

3. The method according to claim 1, characterized in that, When the placement trajectory is a plurality of concentric circle trajectories, generating at least one vertex auxiliary graphic arranged on the placement trajectory includes: Starting from the center of the plurality of concentric circle trajectories, the vertex auxiliary graphics arranged on each of the concentric circle trajectories are generated in order from the inner circle to the outer circle.

4. The method according to claim 1, characterized in that, When the placement trajectory is multiple concentric circle trajectories, after obtaining the chip design layout and its geometric parameters, the method further includes: Based on the order of the edge auxiliary graphics of the sparse graphics in the chip design layout, determine the number of circles of the concentric circle trajectory, and determine the order of the auxiliary graphics corresponding to each concentric circle trajectory; Determining the radius of the placement trajectory based on the side length of the sparse pattern and the minimum spacing of the dense pattern includes: The weighting coefficient of the minimum spacing of the dense graphics is determined based on the order of the auxiliary graphics corresponding to the concentric circle trajectory, and the weighting coefficient is positively correlated with the order of the auxiliary graphics corresponding to the concentric circle trajectory. The radius is determined based on the side length of the sparse graph, the minimum spacing of the dense graph, and the weighting coefficient, wherein the radius is positively correlated with the weighting coefficient. Generating at least one vertex auxiliary graph arranged on the placement trajectory includes: For each of the concentric circle trajectories, at least one vertex auxiliary graph is generated.

5. The method according to claim 1, characterized in that, Generating at least one vertex auxiliary graph arranged on the placement trajectory includes: Using the coordinates of the target vertex as the origin of the coordinate system, the placement coordinates of the auxiliary graphics arranging the vertex on the placement trajectory are calculated using the following formula: ， in, n The first one arranged on the placement trajectory n The aforementioned vertex auxiliary graph x n The x-coordinate value of the placement coordinates. y n The vertical coordinate value of the placement coordinates. x 0 and y 0 Let these be the coordinates of the center of the circle. r The radius is... N The preset number of auxiliary graphics for the vertices.

6. The method according to claim 5, characterized in that, Generating at least one vertex auxiliary graph arranged on the placement trajectory includes: The vertex auxiliary graphic is generated outside the placement trajectory using the placement coordinates as the vertex coordinates of the auxiliary graphic.

7. A computer program product, characterized in that, The method includes computer execution instructions, which, when executed by a processor of an electronic device, cause the electronic device to perform the method as described in any one of claims 1-6.

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