Embedded code-oriented large model debugging method and system

Abstract

The invention discloses an embedded code-oriented large model debugging method and system. The method comprises the following steps of: preparing a correct embedded code sample; code samples with various types of errors are generated on the basis of a data enhancement method, and error labels are attached to the code samples; constructing a debugging prompt as model input; in the model training stage, using a cross entropy loss function and a back propagation algorithm to update model parameters; and iterating the training data to obtain an embedded code debugging model. According to the method, the optimization of embedded error detection is realized in a model training mode. The method does not depend on a fixed template or a static rule, a large model can learn register operation rules, bit operation logic and hardware constraint relations in embedded C codes by constructing a data set with supervised training, and therefore reasoning and automatic generation are achieved in tasks such as logic verification and error positioning.

Description

Technical Field

[0001] This invention relates to the field of automatic code writing technology, and specifically to a method and system for large-scale error checking of embedded code. Background Technology

[0002] Embedded systems are widely used in fields such as the Internet of Things (IoT), smart hardware, and industrial control. The reliability, real-time performance, and hardware adaptability of the code directly affect system performance and security. Embedded C language remains the primary development language in this field due to its close proximity to hardware and high execution efficiency. However, manually writing and maintaining embedded C code is complex and prone to causing system defects due to register configuration errors, bitwise operation mistakes, or misjudgments of active high / low signals.

[0003] Therefore, people have been exploring and researching methods for automatic code generation, such as generating partially fixed-structure code using template-based code generation tools. However, these methods lack corresponding error detection mechanisms. Static analysis tools can detect syntax errors, but they struggle to identify logic errors specific to embedded systems. Summary of the Invention

[0004] One of the objectives of this invention is to provide a large-scale error-checking method for embedded code, in order to address the shortcomings of existing code generation tools that are difficult to adapt to complex embedded scenarios.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A method for debugging large models of embedded code, comprising: Prepare the correct embedded code sample; Subsequently, code samples with various types of errors were generated based on data augmentation methods, along with error labels; Construct error-checking prompts as model input; During the model training phase, the cross-entropy loss function and backpropagation algorithm are used to update the model parameters; The embedded code debugging model is obtained by iteratively training the data.

[0006] Furthermore, the embedded code sample includes one or more modules such as register assignment, pin initialization, clock configuration, and control logic, and establishes a register-pin-function mapping knowledge base by combining chip manual and header file information.

[0007] Furthermore, the error label identifies the error type and location. The error type includes one or more of the following: variable source error, register name error, bit operation direction error, misjudgment of high and low significant bits, and function call omission.

[0008] Furthermore, during the model training phase, the model simultaneously learns the syntactic features, semantic dependencies, and hardware rule relationships of the code, enabling it to distinguish between different types of errors.

[0009] Furthermore, it also includes the model application stage: classifying error types using the trained model; applying different prompt word templates to the identified errors so that the model can correct them; generating an error-checking workflow for embedded code until compilation is successful.

[0010] Furthermore, the error types include variable source errors, bit operation misuse, misjudgment of high and low valid signals, and logic omissions.

[0011] Furthermore, the workflow for generating error-checking for embedded code includes injecting errors through data augmentation, constructing error-checking prompts, and performing model-based detection.

[0012] The second objective of this invention is to provide a large-scale error-checking system for embedded code, in order to solve the problem that existing code generation tools are difficult to adapt to complex embedded scenarios. To achieve the above objectives, the present invention adopts the following technical solution: A large model debugging system for embedded code includes a large model that performs the large model debugging method for embedded code as described above.

[0013] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: This method optimizes embedded error detection through model training. It does not rely on fixed templates or static rules; instead, it constructs a supervised training dataset, enabling large models to learn register operation patterns, bitwise logic, and hardware constraints in embedded C code. This allows for reasoning and automatic generation in tasks such as logic verification and error localization. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the model completion training method of the present invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0016] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art. Example

[0017] Please refer to Figure 1 As shown, this invention discloses a large-scale error detection method for embedded code, which includes: preparing correct embedded code samples; subsequently generating code samples with various types of errors and attaching error labels based on data augmentation methods; constructing error detection prompts as model input; updating model parameters using cross-entropy loss function and backpropagation algorithm during the model training phase; and iteratively training the data to obtain an embedded code error detection model.

[0018] The embedded code samples refer to a collection of correct code extracted from real-world projects. These samples can be implemented using open-source project code, internal enterprise code repositories, or verified, manually written code. They cover common modules such as register assignment, pin initialization, clock configuration, and control logic. The selection of these modules is based on frequently occurring and error-prone operations in actual development, aiming to ensure that the training data covers the core hardware operation scenarios of embedded systems.

[0019] This process also incorporates information from the chip datasheet and header files to establish a register-pin-function mapping knowledge base. This knowledge base is a set of hardware configuration rules built based on the chip datasheet and header file information. By mapping register bit field configurations to physical pin states and function outputs, it helps the model understand the logical relationships at the hardware level, thereby accurately distinguishing error types during detection. This is achieved by parsing the chip datasheet, extracting header file definitions, or integrating hardware abstraction layer interfaces.

[0020] Based on the collected embedded code samples, error-laden samples are generated using data augmentation methods. Data augmentation methods are techniques that modify correct code to simulate diverse error scenarios, such as randomly inserting incorrect variables, replacing register names, adjusting bit operation directions, and changing the high and low level definitions of signals.

[0021] By injecting various types of errors, error-containing samples were constructed, each accompanied by an error label identifying the error type and location. The error types include variable source errors, register name errors, bit operation direction errors, misjudgment of significant and insignificant bits, and function call omissions. These error types are specifically learned for hardware interaction scenarios in embedded development. For example, when the model encounters a register name error, it can identify configuration problems based on the register definitions in the chip manual; for bit operation direction errors, the model can analyze the correctness of the bit operation logic and detect shift or masking errors; and for misjudgment of significant and insignificant bits, the model can correct deviations in high and low level processing, thereby improving the model's understanding of the rules specific to the embedded environment. Error location refers to the specific point in the code where the error occurs, which can be identified by line number, column number, or code segment identifier, helping the model accurately locate errors and learn error patterns. In this way, a comprehensive and clearly defined error-detection training dataset is formed through data augmentation methods.

[0022] Code snippets, knowledge base information, and error-checking prompt templates are combined as model input. Error-checking prompts are designed to include task descriptions, example formats, and output constraints. For example, a prompt template could be "Register X is used to control function Y, and the common configuration value is Z," ensuring that the model can identify the error type and its corresponding location under a unified semantic framework.

[0023] Finally, the system uses the incorrect samples and their corresponding incorrect labels as input-output pairs, employs the cross-entropy loss function to measure the difference between the model's predicted distribution and the true label distribution, and combines the backpropagation algorithm to gradually adjust the model parameters.

[0024] In addition, the model learns the syntactic features, semantic dependencies, and hardware rule relationships of the code simultaneously during training, enabling it to distinguish different types of errors.

[0025] Syntactic features refer to the basic structure and rules of code that conform to language specifications, which can be implemented by parsing abstract syntax trees or building lexical analyzers. Semantic dependencies can be understood as the learning process of code logic chains and contextual relationships, avoiding errors caused by missing logic. Hardware rule relationships refer to knowledge specific to the embedded environment, such as register configuration, pin initialization, and bit operation rules, which can be implemented by combining chip manual information or hardware description languages ​​for modeling. By synchronously integrating these three aspects of learning, the model can comprehensively analyze the root causes of errors, tightly combining syntax, logic, and hardware context, thereby effectively solving the problem of error type confusion caused by ignoring hardware rules and achieving a comprehensive distinction of embedded code errors.

[0026] Model application phase: First, leveraging the syntactic features, semantic dependencies, and hardware rule relationships learned during the model's training phase, the model categorizes errors into types such as variable source errors, bit operation misuse, high / low valid signal misjudgment, and logic omissions. Variable source errors refer to the failure to correctly reflect the close relationship between variable initialization and register assignment in the embedded environment; bit operation misuse refers to the failure to correctly execute the high dependence on bit operations in the embedded code; high / low valid signal misjudgment refers to deviations in signal polarity determination in the embedded system; and logic omissions refer to omissions in conditional judgments or state transitions in the embedded control logic.

[0027] Subsequently, matching prompt word templates are selected based on different error types to guide the model in generating targeted repair suggestions. These prompt word templates can be implemented using a predefined template library or dynamically generated templates, aiming to guide the model in generating repair code that conforms to hardware rules and contextual semantics. Finally, an error-checking workflow for embedded code is generated, including injecting errors through data augmentation, constructing error prompts, and executing model detection. Data augmentation injects potential error patterns and combines chip manual and hardware knowledge base information to construct error prompts, enabling the model to cover a wider range of error scenarios, especially complex logic errors unique to embedded systems, such as register-pin dependencies. The modified code is then compiled; if this fails, prompt words are reconstructed based on the compiler's feedback to guide the model in modifying the code until compilation succeeds.

[0028] Another aspect of the present invention provides a large model error checking system for embedded code, which solves the problem that existing code generation tools are difficult to adapt to complex embedded scenarios by incorporating the aforementioned large model.

[0029] For system embodiments, since they correspond to method embodiments, the relevant parts can be referred to in the description of the method embodiments.

[0030] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for debugging large models of embedded code, characterized in that, include: Prepare the correct embedded code sample; Subsequently, code samples with various types of errors were generated based on data augmentation methods, along with error labels; Construct error-checking prompts as model input; During the model training phase, the cross-entropy loss function and backpropagation algorithm are used to update the model parameters; The embedded code debugging model is obtained by iteratively training the data.

2. The method for large-scale error checking of embedded code as described in claim 1, characterized in that: The embedded code sample includes one or more modules such as register assignment, pin initialization, clock configuration, and control logic. Combined with chip manual and header file information, a knowledge base for mapping register-pin-function is established.

3. The method for large-scale error checking of embedded code as described in claim 1, characterized in that: The error label identifies the error type and location. The error type includes one or more of the following: variable source error, register name error, bit operation direction error, misjudgment of significant and insignificant bits, and function call omission.

4. The method for large-scale error checking of embedded code as described in claim 1, characterized in that: During the model training phase, the model simultaneously learns the syntactic features, semantic dependencies, and hardware rule relationships of the code, enabling it to distinguish between different types of errors.

5. The method for large-scale error checking of embedded code as described in claim 1, characterized in that, It also includes the model application phase: Error types are categorized using a trained model; The identified errors are then fitted with different prompt word templates to allow the model to correct them. Generate a debugging workflow for embedded code until compilation succeeds.

6. The method for large-scale error checking of embedded code as described in claim 5, characterized in that: The error types include variable source errors, bit operation misuse, misjudgment of high and low valid signals, and logic omissions.

7. The method for large-scale error checking of embedded code as described in claim 5, characterized in that, The workflow for generating error-checking for embedded code includes: injecting errors through data augmentation, constructing error-checking prompts, and performing model detection.

8. A large-scale error-checking system for embedded code, characterized in that, Includes a large model, which performs the large model debugging method for embedded code as described in any one of claims 1-7.

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