A current mode driven transmitting circuit

Abstract

The application relates to the driving field and particularly relates to a current mode driving sending end circuit. The current mode driving sending end circuit comprises a voltage bias circuit, a current bias circuit and a driving circuit; the voltage bias circuit is used for generating an adjustable amplitude voltage VR2 through an input reference voltage Vref, the adjustable amplitude voltage VR2 is equal to the output voltage amplitude of the current mode driving sending end circuit; the current bias circuit is connected with the voltage bias circuit and is used for generating a bias current, the bias current generates a proportional mirror current in the driving circuit; the driving circuit is connected with the current bias circuit, is used for receiving a differential signal and outputs the differential signal. The output stage provides a precise bias current which is not affected by the process, the power voltage and the temperature. Low-voltage devices are used to control the output signal logic, the working speed of the driver is improved, and the damage of the switch noise generated by the high-voltage digital logic to the integrity of the high-voltage domain power supply is effectively avoided.

Description

Technical Field

[0001] This invention relates to the field of driving, and in particular to a current-mode driven transmitting circuit. Background Technology

[0002] In high-speed communication systems, the transmitting end driver circuit operates at the highest data rate in the entire communication system. This not only affects the power consumption and data rate limit of the entire transmitting end, but also the quality of the signal transmitted into the channel, such as amplitude attenuation, jitter, crosstalk, inter-symbol interference, EMI, and so on.

[0003] Transmitter driver circuits are divided into two types: voltage-mode and current-mode, each with its own advantages, disadvantages, and suitable application scenarios. Current-mode drivers in existing technology struggle to balance speed and power consumption. Because of the terminating resistor connected to a 3.3V power supply at the receiver, the transmitter driver circuit must use a high-voltage transistor in the 3.3V range. However, the area and capacitive parasitics of high-voltage transistors are significantly larger than those of low-voltage transistors. If a high-voltage transistor is used to control the high and low levels of the transmitted signal, the size of the switching transistor will inevitably be large due to the need to handle milliampere-level currents, affecting transmission speed and hindering the transmission of high-resolution images. Furthermore, the front-end driver also requires correspondingly large high-voltage components, greatly increasing the overall area and power consumption of the transmitter, as well as increasing switching noise on the power lines, adversely affecting other modules in the transmitter. Summary of the Invention

[0004] The purpose of this invention is to solve the aforementioned problems by designing a current-mode driven transmitting circuit. To achieve the above objective, this invention provides the following solution:

[0005] A current-mode driven transmitter circuit includes a voltage bias circuit, a current bias circuit, and a drive circuit.

[0006] The voltage biasing circuit is used to generate an adjustable amplitude voltage VR2 by means of an input reference voltage Vref. The adjustable amplitude voltage VR2 is equal to the output voltage amplitude of the current-mode driven transmitting circuit.

[0007] The current bias circuit and the voltage bias circuit are connected to generate a bias current, which generates a proportional mirror current in the drive circuit.

[0008] The driving circuit is connected to the current bias circuit to receive differential signals and output differential signals.

[0009] As a further improvement to this technical solution, the current bias circuit includes a first resistor array, and the driving circuit includes a second resistor array and a third resistor array; the resistance values ​​of the second resistor array and the third resistor array are equal; the ratio of the resistance value of the first resistor array to the resistance values ​​of the second and third resistor arrays is n:1, and the ratio is adjustable.

[0010] As a further improvement to this technical solution, the second resistor array and the third resistor array are resistor arrays with adjustable resistance values; when the resistance values ​​of the second resistor array and the third resistor array change, the resistance values ​​of the second resistor array and the third resistor array are always equal.

[0011] As a further improvement to this technical solution, the voltage bias circuit includes an amplifier AMP1, a resistor R1, an NMOS transistor NM0, and an adjustable resistor R2.

[0012] The reference voltage Vref is connected to the inverting input terminal of the amplifier AMP1. The non-inverting input terminal of the amplifier AMP1 is connected to one end of the resistor R1 and also to the drain of the NMOS transistor NM0. The output terminal of the amplifier AMP1 is connected to the gate of the NMOS transistor NM0, and the source of the NMOS transistor NM0 is grounded. The other end of the resistor R1 is connected to the first end of the adjustable resistor R2, and the first end of the adjustable resistor R2 is connected to the power supply VCC. The output terminal of the voltage bias circuit is connected to the connection line between the resistor R1 and the adjustable resistor R2, and is also connected to the current bias circuit.

[0013] As a further improvement to this technical solution, the current bias circuit includes amplifier AMP2, resistor array RES0, NMOS transistor NM2, and NMOS transistor NM3;

[0014] The negative input terminal of amplifier AMP2 is the input terminal of the current bias circuit. The positive input terminal of amplifier AMP2 is connected to one end of resistor array RES0 and simultaneously to the drain of low-voltage NMOS transistor NM2. The other end of RES0 is connected to power supply VCC. The gate of NMOS transistor NM2 is connected to power supply VDD, and the source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM3. The gate of NMOS transistor NM3 is connected to the output terminal of amplifier AMP2. The output terminal of the current bias circuit is connected between the gate of NMOS transistor NM3 and the output terminal of amplifier AMP2. The source of NMOS transistor NM3 is grounded.

[0015] The output terminal of the current bias circuit is connected to the input terminal of the drive circuit.

[0016] As a further improvement to this technical solution, the current biasing circuit also includes an NMOS transistor NM1;

[0017] The connection between the drain of the NMOS transistor NM2 and the resistor array RES0 is broken;

[0018] The gate of the NMOS transistor NM1 is connected to the power supply VBH; the source of the NMOS transistor NM1 and the drain of the NMOS transistor NM2 are connected; the positive input terminal of the amplifier AMP2 is connected to one end of the resistor array RES0, and is also connected to the drain of the NMOS transistor NM1.

[0019] As a further improvement to this technical solution, the driving circuit includes resistor array RES1, resistor array RES2, NMOS transistors NM5, NMOS transistors NM6, NMOS transistors NM8, NMOS transistors NM9, PMOS transistors PM1, PMOS transistors PM2, first buffer Buffer1, and second buffer Buffer2.

[0020] The gate of the NMOS transistor NM6 is connected to the first input terminal of the driving circuit, and the gate of the low-voltage NMOS transistor NM9 is connected to the first input terminal of the driving circuit.

[0021] The source of NMOS transistor NM6 is grounded, and the source of NMOS transistor NM9 is grounded;

[0022] The drain of NMOS transistor NM6 is connected to the drain of NMOS transistor NM9;

[0023] The source of NMOS transistor NM5 is connected to the drain of NMOS transistor NM6; the source of NMOS transistor NM8 is connected to the drain of NMOS transistor NM9; and the source of NMOS transistor NM5 is connected to the source of NMOS transistor NM8.

[0024] The first input signal VIP is connected to the gate of the NMOS transistor NM5 via the first buffer Buffer1; the second input signal VIN is connected to the gate of the NMOS transistor NM8 via the second buffer Buffer2.

[0025] The gate of the PMOS transistor PM1 is connected to the gate of the NMOS transistor NM5; the drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM5; the source of the PMOS transistor PM1 is connected to the power supply VDD.

[0026] The gate of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM8; the drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM8; the source of the PMOS transistor PM2 is connected to the power supply VDD.

[0027] The drain of the NMOS transistor NM5 is connected to one end of the resistor array RES1, and the other end of the resistor array RES1 is connected to the power supply VCC. The first output terminal VON of the current-mode driven transmitter circuit is connected between the drain of the NMOS transistor NM5 and the resistor array RES1.

[0028] The drain of the NMOS transistor NM8 is connected to one end of the resistor array RES2, and the other end of the resistor array RES2 is connected to the power supply VCC. The second output terminal VOP of the current-mode driven transmitter circuit is connected between the drain of the NMOS transistor NM8 and the resistor array RES2.

[0029] As a further improvement to this technical solution, the driving circuit also includes NMOS transistor NM4, NMOS transistor NM7, switch SW1, switch SW2, and switch SW3;

[0030] The switch SW3 is a single-pole double-throw switch;

[0031] The drain of NMOS transistor NM5 is disconnected from resistor array RES1; the drain of NMOS transistor NM8 is disconnected from resistor array RES2.

[0032] The gate of the NMOS transistor NM4 is connected to the power supply VBH; the source of the NMOS transistor NM4 is connected to the drain of the NMOS transistor NM5; the drain of the NMOS transistor NM4 is connected to one end of the resistor array RES1, and the other end of the resistor array RES1 is connected to the power supply VCC via a switch SW1.

[0033] The gate of the NMOS transistor NM7 is connected to the power supply VBH; the source of the NMOS transistor NM7 is connected to the drain of the NMOS transistor NM8; the drain of the NMOS transistor NM7 is connected to one end of the resistor array RES2, and the other end of the resistor array RES2 is connected to the power supply VCC via switch SW2.

[0034] The first output terminal VON of the current-mode driven transmitting circuit is reconnected between the drain of the NMOS transistor NM4 and the resistor array RES1; the second output terminal VOP of the current-mode driven transmitting circuit is connected between the drain of the NMOS transistor NM7 and the resistor array RES2.

[0035] The connection between the gate of the NMOS transistor NM9 and the first input terminal of the driving circuit is disconnected; the gate of the NMOS transistor NM9 is connected to the common terminal of the switch SW3; the first selection terminal of the SW3 is connected to the first input terminal of the driving circuit; the second selection terminal of the SW3 is connected to ground.

[0036] As a further improvement to this technical solution, the switch SW3 is composed of a transmission gate TG, an inverter INV, and an NMOS transistor NM10;

[0037] The input terminal of the transmission gate TG is the common terminal of the switch SW3 and is connected to the drain of the NMOS transistor NM10.

[0038] The output terminal of the transmission gate TG is the first selection terminal of the switch SW3;

[0039] The high-level enable terminal of the transmission gate TG is connected to the control signal TR_SEL and to the input terminal of the inverter INV.

[0040] The output of the inverter INV is connected to the low-level enable terminal of the transmission gate TG and is connected to the gate of the NMOS transistor NM10.

[0041] The source terminal of the NMOS transistor NM10 is the second selection terminal of the switch SW3 and is connected to ground.

[0042] As a further improvement to this technical solution, the first resistor array is composed of resistor R0 and PMOS transistor PMR0;

[0043] The drain of the PMOS transistor PMr0 is connected to the first terminal of the resistor R0, the gate of the PMOS transistor PMr0 is grounded, and the source of the PMOS transistor PMr0 serves as the first connection terminal of the first resistor array; the second terminal of the resistor R0 serves as the second connection terminal of the first resistor array.

[0044] The second and third resistor arrays are composed of n resistors R11 to R1n and n PMOS transistors PMr11 to PMr1n; the drains of the n PMOS transistors PMr11 to PMr1n are respectively connected to the first terminals of the n resistors R11 to R1n; the gates of the n PMOS transistors PMr11 to PMr1n are connected in parallel and then connected to the resistance control signal TR_SELB; the sources of the n PMOS transistors PMr11 to PMr1n are connected in parallel and then form the first connection terminal of the second and third resistor arrays; the second terminals of the n resistors R11 to R1n are connected in parallel and then form the second connection terminal of the second and third resistor arrays. Attached Figure Description

[0045] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0046] Figure 1This is a schematic diagram of the structure of a current-mode driven transmitting circuit according to the present invention;

[0047] Figure 2 This is a schematic diagram of another structure of a current-mode driven transmitting circuit according to the present invention;

[0048] Figure 3 This is a schematic diagram of another structure of a current-mode driven transmitting circuit according to the present invention;

[0049] Figure 4 This is a schematic diagram of a resistor array in a current-mode driven transmitting circuit according to the present invention.

[0050] Figure 5 This is a schematic diagram of the switch SW3 in a current-mode driven transmitting circuit according to the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0052] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” and “described” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0053] The present invention will now be described in detail with reference to the accompanying drawings. Example

[0054] like Figure 1 The figure shows a schematic diagram of a current-mode driven transmitting circuit.

[0055] The current-mode driven transmitter circuit consists of a voltage bias circuit (VBIAS), a current bias circuit (IBIAS), and a driver circuit (DRIVER).

[0056] The voltage bias circuit VBIAS provides a reference voltage equal to the amplitude of the output signal for subsequent circuits; this reference voltage is adjustable.

[0057] The IBIAS current bias circuit provides a stable bias current to the drive circuit that is unaffected by process, voltage, and temperature.

[0058] The current bias of the driver circuit is provided by the IBIAS module of the preceding current bias circuit. The switching transistor controlling the high / low level switching of its control signal is a low-voltage device, which can be clamped using a high-voltage device to isolate the low-voltage device from the signal output interface, preventing the switching transistor from facing an overvoltage environment. It also integrates an optional transmitting-end terminating resistor. The driver circuit inputs differential signals VIP and VIN, and outputs high-speed differential signals VOP and VON. Example

[0059] like Figure 2 The figure shows a schematic diagram of a current-mode driven transmitting circuit.

[0060] This embodiment is a schematic diagram of the structure when the present invention is applied to a DC-coupled system.

[0061] In the voltage bias circuit, the reference voltage Vref is connected to the inverting input of amplifier AMP1. The non-inverting input of AMP1 is connected to the second terminal of resistor R1, and also to the drain of NMOS transistor NM0. The output of the amplifier is connected to the gate of NM0, and the source of NM0 is grounded. The first terminal of resistor R1 is connected to the second terminal of adjustable resistor R2, and also to the inverting input of amplifier AMP2. The first terminal of adjustable resistor R2 is connected to the power supply VCC. The output of the voltage bias circuit is led out from the connection line between resistor R1 and adjustable resistor R2. The input reference voltage Vref generates a voltage VR2 with the same amplitude as the output signal. For example, if VCC voltage is 3.3V and the required signal amplitude is 400mV, then VR2 is 2.9V. By adjusting the adjustable resistor R2, VR2 can be adjusted, thereby indirectly adjusting the amplitude of the output signal.

[0062] In the current bias circuit, the negative input terminal of amplifier AMP2 is the input terminal of the current bias circuit. The positive input terminal of amplifier AMP2 is connected to one end of resistor array RES0 and also to the drain of NMOS transistor NM1. The output terminal of amplifier AMP2 is connected to the gate of NMOS transistor NM3 and also to the output terminal of the current bias circuit. The first terminal of resistor array RES0 is connected to the power supply VCC, and its resistance is in an N:1 ratio with the resistance values ​​of resistor arrays RES1 and RES2 in the drive circuit. The gate of NMOS transistor NM1 is connected to an external bias voltage VBH, and its source is connected to the drain of NMOS transistor NM2. The width of NM1 is in a 1:N ratio to that of NMOS transistors NM4 and NM7, and they have the same channel length. The gate of NMOS transistor NM2 is connected to a low-voltage power supply VDD, and its source is connected to the drain of NMOS transistor NM3. The substrate is grounded. The width of NMOS transistor NM2 is in a 1:N ratio to that of NMOS transistors NM5 and NM8, and they have the same channel length. The source and substrate of NMOS transistor NM3 are grounded, and its width is in a 1:N ratio to that of NMOS transistors NM6 and NM9, and they have the same channel length. The source of NMOS transistor NM3 is grounded. The function of NMOS transistor NM1 is to protect NMOS transistor NM2, ensuring that its drain voltage remains within a safe range.

[0063] The current biasing circuit generates a corresponding bias current flowing through NMOS transistor NM3 via the input voltage VR2. Since the width of NMOS transistor NM3 is in a 1:N ratio to that of NMOS transistors NM6 and NM9, and their gate voltages and channel lengths are equal, a proportional current will flow through NMOS transistors NM6 and NM9. Compared to a conventional current mirror, because the drain-source voltage of NMOS transistor NM3 is strictly equal to that of NMOS transistors NM6 and NM9, the channel length modulation effect is consistent, resulting in a highly accurate mirrored current that is unaffected by process technology, voltage, or temperature.

[0064] In the drive circuit, the first terminal of switch SW1 is connected to the power supply VCC, and the second terminal is connected to the drain of NMOS transistor NM4 after being connected in series with resistor array RES1. Switch SW2 is exactly the same as SW1, with its first terminal connected to VCC and its second terminal connected to the drain of NMOS transistor NM7 after being connected in series with resistor array RES2. The function of NMOS transistors NM4 and NM7 is to protect NMOS transistors NM5 and NM8, and PMOS transistors PM1 and PM2, ensuring that their drain voltages are always within a safe range.

[0065] The gate of NMOS transistor NM4 is connected to an external bias voltage VBH, and its source is connected to the drain of NMOS transistor NM5 and the drain of PMOS transistor PM1. The gate of NMOS transistor NM7 is connected to an external bias voltage VBH, and its source is connected to the drain of NMOS transistor NM8 and the drain of PMOS transistor PM2. NMOS transistors NM4 and NMOS transistor NM7 have the same dimensions.

[0066] The gate of NMOS transistor NM5 is connected to the gate of PM1 and the output of buffer Buffer1. The source of NMOS transistor NM5 is connected to the drain of low-voltage NMOS transistors NM6 and NM9, and also to the source of NMOS transistor NM8. The source and substrate of PMOS transistor PM1 are connected to the power supply VDD.

[0067] The gate of NMOS transistor NM8 is connected to the output of buffer Buffer2 and the gate of low-voltage PMOS transistor PM2. Buffer1 is identical to Buffer2. The substrate of NMOS transistor NM8 is grounded. The dimensions of NMOS transistor NM8 are identical to those of NMOS transistor NM5. The source and substrate of PMOS transistor PM2 are connected to VDD. PMOS transistor PM2 is identical in dimensions to PMOS transistor PM1. Its function is to improve the rise time of the output signal, adjust the matching of the rise and fall times of the output signal, and improve the crossover point of the differential output signal pair. The source and substrate of NMOS transistor NM6 are grounded, and its gate is connected to the input of the drive circuit. The source and substrate of NMOS transistor NM9 are grounded. NMOS transistor NM9 is identical in dimensions to NMOS transistor NM6. The gate of NMOS transistor NM9 is connected to the common terminal of single-pole double-throw switch SW3. The first selection terminal of switch SW3 is connected to the input of the drive circuit, and the second selection terminal is connected to ground.

[0068] The input terminal of buffer Buffer1 is connected to the positive terminal VIP of the input differential signal, and the input terminal of buffer Buffer2 is connected to the negative terminal VIN of the input differential signal; the inverted output terminal VON is led out from the connection line between NMOS transistor NM4 and resistor array RES1, and the positive output terminal VOP is led out from the connection line between NMOS transistor NM7 and resistor array RES2. Example

[0069] like Figure 3 The figure shows a schematic diagram of a current-mode driven transmitting circuit.

[0070] This embodiment is a schematic diagram of the structure of the present invention applied to an AC coupling system. In an AC coupling system, due to the presence of a DC blocking capacitor between the transmitting and receiving ends, a terminating resistor is required at the transmitting end; otherwise, the transmitting end cannot establish a DC operating point and thus cannot transmit signals correctly. Therefore, this embodiment removes switches SW1, SW2, and SW3, and to save power, replaces the high-voltage power supply with a low-voltage power supply, also removing high-voltage clamping transistors NM1, NM4, and NM7. In the current bias circuit, NMOS transistor NM2 is directly connected to the resistor array RES0 and the positive input terminal of amplifier AMP2. In the driving circuit, the drain of NMOS transistor NM5 and the drain of PMOS transistor PM1 are directly connected to the resistor array RES1; the drain of NMOS transistor NM8 and the drain of PMOS transistor PM2 are directly connected to the resistor array RES2. The inverting output terminal VON is connected to the connection line between the resistor array RES1 and NMOS transistors NM5 and PM1, and the positive output terminal VOP is connected to the connection line between the resistor array RES2 and NMOS transistors NM8 and PM2. After switching SW3 is turned off, the gate of NMOS transistor NM9 is connected to the input terminal of the drive circuit, and the source is grounded. Example

[0071] like Figure 4 The figure shows a schematic diagram of a resistor array in a current-mode driven transmitter circuit.

[0072] Figure 4 a represents the resistor array RES0, which consists of resistor R0 and PMOS transistor PMr0. The drain of PMOS transistor PMr0 is connected to the first terminal of resistor R0, and its gate is grounded. The source of PMr0 serves as the first connection terminal of resistor array RES0. The other terminal of resistor R0 serves as the second connection terminal of resistor array RES0.

[0073] Figure 4 b represents resistor arrays RES1 and RES2, each composed of n resistors R11 to R1n and n PMOS transistors PMr11 to PMr1n. Resistors R0, R11, and R12 to R1n all have the same resistance value. The drains of the n PMOS transistors PMr11 to PMr1n are connected to one end of each of the n resistors R11 to R1n. The gates of the n PMOS transistors PMr11 to PMr1n are connected in parallel and then connected to the resistance control signal TR_SELB. The sources of the n PMOS transistors PMr11 to PMr1n are connected in parallel, forming the first connection terminal of the resistor array. The other ends of the n resistors R11 to R1n are connected in parallel, serving as the second connection terminal of the resistor array. By sending the n-bit control signal TR_SELB, the conduction or cutoff of the PMOS transistors PMr11 to PMr1n in the resistor array can be selected, but the resistance values ​​of resistor arrays RES1 and RES2 remain constant throughout the resistance changes. Example

[0074] like Figure 5 The diagram shows a schematic of the switch SW3 in a current-mode driven transmitting circuit.

[0075] The single-pole double-throw switch SW3 consists of a transmission gate TG, an inverter INV, and an NMOS transistor NM10.

[0076] The input terminal of the transmission gate TG is the common terminal of the switch SW3 and is connected to the drain of the NMOS transistor NM10; the output terminal of the transmission gate TG is the first selection terminal of the switch SW3.

[0077] The high-level enable terminal of the transmission gate TG is connected to the control signal TR_SEL and to the input terminal of the inverter INV; the output terminal of the inverter INV is connected to the low-level enable terminal of the transmission gate TG and to the gate of the NMOS transistor NM10; the source terminal of the NMOS transistor NM10 is the second selection terminal of the switch SW3 and is connected to ground.

[0078] TR_SEL is the selection signal for a single-pole double-throw switch. When TR_SEL is at a logic high level, the output and input terminals of the transmission gate TG are connected, and the NMOS transistor NM10 is turned off, that is, the common terminal and the first selection terminal of switch SW3 are connected.

[0079] When TR_SEL is at a logic low level, the transmission gate TG is turned off, and the NMOS transistor NM10 is turned on, that is, the common terminal and the second selection terminal of switch SW3 are turned on.

[0080] In summary, the current-mode driven transmitter circuit proposed in this invention generates the required output signal amplitude through a precise reference voltage Vref. Simultaneously, a specially designed current mirror method provides the output stage with a precise bias current unaffected by process, voltage, or temperature, thereby ensuring stable and controllable output signal amplitude. The use of low-voltage devices for switching transistors to control the output signal logic improves the driver's operating speed. Furthermore, implementing the pre-driver stage and parallel-to-serial conversion logic circuits within the low-voltage domain saves area and power consumption, and effectively avoids the disruption of high-voltage power integrity caused by switching noise generated by high-voltage domain digital logic.

Claims

1. A current-mode driven transmitting circuit, characterized in that, Includes voltage bias circuit, current bias circuit and drive circuit; The voltage biasing circuit is used to generate an adjustable amplitude voltage VR2 by means of an input reference voltage Vref. The adjustable amplitude voltage VR2 is equal to the output voltage amplitude of the current-mode driven transmitting circuit. The current bias circuit and the voltage bias circuit are connected to generate a bias current, which generates a proportional mirror current in the drive circuit. The driving circuit is connected to the current bias circuit to receive differential signals and output differential signals. The driving circuit includes resistor array RES1, resistor array RES2, NMOS transistors NM5, NMOS transistors NM6, NMOS transistors NM8, NMOS transistors NM9, PMOS transistors PM1, PMOS transistors PM2, first buffer Buffer1, and second buffer Buffer2; The gate of the NMOS transistor NM6 is connected to the input terminal of the driving circuit, and the gate of the NMOS transistor NM9 is connected to the input terminal of the driving circuit. The source of NMOS transistor NM6 is grounded, and the source of NMOS transistor NM9 is grounded; The drain of NMOS transistor NM6 is connected to the drain of NMOS transistor NM9; The source of NMOS transistor NM5 is connected to the drain of NMOS transistor NM6; the source of NMOS transistor NM8 is connected to the drain of NMOS transistor NM9; and the source of NMOS transistor NM5 is connected to the source of NMOS transistor NM8. The first input signal VIP is connected to the gate of the NMOS transistor NM5 via the first buffer Buffer1; the second input signal VIN is connected to the gate of the NMOS transistor NM8 via the second buffer Buffer2. The gate of the PMOS transistor PM1 is connected to the gate of the NMOS transistor NM5; the drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM5; the source of the PMOS transistor PM1 is connected to the power supply VDD. The gate of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM8; the drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM8; the source of the PMOS transistor PM2 is connected to the power supply VDD. The drain of the NMOS transistor NM5 is connected to one end of the resistor array RES1, and the other end of the resistor array RES1 is connected to the power supply VCC. The first output terminal VON of the current-mode driven transmitter circuit is connected between the drain of the NMOS transistor NM5 and the resistor array RES1. The drain of the NMOS transistor NM8 is connected to one end of the resistor array RES2, and the other end of the resistor array RES2 is connected to the power supply VCC. The second output terminal VOP of the current-mode driven transmitter circuit is connected between the drain of the NMOS transistor NM8 and the resistor array RES2.

2. The current-mode driven transmitting circuit according to claim 1, characterized in that, The current bias circuit includes a first resistor array, and the driving circuit includes a second resistor array and a third resistor array; the resistance values ​​of the second resistor array and the third resistor array are equal; the ratio of the resistance value of the first resistor array to the resistance values ​​of the second and third resistor arrays is n:1, and the ratio is adjustable.

3. The current-mode driven transmitting circuit according to claim 2, characterized in that, The second resistor array and the third resistor array are resistor arrays with adjustable resistance values; when the resistance values ​​of the second resistor array and the third resistor array change, the resistance values ​​of the second resistor array and the third resistor array are always equal.

4. The current-mode driven transmitting circuit according to claim 1, characterized in that, The voltage bias circuit includes amplifier AMP1, resistor R1, NMOS transistor NM0, and adjustable resistor R2; The reference voltage Vref is connected to the inverting input terminal of the amplifier AMP1. The non-inverting input terminal of the amplifier AMP1 is connected to one end of the resistor R1 and also to the drain of the NMOS transistor NM0. The output terminal of the amplifier AMP1 is connected to the gate of the NMOS transistor NM0, and the source of the NMOS transistor NM0 is grounded. The other end of the resistor R1 is connected to the first end of the adjustable resistor R2, and the first end of the adjustable resistor R2 is connected to the power supply VCC. The output terminal of the voltage bias circuit is connected to the connection line between the resistor R1 and the adjustable resistor R2, and is also connected to the current bias circuit.

5. The current-mode driven transmitting circuit according to claim 1, characterized in that, The current biasing circuit includes amplifier AMP2, resistor array RES0, NMOS transistor NM2, and NMOS transistor NM3; The negative input terminal of amplifier AMP2 is the input terminal of the current bias circuit. The positive input terminal of amplifier AMP2 is connected to one end of resistor array RES0 and also to the drain of NMOS transistor NM2. The other end of RES0 is connected to power supply VCC. The gate of NMOS transistor NM2 is connected to power supply VDD, and the source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM3. The gate of NMOS transistor NM3 is connected to the output terminal of amplifier AMP2. The output terminal of the current bias circuit is connected between the gate of NMOS transistor NM3 and the output terminal of amplifier AMP2. The source of NMOS transistor NM3 is grounded. The output terminal of the current bias circuit is connected to the input terminal of the drive circuit.

6. The current-mode driven transmitting circuit according to claim 5, characterized in that, The current biasing circuit also includes an NMOS transistor NM1; The connection between the drain of the NMOS transistor NM2 and the resistor array RES0 is broken; The gate of the NMOS transistor NM1 is connected to the power supply VBH; the source of the NMOS transistor NM1 and the drain of the NMOS transistor NM2 are connected; the positive input terminal of the amplifier AMP2 is connected to one end of the resistor array RES0, and is also connected to the drain of the NMOS transistor NM1.

7. The current-mode driven transmitting circuit according to claim 1, characterized in that, The driving circuit also includes NMOS transistors NM4 and NMOS transistors NM7, switches SW1, SW2, and SW3; The switch SW3 is a single-pole double-throw switch; The drain of NMOS transistor NM5 is disconnected from resistor array RES1; the drain of NMOS transistor NM8 is disconnected from resistor array RES2. The gate of the NMOS transistor NM4 is connected to the power supply VBH; the source of the NMOS transistor NM4 is connected to the drain of the NMOS transistor NM5; the drain of the NMOS transistor NM4 is connected to one end of the resistor array RES1, and the other end of the resistor array RES1 is connected to the power supply VCC via a switch SW1. The gate of the NMOS transistor NM7 is connected to the power supply VBH; the source of the NMOS transistor NM7 is connected to the drain of the NMOS transistor NM8; the drain of the NMOS transistor NM7 is connected to one end of the resistor array RES2, and the other end of the resistor array RES2 is connected to the power supply VCC via switch SW2. The first output terminal VON of the current-mode driven transmitting circuit is reconnected between the drain of the NMOS transistor NM4 and the resistor array RES1; the second output terminal VOP of the current-mode driven transmitting circuit is connected between the drain of the NMOS transistor NM7 and the resistor array RES2. The connection between the gate of the NMOS transistor NM9 and the first input terminal of the driving circuit is disconnected; the gate of the NMOS transistor NM9 is connected to the common terminal of the switch SW3; the first selection terminal of the SW3 is connected to the first input terminal of the driving circuit; the second selection terminal of the SW3 is connected to ground.

8. The current-mode driven transmitting circuit according to claim 7, characterized in that, The switch SW3 consists of a transmission gate TG, an inverter INV, and an NMOS transistor NM10. The input terminal of the transmission gate TG is the common terminal of the switch SW3 and is connected to the drain of the NMOS transistor NM10. The output terminal of the transmission gate TG is the first selection terminal of the switch SW3; The high-level enable terminal of the transmission gate TG is connected to the control signal TR_SEL and to the input terminal of the inverter INV. The output of the inverter INV is connected to the low-level enable terminal of the transmission gate TG and is connected to the gate of the NMOS transistor NM10. The source terminal of the NMOS transistor NM10 is the second selection terminal of the switch SW3 and is connected to ground.

9. The current-mode driven transmitting circuit according to claim 3, characterized in that, The first resistor array consists of resistor R0 and PMOS transistor PMR0; The drain of the PMOS transistor PMr0 is connected to the first terminal of the resistor R0, the gate of the PMOS transistor PMr0 is grounded, and the source of the PMOS transistor PMr0 serves as the first connection terminal of the first resistor array; the second terminal of the resistor R0 serves as the second connection terminal of the first resistor array. The second and third resistor arrays are composed of n resistors R11 to R1n and n PMOS transistors PMr11 to PMr1n; the drains of the n PMOS transistors PMr11 to PMr1n are respectively connected to the first terminals of the n resistors R11 to R1n; the gates of the n PMOS transistors PMr11 to PMr1n are connected in parallel and then connected to the resistance control signal TR_SELB; the sources of the n PMOS transistors PMr11 to PMr1n are connected in parallel and then form the first connection terminal of the second and third resistor arrays; the second terminals of the n resistors R11 to R1n are connected in parallel and then form the second connection terminal of the second and third resistor arrays.

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