Computer storage device and classification method thereof

Abstract

The invention provides a computer storage device and a classification method thereof. The classification method of the storage device comprises the following steps of: performing a first operation on input data and a plurality of first weights to generate a plurality of first operation results; comparing the first operation results with a threshold value to obtain a comparison result; according to the comparison result, a first part of a plurality of second weights related to a plurality of candidate classifications is read from a storage unit, and a bit length of the second weights is longer than a bit length of the first weight; a second operation is performed on the input data and the first portion of the second weights to generate a plurality of second operation results. According to the second operation results, selecting a plurality of target candidate classifications with the highest product value or the first high product values from the candidate classifications;

Description

Technical Field

[0001] This invention relates to a computer storage device and a method for classifying the same. Background Technology

[0002] Extreme classification is an emerging field in machine learning that involves a massive number of categories. Its rise stems from the widespread adoption of multi-class and multi-label classification tasks. These tasks involve labels that are diverse, detailed, and complex, resulting in a significantly increased number of categories compared to traditional classification tasks. This complexity is particularly prevalent in modern real-world applications such as product search, recommendation systems, language models, and image recognition, which heavily rely on extreme classification to identify the most relevant labels from a vast array of categories. The number of categories or labels in extreme classification continues to grow, sometimes reaching millions or even billions.

[0003] Generally, a neural network for extreme classification will include at least an encoding layer and a final fully-connected layer. The final fully-connected layer can also be called the final classification layer.

[0004] The final classification layer faces increasing challenges in real-world scenarios and next-generation applications. It becomes a performance bottleneck for the overall model, consuming significant resources. This is because computational complexity and memory usage are proportional to the size of the classes, a trend that is growing and expected to continue. Therefore, the final classification layer is becoming a critical performance bottleneck, making it essential to accelerate its operation. The expansion of classes makes data transfer a significant issue, far exceeding the capacity of on-chip memory, and the parameters transferred lack reusability. Adopting a memory-centric approach is crucial to addressing this challenge. Current technology employs a near-data processing technique, processing the final layer close to DRAM, thereby eliminating large data transfers across the system bus. However, due to the limited bit density of main memory, this solution struggles to store the final layer, as the classifier's parameters can reach thousands of gigabytes. Summary of the Invention

[0005] According to a first aspect of the present invention, a classification method for a storage device is provided, comprising: performing a first operation on an input data and a plurality of first weights stored in a computation in memory (CIM) unit of the storage device to generate a plurality of first operation results; comparing the first operation results with a threshold to obtain a comparison result; reading a first portion of a plurality of second weights related to a plurality of candidate classifications from a storage unit of the storage device based on the comparison result, wherein the storage unit stores the second weights, and the bit length of the second weights is longer than the bit length of the first weights; performing a second operation on the input data and the first portion of the second weights to generate a plurality of second operation results; and selecting a plurality of target candidate classifications having the highest or top few high product values ​​from the candidate classifications based on the second operation results.

[0006] According to a second aspect of the invention, a storage device is provided, comprising: an in-memory computing unit storing a plurality of first weights; a storage unit storing a plurality of second weights, wherein the second weights are related to the first weights, and a bit length of the second weight is longer than the bit length of the first weight; a controller coupled to the in-memory computing unit and the storage unit; and a classification accelerator coupled to the in-memory computing unit, the storage unit, and the controller. The in-memory computing unit calculates input data and the first weights to generate a plurality of first operation results; the classification accelerator compares the first operation results with a threshold to obtain a comparison result; based on the comparison result, the controller reads a first portion of the second weights related to a plurality of candidate classifications from the storage unit; the classification accelerator calculates the input data and the first portion of the second weights to generate a plurality of second operation results; and based on the second operation results, the classification accelerator selects a plurality of target candidate classifications from the candidate classifications having the highest or top-ranking product values.

[0007] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0008] Figure 1 A functional block diagram of a solid-state drive (SSD) according to an embodiment of the present invention is shown.

[0009] Figure 2 This diagram shows a flowchart of a limit classification method according to an embodiment of the present invention.

[0010] Figure 3 Show the concept of the impact of the threshold on top-K.

[0011] Figure 4This illustrates a threshold optimization concept according to an embodiment of the present invention.

[0012] Figure 5 A schematic diagram of a threshold adjuster according to an embodiment of the present invention is shown.

[0013] Explanation of reference numerals in the attached figures:

[0014] 100: Solid State Drive (SSD) 110: Computing Unit in Memory

[0015] 120: Storage unit; 130: Flash memory controller

[0016] 140: Data buffer; 150: Classification accelerator

[0017] 160: Dynamic Random Access Memory (DRAM)

[0018] 170: Dynamic Random Access Memory Controller

[0019] 180: Embedded processor 190: Bus

[0020] 152: Comparator; 154: Threshold adjuster

[0021] 156: Computation Unit; 158: Scheduling Unit

[0022] CH1-CH2: Channel IN: Input data

[0023] S210-S250: Steps q1 and q2: Input

[0024] W: Weights o1 and o2: Output

[0025] W(1)-W(N): Sub-weights; 510: Accumulator

[0026] 520: Threshold comparator; 530: Multiplexer Detailed Implementation

[0027] The technical terms used in this specification are based on common terminology in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment of the present invention has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0028] Figure 1A functional block diagram of a solid-state drive (SSD) according to an embodiment of the present invention is shown. The computer storage device of the present invention is described herein using an SSD as an example, but it should be understood that the present invention is not limited thereto, and other types of storage devices can also be applied to the present invention.

[0029] A solid-state drive 100 according to an embodiment of the present invention includes: at least one computing-in-memory (CIM) unit 110, at least one storage unit 120, at least one flash memory controller 130, a data buffer 140, a classification accelerator 150, dynamic random access memory (DRAM) 160, a DRAM controller 170, an embedded processor 180, and a bus 190. Here, the CIM unit 110 and the storage unit 120 are described using three-dimensional NAND flash memory as an example, but the present invention is not limited thereto. The classification accelerator 150 includes: a comparator 152, a threshold adjuster 154, an arithmetic unit 156, and a scheduling unit 158. The scheduling unit 158 ​​can be implemented using a state machine.

[0030] In-memory computing unit 110 is coupled to bus 190. In-memory computing unit 110 includes multiple in-memory computing units (not shown). In-memory computing unit 110 stores multiple approximate mode weights. These approximate mode weights are, for example, full-dimensional weights, but with a smaller number of bits (e.g., but not limited to, 4 bits).

[0031] Storage cell 120 is coupled to bus 190. Storage cell 120 includes multiple storage units (not shown). Storage cell 120 stores multiple full-dimensional floating weights (e.g., 32 bits). For in-memory compute units 110 and storage cell 120 coupled to the same channel (CH1 or CH2), the approximate model weights of in-memory compute unit 110 are one-to-one with the full-dimensional floating weights of storage cell 120. That is, the full-dimensional floating weights of the relevant storage cell 120 are projected into approximate model weight matrices of the same dimension but with lower precision and stored in in-memory compute unit 110. In other words, the approximate model weights of in-memory compute unit 110 are full-dimensional weights with lower precision, while the full-dimensional floating weights of storage cell 120 are full-dimensional weights with higher precision. The number of bits for the approximate model weights of in-memory compute unit 110 is less than that for the full-dimensional floating weights of storage cell 120. In one embodiment of the present invention, the weights stored in the computing unit 110 and the storage unit 120 in the memory have different precisions, but may have the same or different dimensions, which are all within the spirit and scope of the present invention.

[0032] The flash memory controller 130 is coupled to the bus 190. The flash memory controller 130 is used to control the computing unit 110 and the storage unit 120 within the memory.

[0033] Data buffer 140 is coupled to bus 190 to buffer data output from computing unit 110, storage unit 120 or classification accelerator 150 in memory.

[0034] The classification accelerator 150 is used to perform extreme classification. Details of the classification accelerator 150 will be described below.

[0035] Dynamic random access memory 160 is used to store data.

[0036] Dynamic random access memory controller 170 is coupled to dynamic random access memory 160 and bus 190 to control dynamic random access memory 160.

[0037] The embedded processor 180 is coupled to the bus 190.

[0038] The comparator 152, threshold adjuster 154, arithmetic unit 156 and scheduling unit 158 ​​are coupled to each other.

[0039] Comparator 152 compares the calculation results of the in-memory computing unit 110 with a threshold to identify which vectors are above the threshold.

[0040] Threshold adjuster 154 adjusts the threshold of comparator 152.

[0041] The arithmetic unit 156 performs operations on the full-dimensional floating weights of the storage unit 120 and the input data IN. The arithmetic unit 156, for example and not limited to, performs a floating-point 32-bit multiply-accumulate (MAC) operation. When the classification accelerator is used to classify images, the input data IN is, for example, image data. Of course, the invention is not limited to this.

[0042] The scheduling unit 158 ​​sorts the operations of the comparator 152, the threshold adjuster 154, and the arithmetic unit 156.

[0043] Figure 2 This diagram shows a flowchart of a limit classification method according to an embodiment of the present invention. Figure 2 Please match Figure 1 Let's refer to each other's experiences.

[0044] In step S210, the input data IN is input to the computation unit 110 in memory to calculate the MAC operation result of these approximate model weights and the input data IN. The main advantage of step S210 is that it eliminates the need to move the weights to the computation unit, allowing MAC operations to be performed directly and simultaneously within multiple NAND flash memory packages.

[0045] In step S220, the in-memory computing unit 110 transmits the MAC operation result of these approximate model weights and the input data IN to the comparator 152. The comparator 152 compares the MAC operation result with the threshold to filter out MAC operation results below the threshold. That is, in step S220, the comparator uses the threshold to filter irrelevant classifications. If the first MAC operation result of a first approximate model weight is lower than the threshold, then the first classification of the first full-dimensional floating weight related to the first approximate model weight is defined as an irrelevant classification. Conversely, if the second MAC operation result of a second approximate model weight is higher than the threshold, then the second classification of the second full-dimensional floating weight related to the second approximate model weight is defined as a candidate classification.

[0046] In step S230, comparator 152 sends the comparison result back to flash memory controller 130, allowing flash memory controller 130 to omit the weights of irrelevant categories. That is, based on the comparison result, flash memory controller 130 decides to read the full-dimensional floating weights of candidate categories from storage unit 120 and send them to the processing unit 156 of classification accelerator 150, and flash memory controller 130 decides not to read the full-dimensional floating weights of "irrelevant categories" from storage unit 120.

[0047] In step S240, the MAC operation result of the candidate classification is calculated.

[0048] In step S250, based on the MAC operation results of these candidate classifications, the classifications with the highest MAC product values ​​are selected from these candidate classifications (this selection is, for example but not limited to, performed by the embedded processor 180) and used as the final classification.

[0049] Figure 3 Display the concept of the impact of the threshold on the top-K. For example... Figure 3 As shown, inputting inputs q1 and q2 into weight W yields two outputs o1 and o2. Figure 3 It also shows the distribution of outputs o1 and o2. Among them, the MAC product values ​​above the threshold can be considered as related to the top-K (in Figure 3 In this context, top-K is the product of the MAC values ​​of the top few highs (the top K highs).

[0050] If the threshold is low, the top-K values ​​of the small-mean distribution can be preserved. For example, the distribution of output o1 is a small-mean distribution. In one embodiment of the invention, if the same threshold is used for a large-mean distribution as for a small-mean distribution, more candidate categories will be selected, leading to a higher likelihood of false positives. The distribution of output o2 is a large-mean distribution.

[0051] Therefore, in one embodiment of the present invention, the problem of false positives with a large average distribution can be avoided by adjusting the threshold (i.e., optimizing the threshold).

[0052] Figure 4 This illustrates a threshold optimization concept according to an embodiment of the present invention. In one embodiment of the present invention, regarding the opportunity to adjust the threshold, since it is impossible to compute all weight matrices (i.e., the approximate model weights of the computation unit 110 in memory) within one cycle, a single (approximate model) weight (which is a matrix N × L) is divided into N (approximate model) sub-weights (each sub-weight W(1)-W(N) is a matrix of 1 × L). In one embodiment of the present invention, the threshold used next time is adjusted based on the computation result of the previous sub-weight (i.e., the threshold is adjusted iteratively). By (iteratively) adjusting the threshold, the number of classifications passed (n) (i.e., the number of candidate classifications in each operation) multiplied by the number of operations (N) equals the target number k (k is the number of candidate classifications with the highest MAC product value, also called the "number of selected candidate classifications"), that is, N*n=k.

[0053] Figure 5 A schematic diagram of a threshold adjuster 154 according to an embodiment of the present invention is shown. The threshold adjuster 154 includes an accumulator 510, a threshold comparator 520, and a multiplexer 530. The threshold adjuster 154 can iteratively adjust the threshold to optimize it.

[0054] At Figure 5 In this process, comparator 152 compares the calculation result of the memory-in-memory computation unit 110 (which can be represented as an inner product vector, for example, but not limited to 10 bits) with the threshold th[t], and transmits the comparison result to the accumulator 510 of the threshold adjuster 154. The accumulator 510 transmits the accumulated result to the threshold comparator 520. Here, whenever the calculation result of the memory-in-memory computation unit 110 is higher than the threshold th[t], the accumulated result is incremented by 1.

[0055] The threshold comparator 520 compares the accumulated result (i.e., the number of candidate categories above the threshold) with a reference value. The sum of the sums (+ζ) is used to obtain an accumulated comparison result, which is then sent to the multiplexer 530. The parameter “ζ” is used to avoid incorrectly filtering out categories that should remain due to an excessively high threshold after the update.

[0056] When the cumulative comparison result is less than the reference value ( When +ζ), the threshold comparator 520 outputs logic 1 to the multiplexer 530, making the updated threshold th[t+1] = th[t] (i.e., the threshold is not updated); and when the accumulated comparison result is equal to or greater than the reference value ( When the threshold comparator 520 outputs logic 0 to the multiplexer 530, the updated threshold th[t+1] = th[t] + α, where the parameter α is a threshold accumulation parameter, for example, but not limited to, α = 1~1.5. That is, when the accumulated comparison result is equal to or greater than the reference value ( When +ζ), the threshold is added to the threshold accumulation parameter to obtain the updated threshold.

[0057] In one embodiment of the present invention, the classification accelerator 150 and its internal units may be control circuitry or application-specific integrated circuits (ASICs). Alternatively, in other possible embodiments of the present invention, the classification accelerator 150 and its internal units may be implemented, for example, by using a chip, a circuit block within the chip, firmware code, or a circuit board containing several electronic components and wires.

[0058] Furthermore, the present invention is not limited to the threshold update method described above. Other methods or functions that can update the threshold can also be applied to the present invention, and all of these are within the spirit and scope of the present invention.

[0059] One embodiment of this invention proposes an in-memory computing architecture using 3D-NAND flash memory to overcome the problems encountered in existing extreme classification. This embodiment eliminates the bottleneck caused by internal data movement (in the prior art, approximate model parameters need to be moved from DRAM to the classification accelerator, resulting in a large amount of internal data movement), and provides a more accurate approximation algorithm to improve the filtering rate, further reducing overall data transmission.

[0060] Furthermore, one embodiment of the present invention proposes a hardware and software co-design method to improve the performance of extreme classification through data clustering and threshold optimization. Data clustering improves the efficiency of the in-memory computing architecture during execution. Threshold optimization ensures that the expected filtering rate is maintained during different inference processes. Thus, the classification accelerator of the present invention can improve the processing speed of extreme classification and reduce power consumption.

[0061] This invention proposes an architecture capable of processing extreme classification tasks within a computer storage device (e.g., but not limited to SSDs). The invention employs an approximation algorithm to simplify the extreme classification task. The extreme classification process of this invention comprises two stages: low-precision filtering and full-precision computation. Low-precision filtering refers to using a CIM unit to calculate the MAC operation result between the low-precision approximation model weights and the input, and using a comparator to initially filter out irrelevant classifications. Full-precision computation refers to calculating the MAC operation result with high-precision weights (stored in storage unit 120) for these candidate classifications that have passed the low-precision filtering, and selecting the classification with the highest MAC product value from these candidate classifications as the classification result.

[0062] In other words, during the low-precision (LP) filtering stage, the original full-precision matrix is ​​projected onto a lower-precision full-dimensional matrix (stored within CIM cell 110). By computing the low-precision matrix and comparing the results with a threshold, it is determined which full-precision (FP) weight vectors need to be precisely computed during the full-precision computation stage. After the full-precision computation stage is completed, the final prediction results (top-K) can be obtained at the classification layer. These final prediction results are then sent back to the host for subsequent model processing. This method significantly reduces the amount of full-precision vectors transmitted and the need to compute the entire full-precision matrix.

[0063] This invention utilizes 3D-NAND flash memory with computation in memory (CIM) to perform approximate models, achieving a higher filtering rate because the quantized weight matrix (also known as the approximate model) is stored directly in the CIM cell. In this invention, "filtering rate" refers to the proportion of weight vectors discarded while still obtaining the correct first k weight vectors. Therefore, in this invention, the reduced-precision weight matrix does not cause any internal data movement or SSD DRAM capacity issues, and 3D-NAND flash memory is well-suited for datasets ranging from millions to billions in size.

[0064] This invention employs an "approximate screening algorithm." The main idea of ​​this algorithm is to project the original full-precision weight matrix onto a lower-precision matrix, reducing the dimensionality by 75% and compressing the full precision to 4 bits. By calculating the lower-precision matrix and comparing the result with a threshold, it determines which full-precision weight vectors need to be calculated to obtain the final top K predictions in the classification layer. This method significantly reduces the need to compute the entire full-precision matrix, thus alleviating the burden of full-precision computation.

[0065] This invention addresses the shortcomings of existing technologies that result in underutilization of channel bandwidth. After a multiply-accumulate (MAC) operation is completed in memory, a threshold can be used to determine whether a category is a candidate. The distribution of candidate categories represents the distribution of data access. However, in conventional operations, the distribution of these candidate categories in each flash memory channel is uneven, causing transmission to be limited to the flash memory channel with the most candidate categories. Ideally, all candidate categories should be evenly distributed in each flash memory channel to fully utilize channel bandwidth. This uneven distribution can lead to a 30% to 50% decrease in overall end-to-end performance. Therefore, in one embodiment of this invention, weight preprocessing can be performed before storing these approximate model weights in the in-memory computing unit 110 and before storing these full-dimensional floating weights in the storage unit 120 to improve channel balance. Here, weight preprocessing includes, for example, storing weights that may be read together as evenly as possible in different in-memory computing units 110 and different storage units 120 in different channels. In this way, multiple channels can be used to transmit weights simultaneously when reading weights, thereby improving the efficiency of reading weights and enhancing channel balance.

[0066] Furthermore, this invention addresses the shortcomings of existing technologies, such as inappropriate thresholds. Since embodiments of this invention use a threshold to select candidate categories, rather than directly selecting the top 1% of vectors using a sorting circuit, the threshold must be set very precisely to ensure that only the top 1% of vectors are selected. However, in the prior art, the threshold is set to a fixed value, which leads to variations in the number of selected candidate categories across different inference processes because the previous layer latent vectors obtained in each inference process are different. There is no single value suitable for every inference, resulting in suboptimal filtering rates. If the filtering rate is suboptimal, more data needs to be shifted, leading to a decrease in overall performance. Therefore, this invention proposes an online threshold optimization adjustment method to avoid filtering rate fluctuations.

[0067] In summary, this invention proposes an in-memory 3D-NAND flash memory architecture to accelerate extreme classification. This in-memory architecture avoids internal data movement, enabling the execution of approximation algorithms without incurring data transfer costs. By improving the filtering rate through an approximation algorithm designed specifically for CIM 3D-NAND flash memory, this invention further reduces the overall data movement. Therefore, it improves the processing speed of extreme classification and reduces power consumption. This demonstrates the potential of this invention's architecture in handling the complexity of extreme classification in large-scale datasets.

[0068] The foregoing primarily describes the solutions provided in the embodiments of this application from the perspective of extreme classification. It is understood that, to achieve the above-described functions, the classification accelerator includes corresponding hardware structures and / or software modules that perform the functions. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the embodiments described in this specification, this application can be implemented in hardware or in a combination of hardware and computer software. Whether the function is performed by hardware or by hardware driven by computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the functions described in each specific application, but such implementations should not be considered beyond the scope of this application.

[0069] In one embodiment of this application, the classification accelerator can be divided into functional modules based on the aforementioned method examples. For example, it can be divided according to each corresponding function to obtain each functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that in the embodiments of this application, the division into modules is only an example and is a logical functional division. In actual implementation, other division methods can be used. The following description uses an example of dividing according to each corresponding function to obtain each functional module.

[0070] While the invention may describe many specific details, these should not be construed as limiting the scope of the claimed invention, but rather as descriptions of the characteristics of particular embodiments. In this description, certain features described in the context of a single embodiment may also be implemented in combination in that single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, while features may initially be described as functioning in certain combinations, or even initially described as such combinations, in some cases one or more features may be removed from that combination, and the described combination may be for a sub-combination or a variation thereof. Similarly, while operations are depicted in the figures as being performed in a specific order, this should not be construed as requiring these operations to be performed in the specific order or sequence shown, or that all depicted operations must be performed to achieve the desired result.

[0071] Although the above embodiments of the present invention only disclose some examples and implementations, changes, modifications, and enhancements can be made to the examples, implementations, and other implementations based on the disclosed content.

[0072] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for classifying storage devices, comprising: A first operation is performed on an input data and a plurality of first weights stored in an in-memory computation (CIM) unit of the storage device to produce a plurality of first operation results; Compare these first operation results with a threshold to obtain a comparison result; Based on the comparison result, a first portion of multiple second weights related to multiple candidate classifications is read from a storage unit of the storage device, wherein the storage unit stores these second weights, and the bit length of the second weight is longer than the bit length of the first weight. A second operation is performed on the first portion of the input data and these second weights to produce multiple second operation results; as well as Based on these second operation results, select multiple target candidate categories from these candidate categories that have the highest or top few high product values.

2. The method for classifying storage devices according to claim 1, wherein, Based on the comparison result, when the first part of the second weights related to these candidate classifications is read from the storage unit, it is decided not to read a second part of the second weights related to multiple unrelated classifications from the storage unit. If the result of the first calculation for a specific first weight is lower than the threshold, then a category associated with a specific second weight related to the first weight is defined as the unrelated category; and Once the result of the first operation for a particular first weight is higher than the threshold, the category associated with the particular second weight related to the first weight is defined as the candidate category.

3. The method for classifying storage devices according to claim 1 further includes: Divide the first weight into multiple sub-weights; as well as A third operation is performed on the input data and these sub-weights to produce multiple third operation results, and the threshold of a current sub-weight is adjusted based on the third operation result of a previous sub-weight.

4. The method for classifying storage devices according to claim 1, further comprising: The comparison results are summed to obtain a cumulative result; Compare the accumulated result with a reference value to obtain an accumulated comparison result; as well as The threshold is updated based on the accumulated comparison result and a threshold accumulation parameter.

5. The method for classifying storage devices according to claim 4, wherein, Once it is determined that the first operation result of the computing unit in the memory is higher than the threshold, the accumulated result is incremented by 1; Once it is determined that the cumulative comparison result is less than the reference value, the threshold is not updated; as well as Once it is determined that the cumulative comparison result is equal to or greater than the reference value, the threshold is added to the threshold accumulation parameter to obtain the updated threshold.

6. A storage device, comprising: A computational unit within memory stores multiple first weights; A storage unit stores multiple second weights, wherein these second weights are related to the first weights, and the bit length of the second weight is longer than the bit length of the first weight; A controller, coupled to the computing unit and the storage unit within the memory, and A classification accelerator is coupled to the computing unit, the storage unit and the controller within the memory; in, The computational unit within the memory performs calculations on a pair of input data and these first weights to produce multiple first computation results; The classification accelerator compares these first operation results with a threshold to obtain a comparison result; Based on the comparison result, the controller reads a first portion of these second weights related to the multiple candidate classifications from the storage unit; The classification accelerator calculates the input data with the first portion of these second weights to produce multiple second computation results; and Based on these second calculation results, the classification accelerator selects multiple target candidate classifications from these candidate classifications that have the highest or top few high product values.

7. The storage device according to claim 6, wherein, Based on the comparison result, when the controller reads the first portion of the second weights related to these candidate classifications from the storage unit, the controller decides not to read a second portion of the second weights related to multiple unrelated classifications from the storage unit; If the result of the first calculation for a specific first weight is lower than the threshold, then a category associated with a specific second weight related to the first weight is defined as the unrelated category; and Once the result of the first operation for a particular first weight is higher than the threshold, the category associated with the particular second weight related to the first weight is defined as the candidate category.

8. The storage device according to claim 6, wherein, The classification accelerator architecture is as follows: Divide the first weight into multiple sub-weights; and A third operation is performed on the input data and these sub-weights to produce multiple third operation results, and the threshold of a current sub-weight is adjusted based on the third operation result of a previous sub-weight.

9. The storage device according to claim 6, wherein, The classification accelerator architecture is as follows: The comparison results are summed to obtain a cumulative result; Compare the accumulated result with a reference value to obtain an accumulated comparison result; as well as The threshold is updated based on the accumulated comparison result and a threshold accumulation parameter.

10. The storage device according to claim 9, wherein, The classification accelerator architecture is as follows: Once it is determined that the first operation result of the computing unit in the memory is higher than the threshold, the accumulated result is incremented by 1; Once it is determined that the cumulative comparison result is less than the reference value, the threshold is not updated; as well as Once it is determined that the cumulative comparison result is equal to or greater than the reference value, the threshold is added to the threshold accumulation parameter to obtain the updated threshold.

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