Internal performance testing circuit and testing methods for chips

Abstract

This application provides a chip internal performance testing circuit and method. The chip internal performance testing circuit includes: a distributed counter array deployed in the chip's computing block and comprising multiple configurable counters, the counter array being driven by a dedicated clock source independent of the chip's core clock, and extracting event signals from the execution unit within the computing unit via a dedicated hardware monitoring path; a central processing unit including a sampling and packaging module, a data receiving module, and a timestamp generator; a configuration and control module for configuring counter event binding, sampling period, external memory start address, and test start / stop status; and an on-chip interconnect bus for writing data blocks to external memory. The counter array according to this application uses an independent asynchronous clock, fundamentally avoiding mutual interference with core computing resources.

Description

Technical Field

[0001] This application relates to the field of chip design technology, specifically to a chip internal performance testing circuit and testing method. Background Technology

[0002] With the widespread use of high-performance chips such as GPUs, FPGAs, and ASICs in AI training, autonomous driving, and supercomputing, internal chip performance testing (such as the computational efficiency of SM / Block, cache hit rate, and thread scheduling latency) has become a core part of chip design verification. Internal chip performance testing circuits must meet the requirements of "non-interference, high precision, and fine granularity," meaning the testing circuits cannot occupy the chip's core computing resources and can accurately collect nanosecond-level timing data and multi-dimensional event counts.

[0003] Existing chip performance testing circuits can be divided into two categories: interrupt-type testing circuits and non-interrupt-type testing circuits. Interrupt-type testing circuits consist of a centralized counter, a bus arbiter, and a CPU control circuit. The counter shares computing resources with the chip's core computing unit. During testing, the CPU sends an interrupt signal to pause the computing task and start counting. Patent US8144828B2 discloses such a centralized interrupt-type performance counter circuit.

[0004] Non-interruptible test circuits employ a bypass counter design, where the counter and computing unit operate in parallel. However, they lack a distributed architecture, the synchronization circuit uses a fixed clock cycle, and the storage interface relies on on-chip SRAM cache. A typical application is the non-intrusive monitoring circuit for the AMD RDNA3 GPU. The IEEE TCAD 2023 paper "A Non-Intrusive Performance Monitoring Circuit for GPU" also proposed a similar bypass counter design.

[0005] However, existing technologies have several circuit-level defects: First, resource conflicts arise because the counter in the interrupt-type circuit shares ALU and register resources with the SM, leading to a decrease in the core chip performance during testing. Second, clock coupling and synchronization are rigid. The counter clock is usually from the same source as the core clock or is forced to be synchronized, resulting in high coupling. Furthermore, the synchronization circuit uses a fixed clock cycle, which can lead to bus congestion and data loss under high load. Third, there is a bottleneck in the storage interface. The technology relies on on-chip SRAM to cache data, but the SRAM capacity is limited, leading to data overflow and loss in high-bandwidth scenarios. Fourth, configuration flexibility is poor. The event binding of the counter is achieved through hardware programming and cannot be dynamically configured through software, limiting its adaptability to specific chip models.

[0006] Therefore, there is an urgent need for an internal chip test circuit that can solve the above-mentioned defects and meet the requirements of non-interference, high-precision synchronization, dynamic adaptation, high-bandwidth storage and flexible configuration. Summary of the Invention

[0007] In view of this, this application provides a chip internal performance testing circuit and testing method to solve the above-mentioned technical problems in the prior art.

[0008] According to one aspect of this application, a chip internal performance testing circuit is provided, comprising:

[0009] A distributed counter array, deployed in the computing block of the chip and comprising multiple configurable counters, is driven by a dedicated clock source independent of the chip's core clock and extracts event signals from the execution unit within the computing unit via a dedicated hardware monitoring path.

[0010] The central processing unit includes:

[0011] The sampling and packaging module is used to send sampling window synchronization signals to the counter array and receive sampling event signals from the computation block, and to merge test data into data blocks;

[0012] The data receiving module is used to receive counter data from the counter array and send the counter data to the sampling and packaging module;

[0013] A timestamp generator is used to generate timestamps for counter data received from the counter array;

[0014] The configuration and control module is used to configure counter event binding, sampling period, external memory start address, and test start / stop status.

[0015] The on-chip interconnect bus is used to write data blocks to external memory.

[0016] The sampling and packaging module includes a window controller and a first cross-clock domain synchronization compensation module. The window controller generates a sampling window synchronization signal, and the cross-clock domain synchronization compensation module synchronizes the sampling events to the central processing unit through two levels of triggers.

[0017] Furthermore, the on-chip interconnect bus includes a load detection module for calculating the effective period ratio of the AWVALID and / or WVALID signals of the interconnect bus to calculate the bus utilization rate. The sampling and packaging module is configured to adjust the sampling window period according to the bus utilization rate.

[0018] According to a preferred embodiment of this application, the chip is a GPU, FPGA, or ASIC chip.

[0019] According to a preferred embodiment of this application, adjusting the sampling window period based on bus utilization includes extending the next sampling window period if the bus utilization is higher than a first threshold, and shortening the next sampling window period if the bus utilization is lower than a second threshold.

[0020] According to a preferred embodiment of this application, the sampling and packaging module is configured to assign a window ID to each sampling window.

[0021] According to a preferred embodiment of this application, the test data includes a window ID, a reference timestamp, a computation block ID, and counter data in the counter array. The reference timestamp is the timestamp at which the central processing unit receives the first counter data within the time window.

[0022] According to a preferred embodiment of this application, the data receiving module includes a second cross-clock domain synchronization compensation module, which is configured to compensate the receiving time of the counter data based on the frequency ratio between the chip core clock domain and the local clock domain of the computing block, and generate a timestamp through the timestamp generator.

[0023] According to a preferred embodiment of this application, the timestamp generator uses a counter that is from the same source as the chip's core clock to generate timestamps.

[0024] According to a preferred embodiment of this application, the on-chip interconnect bus writes data blocks to external memory through a DDR or PCIe interface module.

[0025] According to a preferred embodiment of this application, each counter in the counter array is bound to a monitored hardware event according to the settings of the configuration and control module.

[0026] According to another aspect of this application, a chip performance testing method is provided, the method being executed by the chip internal performance testing circuit described above, the method comprising:

[0027] The initialization configuration steps include:

[0028] Configure the hardware event bound to each counter in the counter array;

[0029] Set the sampling window period and the starting address of the external memory;

[0030] The dynamic sampling and asynchronous counting steps include:

[0031] The central processing unit sends a sampling window synchronization signal to the counter array based on the sampling window period;

[0032] The chip's computation blocks perform calculations, and the counter array counts the bound hardware events;

[0033] The load detection module detects the bus utilization rate. If the bus utilization rate is higher than the first threshold, the next sampling window period is extended. If the bus utilization rate is lower than the second threshold, the next sampling window period is shortened.

[0034] The latching, synchronization, and data transmission steps include:

[0035] At the end of the current sampling window, the counter array latches the counter data in parallel;

[0036] The central processing unit receives counter data via the on-chip bus;

[0037] The second cross-clock domain synchronization compensation module is configured to compensate the receiving time of the counter data according to the frequency ratio between the chip core clock domain and the local clock domain of the computing block, and generate a timestamp through the timestamp generator.

[0038] Data packaging and storage steps include:

[0039] The central processing unit merges the window ID, base timestamp, calculation block ID, and counter data into a data block;

[0040] Data blocks are written to external memory via the on-chip interconnect bus.

[0041] The chip internal performance testing circuit and testing method according to this application can achieve the following technical effects:

[0042] 1. Architecture-level clock decoupling: The counters of the computing blocks use independent asynchronous clocks, which avoids mutual interference with core computing resources from the root.

[0043] 2. High-precision asynchronous synchronization mechanism: Through the cross-clock domain synchronization compensation module, the problem of high-precision time alignment of multi-source asynchronous data is solved while allowing clock independence.

[0044] 3. Load-aware dynamic synchronization strategy: The synchronization cycle can be dynamically adjusted according to the bus load, combining flexibility and stability.

[0045] 4. High-bandwidth direct-write architecture: Abandoning the traditional SRAM cache, it adopts a direct-write external storage solution to break through the storage bandwidth bottleneck.

[0046] 5. Fully configurable software: It enables full-process software configuration from event selection and sampling frequency to storage management, and has strong versatility. Attached Figure Description

[0047] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application, but do not constitute a limitation on the technical solutions of this application.

[0048] Figure 1 A structural block diagram of the chip internal performance testing circuit provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0049] Various exemplary embodiments of this application will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are not intended to limit the scope of this application or its application or use. This application can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the application thorough and complete, and to fully express the scope of this application to those skilled in the art.

[0050] Unless explicitly stated otherwise, an element may be one or more unless otherwise specified. The terms “multiple / several” mean two or more, the term “based on” should be interpreted as “at least partially based on,” and the terms “and / or” and “at least one of…” cover any one of the listed items and all possible combinations thereof. Furthermore, expressions such as “first,” “second,” etc., are for descriptive purposes only and do not indicate or imply their relative importance or implicitly specify the number of technical features indicated.

[0051] Figure 1 A structural block diagram of the chip internal performance testing circuit provided in an exemplary embodiment of this application is shown.

[0052] like Figure 1 The chip internal performance testing circuit provided in the exemplary embodiments of this application includes a distributed counter array, a central processing unit, a configuration and control module, and an on-chip interconnect bus.

[0053] The distributed counter array comprises multiple configurable counters, enabling non-interruptible fine-grained counting under independent clocks. An independent event counter array is integrated into each compute block (Block or SM) of the GPU. Each array contains, for example, eight configurable 32-bit counters. The key innovation lies in the fact that each counter array is driven by a dedicated clock source with a fixed frequency (e.g., a 100MHz clock domain) independent of the GPU core clock, achieving physical decoupling from the core compute clock. In other embodiments of this application, the number of counters within each block can be expanded from eight to sixteen or thirty-two, and a higher level of multiplexers can be added to support the synchronous monitoring of more types of events, making it suitable for more complex multi-dimensional performance profiling scenarios.

[0054] The configuration and control module dynamically binds each counter to monitored hardware events (such as texture sampling and cache misses). Event signals are extracted directly from the execution units (such as texture units and cache controllers) within the compute block via a dedicated hardware monitoring path, without occupying any compute block resources (ALU, registers, etc.).

[0055] When the counter array receives a "latch" signal from the central processing unit, the latching logic of the counter array works in parallel with the execution pipeline of the computation block, instantly latching the current count value without pausing any computation tasks. The latched data is temporarily stored in a local buffer.

[0056] The central processing unit coordinates asynchronous data and achieves high-precision synchronization. It includes a sampling and packaging module, which sends sampling window synchronization signals to the counter array and receives sampling event signals from the computation block, and merges test data into data blocks; a data receiving module, which receives counter data from the counter array and sends the counter data to the sampling and packaging module; and a timestamp generator, which generates timestamps for the counter data received from the counter array.

[0057] The sampling and packaging module includes a dynamic window controller for adaptive sampling scheduling, specifically including the following functions.

[0058] Cycle Generation and Load Detection: Based on a stable clock reference, an initial sampling window (Window) cycle signal is generated. The on-chip interconnect bus integrates a bus load detection circuit, which monitors the effective cycle percentage of signals such as AWVALID and / or WVALID on the on-chip interconnect bus (AXI4 bus) in real time and calculates the bus utilization. When the utilization rate is higher than a first threshold (e.g., 80%), the window controller automatically extends the next Window cycle (e.g., doubles it); when the utilization rate is lower than a second threshold (e.g., 30%), the window controller automatically shortens the cycle, achieving dynamic adaptation.

[0059] Synchronization Marking and Signal Distribution: The window controller assigns a unique 32-bit synchronization identifier (Window ID) to each Window. The Window startup signal and Window ID need to be processed by the cross-clock domain synchronization compensation module before being distributed to the asynchronous counter array of each block to ensure reliable signal transmission between asynchronous clock domains.

[0060] The sampling and packaging module also includes a cross-clock domain synchronization compensation module for high-precision alignment. This module employs a hybrid mechanism of "dual-flip-flop synchronization chain + digital frequency mapper." First, events from different computation blocks are synchronized to the central processing unit via two levels of flip-flops. Furthermore, the cross-clock domain synchronization compensation module uses a digital frequency mapper to timestamp the synchronized events based on the known frequency ratio between the core clock domain and the local clock domain of each block, ultimately controlling the time alignment error of the data latched by events in different blocks within a manageable range. For example, the chip's core clock domain has a frequency of 1GHz, used to drive the central processing unit (including the timestamp generator); the computation block (Block0) local clock domain has an independent dedicated clock with a frequency of 100MHz, and there are 10 pipelines from block0 to the central processing unit; the computation block (Block1) local clock domain has an independent dedicated clock with a frequency of 200MHz, and there are 20 pipelines from block1 to the central processing unit. When the central processing unit receives an event from block0, the recorded timestamp is 2000. However, the deduced time of this event should be 2000 - 10 (number of pipelines) × 1000M / 100M - 2 (level 2 synchronization time) = 1898. When the central processing unit receives an event from block1, the recorded timestamp is 3000. However, the deduced time of this event should be 3000 - 20 (number of pipelines) × 1000M / 200M - 2 (level 2 synchronization time) = 2898.

[0061] In other embodiments of this application, the above-mentioned hybrid mechanism of "dual trigger synchronization chain + digital frequency mapper" can be replaced by the scheme of "Gray code counter synchronization + digital phase-locked loop (DPLL) auxiliary phase calibration".

[0062] The sampling and packaging module is also configured to package the data of each received block (including Window ID, base timestamp, Block ID, and 8 counter data) into a standard 64-byte aligned data packet and add a CRC16 checksum. Once all block data for the same Window has been collected, it is merged into a single large block (e.g., 16 blocks merged into 1KB) to improve subsequent storage efficiency.

[0063] The timestamp generator of the central processing unit uses an independent high-precision counter derived from the chip's core clock. When the count data of the first block within a window arrives at the central processing unit, the current timestamp is immediately latched as the base timestamp for that window. All subsequent block data arriving within the same window are associated with this base timestamp, ensuring global time consistency.

[0064] In other embodiments of this application, an on-chip ring buffer and triggering logic can be added to the circuit to support triggered sampling capture based on specific events (such as cache misses exceeding a threshold), which facilitates debugging of occasional performance problems.

[0065] The on-chip interconnect bus is used to write data blocks to external memory. The on-chip interconnect bus can directly write data from the central processing unit to external mass storage via DDR or PCIe direct write interfaces, completely bypassing the on-chip SRAM cache and eliminating capacity bottlenecks. The on-chip interconnect bus also has a built-in address generator that allocates storage addresses consecutively according to the "Window ID + Block ID" rule. Combined with the AXI4 protocol's Burst Transfer mode, packaged large data blocks are written continuously in a high-bandwidth, high-efficiency manner. In other embodiments of this application, a PCIe endpoint controller circuit can be integrated in parallel on top of the DDR direct write interface, enabling performance data to be streamed to host memory or a remote server in real time, achieving "online" analysis and monitoring.

[0066] The configuration and control module provides a flexible, software-configurable interface for configuring counter event bindings, sampling periods, external memory start addresses, and test start / stop states. Specifically, the module provides a standard AXI Lite slave interface for access by the upper-layer driver software. The upper-layer driver software can dynamically configure: the event types bound to each counter, the initial window cycle length, the DDR memory start address, and test start / stop. Configuration information is distributed to relevant modules in real-time via register mapping, enabling "soft" definition of the test strategy without hardware modification.

[0067] The test circuit according to the embodiments of this application can be packaged as an independent performance monitoring IP core, and can be deployed in a chiplet system through a consistency bus (such as CXL) interface to perform unified performance observation on multiple computing chips.

[0068] Exemplary embodiments of this application also relate to a chip performance testing method. The following uses a performance test of a GPU chip running a 3D rendering application as an example to describe the chip performance testing method according to embodiments of this application.

[0069] Step 1: Initialize Configuration

[0070] The test program configures the module through the AXI Lite interface: sets counter 0 to monitor texture sampling, counter 1 to monitor L2 cache misses, sets the event to the event that SM starts executing; sets the initial window cycle to 2048 core clock cycles; sets the DDR storage start address to 0x8000_0000; and sends the start command.

[0071] Step 2: Dynamic Sampling and Asynchronous Counting

[0072] The dynamic Window controller generates a Window startup signal (assignment ID=0x0001) with an initial interval of 2048 cycles, which is then distributed to the counter array of each block via the cross-clock domain synchronization module.

[0073] The GPU's SM (Streaming Manager) begins rendering. Each block's counter array, driven by an independent GPU clock, counts bound events through a dedicated path, operating in complete parallel with the SM's rendering computation.

[0074] The bus load detection sub-circuit performs real-time calculations and finds that the initial bus utilization is only 20% (<30%). Based on this, the dynamic window controller dynamically shortens the cycle of the next window (ID=0x0002) to 1024 core clock cycles to improve the sampling rate (it can also be configured to a fixed sampling rate that does not change with bandwidth).

[0075] Step 3: Latching, Synchronization, and Data Transmission

[0076] When Window 0x0001 ends, latch signals arrive at each Block. Each counter array latches the current value in parallel (e.g., Block0: texture sampling = 150 times, cache misses = 35 times).

[0077] The latched data is transmitted to the central processing unit via the on-chip bus.

[0078] The cross-clock domain synchronization compensation module performs compensation calculations for the arrival time of event data from different clock domains. When the first event data arrives, the timestamp generator records the core clock count value T=0x1234_5678 at that moment, as the base timestamp for Window 0x0001. Then, based on the different clock frequencies and pipeline delays, it calculates the precise time of this event. When a non-event arrives, this counter is stored and prepared for packaging.

[0079] Step 4: Data Packaging and High-Bandwidth Storage

[0080] The data packaging unit attaches a Window ID (0x0001), a base timestamp (T), and a Block ID to the data of each Block, and packages them into a 64B data packet.

[0081] After collecting all the block data of the window, merge them into a 1KB data block.

[0082] The DDR direct write interface module initiates an AXI4 burst write transaction, directly and continuously writing the 1KB data block to the region starting at DDR address 0x8000_0000. The write process is efficient and non-blocking.

[0083] The following is an example structure of a synthesized data block according to an embodiment of this application.

[0084]

[0085] Step 5: Dynamic Adaptation and Continuous Testing

[0086] As rendering progresses into complex scenes, bus utilization rises to 85% (>80%). The dynamic Window controller automatically extends subsequent Window cycles to 4096 core clock cycles to prevent test data transmission from exacerbating bus congestion.

[0087] The above process continues until the test end command is issued, and the circuit enters an idle state after completing the last batch of data storage.

[0088] Step 6: Offline Analysis

[0089] After the test is completed, the analysis software reads data from DDR. Using the Window ID and timestamp, the performance profile of all blocks within each time slice can be accurately reconstructed, enabling performance bottleneck location and trend analysis.

[0090] The foregoing description and illustrations of the present invention are not restrictive. It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the scope of protection claimed by the present invention is defined by the claims rather than the foregoing description, and all variations falling within the meaning and scope of equivalents of the claims are covered within the scope of protection of the present invention.

Claims

1. A chip internal performance testing circuit, characterized in that, Comprise: a distributed counter array deployed in a compute block of a chip and comprising a plurality of configurable counters, the counter array being driven by a dedicated clock source independent of a chip core clock, and bypassing event signals from execution units within the compute unit through a dedicated hardware monitoring channel; a central processing unit comprising: a sampling and packing module for sending a sampling window synchronization signal to the counter array and receiving sampling event signals from the compute block, and merging test data into data blocks; a data receiving module for receiving counter data from the counter array and sending the counter data to the sampling and packing module; a timestamp generator for generating timestamps for the counter data received from the counter array; a configuration and control module for configuring counter event bindings, sampling periods, external memory start addresses, and test start-stop states; an on-chip interconnect bus for writing the data blocks to an external memory, wherein the sampling and packing module comprises a window controller for generating the sampling window synchronization signal and a first cross-clock-domain synchronization compensation module for synchronizing the sampling events to the central processing unit through two stages of flip-flops, and wherein the on-chip interconnect bus comprises a load detection module for calculating a total bus utilization by calculating a ratio of active periods of AWVALID and / or WVALID signals of the interconnect bus, and the sampling and packing module is configured to adjust the sampling window period according to the bus utilization.

2. The on-chip performance test circuit of claim 1, wherein, The chip is a GPU, FPGA, or ASIC chip.

3. The on-chip performance test circuit of claim 1, wherein, Adjusting the sampling window period according to the bus utilization comprises lengthening the next sampling window period if the bus utilization is higher than a first threshold, and shortening the next sampling window period if the bus utilization is lower than a second threshold.

4. The on-chip performance test circuit of claim 1, wherein, The sampling and packing module is configured to assign a window ID for each sampling window.

5. The on-chip performance test circuit of claim 4, wherein, The test data comprises the window ID, a reference timestamp of the central processing unit receiving the first counter data within the time window, a compute block ID, and counter data in the counter array.

6. The on-chip performance test circuit of claim 1, wherein, The data receiving module comprises a second cross-clock-domain synchronization compensation module configured to compensate for the reception time of the counter data according to a frequency ratio of a chip core clock domain and a compute block local clock domain, and generate timestamps through the timestamp generator.

7. The on-chip performance test circuit of claim 6, wherein, The timestamp generator generates timestamps using a counter that is derived from the chip core clock.

8. The on-chip performance test circuit of claim 1, wherein, The on-chip interconnect bus writes the data blocks to the external memory through a DDR or PCIe interface module.

9. The on-chip performance test circuit of claim 1, wherein, Each counter in the counter array is bound to a monitored hardware event according to settings of the configuration and control module.

10. A method of testing the performance of a chip, characterized by The method is performed by the chip internal performance test circuit of any one of claims 1-9, and the method comprises: an initialization configuration step comprising: setting a hardware event bound to each counter in the counter array; setting a sampling window period and a start address of an external memory; a dynamic sampling and asynchronous counting step comprising: the central processing unit sending a sampling window synchronization signal to the counter array based on the sampling window period; The computing blocks of the chip perform the computation, and the counter array counts the bound hardware events; The load detection module detects the bus utilization rate, and if the bus utilization rate is higher than a first threshold, the next sampling window period is extended, and if the bus utilization rate is lower than a second threshold, the next sampling window period is shortened; The latch, synchronization and data transmission step includes: At the end of the current sampling window, the counter array latches the counter data in parallel; The central processing unit receives the counter data through the on-chip bus; The second cross-clock-domain synchronization compensation module is configured to compensate the receiving time of the counter data according to the frequency ratio of the chip core clock domain and the computing block local clock domain, and generate a timestamp through the timestamp generator; The data packaging and storage step includes: The central processing unit merges the window ID, the reference timestamp, the computing block ID and the counter data into a data block; The data block is written into the external memory through the on-chip interconnection bus.

Images