Error amplifier for preventing dc-dc start-up overshoot

Abstract

This invention discloses an error amplifier for preventing DC-DC converter startup overshoot, belonging to the field of electronic circuit technology. It includes a main amplifier circuit and a soft-start circuit. The main amplifier circuit compares the feedback voltage Vfb with a first reference voltage Vref1, and the soft-start circuit stabilizes the voltage rise during startup. This invention optimizes power-on overshoot by connecting the soft-start voltage VSS to the substrate of the first P-type MOSFET PM1 in the main amplifier circuit and the gate of the ninth P-type MOSFET PM9 in the soft-start circuit, respectively. The solution is simple and significantly saves chip area and power consumption.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to an error amplifier for preventing DC-DC start-up overshoot. Background Technology

[0002] DC DC circuit, i.e., direct current A DC-DC converter is an electronic device that converts a fixed DC voltage to a different DC voltage level. This type of converter is widely used in various electronic systems and devices that require power supplies at different voltage levels. A DC / DC converter typically connects a soft-start module (integrator) to the output of the error amplifier. During soft-start, this module integrates the voltage difference between the input terminals of the error amplifier (i.e., the voltage difference between the reference voltage and the output voltage of the DC / DC converter), accumulating this voltage difference and controlling the amplitude of the amplified voltage input to the pulse width modulation generator. After soft-start (i.e., when the DC / DC converter is operating normally), by accumulating this voltage difference, the error between the output voltage of the DC / DC converter (i.e., the output voltage of the DC / DC converter circuit) and the target voltage is minimized.

[0003] During power-up, a DC / DC converter needs to charge its output capacitor (which determines the output voltage of the DC / DC converter, i.e., the output voltage of the DC / DC conversion circuit). This process requires soft-start to avoid excessive charging current or output voltage overshoot at the end of charging, which could exceed the load's voltage tolerance and damage the load. Soft-start is typically achieved by generating a linearly rising voltage internally within the DC / DC converter. A feedback circuit then controls the output voltage to rise at the same slope to the target voltage, thus achieving soft-start and preventing current overshoot.

[0004] Because the output capacitor and startup load vary significantly depending on the application scenario, a single soft-start voltage slope can lead to overshoot risk in extreme cases. During soft-start, if the output capacitor is large, or if the load current is also large, the charging speed of the output capacitor may lag behind the soft-start voltage slope (i.e., the soft-start voltage rise rate), resulting in excessively high output or saturation of the integrator circuit. When the soft-start ends (i.e., the output voltage reaches the target voltage), the integrator circuit needs time to recover from saturation. During this process, excessive energy in the inductor will discharge to the output terminal, causing output voltage overshoot. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a novel error amplifier architecture that can achieve soft-start effect without adding a soft-start module, and can prevent overshoot of the DC-DC circuit. The solution is simple and significantly saves chip area and power consumption.

[0006] To achieve the above objectives, the present invention provides an error amplifier for preventing DC-DC start-up overshoot, comprising: a main amplifier circuit and a soft-start circuit;

[0007] The main amplifier circuit is used to compare the feedback voltage Vfb with the first reference voltage Vref1, and includes a first P-type MOSFET PM1, a second P-type MOSFET PM2, a third P-type MOSFET PM3, a fourth P-type MOSFET PM4, a fifth P-type MOSFET PM5, a first N-type MOSFET NM1, a second N-type MOSFET NM2, a third N-type MOSFET NM3, and a fourth N-type MOSFET NM4; the soft-start circuit is used to stabilize the rising voltage during startup, and includes a sixth P-type MOSFET PM6, a seventh P-type MOSFET PM7, an eighth P-type MOSFET PM8, a ninth P-type MOSFET PM9, a tenth P-type MOSFET PM10, a fifth N-type MOSFET NM5, a sixth N-type MOSFET NM6, a seventh N-type MOSFET NM7, a first resistor R1, a second resistor R2, and a first capacitor C1;

[0008] In the main amplifier circuit, the substrate of the first P-type MOS transistor PM1 is connected to the soft-start voltage VSS to prevent startup overshoot; the drain of the first P-type MOS transistor PM1 is connected to the drain of the eighth P-type MOS transistor PM8; and the drain of the second P-type MOS transistor PM2 is connected to the drain of the ninth P-type MOS transistor PM9.

[0009] In the soft-start circuit, the gate of the sixth P-type MOSFET PM6 is connected to the second bias voltage Vbias1, the gate of the seventh P-type MOSFET PM7 is connected to the third bias voltage Vbias2, and the gate of the tenth P-type MOSFET PM10 is connected to the fourth bias voltage Vbias3; the sources of the sixth P-type MOSFET PM6, the seventh P-type MOSFET PM7, the tenth P-type MOSFET PM10, the substrate of the eighth P-type MOSFET PM8, and the substrate of the ninth P-type MOSFET PM9 are connected to the internal power supply voltage VDD; the drain of the sixth P-type MOSFET PM6 is connected to the drain of the fifth N-type MOSFET NM5; the source of the fifth N-type MOSFET NM5 is connected to ground GND after being connected to the first resistor R1 and the second resistor R2 in sequence, and the gate of the fifth N-type MOSFET NM5 is connected to the output V of the main amplifier circuit. ea_out; The substrate of the fifth N-type MOSFET NM5 is connected to ground GND; The drain of the seventh P-type MOSFET PM7, the drain of the sixth N-type MOSFET NM6, the source of the eighth P-type MOSFET PM8, and the source of the ninth P-type MOSFET PM9 are connected; The gate of the eighth P-type MOSFET PM8 is connected to the second reference voltage Vref2; The gate of the ninth P-type MOSFET PM9, the drain of the seventh N-type MOSFET NM7, the drain of the tenth P-type MOSFET PM10, and one end of the first capacitor are connected; The other end of the first capacitor is grounded to GND; The source of the sixth N-type MOSFET NM6 is grounded to GND, and its gate is connected to the connection of the first resistor R1 and the second resistor R2; The source of the seventh N-type MOSFET NM7 is grounded to GND, and its gate is connected to the soft-start control signal ctrlA.

[0010] Furthermore, in the main amplifier circuit, the source of the first P-type MOSFET PM1, the source of the second P-type MOSFET PM2, and the drain of the third P-type MOSFET PM3 are connected; the gate of the first P-type MOSFET PM1 is connected to the feedback voltage Vfb, and the gate of the second P-type MOSFET PM2 is connected to the first reference voltage Vref1; the gate of the third P-type MOSFET PM3 is connected to the first bias voltage Vbias0; the source of the third P-type MOSFET PM3, the source of the fourth P-type MOSFET PM4, the source of the fifth P-type MOSFET PM5, and the substrate of the second P-type MOSFET PM2 are connected to the internal power supply voltage VDD; the gate and drain of the fourth P-type MOSFET PM4 and the fifth P-type MOSFET PM5 are connected to the substrate of the second P-type MOSFET PM2. The gate of M5 is connected to the drain of the second N-type MOSFET NM2; the drain of the fifth P-type MOSFET PM5 is connected to the drain of the fourth N-type MOSFET NM4 and serves as the output Vea_out of the main amplifier circuit; the source of the first N-type MOSFET NM1, the source of the second N-type MOSFET NM2, the source of the third N-type MOSFET NM3, and the source of the fourth N-type MOSFET NM4 are connected to ground GND; the drain and gate of the first N-type MOSFET NM1 are connected to the drain of the first P-type MOSFET PM1 and the gate of the second N-type MOSFET NM2; the drain and gate of the third N-type MOSFET NM3 are connected to the drain of the second P-type MOSFET PM2 and the gate of the fourth N-type MOSFET NM4.

[0011] Furthermore, the soft-start voltage VSS is the voltage formed by charging the first capacitor C1 with current.

[0012] The present invention also provides a method for preventing start-up overshoot in an error amplifier for a DC-DC converter, based on the above-described error amplifier for preventing start-up overshoot in a DC-DC converter, comprising the following steps:

[0013] After the chip is powered on, the soft-start control signal ctrlA controls the seventh N-type MOSFET NM7 to set the potential VSS of the first capacitor C1 to 0. Then, the current I5 flowing through the tenth P-type MOSFET PM10 charges the first capacitor C1, and the voltage VSS on the upper plate of the first capacitor C1 slowly increases. The VSS voltage connects the gate of the ninth P-type MOSFET PM9 and the substrate of the first P-type MOSFET PM1.

[0014] When VSS < Vref2, the turn-on threshold of the first P-type MOS transistor PM1 increases. Therefore, the drain current of the third P-type MOS transistor PM3 mainly flows through the second P-type MOS transistor PM2; that is, the current I6 flowing through the second P-type MOS transistor PM2 > the current I7 flowing through the first P-type MOS transistor PM1; at the same time, the current I4 flowing through the ninth P-type MOS transistor PM9 > the current I3 flowing through the eighth P-type MOS transistor PM8; since the drains of the eighth P-type MOS transistor PM8 and the ninth P-type MOS transistor PM9 are respectively connected to the main amplifier circuit, we get:

[0015] I10 = I9 = I7 + I3

[0016] I8 = I6 + I4

[0017] Where: I10 is the current flowing through the fifth P-type MOS transistor PM5, I9 is the current flowing through the fourth P-type MOS transistor PM4, I7 is the current flowing through the first P-type MOS transistor PM1, I3 is the current flowing through the eighth P-type MOS transistor PM8, I8 is the current flowing through the fourth N-type MOS transistor NM4, I6 is the current flowing through the second P-type MOS transistor PM2, and I4 is the current flowing through the ninth P-type MOS transistor PM9;

[0018] Since I10 < I8, the gate voltage Vea_out of the fifth N-type MOS transistor NM5 is 0, and the fifth N-type MOS transistor NM5 cannot be turned on. Then the voltage division Vc at the connection point C of the first resistor R1 and the second resistor R2 is 0, the sixth N-type MOS transistor NM6 is turned off, the current I1 flowing through it is 0, and the current I2 flowing through the seventh P-type MOS transistor PM7 flows through the eighth P-type MOS transistor PM8 and the ninth P-type MOS transistor PM9, I2 = I3 + I4;

[0019] As the VSS voltage increases, when VSS > Vref2, I4 < I3, I10 > I8. Therefore, Vea_out rises, which controls the fifth N-type MOS transistor NM5 to turn on, and the voltage division Vc at the connection point C of the first resistor R1 and the second resistor R2 increases; when Vc increases to turn on the sixth N-type MOS transistor NM6, the current flowing through the seventh P-type MOS transistor PM7 flows through the sixth N-type MOS transistor NM6, and I2 = 0;

[0020] When the VSS voltage rises to the internal power supply voltage VDD, the main amplifier of the error amplifier works normally.

[0021] A DCDC circuit for preventing startup overshoot in the present invention includes the above-mentioned error amplifier.

[0022] The beneficial effects of the present invention:

[0023] The error amplifier provided by this invention can achieve soft-start effect without adding a soft-start module, and optimizes power-on overshoot by connecting the substrate of PM1 to VSS, resulting in a simple solution and significantly saving chip area and power consumption. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a traditional DC-DC implementation architecture.

[0025] Figure 2 This is a schematic diagram of the error amplifier in a traditional DC-DC implementation architecture.

[0026] Figure 3 This is a schematic diagram of the DC-CDC implementation architecture according to an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of an error amplifier used to prevent DC-DC start-up overshoot in an embodiment of the present invention.

[0028] Figure 5 This is a waveform diagram of the error amplifier used to prevent DC-DC start-up overshoot in an embodiment of the present invention.

[0029] Figure 6 This is a schematic diagram of the output waveform of a traditional DC-DC converter.

[0030] Figure 7 This is a schematic diagram of the DC-DC output waveform using an error amplifier employed in an embodiment of the present invention to prevent DC-DC start-up overshoot. Detailed Implementation

[0031] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0032] like Figure 1 As shown, the traditional DC-DC architecture is the part framed in the diagram, consisting of an error amplifier (EA), a soft-start module, a comparator, a clock module, control logic, a high-side driver (Hdrv), a low-side driver (Ldrv), and power transistors.

[0033] An error amplifier is used to amplify the difference between the output voltage Vfb of a DC / DC converter circuit and the reference voltage Vref to generate an amplified voltage. Its architecture is as follows: Figure 2 As shown. In traditional DC-DC architectures, the output of the error amplifier usually needs to be connected to a soft-start module to process the voltage difference between the input terminals of the error amplifier during the soft-start process. This optimizes the overshoot of the DC-DC output, but the implementation circuit is relatively complex.

[0034] To address the aforementioned problems, this invention presents a novel error amplifier architecture that replaces existing error amplifiers. In the DC-DC architecture, the soft-start module can be eliminated, and the output of the error amplifier is directly connected to a comparator, such as... Figure 3 As shown, the framed part is the DC-DC architecture of this invention, which has a simple implementation and greatly saves chip area and power consumption.

[0035] An error amplifier for preventing DC-DC start-up overshoot is proposed in this embodiment of the invention, such as... Figure 4 As shown, it includes: main amplifier circuit ( Figure 4 (The part enclosed in the middle frame) and the soft-start circuit.

[0036] The main amplifier circuit compares the feedback voltage Vfb with the first reference voltage Vref1, and includes a first P-type MOSFET PM1, a second P-type MOSFET PM2, a third P-type MOSFET PM3, a fourth P-type MOSFET PM4, a fifth P-type MOSFET PM5, a first N-type MOSFET NM1, a second N-type MOSFET NM2, a third N-type MOSFET NM3, and a fourth N-type MOSFET NM4. The substrate of the first P-type MOSFET PM1 is connected to the soft-start voltage VSS to prevent startup overshoot. The source of the first P-type MOSFET PM1, the source of the second P-type MOSFET PM2, and the drain of the third P-type MOSFET PM3 are connected; the gate of the first P-type MOSFET PM1 is connected to the feedback voltage Vfb, and the gate of the second P-type MOSFET PM2 is connected to the first reference voltage Vref1; the gate of the third P-type MOSFET PM3 is connected to the first bias voltage Vbias0; the source of the third P-type MOSFET PM3, the source of the fourth P-type MOSFET PM4, the source of the fifth P-type MOSFET PM5, and the substrate of the second P-type MOSFET PM2 are connected to the internal power supply voltage VDD; the gate and drain of the fourth P-type MOSFET PM4, the gate of the fifth P-type MOSFET PM5, and the drain of the second N-type MOSFET NM2 are connected; the fifth P-type MOSFET PM3... The drain of MOSFET PM5 is connected to the drain of the fourth N-type MOSFET NM4 and serves as the output Vea_out of the main amplifier circuit; the sources of the first N-type MOSFET NM1, the second N-type MOSFET NM2, the third N-type MOSFET NM3, and the fourth N-type MOSFET NM4 are connected to ground GND; the drain (point A) and gate of the first N-type MOSFET NM1 are connected to the drain of the first P-type MOSFET PM1, the gate of the second N-type MOSFET NM2, and the drain of the eighth P-type MOSFET PM8; the drain (point B) and gate of the third N-type MOSFET NM3 are connected to the drain of the second P-type MOSFET PM2, the gate of the fourth N-type MOSFET NM4, and the drain of the ninth P-type MOSFET PM9.

[0037] The soft-start circuit, used to stabilize the rising voltage during startup, includes six P-type MOSFETs PM6, PM7, PM8, PM9, and PM10, five N-type MOSFETs NM5, NM6, and NM7, a first resistor R1, a second resistor R2, and a first capacitor C1. The gate of the sixth P-type MOSFET PM6 is connected to a second bias voltage Vbias1, the gate of the seventh P-type MOSFET PM7 is connected to a third bias voltage Vbias2, and the gate of the tenth P-type MOSFET PM10 is connected to a fourth bias voltage Vbias3. The sources of the sixth P-type MOSFET PM6, the seventh P-type MOSFET PM7, and the tenth P-type MOSFET PM10, the substrate of the eighth P-type MOSFET PM8, and the substrate of the ninth P-type MOSFET PM9 are connected to the internal power supply voltage VDD. The drain of the sixth P-type MOSFET PM6 is connected to the drain of the fifth N-type MOSFET NM5. The source of the fifth N-type MOSFET NM5 is connected to ground (GND) via resistors R1 and R2. The gate of NM5 is connected to the output Vea_out of the main amplifier circuit (the junction of the drains of PM5 and NM4). The substrate of NM5 is connected to ground (GND). The drains of the seventh P-type MOSFET PM7, the sixth N-type MOSFET NM6, the source of the eighth P-type MOSFET PM8, and the source of the ninth P-type MOSFET PM9 are connected. The gate of the eighth P-type MOSFET PM8 is connected to the second reference voltage Vref2. The gate of the ninth P-type MOSFET PM9, the drain of the seventh N-type MOSFET NM7, the drain of the tenth P-type MOSFET PM10, and one end of the first capacitor are connected. The other end of the first capacitor is grounded (GND). The source of the sixth N-type MOSFET NM6 is grounded (GND), and its gate is connected to the junction of resistors R1 and R2 (point C). The source of the seventh N-type MOSFET NM7 is grounded at GND, and the gate is connected to the soft-start control signal ctrlA.

[0038] The soft-start voltage VSS is the voltage formed by charging the first capacitor C1 through the current. The VSS voltage connects the gate of the ninth P-type MOSFET PM9 and the substrate of the first P-type MOSFET PM1. This can optimize power-on overshoot, simplify the solution, and significantly save chip area and power consumption.

[0039] This invention also provides a method for preventing start-up overshoot in an error amplifier for a DC-DC converter, based on the aforementioned error amplifier for preventing start-up overshoot in a DC-DC converter, comprising the following steps:

[0040] After the chip is powered on, the seventh N-type MOS transistor NM7 is controlled by the soft-start control signal ctrlA to discharge the potential VSS of the first capacitor C1 to 0 potential; then the first capacitor C1 is charged by the current I5 flowing through the tenth P-type MOS transistor PM10, and the voltage VSS of the upper plate of the first capacitor C1 slowly increases; the VSS voltage is connected to the gate of the ninth P-type MOS transistor PM9 and the substrate of the first P-type MOS transistor PM1.

[0041] When VSS < Vref2, the turn-on threshold of the first P-type MOS transistor PM1 becomes larger, so the drain current of the third P-type MOS transistor PM3 mainly flows through the second P-type MOS transistor PM2; that is, the current I6 flowing through the second P-type MOS transistor PM2 > the current I7 flowing through the first P-type MOS transistor PM1; at the same time, the current I4 flowing through the ninth P-type MOS transistor PM9 > the current I3 flowing through the eighth P-type MOS transistor PM8; since the drains of the eighth P-type MOS transistor PM8 and the ninth P-type MOS transistor PM9 are respectively connected to the main amplifier circuit, we get:

[0042] I10 = I9 = I7 + I3

[0043] I8 = I6 + I4

[0044] Where: I10 is the current flowing through the fifth P-type MOS transistor PM5, I9 is the current flowing through the fourth P-type MOS transistor PM4, I7 is the current flowing through the first P-type MOS transistor PM1, I3 is the current flowing through the eighth P-type MOS transistor PM8, I8 is the current flowing through the fourth N-type MOS transistor NM4, I6 is the current flowing through the second P-type MOS transistor PM2, and I4 is the current flowing through the ninth P-type MOS transistor PM9.

[0045] Since I10 < I8, the gate voltage Vea_out of the fifth N-type MOS transistor NM5 is 0, and the fifth N-type MOS transistor NM5 cannot be turned on, so the voltage division Vc at the connection point C of the first resistor R1 and the second resistor R2 is 0, the sixth N-type MOS transistor NM6 is turned off, the current I1 flowing through it is 0, and the current flowing through the seventh P-type MOS transistor PM7 flows through the eighth P-type MOS transistor PM8 and the ninth P-type MOS transistor PM9, I2 = I3 + I4.

[0046] As the VSS voltage increases, when VSS > Vref2, I4 < I3, I10 > I8, so Vea_out increases, which controls the fifth N-type MOS transistor NM5 to turn on, and the voltage division Vc at the connection point C of the first resistor R and the second resistor R2 increases; when Vc increases to turn on the sixth N-type MOS transistor NM6, the current flowing through the seventh P-type MOS transistor PM7 flows through the sixth N-type MOS transistor NM6, and I2 = 0.<0000·111>

[0047] When the VSS voltage rises to the internal power supply voltage VDD, the main amplifier of the error amplifier operates normally.

[0048] The operating waveform of the error amplifier (EA) is as follows: Figure 5 As shown.

[0049] This invention also provides a DC-DC circuit to prevent startup overshoot, including a comparator, a clock module, control logic, a high-side driver (Hdrv), a low-side driver (Ldrv), a power transistor, and the aforementioned error amplifier, with the connections as follows: Figure 3 As shown.

[0050] Figure 6 , Figure 7 The output waveforms of the traditional DC-DC architecture and the DC-DC architecture with an error amplifier to prevent DC-DC start-up overshoot are given. It can be seen that the output waveform of the DC-DC architecture with an error amplifier to prevent DC-DC start-up overshoot is smoother and avoids the phenomenon of voltage overshoot.

[0051] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and various changes or modifications can be made to these embodiments without departing from the principles and essence of the present invention.

Claims

1. An error amplifier for preventing DC-DC start-up overshoot, characterized in that, include: Main amplifier circuit and soft-start circuit; The main amplifier circuit is used to compare the feedback voltage Vfb with the first reference voltage Vref1, and includes a first P-type MOSFET PM1, a second P-type MOSFET PM2, a third P-type MOSFET PM3, a fourth P-type MOSFET PM4, a fifth P-type MOSFET PM5, a first N-type MOSFET NM1, a second N-type MOSFET NM2, a third N-type MOSFET NM3, and a fourth N-type MOSFET NM4; the soft-start circuit is used to stabilize the rising voltage during startup, and includes a sixth P-type MOSFET PM6, a seventh P-type MOSFET PM7, an eighth P-type MOSFET PM8, a ninth P-type MOSFET PM9, a tenth P-type MOSFET PM10, a fifth N-type MOSFET NM5, a sixth N-type MOSFET NM6, a seventh N-type MOSFET NM7, a first resistor R1, a second resistor R2, and a first capacitor C1; In the main amplifier circuit, the substrate of the first P-type MOS transistor PM1 is connected to the soft-start voltage VSS to prevent startup overshoot; the drain of the first P-type MOS transistor PM1 is connected to the drain of the eighth P-type MOS transistor PM8; and the drain of the second P-type MOS transistor PM2 is connected to the drain of the ninth P-type MOS transistor PM9. In the soft-start circuit, the gate of the sixth P-type MOSFET PM6 is connected to the second bias voltage Vbias1, the gate of the seventh P-type MOSFET PM7 is connected to the third bias voltage Vbias2, and the gate of the tenth P-type MOSFET PM10 is connected to the fourth bias voltage Vbias3; the sources of the sixth P-type MOSFET PM6, the seventh P-type MOSFET PM7, the tenth P-type MOSFET PM10, the substrate of the eighth P-type MOSFET PM8, and the substrate of the ninth P-type MOSFET PM9 are connected to the internal power supply voltage VDD; the drain of the sixth P-type MOSFET PM6 is connected to the drain of the fifth N-type MOSFET NM5; the source of the fifth N-type MOSFET NM5 is connected to ground GND after being connected to the first resistor R1 and the second resistor R2 in sequence, and the gate of the fifth N-type MOSFET NM5 is connected to the output V of the main amplifier circuit. ea_out; The substrate of the fifth N-type MOSFET NM5 is connected to ground GND; The drain of the seventh P-type MOSFET PM7, the drain of the sixth N-type MOSFET NM6, the source of the eighth P-type MOSFET PM8, and the source of the ninth P-type MOSFET PM9 are connected; The gate of the eighth P-type MOSFET PM8 is connected to the second reference voltage Vref2; The gate of the ninth P-type MOSFET PM9, the drain of the seventh N-type MOSFET NM7, the drain of the tenth P-type MOSFET PM10, and one end of the first capacitor are connected; The other end of the first capacitor is grounded to GND; The source of the sixth N-type MOSFET NM6 is grounded to GND, and its gate is connected to the connection of the first resistor R1 and the second resistor R2; The source of the seventh N-type MOSFET NM7 is grounded to GND, and its gate is connected to the soft-start control signal ctrlA.

2. The error amplifier for preventing DC-DC start-up overshoot according to claim 1, characterized in that: In the main amplifier circuit, the source of the first P-type MOS transistor PM1, the source of the second P-type MOS transistor PM2, and the drain of the third P-type MOS transistor PM3 are connected; the gate of the first P-type MOS transistor PM1 is connected to the feedback voltage Vfb, and the gate of the second P-type MOS transistor PM2 is connected to the first reference voltage Vref1; the gate of the third P-type MOS transistor PM3 is connected to the first bias voltage Vbias0; the source of the third P-type MOS transistor PM3, the source of the fourth P-type MOS transistor PM4, the source of the fifth P-type MOS transistor PM5, and the substrate of the second P-type MOS transistor PM2 are connected to the internal power supply voltage VDD; the gate and drain of the fourth P-type MOS transistor PM4, the gate of the fifth P-type MOS transistor PM5, and the drain of the second N-type MOS transistor NM2 are connected; the drain of the fifth P-type MOS transistor PM5 is connected to the drain of the fourth N-type MOS transistor NM4 and serves as the output Vea_out of the main amplifier circuit; the sources of the first N-type MOS transistor NM1, the second N-type MOS transistor NM2, the third N-type MOS transistor NM3, and the fourth N-type MOS transistor NM4 are connected to the ground terminal GND; the drain and gate of the first N-type MOS transistor NM1, the drain of the first P-type MOS transistor PM1, and the gate of the second N-type MOS transistor NM2 are connected; the drain and gate of the third N-type MOS transistor NM3, the drain of the second P-type MOS transistor PM2, and the gate of the fourth N-type MOS transistor NM4 are connected.

3. The error amplifier for preventing DC-DC start-up overshoot according to claim 1, characterized in that: The soft start voltage VSS is a voltage formed by charging the first capacitor C1 with a current.

4. A method for preventing start-up overshoot in an error amplifier for a DC-DC converter, based on the error amplifier for preventing start-up overshoot according to any one of claims 1-3, characterized in that, It includes the following steps: After the chip is powered on, the seventh N-type MOS transistor NM7 is controlled by the soft start control signal ctrlA to discharge the potential VSS of the first capacitor C1 to 0 potential; then the first capacitor C1 is charged with the current I5 flowing through the tenth P-type MOS transistor PM10, and the voltage of the upper plate of the first capacitor C1, VSS, slowly increases; the VSS voltage is connected to the gate of the ninth P-type MOS transistor PM9 and the substrate of the first P-type MOS transistor PM1. When VSS < Vref2, the threshold voltage of the first P-type MOS transistor PM1 increases, so the drain current of the third P-type MOS transistor PM3 mainly flows through the second P-type MOS transistor PM2; that is, the current I6 flowing through the second P-type MOS transistor PM2 > the current I7 flowing through the first P-type MOS transistor PM1; at the same time, the current I4 flowing through the ninth P-type MOS transistor PM9 > the current I3 flowing through the eighth P-type MOS transistor PM8; since the drains of the eighth P-type MOS transistor PM8 and the ninth P-type MOS transistor PM9 are respectively connected to the main amplifier circuit, we get: I10 = I9 = I7 + I3 I8 = I6 + I4 Where: I10 is the current flowing through the fifth P-type MOS transistor PM5, I9 is the current flowing through the fourth P-type MOS transistor PM4, I7 is the current flowing through the first P-type MOS transistor PM1, I3 is the current flowing through the eighth P-type MOS transistor PM8, I8 is the current flowing through the fourth N-type MOS transistor NM4, I6 is the current flowing through the second P-type MOS transistor PM2, and I4 is the current flowing through the ninth P-type MOS transistor PM9; Since I10 < I8, the gate voltage Vea_out of the fifth N-type MOS transistor NM5 is 0, and the fifth N-type MOS transistor NM5 cannot be turned on. Then, the voltage division Vc at the connection point C of the first resistor R1 and the second resistor R2 is 0, the sixth N-type MOS transistor NM6 is turned off, the current I1 flowing through it is 0, and the current flowing through the seventh P-type MOS transistor PM7 flows through the eighth P-type MOS transistor PM8 and the ninth P-type MOS transistor PM9, so I2 = I3 + I4; As the VSS voltage increases, when VSS > Vref2, I4 < I3, I10 > I8. Therefore, Vea_out increases, which controls the fifth N-type MOS transistor NM5 to turn on, and the voltage division Vc at the connection point C of the first resistor R1 and the second resistor R2 increases. When Vc increases to turn on the sixth N-type MOS transistor NM6, the current flowing through the seventh P-type MOS transistor PM7 flows through the sixth N-type MOS transistor NM6, and I2 = 0; When the VSS voltage rises to the internal power supply voltage VDD, the main amplifier of the error amplifier operates normally.

5. A DC-DC circuit for preventing startup overshoot, characterized in that: Including the error amplifier according to any one of claims 1-3.

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