A radio frequency signal transmission method, device, medium, and product

Abstract

This application discloses a radio frequency (RF) signal transmission method, device, medium, and product, relating to the field of signal transmission technology. It addresses the technical problems of repetitive RF signal transmission, large-volume data acquisition, and data congestion and omissions caused by limited memory in acquisition devices. The method achieves RF signal transmission between the first and second controllers using a computationally fast link protocol, and parallel transmission of multi-channel processing via an antenna array combined with the CXL.io protocol. Simultaneously, it predicts the acquisition duration supported by the local remaining memory based on actual bandwidth, allowing for flexible matching and calling of acceleration devices. This saves waiting time during data transmission and storage, avoids congestion and omissions, and improves transmission efficiency, thereby enhancing the reliability of the signal acquisition device.

Description

Technical Field

[0001] This application relates to the field of signal transmission technology, and in particular to a radio frequency signal transmission method, device, medium and product. Background Technology

[0002] Software-defined radio (SDR) acquisition equipment typically consists of an antenna, a radio frequency (RF) module, a field-programmable gate array (FPGA) processing module, and a main processor module. The antenna receives wireless signals, which are then filtered, amplified, and frequency-converted by the RF module to convert the analog signals into digital signals. These digital signals are then acquired, stored, and processed by the FPGA and main processor modules before being transmitted to a host computer or subsequent processing system via an interface. Data transmission between the FPGA and main processor modules occurs via a software protocol stack. After acquiring the RF signal, the FPGA module buffers it in its own cache. When transmitting to the main processor module, the data is retrieved from the FPGA's cache and transferred to its own cache. This multiple transmission process causes RF signal delays, which can lead to data congestion and even partial signal loss in scenarios involving sudden large volumes of data, such as radar echoes. Furthermore, the memory and computing resources of the acquisition device are limited. If the memory and computing resources are about to be exhausted during the multi-signal processing of radio frequency signals, the radio frequency signals need to wait in the transmission channel, which will further cause radio frequency signal transmission blockage and reduce the transmission reliability of the software radio acquisition device.

[0003] Therefore, improving the transmission efficiency of radio frequency signals to enhance the transmission reliability of acquisition equipment is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a radio frequency signal transmission method, device, medium, and product to at least solve the problem of congestion and omission caused by repeated transmission of radio frequency signals in related technologies, which reduces transmission reliability.

[0005] This application provides a radio frequency signal transmission method applied to a first controller of a signal acquisition device. The first controller and a second controller of the signal acquisition device transmit signals using a computationally fast link protocol. The first controller is connected to an acceleration device. The method includes:

[0006] Acquire baseband data obtained from baseband processing of radio frequency signals;

[0007] The baseband data is processed using the input / output protocol of the fast link protocol multi-channel processing based on the number of antenna arrays to which the radio frequency signal belongs, to obtain multi-channel baseband data.

[0008] The predicted acquisition duration supported by the actual remaining memory of the first controller is determined based on the actual bandwidth of the radio frequency signal and the amount of cached data of the first controller.

[0009] The matching call for the acceleration device is determined based on the relationship between the predicted acquisition duration and the preset acquisition duration, and the multi-channel baseband data is transmitted to the called acceleration device so that the second controller can call and process it.

[0010] This application also provides a signal acquisition device, including an antenna, a radio frequency module, a first controller and a second controller, wherein the first controller and the second controller transmit data using a computation fast link protocol, and the first controller is connected to an acceleration device;

[0011] The antenna receives radio frequency signals;

[0012] The radio frequency module is used to convert the radio frequency signal from analog to digital form.

[0013] The first controller is used to execute the steps of the radio frequency signal transmission method described above to realize the transmission of radio frequency signals so that the second controller can call and process them.

[0014] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described radio frequency signal transmission methods.

[0015] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described radio frequency signal transmission methods.

[0016] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described radio frequency signal transmission methods.

[0017] This application addresses the common problem of redundant transmissions and data congestion during data transfer caused by conventional methods that use software protocol stacks to transmit radio frequency (RF) signals between the first and second controllers. The limited memory of the first controller further exacerbates this congestion. Firstly, this application addresses this issue by using a computationally fast link protocol for RF signal transmission between the first and second controllers of the signal acquisition device. Compared to software protocol stacks, this protocol reduces redundant transmissions, such as fetching data from the first controller's cache to the second controller's own cache, allowing data processing directly from the first controller's cache. This achieves cache consistency and reduces transmission latency. Secondly, the first controller is connected to an acceleration device. Unlike conventional solutions where the first controller's memory and computing power are fixed, this application allows for flexible use of the acceleration device, enabling real-time memory expansion based on the amount of RF signal data and the corresponding computing load. This ensures both memory and computing power expansion. Secondly, based on the number of antenna arrays to which the radio frequency signal belongs, the baseband data is processed using the CXL.io protocol to obtain multi-channel baseband data. Compared to traditional serial wireless transmission, this application combines the antenna array with CXL multi-channel to achieve end-to-end parallel transmission, thereby reducing transmission latency. Finally, considering the usage of the acceleration device, compared to conventional solutions where data volume has already flowed into the local memory of the first controller before calculating the memory space and comparing it with a fixed remaining memory threshold to see if it is sufficient for storage, leading to data congestion as subsequent radio frequency signal data flows in while data not yet stored in local memory awaits calculation results, this application can characterize the amount of data per unit time by using the real-time bandwidth (actual bandwidth) of the radio frequency signal before it is stored in local memory. This allows for prediction of the acquisition duration. For sudden acquisition scenarios such as radar echoes with large volumes of data, the acceleration device can be called in advance to prevent data congestion caused by the influx of subsequent radio frequency signal data while the radio frequency signal is waiting for calculation in the local memory. This achieves data transmission while also predicting the storage usage of local memory space in advance and calling the acceleration device in real time, avoiding data loss, improving data transmission efficiency, and enhancing the transmission reliability of the acquisition device.

[0018] Therefore, it can solve the technical problems of repeated transmission of radio frequency signals, data congestion and omission caused by large-volume data acquisition and limited memory of acquisition devices. It achieves the following: radio frequency signal transmission between the first controller and the second controller is carried out using a fast computation link protocol. In addition, the CXL.io protocol is combined with the antenna array of radio frequency signals to realize parallel transmission of multi-channel processing. During transmission, the predicted acquisition time supported by the actual remaining local memory is predicted in advance based on the actual bandwidth, so as to determine the flexible matching and calling of the acceleration device, save the waiting time of data at the beginning of transmission and during transmission and storage, avoid congestion and omission, improve transmission efficiency and improve the reliability of signal acquisition devices. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the signal acquisition equipment in a conventional solution;

[0021] Figure 2 A schematic diagram of the CXL protocol portion of a signal acquisition device provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the architecture of a signal acquisition device provided in an embodiment of this application;

[0023] Figure 4 A flowchart illustrating a radio frequency signal transmission method provided in this application embodiment;

[0024] Figure 5 A flowchart illustrating the data reception process based on a signal acquisition device is provided in this application embodiment.

[0025] Figure 6 A schematic diagram illustrating a CXL protocol layering method provided in an embodiment of this application;

[0026] Figure 7 A schematic diagram of transaction layer message management for a CXL protocol structure provided in this application embodiment;

[0027] Figure 8 A schematic diagram of a signal acquisition device that only receives radio frequency signals, provided as an embodiment of this application;

[0028] Figure 9 A schematic diagram of a signal acquisition device including a call acceleration card for receiving radio frequency signals is provided in an embodiment of this application;

[0029] Figure 10 This is a schematic diagram of a radio frequency signal transmission device provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0031] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Conventional software-defined radio is a commonly used wireless communication technology architecture. Figure 1 This is a schematic diagram of the signal acquisition equipment structure in a conventional solution, such as... Figure 1As shown, the system includes an antenna, a radio frequency (RF) module, a programmable device (FPGA processing module), and a main processor module. During operation, the antenna receives wireless signals, which are then filtered, amplified, and frequency-converted by the RF module. An analog-to-digital converter (ADC) converts the analog signals into digital signals. The FPGA processing module and the main processor module then acquire, store, and perform preliminary processing on the digital signals. Finally, the data is transmitted to a host computer or subsequent processing system via an interface. Common interfaces for software-defined radio (SDR) signal acquisition devices include Peripheral Component Interconnect Express (PCIE), Universal Serial Bus (USB), and Ethernet. Multi-bus parallel interfaces can achieve data transfer speeds of hundreds of MB / s. However, existing SDR devices use a fixed hardware architecture, requiring data to be transmitted between modules via a software protocol stack, resulting in high latency. Furthermore, they cannot dynamically expand memory capacity, making them unsuitable for handling sudden large-volume data acquisition scenarios such as radar echoes.

[0034] The radio frequency (RF) module is mainly used for receiving and transmitting RF signals. After receiving RF signals through the antenna, the RF unit processes them and the ADC converts the analog signal into a digital signal. This process belongs to the receiving link. It can also support signal transmission. The transmitting link uses a digital-to-analog converter (DAC) to convert the digital signal into an analog RF signal, which is then amplified by the RF unit and transmitted by the antenna.

[0035] The FPGA processing module is used to complete the baseband signal processing. It integrates resources such as a Digital Signal Processor (DSP), System Gates, and Random Access Memory (RAM) to process digital signals transmitted from the RF receiving module, such as digital filtering and down-conversion, and to sample signals to obtain baseband data. It also has standard input / output (I / O) interfaces for data interaction and integrates modules such as an ADC to monitor and acquire analog signals within the platform. In addition, a high-speed data transmission channel (PCIe bus) is built between the FPGA processing module and the main processor module to support efficient data transmission.

[0036] The main processor module can perform more complex algorithm calculations and system control on the data processed by the FPGA processing module, such as running the communication protocol stack and implementing advanced signal modulation and demodulation algorithms. The storage module is configured with a non-volatile storage device with a capacity of at least 2Tb to store system programs, configuration files, and acquired signal data, ensuring long-term reliable data preservation. The interface module offers a rich set of interfaces, including two Low Voltage Differential Signaling (LVDS) interfaces (70Mbps bit rate), one Ethernet port (100Mbps rate), a USB interface supporting USB 2.0 and 3.0, a High-Definition Multimedia Interface (HDMI) interface, a Serial Advanced Technology Attachment (SATA) storage interface, two Controller Area Network (CAN) buses (500Kbps baud rate), one 422 interface (100Kbps baud rate), and one Bayonet Neill-Concelman (BNC) interface (for pulse per second (PPS) input for time synchronization).

[0037] exist Figure 1 In this architecture, the FPGA acts as a hardware accelerator, with its digital signal processor executing high-speed digital signal algorithms (such as filtering, modulation / demodulation, and signal equalization) to process the raw digital signals (RF signals) from the ADC. System gate circuits provide logic control and timing management, coordinating the working rhythm of each module. Input / output interfaces serve as a bridge between the FPGA and the main processor, responsible for physical layer adaptation for data transmission and reception. Random access memory (RAM) acts as a temporary data warehouse for the FPGA, caching intermediate data to be processed or already processed, improving processing efficiency. Multiplexers select one or more input signals from multiple input signals and transmit them through a single output channel, thereby achieving efficient signal multiplexing and saving transmission resources. Direct memory access (DMI) is a high-performance direct memory access technology based on the PCIe bus designed for the FPGA. Its main function is to establish a high-speed data transmission channel between the FPGA and the host (such as the CPU), enabling rapid data transfer between the FPGA device and system memory without CPU intervention.

[0038] The core of the main processor module executes system-level instructions and schedules various peripherals and modules; it is the brain of the main processor. The processor is a dedicated acceleration module responsible for accelerating specific algorithms. The frame rate display controller is responsible for controlling the screen display frame rate and signal output, supporting 60 frames per second high-definition display. The memory controller manages the read and write operations of Double Data Rate 4 (DDR4) memory, providing high-speed storage resources for the system and serving as the main data repository. The image signal processor processes the image signals input from the camera (such as noise reduction, color restoration, and High Dynamic Range (HDR)), outputting high-quality image data.

[0039] The entire signal acquisition equipment is deployed with an operating system that supports custom communication systems and corresponding software programs through code writing, flexibly adapting to the development needs of different communication standards and application scenarios. The overall workflow is as follows: the antenna receives / transmits radio frequency signals; the radio frequency module performs radio frequency-to-digital / digital-to-radio frequency conversion; the FPGA processing module performs preliminary processing on the digital signals, which are then transmitted to the main processor module via the PCIe interface for in-depth computation and control. Data can be stored in the storage module, while the interface module is used to connect external devices (such as display devices, storage expansion devices, and other control devices) to achieve data interaction and system expansion. With the help of the operating system and custom programming, diverse communication systems can be built.

[0040] The aforementioned signal acquisition devices employ software protocol stacks such as the PCIe bus, which require multiple transmission processes, resulting in radio frequency (RF) signal delays. Furthermore, in scenarios involving sudden, high-volume data acquisition such as radar echoes, signal delays can cause data congestion, and even partial RF signal loss. Moreover, the acquisition devices have limited memory and computing resources. If these resources are nearing exhaustion during multi-signal processing of RF signals, the RF signals must wait in the transmission channel, further causing RF signal transmission congestion and reducing the transmission reliability of the software-defined radio acquisition devices. This application provides an RF signal transmission method that solves the above-mentioned technical problems.

[0041] The specific application environment architecture or specific hardware architecture on which the execution of the radio frequency signal transmission method depends is described here.

[0042] The first and second controllers of the signal acquisition device use the Compute Express Link (CXL) protocol for data transmission. Figure 2 This is a schematic diagram of a signal acquisition device for the CXL protocol portion provided in an embodiment of this application, as shown below. Figure 2As shown, the CXL protocol supports CXL.io (Compute Fast Link Input / Output), CXL.cache (Compute Fast Link Cache), and CXL.mem (Compute Fast Link Memory) protocols. CXL.io is the foundational part of the CXL protocol, defining the basic input / output communication mechanism between devices, similar to PCIe functionality but offering higher performance and lower latency. CXL.cache allows the Central Processing Unit (CPU) to use the memory space of other devices (such as Graphics Processing Units (GPUs) or FPGAs) as a cache. This makes data sharing between devices more efficient and reduces data transfer latency. CXL.mem allows devices to directly access the CPU's memory space or use the device's memory space as extended memory for the CPU. This further improves memory utilization and data access speed.

[0043] The CXL device (first controller) communicates with the host (second controller) via a coherency bridge. The CXL device contains an internal cache for storing and managing data, while the host contains a home agent responsible for managing and coordinating data transfer and memory access with the CXL device. The system utilizes host-managed device memory (HDM) and host-attached memory. HDM is managed and controlled by the host, while host-attached memory is directly connected to the host's memory resources. This architecture allows the CXL device to efficiently exchange data and share memory with the host, thereby improving overall system performance and efficiency.

[0044] Figure 3 This is a schematic diagram of the architecture of a signal acquisition device provided in an embodiment of this application, such as... Figure 3 As shown, it is based on Figure 2 The abstract architecture is concretized in this way. The first controller not only integrates baseband signal processing units, such as DSP, Block Random Access Memory (BRAM), and Look-Up Table (LUT), but also includes interfaces such as CXL.io and CXL.cache Request. It undertakes both digital signal processing functions and implements data caching and the CXL protocol on the CXL device side. Figure 2 The CXL Device maintains consistent device-side data management and protocol interaction. Figure 2In the context of consistency bridges and home agents (managing device-host data transfer and memory access), in Figure 3 The second controller's internal functions handle this: its CXL.io and CXL.cache / mem interfaces, along with the built-in Home Agent component, collectively implement consistent bridging and memory access management. Figure 2 The collaboration logic of Coherency Bridge + Home Agent. Figure 2 HDM correspondence in Figure 3 The memory in the first controller is managed and controlled by the second controller, which provides data caching support for the first controller. Figure 2 Host-attached memory in: corresponding Figure 3 The Host Memory of the second control module is directly connected to the host's memory resources, allowing the host's core services to directly access them. Figure 2 The CXL device and the host achieve efficient data exchange and memory sharing through protocol / memory mechanisms. Figure 3 The system is interconnected through the CXL protocol between the first and second controllers. With the help of the CXL.io and CXL.cache / mem mechanisms, the first and second controllers achieve low-latency data transmission, shared memory access, and cache consistency assurance, ultimately improving the overall performance and efficiency of the signal acquisition system.

[0045] Figure 4 A flowchart of a radio frequency signal transmission method provided in this application embodiment is shown below. Figure 4 As shown, a first controller is applied to a signal acquisition device. The first controller and a second controller of the signal acquisition device transmit data using a computationally fast link protocol. The first controller is connected to an acceleration device. The method includes:

[0046] S11: Acquire baseband data obtained by baseband processing of radio frequency signals;

[0047] S12: Calculate the baseband data based on the number of antenna arrays to which the radio frequency signal belongs, and perform multi-channel processing of the input / output protocol of the fast link protocol to obtain multi-channel baseband data;

[0048] S13: Determine the predicted acquisition duration supported by the actual remaining memory of the first controller based on the actual bandwidth of the radio frequency signal and the amount of cached data of the first controller;

[0049] S14: Determine the matching call of the acceleration device based on the relationship between the predicted acquisition duration and the preset acquisition duration, and transmit the multi-channel baseband data to the called acceleration device so that the second controller can call and process it.

[0050] Specifically, the execution entity of this application is the first controller, which transmits radio frequency signals with the second controller via the CXL protocol. Regarding these radio frequency signals, timely response is required, ideally within a local area network or mobile internet, even down to milliseconds, for applications such as vehicle-to-everything (V2X) communication, radar detection, and real-time control. Transmission latency and data congestion must be minimized at every stage of transmission. Similarly, this method is also applicable to the transmission of other signals requiring high real-time performance, such as traffic control, vehicle control signals, rail transit signals, or medical equipment. No specific limitations are imposed; the method can be configured according to the actual situation.

[0051] The baseband processing of radio frequency (RF) signals can be the same as or different from conventional methods; no specific limitations are specified here. Regarding signal reception and RF processing, the antenna acts as the signal input front-end, capturing spatial RF signals. In the receiving link, the RF module amplifies, filters, and down-converts the RF signal captured by the antenna, outputting an analog intermediate frequency (IF) signal. The transmitting link receives the digital signal after baseband processing, up-converts and amplifies it, converting it back into an RF signal for transmission via the antenna. This can be used for signal transmission tasks. The ADC (Analog-to-Digital Converter) is responsible for converting the analog IF signal output by the RF module into a digital signal, providing the foundation for digital domain processing. The DAC (Digital-to-Digital Converter), when a signal needs to be transmitted, converts the digital signal after baseband processing back into an analog signal and sends it to the RF module's transmitting link.

[0052] The primary controller is crucial for core digital signal processing. It receives the digital signal (RF signal) output from the ADC and, leveraging its abundant logic resources and algorithm acceleration capabilities, completes baseband signal processing. The basic logic and control section includes: a multiplexer (MUX) for flexible signal path switching; a lookup table for performing various complex logical operations; flip-flops (FFs) for temporary data storage and precise timing control; and BRAM for high-speed local data storage. Furthermore, System Gates ensures the stability of the system's logic gating operations and basic timing. Utilizing a DSP hard core, it can efficiently handle digital signal processing algorithms such as filtering, demodulation, and encoding / decoding, thereby significantly improving the overall efficiency of signal processing.

[0053] In terms of interface and cache design, on the one hand, the standard I / O interface enables basic data interaction between the first controller and external modules, ensuring basic data input and output requirements; on the other hand, the CXL-based components focus on improving the efficiency of cross-module data interaction. Internally, the first controller interfaces with the CXL I / O interface through the CXL controller IP core (integrated circuit module). Modules such as CXL.io and CXL.cache Request in the first controller are supported by the CXL controller IP core, a pre-packaged hard-core unit from the first controller manufacturer for the CXL protocol, possessing stable protocol parsing and data forwarding capabilities. The Device's Coherency Engine (DCOH) is directly connected to the CXL.cache protocol layer module and the first controller's local cache via the first controller's internal high-speed interconnect bus. Simultaneously, DCOH communicates with the main processor module through the CXL.cache protocol to jointly maintain system-level cache consistency. CXL.io is responsible for high-speed data transmission, ensuring that massive amounts of data can flow quickly and stably between different modules. The CXL.cache protocol support in DCOH further improves the efficiency and stability of data interaction by optimizing data caching and access mechanisms. This allows the first controller processing module to access the memory of the second controller, enabling it to better adapt to the stringent requirements of high-performance computing scenarios. In addition, the first controller is also equipped with memory as a local data cache. The second controller can directly access the memory through the CXL.mem protocol, further optimizing data read and write operations and ensuring the continuity and efficiency of signal processing.

[0054] Within the first controller, the baseband data undergoes multi-channel processing using the CXL protocol's input / output protocol based on the number of antenna arrays to which the RF signal belongs. The CXL protocol's multi-channel capability improves data transmission bandwidth and efficiency through multiple channels or links. The number of channels depends on the hardware design and system requirements. The first controller can configure different numbers of channels as needed to adapt to varying performance demands. This embodiment considers one or more antenna arrays, combining their corresponding baseband data with the multi-channel characteristics of the CXL.io protocol to form multi-channel baseband data. This can be achieved through a reasonable mapping mechanism between antenna channels and CXL.io channels. Mapping can be based on antenna channels or data block fragmentation; no limitation is imposed here, and the configuration can be tailored to the specific situation.

[0055] In step S13, the predicted acquisition duration supported by the actual remaining memory of the first controller is determined based on the actual bandwidth of the radio frequency signal and the amount of cached data in the first controller. A conventional approach involves calculating the amount of data flowing into the local memory of the first controller while transferring baseband data to memory, comparing the remaining memory space with a fixed space threshold. If the threshold is reached, it indicates that the local memory of the first controller is nearly full, and no further data is transferred. The baseband data currently being transmitted is blocked in the first controller, only being stored again after some data is cleared from the local memory. Considering the real-time nature of the radio frequency signal, it will continuously receive baseband data, leading to blockage in the first controller and even data loss. In this embodiment, during step S12, the actual bandwidth of the radio frequency signal is calculated simultaneously to pre-calculate the predicted acquisition duration supported by the current actual remaining memory of the first controller.

[0056] In electromagnetic spectrum acquisition scenarios, the system needs to cover a wide frequency band from kHz to GHz. The bandwidth difference between different frequency bands directly determines the acquisition rate. Narrowband civilian communication signals have a bandwidth of only a few kHz, corresponding to a low acquisition rate and a small amount of data per unit time. However, broadband radar and cognitive countermeasures signals have bandwidths of hundreds of MHz or even GHz, which will drive the acquisition rate to surge synchronously, resulting in a sudden doubling of the amount of signal data generated per unit time. To avoid data transmission blockage and buffer congestion, this solution abandons the traditional method of relying solely on a fixed remaining memory threshold and instead dynamically adjusts the start threshold by combining the real-time baseband signal bandwidth and the remaining memory. Specifically, the FPGA first calculates the amount of new data per unit time at the corresponding acquisition rate based on the real-time bandwidth of the current acquisition signal, and then, combined with the amount of data already cached in local memory, calculates in real time the maximum acquisition duration that the remaining memory can support, i.e., the predicted acquisition duration.

[0057] In step S14, the matching call for the acceleration device is determined based on the relationship between the predicted acquisition duration and the preset acquisition duration. Multi-channel baseband data is transmitted to the called acceleration device for processing by the second controller. Here, it is necessary to compare the predicted acquisition duration with the preset acquisition duration. If the predicted acquisition duration is longer than the preset acquisition duration, it indicates that the local memory of the first controller cannot handle the subsequent baseband data, and the acceleration device needs to be called. The corresponding calling process can be performed via command or by turning on the acceleration device and connecting it to the first controller via a hardware switch. The number of acceleration devices called can be one, multiple, or determined according to the actual situation. It should be noted that conventional acceleration device calls are based on computing power resources. The acceleration device call in this embodiment considers not only computing power resources but, more importantly, memory space usage, enabling precise matching between the acceleration card startup timing and the data generation rate. This avoids congestion caused by fixed threshold response lag under broadband signals and resource waste caused by excessively high fixed thresholds under narrowband signals, fully adapting to the dynamic characteristics of electromagnetic spectrum acquisition.

[0058] Regarding the first controller in this embodiment, it can be an FPGA or other programmable devices. The second controller is the host. The acceleration device can be an acceleration card, a GPU, or an eXtensible Processing Unit (XPU), etc., and is not limited here.

[0059] about Figure 3The second controller in the system employs a high-performance computing architecture, with its core being a core computing unit responsible for running the operating system and various upper-layer applications. This module can perform high-level analysis on the data processed by the first controller, such as protocol parsing and intelligent algorithm decision-making, and coordinate global logic to ensure efficient system operation. The transaction scheduling part includes a "transaction message scheduler," responsible for managing task queues and allocating system resources to ensure the orderly execution of multiple tasks. Meanwhile, the "general interface" can flexibly adapt to the connection needs of various external devices, enhancing the system's versatility and scalability. Regarding memory and caching architecture, the second controller is optimized using CXL technology. High-speed data flow optimization: Leveraging the high bandwidth of CXL.io, the baseband signal processed by the first controller can be transmitted to the second controller via the CXL.io interface with zero copy, avoiding the delay caused by multiple data copies in traditional buses; simultaneously, CXL.io supports multi-channel parallel transmission, improving the transmission efficiency of high-volume signals, such as multi-antenna array data. Cache access mechanism optimization: DCOH, combined with the CXL.cache protocol, provides prefetching and cache consistency guarantees for the first controller's access to host memory. For example, when the first controller needs to repeatedly access a segment of radar echo data, DCOH caches the data in the first controller's local memory and synchronizes the cache state with the main processor's Home Agent via CXL.cache. This reduces the latency of repeated access to host memory and ensures the consistency of data accessed by the first and second controllers. Memory resource scheduling optimization: The CXL.mem protocol allows the second controller to dynamically partition and manage permissions of the memory resources accessible by the first controller. For example, during peak signal acquisition periods, the second controller can temporarily allocate a larger memory pool to the first controller via CXL.mem to cache high-throughput baseband data, preventing data overflow. During idle periods, resources are reclaimed, improving memory utilization. CXL.cache is responsible for optimizing the caching mechanism, while CXL.mem manages memory resources. This combination of technologies significantly reduces data transmission latency between main memory, the first controller, and peripherals, improving bandwidth utilization. The Home Agent component is responsible for maintaining the consistency of the cache within the system, ensuring consistency and accuracy when multiple modules access memory data, thereby guaranteeing the reliability of data interaction. Figure 3In this architecture, the DCOH within the first controller module has hardware-level protocol and signal connections with the system cache consistency mechanism. Internally, the DCOH connects directly to modules such as CXL.cache Request and Host Cache via the high-speed consistency bus within the first controller, synchronizing cache line status in real time. For cross-module connections, the DCOH establishes a communication link with the Home Agent within the second controller through the CXL.cache protocol physical layer interface, transmitting cache status information from the first controller, such as data updates and invalidation requests, to the Home Agent. The Home Agent then coordinates cache consistency across the first controller and the second controller, ensuring data consistency when multiple modules access shared memory. Furthermore, HostMemory serves as the system memory of the second controller, storing programs and data to support stable Core operation and data caching. Through the combination of these technologies, the second controller can maintain high performance and efficiency when handling complex tasks.

[0060] about Figure 3 The peripheral devices in the system connect to storage modules, Ethernet interfaces, USB interfaces, HDMI interfaces, etc. through various interfaces (Ethernet, USB, HDMI, etc.) to realize functions such as local persistent data storage, network communication, connection of external general-purpose devices, and acceleration of large data transmission, thereby expanding the system's functions and application scenarios.

[0061] In this application embodiment, conventional solutions use a software protocol stack to transmit radio frequency signals between the first and second controllers, leading to repeated transmissions and data transmission congestion during high-volume data transmission. The limited memory of the first controller further exacerbates this congestion problem. Firstly, this application's signal acquisition device uses a computationally fast link protocol for radio frequency signal transmission between the first and second controllers. Compared to a software protocol stack, this protocol reduces repeated transmissions between the second and first controllers, moving data from the first controller's cache to its own cache. Data processing is performed directly from the first controller's cache, achieving cache consistency and reducing transmission latency. Secondly, the first controller is connected to an acceleration device. Unlike conventional solutions where the first controller's memory and computing power resources are fixed, this application allows for flexible use of the acceleration device, enabling real-time expansion of memory based on the amount of radio frequency signal data and the corresponding computing load. This ensures both memory and computing power expansion. Secondly, based on the number of antenna arrays to which the radio frequency signal belongs, the baseband data is processed using the CXL.io protocol to obtain multi-channel baseband data. Compared to traditional serial wireless transmission, this application combines the antenna array with CXL multi-channel to achieve end-to-end parallel transmission, thereby reducing transmission latency. Finally, considering the usage of the acceleration device, compared to conventional solutions where data volume has already flowed into the local memory of the first controller before calculating the memory space and comparing it with a fixed remaining memory threshold to see if it is sufficient for storage, leading to data congestion as subsequent radio frequency signal data flows in while data not yet stored in local memory awaits calculation results, this application can characterize the amount of data per unit time by using the real-time bandwidth (actual bandwidth) of the radio frequency signal before it is stored in local memory. This allows for prediction of the acquisition duration. For sudden acquisition scenarios such as radar echoes with large volumes of data, the acceleration device can be called in advance to prevent data congestion caused by the influx of subsequent radio frequency signal data while the radio frequency signal is waiting for calculation in the local memory. This achieves data transmission while also predicting the storage usage of local memory space in advance and calling the acceleration device in real time, avoiding data loss, improving data transmission efficiency, and enhancing the transmission reliability of the acquisition device.

[0062] Therefore, it can solve the technical problems of repeated transmission of radio frequency signals, data congestion and omission caused by large-volume data acquisition and limited memory of acquisition devices. It achieves the following: radio frequency signal transmission between the first controller and the second controller is carried out using a fast computation link protocol. In addition, the CXL.io protocol is combined with the antenna array of radio frequency signals to realize parallel transmission of multi-channel processing. During transmission, the predicted acquisition time supported by the actual remaining local memory is predicted in advance based on the actual bandwidth, so as to determine the flexible matching and calling of the acceleration device, save the waiting time of data at the beginning of transmission and during transmission and storage, avoid congestion and omission, improve transmission efficiency and improve the reliability of signal acquisition devices.

[0063] In some embodiments, the baseband data is processed using the input / output protocol of the fast link protocol multi-channel processing according to the number of antenna arrays to which the radio frequency signal belongs, to obtain multi-channel baseband data, including:

[0064] Determine the number of antenna arrays to which the radio frequency signal belongs;

[0065] Multiple channel data are obtained by mapping the baseband data corresponding to the number of antenna arrays with the multiple channels of the input / output protocol.

[0066] The data from each channel is marked with transactions and subject to credit flow control to obtain multi-channel baseband data.

[0067] Specifically, in real-time signal acquisition scenarios of Multiple-Input Multiple-Output (MIMO) systems, signals received by multiple antennas are processed by the FPGA baseband to form multiple baseband data streams. These data streams need to be transmitted efficiently to meet real-time requirements. To address this need, a parallel transmission strategy based on CXL.io multi-channels can be designed. Specifically, each baseband data stream is mapped to an independent CXL.io channel for transmission, achieving true hardware-level parallelism.

[0068] Each mapped channel independently performs transaction marking and credit flow control to ensure orderly data transmission. This parallel transmission method features low latency and high bandwidth, which can fully match the characteristics of multi-antenna parallel processing in MIMO systems and meet the real-time transmission requirements of high-speed baseband data.

[0069] This embodiment provides a method to map baseband data based on the number of antenna arrays to multiple channels of the CXL.io protocol to obtain multi-channel baseband data. This method efficiently combines baseband processed data with CXL.io multi-channels to achieve high-bandwidth, low-latency parallel transmission, meeting the data transmission requirements of large-scale antenna array systems.

[0070] In some embodiments, when the number of antenna arrays is one, multiple channel data are obtained by mapping baseband data with multiple channels of input / output protocols, including:

[0071] Get the preset length of the data stream;

[0072] The baseband data stream is divided into multiple sub-data streams based on the preset length of the data stream.

[0073] Multiple sub-data streams are polled and distributed to multiple channels of the input / output protocol to complete the mapping process between the data streams and multiple channels, thereby obtaining data from multiple channels.

[0074] Specifically, the baseband data stream is fragmented into multiple sub-data streams according to a preset length, and then distributed to multiple CXL.io channels in a round-robin fashion. Fragmentation sequence numbers and reassembly information need to be added to the data frames to complete the corresponding mapping mechanism. The preset length of the data stream can be fixed or adjusted according to actual conditions; no specific limitation is made here.

[0075] This embodiment provides a segmented mapping method that divides the baseband data stream according to a preset data stream length to obtain multiple sub-data streams, making full use of multi-channel bandwidth and improving parallel transmission efficiency.

[0076] In some embodiments, when there are multiple antenna arrays, multiple channel data are obtained by mapping baseband data with multiple channels of input / output protocols, including:

[0077] Multiple channel data are obtained by mapping the baseband data corresponding to each of the multiple antenna arrays to the input and output multiple channels.

[0078] Specifically, the baseband data corresponding to each antenna is directly mapped to an independent CXL.io channel. In the scenario where the number of antennas in the MIMO system matches the number of CXL channels, the mapping process is performed directly.

[0079] This embodiment provides a method to map the baseband data corresponding to each of the multiple antenna arrays to the input and output channels to obtain multiple channel data. The mapping relationship is simple and facilitates subsequent signal reassembly. The CXL timestamp mechanism is used to achieve accurate synchronization of multi-channel data and improve the effective transmission efficiency.

[0080] In some embodiments, the predicted acquisition duration supported by the actual remaining memory of the controller is determined in advance based on the actual bandwidth of the radio frequency signal and the amount of cached data of the first controller, including:

[0081] The actual bandwidth of the radio frequency signal and the amount of cached data in the local memory of the first controller are obtained;

[0082] The actual increase in data volume of the radio frequency signal per unit time at the acquisition rate is determined based on the actual bandwidth of the radio frequency signal.

[0083] The predicted acquisition duration is determined based on the actual amount of data added and the amount of data already cached in the local memory of the first controller, based on the actual remaining memory.

[0084] Specifically, the actual bandwidth of the radio frequency (RF) signal is the instantaneous bandwidth of the data acquisition device per unit time, which is also the bandwidth of the actual data stream. The amount of cached data in the local memory of the first controller is the amount of memory already occupied by the first controller in this current operation. The actual increase in data corresponding to the RF signal per unit time under the acquisition rate is determined based on the actual bandwidth of the RF signal; these two data are equivalent. The predicted acquisition duration supported by the actual increase in data and the cached data amount is determined based on the actual remaining memory of the first controller's local memory. The actual remaining memory of the first controller's local memory is the amount of remaining memory that can be used to continue storing the acquired data. The predicted acquisition duration is the maximum predicted data acquisition time for multiple channels of baseband data that the remaining space can support under the current bandwidth.

[0085] The process for determining the predicted acquisition duration provided in this embodiment achieves high-precision duration prediction, ensuring that memory resources are not wasted during data acquisition, nor is data loss due to memory exhaustion. The mechanism of using real-time bandwidth to drive dynamic thresholds allows the accelerator card startup timing to be precisely matched with the data generation rate.

[0086] In some embodiments, determining the predicted acquisition duration supported by the actual remaining memory of the first controller's local memory based on the actual increase in data volume and the amount of cached data includes:

[0087] The amount of remaining data corresponding to the actual remaining memory of the local memory of the first controller is determined based on the amount of cached data.

[0088] The predicted data collection time is obtained by dividing the remaining data volume by the actual increase in data volume.

[0089] Specifically, when the data stream bandwidth is stable and without fluctuations, and there is no additional memory usage (i.e., no other processes are writing to it), it is necessary to know the amount of data remaining in the local memory of the first controller. The predicted acquisition time is obtained by dividing the remaining data amount by the actual increase in data amount.

[0090] The process of dividing the remaining data volume and the actual increased data volume provided in this embodiment to obtain the predicted acquisition time can monitor memory editing in real time and provide early warning of risks, preventing data loss or overflow of subsequent multi-channel baseband data.

[0091] In some embodiments, the process of determining the actual increase in data volume further includes:

[0092] The bandwidth of each time corresponding to the preset acquisition interval before the current time is acquired according to the acquisition interval of the antenna of the signal acquisition device;

[0093] The average bandwidth is obtained by averaging the bandwidth at each time point.

[0094] Obtain the data stream bandwidth compression ratio;

[0095] The actual bandwidth is determined based on the data stream bandwidth compression ratio and average bandwidth, in order to determine the actual increase in data volume.

[0096] Specifically, in actual data acquisition scenarios, data stream bandwidth may fluctuate due to sudden data bursts or changes in channel quality, or be occupied by memory or other processes. Therefore, it is necessary to dynamically adjust the static actual bandwidth to obtain the actual bandwidth, which corresponds to the actual increase in data volume. The bandwidth at each preset acquisition interval before the current moment is collected based on the antenna acquisition interval of the signal acquisition device. The average bandwidth is obtained by averaging the bandwidth at each moment. Statistical characteristics of historical bandwidth data are used to replace the static bandwidth; either the average or peak value can be used. The average bandwidth can predict the duration, while the peak bandwidth provides a conservative prediction of the duration. If the acquired data supports real-time compression, such as lossless compression of radar data or H.264 compression of video data, the actual data volume of the data stream bandwidth will be less than the data volume corresponding to the original bandwidth. Therefore, a data stream bandwidth compression ratio is introduced. The actual bandwidth is determined by the data stream bandwidth compression ratio and the average bandwidth, and then the actual increase in data volume is further determined.

[0097] In the dynamic correction process based on actual bandwidth provided in this embodiment, compression ratio optimization is introduced to predict the acquisition time, avoiding the reduction in bandwidth accuracy caused by data stream bandwidth fluctuations, improving prediction accuracy, and ensuring that memory resources are not wasted or data is lost due to memory exhaustion during the data acquisition process.

[0098] In some embodiments, determining the matching and invocation of acceleration devices based on the relationship between the predicted acquisition duration and the preset acquisition duration includes:

[0099] If the predicted acquisition time exceeds the preset acquisition time, it is determined that some multi-channel baseband data is not stored in the actual remaining memory of the multi-channel baseband data transmitted to the first controller.

[0100] Obtain the target acceleration device to determine the matching call for the target acceleration device.

[0101] It should be noted that the predicted acquisition duration is based on the current actual bandwidth. If it exceeds the preset acquisition duration, it means that the local memory of the first controller cannot carry the multi-channel baseband data. In this case, there will be some multi-channel baseband data that is not stored in memory. At this time, it is necessary to obtain the target acceleration device for matching and calling.

[0102] The target acceleration device here can be the acceleration device that is closest to the first controller in the hardwired connection relationship, or it can be an acceleration device with the same memory space as the current multi-channel baseband data storage, or a suitable acceleration device from multiple dimensions such as space, computing power resources, etc. There are no restrictions here, and it can be set according to the actual situation.

[0103] This embodiment provides a process for triggering the target acceleration device based on the relationship between the predicted acquisition duration and the preset acquisition duration. This enables flexible access to the acceleration device, allowing it to be accessed at any time. At the same time, it improves the accuracy of the first controller's memory space usage and reduces the congestion time of multi-channel baseband data.

[0104] In some embodiments, when there are multiple acceleration devices, the first controller and the acceleration devices are connected via a switch, which is a multiplexer; the first terminal of the multiplexer is connected to the first controller, and the second terminal is connected to the multiple acceleration devices; the process of invoking the target acceleration device specifically includes:

[0105] The number of channels of the multiplexer is determined based on the number of acceleration devices, in order to determine the target number of channels of the multiplexer.

[0106] Pre-match the corresponding binary data of multiple acceleration devices;

[0107] Establish the first mapping relationship between binary data and the address control terminal of the target channel selector;

[0108] Establish a second mapping relationship between the address control terminal of the target channel selector and the input data terminal of the target channel selector;

[0109] When determining the target acceleration device to be matched and invoked among multiple acceleration devices, the call of the target path selector to the target acceleration device is determined according to the target binary data corresponding to the target acceleration device, the first mapping relationship and the second mapping relationship, so as to realize the access of the target acceleration device to the first controller.

[0110] Specifically, if there is only one acceleration device, simply closing the switch will directly connect it. If there are multiple acceleration devices, the selection of the target device can be determined either by using individual hardware switches or by using a multiplexer. The number of channels in the multiplexer is determined by the number of acceleration devices. A multiplexer uses circuit logic to select electrical paths without mechanical action, independent of the mechanical closing or opening of physical contacts.

[0111] The essence of a multiplexer is multiple inputs, single output. Selecting one channel relies on the cooperation of two components: the data input terminal and the address control terminal. The data input terminals (Input): typically labeled D0, D1, D2, D3, ..., Dn-1 (e.g., D0~D3 for a 4-channel MUX, D0~D7 for an 8-channel MUX), each corresponding to a raw data signal to be selected (which can be digital, analog, etc., depending on the MUX type). The address control terminal (Select): typically labeled S0, S1, ..., Sn-1, its input binary control signal determines which data channel is selected—the number of address bits k and the number of input channels n satisfy the following relationship: (For example, a 4-channel MUX requires a 2-bit address S0S1, and an 8-channel MUX requires a 3-bit address S0S1S2). When a specific binary code is input into the address control terminal, the multiplexer will electrically connect the data input terminal corresponding to that code with a single output terminal (usually marked Y). The remaining unselected input terminals will be disconnected from the output terminal, and only the selected data will be output from the output terminal.

[0112] A first mapping relationship is established between binary data and the address control terminal of the target path selector, and a second mapping relationship is established between the address control terminal of the target path selector and the input data terminal of the target path selector. Through the two mapping relationships, the call of the target acceleration device corresponding to the target path selector is determined.

[0113] The multiplexer provided in this embodiment acts as an intelligent gateway between the acceleration device and the first controller. Through flexible link switching, it solves the problems of resource conflicts, complexity, and scalability in the interconnection of multiple devices, while improving the reliability and real-time performance of the system.

[0114] In some embodiments, the process of acquiring the target acceleration device includes:

[0115] Obtain the memory space, computing resources, and memory cost of each of the multiple acceleration devices;

[0116] Each resource is pre-assigned a weight parameter based on its corresponding memory space, computing power resources, and memory cost; among them, the weight parameter of memory space is greater than the weight parameter of computing power resources, and the weight parameter of computing power resources is greater than the weight parameter of memory cost.

[0117] The first data for each of the multiple acceleration devices is obtained by summing their respective memory space, computing power resources, memory costs, and corresponding weight parameters.

[0118] The largest first data point is selected from the first data points corresponding to each of the multiple acceleration devices and used as the target first data point;

[0119] The acceleration device corresponding to the first target data is taken as the target acceleration device.

[0120] Specifically, for an acceleration device, memory space, computing power resources and memory costs can be comprehensively considered. Its core value lies in achieving optimal resource allocation and ensuring the feasibility and economy of tasks.

[0121] In this embodiment, the use of acceleration devices mainly focuses on expanding memory space while also incorporating computing resources and memory costs. To this end, corresponding weight parameters need to be allocated, with different weight parameters being allocated in the order of memory space weight parameter > computing resource weight parameter > memory cost weight parameter.

[0122] The dimensions and their corresponding weight parameters are summed to obtain the first data for each of the multiple acceleration devices. The first data with the largest value is selected as the target first data, and the acceleration device with the target first data is selected as the target acceleration device.

[0123] The target acceleration device provided in this embodiment is selected through three dimensions: memory space, computing power resources, and memory cost. This ensures that tasks can run normally on the device, avoids failures due to insufficient resources, improves the utilization rate of memory and computing power, reduces latency and energy consumption, and minimizes hardware and maintenance costs while meeting performance requirements. It also provides a basis for decision-making for dynamic scheduling and cluster management, and supports the large-scale expansion of the system.

[0124] In some embodiments, the process of acquiring the target acceleration device includes:

[0125] Receive data transmission instructions issued by the second controller;

[0126] The target data stream is determined according to the data transmission instructions; the data volume of the target data stream includes the data volume corresponding to the actual transmitted multi-channel baseband data and the data volume of the first baseband data corresponding to the uncollected radio frequency signal.

[0127] Obtain the memory space corresponding to each of the multiple acceleration devices;

[0128] The memory space corresponding to the target acceleration device is determined according to the memory occupied by the data volume of the target data stream in the memory space corresponding to each of the multiple acceleration devices, so as to obtain the target acceleration device.

[0129] Specifically, in this embodiment, the acquisition process of the target acceleration device is based on a data transmission command issued by the second controller, and the data volume of the target data stream corresponding to this command is clearly known. The data volume of the target data stream includes the data volume corresponding to the actual transmitted multi-channel baseband data and the data volume of the first baseband data corresponding to the uncollected radio frequency signals. Given that the data volume of the target data stream is known, an acceleration device with approximately the same data memory as the target data stream can be matched, thereby reducing resource waste and interaction.

[0130] Therefore, the memory space corresponding to the target acceleration device is determined in the memory space corresponding to each of the multiple acceleration devices according to the memory occupied by the target data stream, so as to obtain the target acceleration device.

[0131] This embodiment provides a criterion for calling the target acceleration device based on the principle that the data volume of the target data stream is approximately the same as the memory space of the acceleration device. This eliminates data segmentation and splicing overhead, improves processing efficiency, maximizes memory bandwidth utilization, and reduces access latency. It also avoids resource redundancy and reduces hardware and energy costs.

[0132] In some embodiments, the process of acquiring the target acceleration device includes:

[0133] If the radio frequency signal collected in the actual time interval corresponds to a tracking task and the tracking task has not ended, obtain the memory space corresponding to each of the multiple acceleration devices.

[0134] Select the largest memory space from the memory spaces corresponding to the multiple acceleration devices, and use the acceleration device with the largest memory space as the target acceleration device.

[0135] Specifically, although the purpose of this embodiment is the same as that of the above embodiments in acquiring the target acceleration device, the difference between this embodiment and the above embodiments is that this embodiment is based on the first controller receiving radio frequency signals, while the above embodiments are based on the instructions called by the second controller for data processing. In this embodiment, the radio frequency signal is triggered by the task type. If it is a tracking task without clear constraints (time, event, data volume) or when the target characteristics are dynamically uncontrollable, the total data volume is difficult to determine in advance. Data will be received continuously for a relatively long period of time. During the process of receiving radio frequency signals, the data volume of the tracking task cannot be known.

[0136] Therefore, if the radio frequency signal collected in the actual time interval can be identified as a tracking task, and the tracking task has not triggered task termination, it means that radio frequency data under the tracking task will be received next. It is necessary to select the acceleration device with the largest memory space from multiple acceleration devices as the target acceleration device to ensure that there is enough memory space to store the corresponding multi-channel baseband data.

[0137] The radio frequency signal type provided in this embodiment is used to select the acceleration device with the largest memory space during the tracking task. Resource redundancy is used to cope with the uncertainty of data volume, avoid task interruption due to insufficient memory, and ensure the continuity and real-time nature of data processing. The core pain point of the unknown total data flow of the tracking task is the inability to predict whether the data volume will exceed the memory limit of the acceleration device—by calling the device with the largest memory space, this uncertainty can be covered by memory redundancy, avoiding data overflow and loss, and using the redundancy of memory resources to obtain the certainty of the task result.

[0138] In some embodiments, after transmitting multi-channel baseband data to the invoked acceleration device, the method further includes:

[0139] Keep the data input terminal of the target channel selector corresponding to the target acceleration device open so that the multi-channel baseband data corresponding to the radio frequency signal collected in the next time interval of the actual time interval before the tracking task ends can be transmitted to the target acceleration device.

[0140] Specifically, in a typical multi-channel baseband data transmission process, after the multi-channel baseband data transmission under the current radio frequency signal is completed, this channel of the multiplexer will be closed so that when the next radio frequency signal arrives, it can be determined whether to call the acceleration device based on the actual bandwidth of the next radio frequency signal.

[0141] If the device is shut down before the tracking task is finished, it needs to be restarted to receive the next radio frequency signal. The above delay will cause the following: loss of initial data of the next signal (e.g., the device is not ready when the radio frequency signal arrives, and the data in the first few milliseconds has not been processed); and break in the time connection of multi-signal tracking (e.g., for radar tracking two targets that appear in succession, the initial position information of the second target is lost due to the device restart).

[0142] In this embodiment, considering that the radio frequency signal collected in the next time interval before the actual time interval ends belongs to the same tracking task as the current radio frequency signal, the data input terminal of the target channel selector corresponding to the target acceleration device is kept open until the multi-channel baseband data corresponding to the radio frequency signal collected in the next time interval is transmitted to the target acceleration device.

[0143] This embodiment provides a method to receive the next radio frequency (RF) signal before the tracking task has ended, without needing to shut down the acceleration device. This avoids the need to restart the device to receive the next RF signal, eliminating the time overhead and state fluctuations caused by device start-up and shutdown, and ensuring the continuity, real-time performance, and efficiency of multi-signal tracking. The device is always in a ready state, and can be directly connected to the processing link upon the arrival of a new RF signal, reducing signal response latency.

[0144] In some embodiments, after the multi-channel baseband data is transmitted to the invoked acceleration device, and before the second controller invokes the process, the method further includes:

[0145] Obtain the actual computing power resources corresponding to the first controller itself;

[0146] When the actual computing power resources do not reach the preset computing power resources, the processing task requirements corresponding to the radio frequency signals transmitted by the second controller are received.

[0147] The radio frequency signals are processed according to the requirements of the processing task to obtain the corresponding processing results;

[0148] The processing results are transmitted to the second controller.

[0149] Specifically, considering that the first controller can bear the computing power resources for data processing of the second controller, when the actual computing power resources of the first controller do not reach the preset computing power resources, it indicates that the computing power resources of the first controller are idle. Therefore, the first controller receives the processing task requirements corresponding to the radio frequency signals transmitted by the second controller; processes the radio frequency signals according to the processing task requirements to obtain the corresponding processing results, and then transmits the processing results to the second controller.

[0150] The main processor (second controller) typically handles core tasks such as multi-task scheduling and complex logical decision-making. If all the raw data transmitted from the first controller is processed by the main processor, it may waste computing power on repetitive calculations (such as signal filtering, Fast Fourier Transform (FFT), and data format conversion). These tasks are precisely the strengths of the first controller (hardware parallel architecture + low latency). By determining whether the first controller is idle and processing it in advance, the main processor can be freed from low-level data processing and focus on higher-order tasks (such as target recognition and decision output), thus achieving a clear division of computing power.

[0151] The processing procedure of the first controller for radio frequency signals in this embodiment is not limited; it can be the same as or different from the conventional solution.

[0152] This embodiment provides a method to dynamically utilize the idle computing resources of the first controller to preprocess data when the first controller's computing resources are idle, thereby optimizing heterogeneous computing resources, revitalizing the idle computing power of the first controller, reducing data interaction overhead, and improving end-to-end processing efficiency. It also dynamically adapts to load fluctuations, enhancing system flexibility.

[0153] In some embodiments, after the plurality of acceleration devices are connected to the first controller via a hardware switch, and before the hardware switch is closed, the method further includes:

[0154] The input / output protocol of the fast link protocol is used to receive hardware configuration instructions for multiple acceleration devices sent by the second controller.

[0155] The hardware configuration information corresponding to the hardware configuration command is sent to multiple acceleration devices to complete the initialization configuration.

[0156] Specifically, in this embodiment, the core role of the second controller is configuration during the system startup phase. It does not interfere with the real-time signal processing flow. Connected to the first controller via the CXL protocol, it is responsible for running the operating system and upper-layer applications, and for further analysis and decision-making on the data processed by the first controller. During initialization, it sends basic hardware configuration instructions for the acceleration device, such as the hardware capability parameters of the accelerator card, to the first controller via the CXL.io protocol. The first controller then forwards these instructions to the accelerator card, completing the accelerator card initialization. During the system initialization phase, the second controller issues basic configuration instructions to the accelerator card through the first controller.

[0157] The process of initializing and configuring the acceleration device using the second controller provided in this embodiment ensures the compatibility, functional correctness, and optimal performance of the acceleration device and the host system. This guarantees system compatibility and avoids hardware interaction anomalies. It also adapts to task requirements, optimizes acceleration device performance, supports functional expansion and dynamic reconfiguration, and enhances system flexibility.

[0158] In some embodiments, transmitting multi-channel baseband data to the invoked acceleration device includes:

[0159] The corresponding difference duration is determined based on the predicted collection duration and the preset collection duration;

[0160] If the predicted acquisition time does not exceed the preset acquisition time and the difference time is less than the preset time, the target multi-channel baseband data that matches the target computing power resources will be selected from the multi-channel baseband data.

[0161] The target multi-channel baseband data is transmitted to the remaining memory of the first controller;

[0162] Transmit the multi-channel baseband data, excluding the target multi-channel baseband data, to the called acceleration device.

[0163] Specifically, if the predicted acquisition time does not exceed the preset acquisition time and the difference time is less than the preset time, it indicates that there is still some space in the local memory of the first controller, and the computing power resources of the first controller are greater than the computing power resources of the target acceleration device. Therefore, the target multi-channel baseband data that matches the target computing power resources is selected from the multi-channel baseband data. The target computing power resources correspond to the first controller, and the target multi-channel baseband data is transferred to the remaining memory of the first controller. The remaining multi-channel baseband data, excluding the target multi-channel baseband data, is transferred to the called acceleration device.

[0164] If all data is transmitted to the accelerator card, when the amount of data exceeds the accelerator card's computing power limit (such as excessive data volume in a single batch or too many concurrent tasks), it will cause the accelerator card to queue tasks and the processing latency to soar. By using the spare computing power of the first controller to share some of the data processing, the total load can be distributed to the dual path of the first controller and the target acceleration device, avoiding overload of a single device.

[0165] This embodiment takes into account that the computing power resources of the first controller are greater than those of the acceleration device. The target multi-channel baseband data will be processed on the remaining local memory of the first controller, while the remaining multi-channel baseband data will be transmitted to the acceleration device. This balances the resource load, reduces data migration overhead, improves the overall system efficiency, avoids overloading of the acceleration device, reduces transmission overhead, and utilizes the high local bandwidth.

[0166] Figure 5 A flowchart of receiving data based on a signal acquisition device is provided for an embodiment of this application, such as... Figure 5 As shown, this step includes:

[0167] S21: Start signal acquisition;

[0168] S22: Antenna receives radio frequency signals;

[0169] S23: The radio frequency signal undergoes frequency conversion, analog-to-digital conversion, and baseband processing to obtain baseband data, which is then buffered and transmitted.

[0170] S24: The first processor determines whether data transmission is required; if yes, proceed to step S25; otherwise, proceed to step S26.

[0171] S25: Utilize the computational fast link protocol to directly perform buffering processing on baseband data;

[0172] S26: Store baseband data on the hard drive;

[0173] S27: Perform signal identification and analysis on the baseband data, and proceed to step S26;

[0174] S28: End signal reception.

[0175] The data reception and processing flow is as follows: After the antenna receives the RF signal, it initiates signal acquisition, performs analog-to-digital conversion, and then performs baseband signal processing, including down-conversion and baseband signal sampling, and buffers the baseband signal. The second controller determines whether data processing is required. If so, it directly operates the baseband signal processing buffer using the CXL protocol to perform signal identification, analysis, and processing. Finally, the data is stored in memory, ending signal reception and transmission. The data processing decision is based on the second controller's task requirements, such as whether the baseband signal requires complex processing like modulation identification and protocol parsing, and system status such as the first controller's load rate and the second controller's idle computing power to determine whether intervention is necessary. If the baseband signal requires Artificial Intelligence (AI) algorithm processing, and the second controller has a trained model, or the first controller is fully loaded while the second controller has idle time, then the second controller is triggered to process the data. The process of the second controller operating the baseband buffer via CXL: The second controller uses the CXL.cache protocol to initiate read / write / invalidation requests to the HDM on the first controller side. Taking baseband signal identification as an example: The second controller sends a read request through CXL.cache to directly obtain the baseband data in the HDM; the second controller runs an AI algorithm to process the data, and then writes the result back to the HDM through a write request through CXL.cache; the entire process relies on CXL's cache consistency mechanism, and the Home Agent synchronizes the cache state with DCOH to ensure the consistency of the data accessed by the first controller and the second controller, and there is no redundant data copying.

[0176] Figure 6 This is a schematic diagram of a CXL protocol layering provided in an embodiment of this application, as shown below. Figure 6 As shown, the hierarchical structure is divided into physical layer, link layer, transport layer and application layer. Taking the first controller as FPGA and the second controller as CPU as an example, a full-stack hardware acceleration interconnection between FPGA and CPU is realized.

[0177] The physical layer comprises the CXL physical layer and the wireless physical layer. The CXL physical layer is responsible for establishing a high-speed, reliable physical connection between the FPGA and the CPU, providing fundamental electrical characteristics and signal integrity guarantees for data transmission. The wireless physical layer is responsible for the physical characteristics related to the transmission and reception of wireless signals, such as modulation and demodulation of radio frequency signals and signal strength control, ensuring reliable transmission of wireless signals over the air. After the radio frequency signals received by the wireless physical layer are converted into digital signals via AD conversion and demodulation, the high-speed serial transceiver inside the FPGA converts the digital signals into differential signals conforming to the CXL electrical specifications (e.g., using 4-Level Pulse Amplitude Modulation coding (PAM4) to support high-bandwidth transmission), providing the electrical carrier for CXL transmission.

[0178] CXL Logic Sublayer Physical Layer + Link Layer Logic: Physical Layer Submodule: Completes 8b / 10b encoding, clock recovery, and signal synchronization to ensure the stability of electrical signal transmission; Link Layer Submodule: Forms CXL transaction packets from digital data groups, adds check fields, and performs flow control to ensure that the digital data converted from wireless signals can be reliably and orderly transmitted through the CXL link.

[0179] Credit-based flow control and Cyclic Redundancy Check (CRC) verification are implemented at the link layer to ensure data transmission reliability. The CXL link layer uses a credit mechanism for flow control, with CXL.io and CXL.cache having independent credit pools. The credit cache caches message data, the IO credit pool manages control data, and the cache credit pool manages cached data, preventing interference between different data transmission types. CXL.cache is configured via the main processor, which sends configuration commands to the FPGA through the CXL.io protocol, setting the core parameters of the CXL.cache Request module: cache line size, such as 64B / 128B, to match the throughput characteristics of signal data. By dynamically adjusting the flow control strategy, credit resources are allocated rationally based on link status and data traffic to avoid data congestion and loss. The CRC verification mechanism performs error detection on the transmitted data, ensuring data integrity and accuracy.

[0180] The transaction layer supports three sub-protocols: CXL.io, CXL.cache, and CXL.mem, which are dynamically scheduled based on data type. Real-time signal data is rapidly transmitted to the FPGA via CXL.io, meeting the high-real-time data processing requirements. Intermediate processing results are cached in the CPU's shared memory via CXL.cache, facilitating rapid sharing and interaction of intermediate calculation results between the CPU and FPGA. Intermediate processing results, such as baseband data generated after the FPGA performs digital down-conversion and preliminary filtering of RF signals, are cached in the shared memory within the main processor module via the CXL.cache protocol. The specific process is as follows: After completing intermediate processing, the FPGA first writes the results to its local cache. Then, the DCOH integrated within the FPGA sends a cache line update notification to the Home Agent in the main processor module via the CXL.cache protocol. Upon receiving the notification, the Home Agent coordinates with the Host Memory to synchronously write the intermediate result cache line. This process relies entirely on the cache consistency mechanism of the CXL.cache protocol. This protocol defines the cache line state synchronization rules between the FPGA's Host Man cache and the host memory. When the FPGA updates intermediate results, the DCOH actively triggers a cache consistency transaction, enabling the Home Agent to detect data changes in real time, thereby ensuring that subsequent access to the Host by the CPU and other modules is not compromised. When using Memory, the latest intermediate results consistent with the FPGA's local cache can be obtained, avoiding signal processing errors caused by data inconsistency. Large-scale data storage is directly written to memory via CXL.mem, improving data storage and retrieval efficiency. The CXL.io sub-protocol is mainly used for the transmission of control information and small amounts of data between the FPGA and the CPU, such as configuration parameters and control commands. It provides a low-latency, high-reliability communication channel, ensuring that system control signals can be transmitted quickly and accurately. The CXL.cache sub-protocol focuses on cache consistency management and is suitable for intermediate calculation results with frequent interactions between the FPGA and the CPU. Through the cache consistency protocol, data consistency in the FPGA and CPU caches is maintained, avoiding errors and performance problems caused by data inconsistency. The FPGA can directly manipulate CPU cache lines through hardware logic, with extremely low synchronization latency, significantly improving upon traditional interrupt mechanisms. The CXL.mem sub-protocol is used for the storage and sharing of large-scale data, such as raw signal data and processed result data. It allows the FPGA to directly access the CPU's memory space, enabling fast data read and write, and improving the overall data processing capability of the system.

[0181] Application Layer: Provides a user-mode driver interface, supporting direct access to shared memory and reducing kernel-user mode data copy overhead. After the RF demodulated signal flows to the FPGA for baseband processing such as filtering and sampling, the baseband data is directly mapped to the CPU's virtual address space via the CXL.mem protocol. This allows application-layer programs to directly access and process the data through the CXL shared memory API. The process is as follows: The CXL physical layer establishes a high-speed electrical connection between the FPGA and the CPU, ensuring reliable data transmission; in the link layer, baseband data is grouped, checksums are added, and flow control is implemented to ensure lossless transmission; in the transaction layer, the FPGA-side HDM is exposed as remote memory directly accessible to the CPU via the CXL.mem protocol; Application Layer: The application calls the CXL shared memory interface to directly read and write baseband data in the remote memory, execute modulation recognition, protocol, and other application logic, ultimately achieving application-layer processing of the RF demodulated signal. Applications can conveniently perform data storage, task scheduling, signal recognition, and other operations through these interfaces to implement various complex functions and algorithms, such as signal modulation and demodulation in software-defined radio, and target detection and tracking in radar signal processing.

[0182] Regarding the interface design of the CXL protocol, it employs a high-speed serial interface, supporting multi-channel data transmission with a data transmission rate of up to 32Gbps per channel. Through parallel transmission across multiple channels, the system achieves ultra-high data bandwidth, meeting the demands of transmitting large amounts of concurrent data. Data transmission mechanism: The CXL protocol utilizes an advanced data transmission mechanism, including data packetization, flow control, and error detection. During transmission, data is segmented into fixed-size packets, each containing header information, payload, and checksum information. The flow control mechanism dynamically adjusts the data transmission rate to prevent data congestion and loss. Simultaneously, error detection ensures the accuracy and reliability of data transmission.

[0183] Figure 7 This application provides a schematic diagram of transaction layer message management for a CXL protocol structure, as shown in the embodiments of this application. Figure 7As shown, the transaction layer message type management demonstrates the layered structure and message type management of the CXL protocol within the system, from the application layer to the link layer. This includes the CXL.cache and CXL.mem interfaces, the transaction layer transaction message queue manager and flow control cache, and the implementation of the link layer. The CXL.cache protocol contains message types such as Device to Host (D2H) requests, D2H responses, D2H data, H2D requests, H2D responses, and H2D data, representing data transmission from FPGA device to host (D2H) and host to FPGA device (H2D). The CXL.mem protocol contains message types such as Memory to Storage (M2S) requests, M2S data, S2M responses, and S2M data, representing data transmission from memory to system (M2S) and system to memory (S2M). Through the CXL.cache and CXL.mem interfaces, the transaction layer breaks down the entire signal acquisition, processing, and storage process into precise message interactions, enabling coordination among each stage. D2H Interaction: After the FPGA processing module completes the RF signal to baseband digital signal conversion, it sends a data ready notification to the main processor via a D2H request. Subsequently, through a D2H data message, the Baseband In-phase and Quadrature Data (BIQD) is transmitted to the host memory via the CXL.cache protocol, in a format containing 1024 sample data points per packet (with metadata such as sampling timestamp and channel identifier (ID) in the header). Upon receiving the D2H response, the main processor immediately triggers the signal analysis task scheduling, ensuring that the data enters the analysis stage without delay. If adjustments to FPGA sampling parameters, such as sampling bandwidth and signal frequency, are needed, the main processor sends configuration commands via an H2D request, which are then transmitted to the FPGA configuration register via the CXL.cache protocol. After the FPGA completes the parameter update, it responds with a D2H response to confirm the configuration takes effect, ensuring real-time synchronization between the acquisition parameters and the processing logic. When the collected data needs to be stored for a long time, such as historical radar echo data, the main processor uses an M2S request and the CXL.mem protocol to write the baseband data temporarily stored in the host memory into the main memory with zero copy. Conversely, S2M data can read historical data from the storage module back to the host memory for the processor to quickly call during retrospective analysis, realizing the data flow of collection, storage and retrospective analysis.

[0184] The CXL protocol's memory sharing capability, through hardware-level address mapping and copy-free transmission, improves the efficiency of signal acquisition and processing. Direct memory communication between the FPGA and the main processor: The main processor, through its internal address mapping table, directly maps the baseband data buffer of the FPGA processing module and the FPGA's built-in 8GB High Bandwidth Memory 2 (HBM2) memory to the host's virtual address space. Signal analysis programs on the main processor can directly access the FPGA's cached baseband data via ordinary memory read / write instructions, eliminating the need for CPU-initiated data copy operations and reducing latency in acquisition and analysis. Dynamic scheduling of multi-module shared memory pools: The system can be divided into shared memory pools, such as 32GB of host memory + 8GB of FPGA HBM2. During peak acquisition traffic, such as when multiple antennas receive data simultaneously, the main processor dynamically expands the shared memory capacity accessible to the FPGA via the CXL.mem protocol, such as temporarily allocating 16GB of host memory to the FPGA for caching, preventing FPGA local cache overflow.

[0185] CXL's cache consistency protocol provides data consistency guarantees for multiple stages, including FPGA acquisition, main processor analysis, and storage modules. After the FPGA performs preliminary filtering on the baseband data and updates the cache, the CXL.cache protocol automatically synchronizes the cache state through interaction between the Home Agent in the main processor and the DCOH in the FPGA. When the main processor analysis module and the storage module access the same data, they always obtain the latest filtered data, avoiding the problem of using dirty data for analysis and old data for storage due to inconsistencies in the caches of multiple modules. A transaction-level consistency fault-tolerance mechanism: If a power outage occurs during signal acquisition when the FPGA cache is partially written, CXL's transactional memory access mechanism will trigger a rollback to ensure the integrity of the corresponding data in the host memory, avoiding data analysis anomalies caused by partial writes and ensuring the reliability of the acquired data.

[0186] The CXL data transmission mechanism's data packetization, flow control, and error detection are scenario-specifically adapted to the high-throughput, low-packet-loss requirements of signal acquisition. Data packetization adapts to the signal frame structure, grouping baseband data into units of signal frames. Each data packet header contains signal-specific metadata such as frame number, timestamp, and channel number, enabling downstream protocol parsing and identification modules to perform logical processing based on frames, aligning with the specific business characteristics of the signal. Dynamic flow control matches the acquisition bandwidth. When FPGA acquisition bandwidth experiences a sudden surge, the link-layer's credit flow control mechanism adjusts the data transmission rate in real time: if the FPGA-side buffer is insufficient, the transmission rate is automatically reduced to avoid data overflow; when the buffer is sufficient, the rate is increased to maximize the utilization of CXL's bandwidth, ensuring no data loss and no congestion during acquisition. Error detection covers key signal parameters: in addition to traditional CRC checksums, additional parameter verification fields are added for key signal acquisition metadata such as sampling timestamps and channel IDs. If verification fails, not only is data packet retransmission triggered, but the FPGA sampling module is also driven to re-acquire data for that time period, ensuring the accuracy of signal parameters from the source.

[0187] The CXL protocol enables resource sharing: It supports memory sharing, allowing FPGA processing modules and high-performance processor modules to share the same memory space. Through memory mapping and address translation mechanisms, the host can directly access the FPGA processing module's cache using memory space mapping, eliminating the need for data copying and transmission, significantly improving data processing efficiency. Simultaneously, to ensure data consistency when different modules access shared memory, the CXL protocol employs a cache consistency protocol. By monitoring cache status, it automatically updates and synchronizes data, ensuring that all modules access the latest data version.

[0188] CXL Protocol Low-Latency Communication: The CXL protocol utilizes hardware acceleration technology to reduce latency during data transmission. By establishing a dedicated hardware communication channel between the FPGA processing module and the high-performance processor module, data can be directly transmitted and processed at the hardware layer, without going through a complex software protocol stack, thus significantly reducing communication latency. The CXL protocol has undergone deep optimization of the communication protocol, reducing overhead and processing time, and improving communication efficiency.

[0189] Figure 8 This application provides a schematic diagram of the structure of a signal acquisition device that only receives radio frequency signals, as shown in the embodiment of the present application. Figure 8 As shown, it mainly includes an antenna, a radio frequency module, a first controller, a second controller, and a storage module. The baseband signal processing and processor are interconnected at high speed via the CXL protocol, enabling efficient data transmission and sharing. The antenna is responsible for receiving radio frequency signals in space and transmitting them to the radio frequency module.

[0190] RF Module: Amplifies, filters, and down-converts the RF signal received by the antenna, converting it into an intermediate frequency (IF) signal suitable for analog-to-digital (ADC) conversion. Analog-to-Digital Converter (ADC): Converts the analog IF signal output from the RF transceiver module into a digital signal, providing the foundation for subsequent digital signal processing. First Controller Processing Module: As the core digital signal processing unit, it is equipped with numerous logic units, digital signal processing (DSP) modules, and block RAM (BRAM). The first controller is programmed using a hardware description language (Verilog or VHDL) to implement signal processing functions such as digital down-conversion, filtering, and sampling. The first and second controllers are interconnected at high speed via the CXL protocol for efficient data transmission and sharing. Signal transmission between the first controller and the RF module uses other suitable interface protocols, such as Low-Voltage Differential Signaling (LVDS) or other dedicated high-speed interfaces. Second Controller: Connected to the first controller processing module via the CXL protocol, it runs the operating system and upper-layer applications, further analyzing and making decisions based on the data processed by the first controller. Storage Module: Used to store system programs, configuration files, and acquired signal data, ensuring long-term reliable data preservation.

[0191] Workflow: 1) Signal Acquisition Stage: The antenna in the RF module receives RF signals from the space. After amplification, filtering, and down-conversion by the RF front-end, the signal is converted into a digital signal by the ADC. This stage ensures complete signal acquisition and high-quality digital conversion, laying the foundation for subsequent processing. 2) Data Transmission Stage: The converted digital signal is transmitted to the first controller processing module through the ADC output interface (such as LVDS). The logic circuits inside the first controller perform preliminary processing on these signals. 3) Signal Processing Stage: The first controller, with its powerful parallel processing capabilities and abundant logic resources, processes the acquired digital signals in real time. The processing includes digital down-conversion, filtering, and sampling to extract the baseband signal. The DSP module inside the first controller efficiently executes complex digital signal processing algorithms, such as Fast Fourier Transform (FFT), to identify the spectral characteristics of the signal. 4) Data Buffering and Transmission Stage: The pre-processed baseband signal is transmitted to the memory area of ​​the second controller via the CXL.io protocol. The CXL.io protocol provides a high-speed serial interface and multi-channel transmission characteristics, ensuring fast data transmission. The second controller accesses the device memory (such as BRAM) in the first controller via the CXL.mem protocol to achieve data sharing and interaction. The CXL.cache protocol is used to maintain cache consistency between the first and second controllers to ensure data synchronization.

[0192] Key performance indicators: 1) Data transmission rate: Transmission rate from the first controller to the second controller: Through the CXL.io protocol, the single-channel data transmission rate can reach 32GT / s, meeting the requirements of high-speed data transmission. 2) Data transmission latency: The latency from the completion of processing by the first controller to the data transmission to the memory of the second controller is less than 100 nanoseconds, meeting the requirements of real-time signal processing. 3) Memory expansion and sharing: Through the CXL.mem protocol, the second controller can access the device memory in the first controller, realizing memory expansion and sharing, effectively improving the system's storage capacity and data processing efficiency.

[0193] Typical Application Scenario: In a 5G signal monitoring system, this embodiment enables real-time acquisition and monitoring of 5G New Radio (NR) signals. Through the efficient data transmission of the CXL protocol, the system can quickly transmit the acquired signal data to analysis software for spectrum analysis, signal quality assessment, and other operations. This efficient signal acquisition and reception capability allows the system to promptly detect and respond to changes in the wireless communication environment, providing strong support for network optimization and spectrum management.

[0194] Figure 9 A schematic diagram of a signal acquisition device including a call acceleration card for receiving radio frequency signals is provided as an embodiment of this application. Figure 9As shown, the system mainly includes an antenna, an RF module, a first controller, a second controller, a storage module, and an accelerator card. The first and second controllers are interconnected at high speed via the CXL protocol, and the accelerator card connects to both controllers via the CXL.io and CXL.cache / mem protocols to achieve efficient data transmission and sharing. The antenna is responsible for receiving RF signals from space. The RF module amplifies, filters, and down-converts the received RF signals, converting them into intermediate frequency (IF) signals. The digital-to-digital converter (ADC) within this module converts the analog IF signal output from the RF receiving module into a digital signal, providing the foundation for subsequent digital signal processing. The first controller, as the core digital signal processing unit, is equipped with numerous logic units, DSP modules, and BRAM. It programs the FPGA using a hardware description language to implement digital down-conversion, filtering, sampling, and other signal processing functions. The second controller, connected to the first controller via the CXL protocol, is responsible for running the operating system and upper-level applications, further analyzing and making decisions based on the data processed by the FPGA. The storage module stores system programs, configuration files, and acquired signal data. Acceleration Card: Connected to the first and second controllers via the CXL.io and CXL.cache / mem protocols, it provides additional computing resources and storage capacity to accelerate signal processing and data analysis tasks.

[0195] The first controller, as the core of the system's real-time processing, adds key functional modules adapted to the CXL accelerator card based on Embodiment 1. It supports three sub-protocols of the CXL protocol, CXL.io / CXL.cache / CXL.mem, and can directly establish a high-speed interconnect link with the accelerator card to achieve low-latency data interaction between devices. It is equipped with a load monitoring unit: it monitors the computing load of the first controller itself in real time, specifically the resource usage of the signal processing unit. When the load reaches a preset threshold, it automatically triggers the activation or deactivation of the accelerator card without external intervention. The data distribution submodule: based on the CXL protocol, it distributes the collected baseband data to the local memory of the first controller or the memory of the accelerator card according to real-time requirements, avoiding data congestion in a single module. The shared memory management unit: it coordinates the local memory of the first controller and the memory of the activated accelerator card to form a unified real-time shared memory pool for direct access by the first controller and the accelerator card.

[0196] As a dedicated coprocessing unit for the first controller, the accelerator card focuses on real-time coprocessing through direct connection to the first controller. Its core function is to supplement computing power and memory, adapting to real-time signal processing needs. The specific design includes: CXL slave controller: directly interconnected with the first controller's CXL master controller, achieving high-speed data interaction with the first controller through the CXL protocol. The accelerator card provides a large capacity of high-speed memory, which can be directly accessed by the first controller through the CXL.mem protocol, and is used to cache multi-channel baseband data distributed by the first controller; computing power unit: integrates dedicated signal processing hardware resources, which can assist the first controller in completing the real-time signal processing process and reduce the computing power pressure on the first controller; control submodule: receives enable / disable commands sent by the first controller through the CXL.io protocol, controls the start and stop of the accelerator card's memory and computing power unit, and simultaneously feeds back its own hardware status, such as memory idle status and computing power load status, to the first controller.

[0197] In this embodiment, the core role of the second controller is configuration during the system startup phase. It does not interfere with the real-time signal processing flow. It is connected to the first controller via the CXL protocol and is responsible for running the operating system and upper-layer applications. It further analyzes and makes decisions on the data processed by the first controller. During initialization, it sends basic hardware configuration instructions for the accelerator card, such as the hardware capability parameters of the accelerator card, to the first controller via the CXL.io protocol. The first controller then forwards these instructions to the accelerator card to complete the accelerator card initialization. For non-real-time data interaction, it does not directly transmit data with the accelerator card. Instead, it reads processed non-real-time data from the real-time shared memory pool of the first controller via the CXL.mem protocol for subsequent analysis or storage. For peripheral management, it interfaces with storage modules, Ethernet, and other peripheral interfaces to achieve persistent storage or remote transmission of non-real-time data.

[0198] The accelerator card design is based on the core logic of a first controller leading the real-time process, with a second controller only participating in initialization. Regarding interaction boundaries, only during system initialization does the second controller issue basic configuration commands to the accelerator card through the first controller. Once in the real-time phase, the second controller no longer sends any control commands, and the accelerator card's processed data flows only between the first controller and the accelerator card in real time. The second controller can only indirectly read non-real-time data through the first controller's real-time shared memory pool. In terms of control permission allocation, real-time control operations such as enabling and disabling the accelerator card, defining data distribution rules, and allocating memory access permissions are entirely led by the first controller via the CXL.io protocol. The response latency is well-suited to the low-latency requirements of real-time signal processing. The second controller only assists by providing basic hardware parameters for the accelerator card during the initialization phase; once configuration is complete, control is fully transferred to the first controller. In the memory management mechanism, the second controller, through the CXL device enumeration mechanism, obtains the memory information (including capacity, access address, etc.) of the first controller and accelerator cards during system initialization and generates a mapping table. This mapping table is only updated when the number of accelerator cards changes. During real-time operation, memory allocation is dynamically scheduled from the real-time shared memory pool by the first controller based on signal processing requirements and the memory availability of the accelerator cards. The core function of the accelerator card hardware switch is to control the enabling and disabling of memory sharing: when the switch is closed, the accelerator card memory accesses the real-time shared memory pool, thus enabling data storage and access capabilities. Memory sharing is a prerequisite for data transmission; only after the switch is closed can the first controller transmit data to the accelerator cards via the CXL protocol. If the switch is open, the data transmission link is automatically interrupted.

[0199] Equipment Workflow: 1) System Initialization Phase: The second controller sends the basic configuration parameters of the accelerator card to the first controller via the CXL.io protocol. After receiving the parameters, the first controller forwards them to the control submodule of the accelerator card to complete the hardware initialization of the accelerator card. After the accelerator card initialization is completed, it feeds back its basic information such as memory capacity and computing power resources to the first controller via the CXL.io protocol. The first controller summarizes the information and reports it to the main processor. The second controller generates a system memory mapping table based on the reported information, records the access addresses and permissions of the memory of the first controller and the accelerator card, and synchronizes it to the first controller. The initialization process ends, and the real-time signal processing phase begins. 2) Signal Acquisition and Reception Phase: The RF module receives RF signals and converts them into digital signals. These signals are then transmitted to the first controller for preliminary processing via a high-speed interface (such as LVDS or other high-speed interfaces). The baseband signal is extracted and cached in shared memory. 3) Real-time Signal Acquisition and Preliminary Processing by the First Controller: The antenna receives multi-channel wireless signals. After processing by the RF module, the signals are converted into digital signals and transmitted to the first controller. The first controller performs preliminary processing on the digital signals, such as filtering and down-conversion, to generate baseband signals. At the same time, the load monitoring unit monitors its own computing power load in real time. 4) Accelerator Card Activation Judgment and Triggering: If the first controller's load monitoring unit detects that its own computing power is insufficient to meet the current processing requirements of multi-channel baseband signals (e.g., the load reaches a preset threshold), it sends an activation command to the accelerator card's control submodule via the CXL.io protocol. After parsing the command, the accelerator card control submodule closes the hardware switch (the master switch for controlling memory access), connects the accelerator card's memory to the first controller's real-time shared memory pool, and simultaneously starts the computing power unit, reporting a ready status to the first controller. 5) Data Distribution and Co-processing under the CXL Protocol: Based on the real-time requirements of the baseband signals, the first controller's data distribution submodule distributes baseband data from different channels to corresponding memory areas via the CXL.cache protocol: signals with extremely high real-time requirements are retained in the first controller's local memory, while other multi-channel signals are written to the accelerator card's memory. The accelerator card reads the allocated baseband data via the CXL.mem protocol, performs real-time processing using its own computing power unit, and writes the processing results directly back to the first controller's real-time shared memory pool via the CXL.cache protocol, without the need for a second controller. 6) Data Aggregation and Subsequent Processing: The first controller aggregates its own and the accelerator card's processing results. If non-real-time analysis is required, the data is temporarily stored in a designated area of ​​the real-time shared memory pool. The second controller reads real-time data from this designated area via the CXL.mem protocol for further analysis or storage in the external storage module. If the first controller's load monitoring unit detects a decrease in signal processing demand (load below a preset threshold), it sends a disable command to the accelerator card via the CXL.io protocol. The accelerator card disconnects its hardware switch, stopping the computing unit. The second controller further analyzes and makes decisions on the processed data and stores it in the storage module.The second controller can also transmit data to other devices via peripheral interfaces such as Ethernet, USB, and HDMI.

[0200] Key performance indicators (taking FPGA as the first controller and host as the second controller as an example): 1) System throughput: The system's signal reception and processing single channel reaches 32GT / s, supporting high data rate communication requirements. 2) Data transmission latency: Utilizing the CXL protocol to reduce transmission latency can be effectively applied to tasks implementing reception and processing. The transmission latency from FPGA to host processor via the CXL.io protocol is less than 100 nanoseconds. Similarly, through the CXL protocol, the data transmission latency between the accelerator card and the host processor can be less than 100 nanoseconds, achieving heterogeneous acceleration, reducing data interaction latency between devices. Simultaneously, the FPGA dominates accelerator card control, avoiding latency losses caused by the host processor acting as a relay. The host does not interfere with the real-time process, reducing the risk of failure caused by multi-module interaction. Furthermore, the memory sharing mechanism of the CXL protocol reduces data copy redundancy. 3) Memory expansion and sharing: The accelerator card provides additional storage resources through the CXL.cache / mem protocol for shared memory. The host processor can access the memory in the accelerator card to realize memory expansion and sharing, effectively improving the system's storage capacity and data processing efficiency. The accelerator card directly supplements the FPGA's computing power and memory, adapts to the real-time processing requirements of multi-channel high-frequency bandwidth signals, and supports dynamic start and stop based on load.

[0201] A typical application scenario is in software-defined radio base stations, where this embodiment enables efficient signal reception and processing for multiple user devices. The base station efficiently collects and processes signals from different users via the CXL protocol, while the accelerator card provides additional computing resources to ensure rapid signal processing and analysis. This efficient signal reception and processing capability allows the base station to support more user connections and higher data transmission rates, improving the performance of the wireless communication network and the user experience.

[0202] like Figure 3As shown, the system mainly includes an antenna, an RF module, a first controller, a second controller, an accelerator card, and a storage module. A transmission function is added, and the modules are interconnected at high speed via the CXL protocol to achieve efficient data transmission and sharing, as well as accelerated processing. The antenna and RF module are responsible for signal acquisition, conversion, and transmission. The RF transceiver module receives RF signals through the antenna, converts them into digital signals via an ADC, and simultaneously, the DAC converts the processed digital signals into analog signals, which are then transmitted through the RF transceiver module and the antenna. The first and second controllers are interconnected at high speed via the CXL protocol. The accelerator card connects to the first controller via the CXL.io and CXL.cache / mem protocols to achieve efficient data transmission and sharing. The first controller performs baseband signal processing on the initially converted digital signals, including modulation, demodulation, and filtering, and caches the processed data in shared memory. The second controller is responsible for the overall control and management of the system, including task scheduling and data transmission.

[0203] System Workflow: System Initialization Phase: The main processor sends the basic configuration parameters of the accelerator card to the first controller via the CXL.io protocol. After receiving the parameters, the first controller forwards them to the control submodule of the accelerator card, completing the hardware initialization of the accelerator card. After the accelerator card initialization is complete, it feeds back its basic information such as memory capacity and computing resources to the first controller via the CXL.io protocol. The first controller summarizes this information and reports it to the main processor. Based on the reported information, the main processor generates a system memory mapping table, adds a record of the transmit data buffer address, records the access addresses of the first controller and the accelerator card memory, and synchronizes it to the first controller. The initialization process ends, and the real-time signal processing and transmission phase begins. The signal acquisition and reception phase, real-time signal acquisition and preliminary processing by the first controller, accelerator card activation judgment and triggering, and data splitting and coprocessing under the CXL protocol are the same as in the above embodiment and will not be repeated here.

[0204] Signal generation and transmission stage: The first controller reads the processed signal data from the real-time shared memory pool. The accelerator card writes the signal transmission data into the shared memory pool through the CXL.mem protocol. The internal transmission link control submodule adjusts the transmission parameters, such as the modulation method and transmission power, to generate a digital transmission signal. The digital transmission signal is transmitted to the DAC module, which converts the digital signal to an analog signal and then transmits it to the transmission unit of the RF transceiver module. The RF transceiver module amplifies and up-converts the analog signal and finally transmits it through the antenna.

[0205] Data aggregation and subsequent processing: The first controller aggregates its own and the accelerator card's processing results. If non-real-time analysis is required, it is temporarily stored in a designated area of ​​the real-time shared memory pool. The main processor reads real-time data from this designated area through the CXL.mem protocol, including processing results and transmission signal logs, for subsequent analysis or storage to the external storage module.

[0206] Key performance indicators: 1) Deep learning inference latency: The accelerator card's latency for deep learning processing of baseband signals is less than 100 nanoseconds, meeting the requirements for real-time signal recognition and processing. 2) Computation speedup: Compared to CPU processing alone, the accelerator card significantly improves the speed of deep learning processing, substantially enhancing the system's processing efficiency. 3) Signal generation and transmission latency: The total latency from generating a new signal from the recognition result to transmission is less than that of traditional architectures, ensuring the system's real-time performance and effectiveness.

[0207] A typical application scenario is in cognitive adversarial systems. This embodiment can acquire enemy communication signals in real time and quickly exchange data with an accelerator card via the CXL protocol interface, executing deep learning algorithms to rapidly classify and identify the signals. Based on the identification results, the system generates new signals for communication or to interfere with enemy communications. This rapid and accurate signal processing and generation capability enables the system to effectively perform monitoring, detection, and jamming tasks in complex electromagnetic environments.

[0208] The above embodiments fully demonstrate the technical advantages and practicality of this application in cognitive adversarial systems, and also reflect the great potential of the CXL protocol in signal acquisition, processing and generation systems.

[0209] Furthermore, this application also provides a signal acquisition device, including an antenna, a radio frequency module, a first controller, and a second controller, wherein the first controller and the second controller transmit data using a computationally fast link protocol, and the first controller is connected to an acceleration device;

[0210] The antenna receives radio frequency signals;

[0211] Radio frequency (RF) modules are used to convert RF signals from analog to digital form.

[0212] The first controller is used to execute the steps of the above-described radio frequency signal transmission method to realize the transmission of radio frequency signals so that the second controller can call and process them.

[0213] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0214] Embodiments of this application also provide a radio frequency signal transmission device. Figure 10 This is a schematic diagram of a radio frequency signal transmission device provided in an embodiment of this application, as shown below. Figure 10 As shown, the device includes:

[0215] Acquisition module 11 is used to acquire baseband data obtained by baseband processing of radio frequency signals;

[0216] Processing module 12 is used to perform multi-channel processing of the input / output protocol of the fast link protocol on the baseband data according to the number of antenna arrays to which the radio frequency signal belongs, and obtain multi-channel baseband data.

[0217] The determination module 13 is used to determine the predicted acquisition duration supported by the actual remaining memory of the first controller based on the actual bandwidth of the radio frequency signal and the amount of cached data of the first controller;

[0218] The calling module 14 is used to determine the matching call of the acceleration device based on the relationship between the predicted acquisition duration and the preset acquisition duration, and to transmit the multi-channel baseband data to the called acceleration device so that the second controller can call and process it.

[0219] For a description of the features in the corresponding embodiment of the device, please refer to the relevant description of the corresponding embodiment of the radio frequency signal transmission method, which will not be repeated here.

[0220] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described radio frequency signal transmission method embodiments.

[0221] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described radio frequency signal transmission method embodiments when it is run.

[0222] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0223] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described radio frequency signal transmission method embodiments.

[0224] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described radio frequency signal transmission method embodiments.

[0225] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0226] The above provides a detailed description of a radio frequency signal transmission method, device, medium, and product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A radio frequency signal transmission method, characterized in that, A first controller is applied to a signal acquisition device, wherein the first controller and a second controller of the signal acquisition device transmit data using a computationally fast link protocol, and the first controller is connected to an acceleration device; the method includes: Acquire baseband data obtained from baseband processing of radio frequency signals; The baseband data is processed using the input / output protocol of the fast link protocol multi-channel processing based on the number of antenna arrays to which the radio frequency signal belongs, to obtain multi-channel baseband data. The predicted acquisition duration supported by the actual remaining memory of the first controller is determined based on the actual bandwidth of the radio frequency signal and the amount of cached data of the first controller. The matching call for the acceleration device is determined based on the relationship between the predicted acquisition duration and the preset acquisition duration, and the multi-channel baseband data is transmitted to the called acceleration device so that the second controller can call and process it.

2. The radio frequency signal transmission method according to claim 1, characterized in that, Based on the number of antenna arrays to which the radio frequency signal belongs, the baseband data is processed using the input / output protocol of the fast link protocol multi-channel processing to obtain multi-channel baseband data, including: Determine the number of antenna arrays to which the radio frequency signal belongs; Multiple channel data are obtained by mapping the baseband data corresponding to the number of antenna arrays with the multiple channels of the input / output protocol. The data from each channel is then subjected to transaction marking and credit flow control to obtain multi-channel baseband data.

3. The radio frequency signal transmission method according to claim 2, characterized in that, When the number of antenna arrays is one, multiple channel data are obtained by mapping the baseband data with the multi-channel input / output protocol, including: Get the preset length of the data stream; The baseband data stream is divided into multiple sub-data streams according to the preset length of the data stream. Multiple sub-data streams are polled and allocated to the multiple channels of the input / output protocol to complete the mapping process between the data streams and the multiple channels, thereby obtaining multiple channel data.

4. The radio frequency signal transmission method according to claim 2, characterized in that, When there are multiple antenna arrays, multiple channel data are obtained by mapping the baseband data with the multiple channels of the input / output protocol, including: Multiple channel data are obtained by mapping the baseband data corresponding to each of the multiple antenna arrays to the input and output multiple channels.

5. The radio frequency signal transmission method according to claim 1, characterized in that, The predicted acquisition duration supported by the actual remaining memory is determined in advance based on the actual bandwidth of the radio frequency signal and the amount of cached data of the first controller, including: Obtain the actual bandwidth of the radio frequency signal and the amount of cached data in the local memory of the first controller; The actual increase in data volume of the radio frequency signal per unit time at the acquisition rate is determined based on the actual bandwidth of the radio frequency signal. The predicted acquisition duration supported by the actual remaining memory of the first controller's local memory is determined based on the actual increase in data volume and the cached data volume.

6. The radio frequency signal transmission method according to claim 5, characterized in that, The predicted acquisition duration supported by the actual remaining local memory of the first controller is determined based on the actual increase in data volume and the cached data volume, including: The amount of remaining data corresponding to the actual remaining memory of the local memory of the first controller is determined based on the amount of cached data. The predicted collection duration is obtained by dividing the remaining data amount by the actual increase in data amount.

7. The radio frequency signal transmission method according to claim 5, characterized in that, The process of determining the actual increase in data volume also includes: The bandwidth of each time corresponding to the preset acquisition interval before the current time is acquired according to the acquisition interval of the antenna of the signal acquisition device; The average bandwidth is obtained by averaging the bandwidth at each time point. Obtain the data stream bandwidth compression ratio; The actual bandwidth is determined based on the data stream bandwidth compression ratio and the average bandwidth, in order to determine the actual increase in data volume.

8. The radio frequency signal transmission method according to claim 1, characterized in that, Determining the matching and invocation of acceleration devices based on the relationship between the predicted acquisition duration and the preset acquisition duration includes: If the predicted acquisition time exceeds the preset acquisition time, it is determined that some multi-channel baseband data is not stored in the actual remaining memory of the multi-channel baseband data transmitted to the first controller. Obtain the target acceleration device to determine the matching call for the target acceleration device.

9. The radio frequency signal transmission method according to claim 8, characterized in that, When there are multiple acceleration devices, the first controller and the acceleration devices are connected by a switch, which is a multiplexer. The first end of the multiplexer is connected to the first controller, and the second end is connected to multiple acceleration devices; The process of invoking the target acceleration device specifically includes: The number of channels of the multiplexer is determined based on the number of acceleration devices, in order to determine the target number of channels of the multiplexer; Pre-match the corresponding binary data of multiple acceleration devices; Establish a first mapping relationship between the binary data and the address control terminal of the multiplexer for the target number of paths; Establish a second mapping relationship between the address control terminal of the target number of channels multiplexer and the input data terminal of the target number of channels multiplexer; When determining the target acceleration device to be matched and invoked among multiple acceleration devices, the call of the target path multiplexer for the target acceleration device is determined according to the target binary data corresponding to the target acceleration device, the first mapping relationship and the second mapping relationship, so as to realize the access of the target acceleration device to the first controller.

10. The radio frequency signal transmission method according to claim 9, characterized in that, The process of acquiring the target acceleration device includes: Receive data transmission instructions issued by the second controller; The corresponding target data stream is determined according to the data transmission instruction; wherein, the data volume of the target data stream includes the data volume corresponding to the actual transmitted multi-channel baseband data and the data volume of the first baseband data corresponding to the uncollected radio frequency signal; Obtain the memory space corresponding to each of the multiple acceleration devices; The memory space corresponding to the target acceleration device is determined in the memory space corresponding to each of the multiple acceleration devices according to the memory occupied by the data volume of the target data stream, so as to obtain the target acceleration device.

11. The radio frequency signal transmission method according to claim 9, characterized in that, The process of acquiring the target acceleration device includes: If the task type corresponding to the radio frequency signal collected in the actual time interval is a tracking task and the tracking task has not ended, obtain the memory space corresponding to each of the multiple acceleration devices. The largest memory space is selected from the memory spaces corresponding to the multiple acceleration devices, and the acceleration device to which the largest memory space belongs is selected as the target acceleration device.

12. The radio frequency signal transmission method according to claim 11, characterized in that, After transmitting the multi-channel baseband data to the invoked acceleration device, the process further includes: Keep the data input terminal of the multiplexer corresponding to the target channel number of the target acceleration device in the open state, so as to transmit the multi-channel baseband data corresponding to the radio frequency signal collected in the next time interval of the actual time interval before the tracking task ends to the target acceleration device.

13. The radio frequency signal transmission method according to claim 11, characterized in that, After the multi-channel baseband data is transmitted to the invoked acceleration device, before the second controller invokes the process, the method further includes: Obtain the actual computing power resources corresponding to the first controller itself; When the actual computing power resources do not reach the preset computing power resources, the processing task requirements corresponding to the radio frequency signal transmitted by the second controller are received; The radio frequency signal is processed according to the processing task requirements to obtain the corresponding processing result; The processing result is transmitted to the second controller.

14. The radio frequency signal transmission method according to claim 1, characterized in that, After multiple acceleration devices are connected to the first controller via a hardware switch, and before the hardware switch is closed, the method further includes: The input / output protocol of the computational fast link protocol receives hardware configuration instructions for multiple acceleration devices sent by the second controller. The hardware configuration information corresponding to the hardware configuration command is sent to multiple acceleration devices to complete the initialization configuration.

15. The radio frequency signal transmission method according to claim 1, characterized in that, Transmitting the multi-channel baseband data to the invoked acceleration device includes: The corresponding difference duration is determined based on the predicted acquisition duration and the preset acquisition duration; If the predicted acquisition time does not exceed the preset acquisition time, and the difference time is less than the preset time, then target multi-channel baseband data that matches the target computing power resources is selected from the multi-channel baseband data. The target multi-channel baseband data is transmitted to the remaining memory of the first controller; All multi-channel baseband data except the target multi-channel baseband data are transmitted to the called acceleration device.

16. A signal acquisition device, characterized in that, It includes an antenna, a radio frequency module, a first controller and a second controller, wherein the first controller and the second controller transmit data using a computation fast link protocol, and the first controller is connected to an acceleration device; The antenna receives radio frequency signals; The radio frequency module is used to convert the radio frequency signal from analog to digital form. The first controller is configured to execute the steps of the radio frequency signal transmission method according to any one of claims 1 to 15, and realize the transmission of radio frequency signals so that the second controller can call and process them.

17. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the radio frequency signal transmission method as described in any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the radio frequency signal transmission method as described in any one of claims 1 to 15.

19. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the radio frequency signal transmission method as described in any one of claims 1 to 15.

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