Network communication chip signal interference suppression processing method

Abstract

The application relates to the field of communication technology and discloses a network communication chip signal interference suppression processing method.The method comprises the following steps: collecting a local oscillator phase jitter sequence in real time through an on-chip phase noise monitoring unit; estimating a Doppler frequency shift and a channel coherence time based on the sequence; dynamically adjusting a phase-locked loop closed loop bandwidth; generating a phase compensation signal and jointly performing time-varying channel minimum mean square error equalization on the received baseband signal to eliminate inter-symbol interference.The system integrates five function modules of phase noise monitoring, channel parameter estimation, phase-locked loop bandwidth regulation, phase compensation generation and interference joint elimination.The application significantly reduces the bit error rate under high-speed movement through dynamic bandwidth reconstruction and high-precision phase compensation, meets the requirements of the 5G millimeter wave communication standard, and has the advantages of full-chip implementation, low delay and high robustness.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to a method for suppressing signal interference in network communication chips. Background Technology

[0002] As 5G and future 6G communication systems continue to evolve towards higher frequency bands, the millimeter-wave band, with its abundant bandwidth resources, has become a key carrier for achieving ultra-high-speed wireless transmission. As the core hardware for signal interaction between terminals and base stations, the performance of network communication chips in the millimeter-wave band directly determines the reliability and efficiency of the communication link. However, the propagation characteristics of millimeter-wave signals are extremely sensitive to phase stability. Phase noise generated by the chip's internal oscillator can severely disrupt the constellation structure of modulation signals such as Orthogonal Frequency Division Multiplexing (OFDM), leading to a significant increase in inter-symbol interference and consequently a sharp rise in the bit error rate at the receiver.

[0003] Phase noise suppression is a core component for ensuring the quality of millimeter-wave communication. Existing solutions generally rely on phase-locked loop (PLL) circuits to stabilize the local oscillator, filtering out high-frequency jitter components by setting a fixed loop bandwidth. This method can maintain basic performance in static or quasi-static channel environments, but in dynamic scenarios such as high-speed movement, multipath abrupt changes, or sudden interference, the fixed bandwidth cannot balance the contradiction between noise suppression and loop response speed: while a narrow bandwidth can effectively filter out phase jitter, it is difficult to track rapid channel changes; while a wide bandwidth improves tracking capability, it introduces more high-frequency noise, exacerbating symbol distortion.

[0004] Baseband processing units typically only execute traditional channel estimation and equalization algorithms, lacking proactive modeling and compensation mechanisms for the dynamic characteristics of phase noise. Real-world data shows that in typical application scenarios such as vehicle-mounted communication or high-speed drone flight, the existing combination of phase-locked loop (PLL) and fixed-parameter baseband processing often results in bit error rates exceeding the 3GPP standard limits by orders of magnitude.

[0005] Even with the introduction of post-processing error correction coding, it is difficult to fundamentally eliminate the systematic symbol shift caused by phase noise. Summary of the Invention

[0006] This invention provides a method for suppressing signal interference in network communication chips, aiming to solve the technical problem that in millimeter-wave band network communication chips, inter-symbol interference caused by phase noise leads to a significant increase in bit error rate, and that existing phase-locked loop technology uses a fixed bandwidth structure, which cannot dynamically adapt to channel changes, resulting in the measured bit error rate exceeding the communication standard limit in high-speed mobile scenarios.

[0007] This invention provides a method for suppressing signal interference in network communication chips, comprising: acquiring the phase jitter sequence of the local oscillator output signal in real time through a phase noise monitoring unit integrated inside the network communication chip; calculating the current channel coherence time and Doppler frequency shift estimate based on the phase jitter sequence; dynamically adjusting the closed-loop bandwidth parameter of the phase-locked loop according to the Doppler frequency shift estimate; using the adjusted phase-locked loop to perform phase tracking and correction on the carrier signal to generate a phase compensation signal; and performing joint inter-symbol interference cancellation processing on the phase compensation signal and the received baseband signal to output a demodulated data stream after interference suppression.

[0008] In one embodiment of the present invention, the phase noise monitoring unit includes a high-resolution time-to-digital converter and a phase difference calculation module; the high-resolution time-to-digital converter quantizes the zero-crossing time difference between the local oscillator output signal and the reference clock signal at a rate of not less than 1 billion samples per second to generate an original time error sequence; the phase difference calculation module performs a first-order difference operation on the original time error sequence to obtain a phase jitter sequence.

[0009] As one embodiment of the present invention, the calculation of the current channel coherence time and Doppler shift estimate specifically includes: performing a sliding window Fourier transform on the phase jitter sequence to obtain the phase noise power spectral density; identifying the frequency offset corresponding to the main lobe width in the phase noise power spectral density; substituting the frequency offset into the Doppler shift formula to inversely deduce the current relative motion velocity; and calculating the reciprocal of the channel coherence time based on the relative motion velocity and the carrier center frequency, and using this as the Doppler shift estimate.

[0010] As one embodiment of the present invention, the dynamic adjustment of the closed-loop bandwidth parameters of the phase-locked loop specifically includes: a preset closed-loop bandwidth mapping table, which defines the correspondence between the estimated Doppler frequency shift and the parameters of the phase-locked loop charge pump current, loop filter resistance, and capacitance; when the estimated Doppler frequency shift changes, the corresponding charge pump current value, resistance value, and capacitance value are retrieved from the closed-loop bandwidth mapping table; and the physical parameters of the phase-locked loop are updated to the retrieved parameter values ​​through an on-chip programmable current source and an adjustable RC network, thereby realizing the dynamic reconstruction of the closed-loop bandwidth.

[0011] In one embodiment of the present invention, the phase-locked loop includes a voltage-controlled oscillator, a phase detector, a charge pump, a loop filter, and a frequency divider; the operating frequency band of the voltage-controlled oscillator covers 28... Up to 39 The phase detector adopts a digital time-to-digital conversion structure, and its phase detection resolution reaches 10 picoseconds. The loop filter consists of a programmable resistor array and a switchable capacitor array. The resistor array contains 16 parallel metal-oxide-semiconductor field-effect transistor switched resistor units, each with a resistance of 500 ohms. The capacitor array contains 32 parallel metal-insulator-metal capacitor units, each with a capacitance of 20 femtofarads.

[0012] As one embodiment of the present invention, the generation of the phase compensation signal specifically includes: aligning the corrected phase value output by the adjusted phase-locked loop with the symbol timing information of the received signal; performing linear interpolation on the corrected phase value to generate a phase compensation sequence that corresponds one-to-one with the sampling points of the received baseband signal; the interpolation factor of the linear interpolation is determined by the ratio of the symbol rate to the phase-locked loop update rate.

[0013] As one embodiment of the present invention, the joint inter-symbol interference cancellation processing specifically includes: constructing a time-varying channel state matrix, each row of which is composed of the phase compensation sequence at the current symbol time and the estimated phase perturbation values ​​of the forward and backward symbols; performing a minimum mean square error equalization operation on the time-varying channel state matrix and the received baseband signal vector; updating the weight coefficients of the minimum mean square error equalization operation online through a recursive least squares algorithm, with the forgetting factor set to 0.995; and the equalization output result is the demodulated data stream after interference suppression.

[0014] As one embodiment of the present invention, the initial covariance matrix of the recursive least squares algorithm is set to the identity matrix multiplied by 1000; in each iteration, the prediction error is calculated first, then the gain vector is updated, and finally the covariance matrix and the equalizer tap coefficients are updated; the number of equalizer taps is 7, covering the time window of the current symbol and the three symbols before and after it.

[0015] In one embodiment of the present invention, before dynamically adjusting the closed-loop bandwidth parameter of the phase-locked loop, a smoothing filter is performed on the Doppler frequency shift estimate; the smoothing filter uses a third-order Butterworth low-pass filter with a cutoff frequency set to 50 Hz. It is used to filter out estimate jumps caused by transient channel fading.

[0016] In one embodiment of the present invention, the network communication chip is integrated into a fifth-generation mobile communication terminal device or a vehicle-mounted unit for vehicle networking; the chip is manufactured using a 28-nanometer complementary metal-oxide-semiconductor process; the local oscillator is a voltage-controlled oscillator based on a transformer feedback structure, and its phase noise is within... Frequency offset is lower than .

[0017] This invention provides a network communication chip signal interference suppression processing system, comprising: a phase noise monitoring unit for real-time acquisition of the phase jitter sequence of the local oscillator output signal; a channel dynamic parameter estimation unit for calculating the current channel coherence time and Doppler frequency shift estimate based on the phase jitter sequence; a phase-locked loop bandwidth adjustment unit for dynamically adjusting the closed-loop bandwidth parameter of the phase-locked loop according to the Doppler frequency shift estimate; a phase compensation generation unit for using the adjusted phase-locked loop to perform phase tracking and correction on the carrier signal to generate a phase compensation signal; and an inter-symbol interference joint cancellation unit for performing joint inter-symbol interference cancellation processing on the phase compensation signal and the received baseband signal to output a demodulated data stream after interference suppression.

[0018] In one embodiment of the present invention, the phase noise monitoring unit includes a high-resolution time-to-digital converter and a phase difference calculation module; the high-resolution time-to-digital converter quantizes the zero-crossing time difference between the local oscillator output signal and the reference clock signal at a rate of not less than 1 billion samples per second to generate an original time error sequence; the phase difference calculation module performs a first-order difference operation on the original time error sequence to obtain a phase jitter sequence.

[0019] In one embodiment of the present invention, the channel dynamic parameter estimation unit is configured to perform a sliding window Fourier transform to obtain the phase noise power spectral density, and identify the frequency offset corresponding to the main lobe width from it, and then back-calculate the Doppler frequency shift estimate.

[0020] In one embodiment of the present invention, the phase-locked loop bandwidth control unit has a built-in closed-loop bandwidth mapping table, which stores the correspondence between the estimated Doppler frequency shift and the phase-locked loop charge pump current, loop filter resistance and capacitance parameters; the phase-locked loop bandwidth control unit is also connected to an on-chip programmable current source and an adjustable RC network, used to update the phase-locked loop physical parameters according to the table lookup results.

[0021] In one embodiment of the present invention, the phase compensation generation unit includes a symbol timing alignment module, a linear interpolation module, and a phase sequence output buffer; the symbol timing alignment module receives a symbol boundary indication signal from the baseband processor; the linear interpolation module determines an interpolation factor based on the ratio of the symbol rate to the phase-locked loop update rate, and generates a phase compensation sequence synchronized with the sampling points of the received baseband signal.

[0022] In one embodiment of the present invention, the joint inter-symbol interference cancellation unit includes a time-varying channel state matrix construction module, a minimum mean square error equalizer, and a recursive least squares weight update module; the time-varying channel state matrix construction module receives a phase compensation sequence and an estimate of the phase perturbation of the preceding and following symbols; the minimum mean square error equalizer has 7 taps; and the recursive least squares weight update module updates the equalizer coefficients online with a forgetting factor of 0.995.

[0023] In one embodiment of the present invention, the system further includes a Doppler frequency shift smoothing filter module, which adopts a third-order Butterworth low-pass filter structure with a cutoff frequency of 50 Hz. It is connected between the channel dynamic parameter estimation unit and the phase-locked loop bandwidth control unit.

[0024] In one embodiment of the present invention, the network communication chip is implemented using a 28-nanometer complementary metal-oxide-semiconductor process, and its local oscillator is a transformer-feedback voltage-controlled oscillator. The phase noise at the frequency offset is lower than .

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] 1. This invention achieves high-precision online sensing of Doppler frequency shift by constructing a joint estimation mechanism for real-time phase noise monitoring and channel dynamic parameters; it introduces a dynamic bandwidth reconstruction architecture for the closed-loop phase-locked loop based on lookup table driving, which makes the response speed of the phase-locked loop strictly match the current channel coherence time, effectively suppressing phase tracking lag or noise amplification caused by bandwidth mismatch.

[0027] 2. By applying minimum mean square error equalization to the dynamic phase compensation signal and the received baseband signal under time-varying channel modeling, inter-symbol interference caused by residual phase noise is significantly reduced. In high-speed mobile scenarios, the measured bit error rate is reduced by more than two orders of magnitude compared to the traditional scheme using a fixed bandwidth phase-locked loop, meeting the bit error rate requirements of the fifth-generation mobile communication standard for millimeter-wave links at a mobile speed of 300 km / h. Furthermore, the entire processing is completed within the chip without external processor intervention, offering engineering advantages such as low latency, high integration, and strong robustness. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the overall technical solution architecture of the network communication chip signal interference suppression processing method proposed in this invention;

[0029] Figure 2 This is a schematic diagram of the core principle framework of dynamic reconstruction of the closed-loop bandwidth of the phase-locked loop based on phase noise monitoring and Doppler frequency shift estimation in this invention.

[0030] Figure 3 This is a logical flowchart of phase noise monitoring and channel dynamic parameter estimation in this invention;

[0031] Figure 4 This is a flowchart illustrating the logic flow of phase-locked loop bandwidth control and phase compensation signal generation in this invention.

[0032] Figure 5 This is a flowchart illustrating the logical flow of the joint inter-symbol interference cancellation process in this invention.

[0033] Figure 6 This is a schematic diagram of the multi-level interaction relationship and data flow of various functional units inside the network communication chip in this invention. Detailed Implementation

[0034] Please refer to Figures 1 to 6 This invention provides a method for suppressing signal interference in network communication chips, addressing the technical problem that inter-symbol interference caused by phase noise in millimeter-wave band communication leads to a significant increase in bit error rate (BER), and that existing phase-locked loop (PLL) technology, with its fixed bandwidth structure, cannot dynamically adapt to channel changes, resulting in a measured BER exceeding communication standard limits in high-speed mobile scenarios. The specific embodiments of this invention will be described in detail below with reference to the accompanying drawings.

[0035] The network communication chip signal interference suppression processing method includes the following steps: S1, real-time acquisition of the phase jitter sequence of the local oscillator output signal through a phase noise monitoring unit integrated inside the network communication chip; S2, calculation of the current channel coherence time and Doppler frequency shift estimate based on the phase jitter sequence; S3, dynamic adjustment of the closed-loop bandwidth parameter of the phase-locked loop according to the Doppler frequency shift estimate; S4, phase tracking and correction of the carrier signal using the adjusted phase-locked loop to generate a phase compensation signal; S5, joint inter-symbol interference cancellation processing of the phase compensation signal and the received baseband signal to output the demodulated data stream after interference suppression.

[0036] In step S1, the phase noise monitoring unit includes a high-resolution time-to-digital converter and a phase difference calculation module. The high-resolution time-to-digital converter quantizes the zero-crossing time difference between the local oscillator output signal and the reference clock signal at a rate of no less than 1 billion samples per second, generating an original time error sequence. This original time error sequence characterizes the instantaneous deviation of the local oscillator output signal relative to the ideal reference clock in the time domain. The phase difference calculation module performs a first-order difference operation on the original time error sequence to obtain a phase jitter sequence. The mathematical expression for the first-order difference operation is:

[0037]

[0038] in, Indicates the first The original time error at each sampling time, This represents the corresponding phase jitter value. This phase jitter sequence reflects the rate of phase change of the local oscillator output signal between adjacent sampling points and serves as the fundamental input data for subsequent channel dynamic parameter estimation. The high-resolution time-to-digital converter is set to a sampling rate of 1 billion times per second to ensure accurate capture of high-frequency components of phase noise in the millimeter-wave band, achieving a time resolution at the picosecond level, meeting the requirements for 28... Up to 39 High-fidelity sampling of phase jitter within the operating frequency band is required.

[0039] In step S2, the current channel coherence time and Doppler shift estimate are calculated based on the phase jitter sequence. This calculation first performs a sliding window Fourier transform on the phase jitter sequence to obtain the phase noise power spectral density. The length of the sliding window is set to 1024 sampling points, and the window sliding step size is 256 points to balance spectral resolution and temporal locality. The frequency shift corresponding to the main lobe width is identified in the phase noise power spectral density. The main lobe width is defined as the frequency span corresponding to the point where the power spectral density drops to half its peak value. This frequency shift is directly related to the Doppler spread characteristics of the channel. The frequency shift is then substituted into the Doppler shift formula to inversely calculate the current relative velocity. The Doppler shift formula is expressed as:

[0040]

[0041] in, This is the estimated value of the Doppler frequency shift. The relative speed between the terminal and the base station. At the speed of light, This is the carrier center frequency. In this embodiment, The value is 32 Based on the relative motion velocity and carrier center frequency, the reciprocal of the channel coherence time is calculated and used as an estimate of the Doppler frequency shift. Channel coherence time Compared with Doppler frequency shift estimates The relationship is:

[0042]

[0043] Therefore, the Doppler frequency shift estimate That is The ratio is a constant multiple, used to characterize the speed of the channel's time-varying characteristics. This estimate serves as the core basis for PLL bandwidth regulation.

[0044] Before performing step S3, a smoothing filter is applied to the Doppler frequency shift estimate. This smoothing filter uses a third-order Butterworth low-pass filter with a cutoff frequency set to 50 Hz. This filter is used to filter out Doppler frequency shift estimates caused by transient channel fading, multipath reflection, or sudden interference, ensuring the stability and continuity of bandwidth control commands. The filtered Doppler frequency shift estimate serves as the input signal to the phase-locked loop bandwidth control unit.

[0045] In step S3, the closed-loop bandwidth parameters of the phase-locked loop (PLL) are dynamically adjusted based on the estimated Doppler frequency shift. This adjustment process relies on a preset closed-loop bandwidth mapping table. This mapping table is generated during chip manufacturing through simulation and experimental calibration and is stored in on-chip non-volatile memory. The mapping table defines the correspondence between the estimated Doppler frequency shift range and the parameters of the PLL charge pump current, loop filter resistance, and capacitance. For example, when the estimated Doppler frequency shift is less than 10... At that time, the corresponding charge pump current is 50 microamps, the loop filter resistance is 8000 ohms, and the capacitor is 320 femtofarads; when the Doppler frequency shift estimate is between 10... Up to 50 Between these points, the charge pump current increases to 100 microamps, the resistance decreases to 4000 ohms, and the capacitance decreases to 160 femtofarads; when the estimated Doppler shift exceeds 50... At this point, the charge pump current is further increased to 200 microamps, the resistance is 2000 ohms, and the capacitance is 80 femtofarads. This mapping ensures that the closed-loop bandwidth of the phase-locked loop increases as the channel coherence time decreases, thereby matching the fast time-varying characteristics of the channel.

[0046] When the Doppler frequency shift estimate changes, the phase-locked loop (PLL) bandwidth control unit looks up the corresponding charge pump current, resistance, and capacitance values ​​from the closed-loop bandwidth mapping table. Subsequently, the PLL's physical parameters are updated to the looked-up values ​​using an on-chip programmable current source and an adjustable RC network. The programmable current source is driven by a digital control word, achieving an output current accuracy of 1 microamp; the adjustable RC network is controlled by a switching array, enabling discrete adjustment of the resistance and capacitance. The resistor array contains 16 parallel metal-oxide-semiconductor field-effect transistor (MOSFET) switched resistor units, each with a resistance of 500 ohms, for a total resistance range of 312.5 ohms to 8000 ohms; the capacitor array contains 32 parallel metal-insulator-metal (MIM) capacitor units, each with a capacitance of 20 femtofarads, for a total capacitance range of 20 femtofarads to 640 femtofarads. Through this mechanism, the dynamic reconstruction of the PLL's closed-loop bandwidth is achieved, ensuring its response speed strictly matches the current channel coherence time.

[0047] The phase-locked loop includes a voltage-controlled oscillator, a phase detector, a charge pump, a loop filter, and a frequency divider. The operating frequency band of the voltage-controlled oscillator covers... Up to 39 It adopts a transformer feedback structure, and its phase noise is in Frequency offset is lower than The phase detector adopts a digital time-to-digital converter structure, with a phase detection resolution of 10 picoseconds, enabling precise quantification of the phase difference between input signals. The frequency divider divides the high-frequency signal output from the voltage-controlled oscillator to the same frequency as the reference clock for comparison by the phase detector. The entire phase-locked loop constitutes a closed-loop control system, and its closed-loop bandwidth is determined by the charge pump current, the loop filter resistance, and the capacitor, expressed as:

[0048]

[0049] in, The closed-loop bandwidth angular frequency, For charge pump current, For voltage-controlled oscillator gain, This is the equivalent resistance of the loop filter. This is the equivalent capacitance. It can be dynamically adjusted. , , This can be achieved. Online reconstruction.

[0050] In step S4, the adjusted phase-locked loop (PLL) is used to perform phase tracking and correction on the carrier signal, generating a phase compensation signal. The PLL operates within the new closed-loop bandwidth, tracking the phase changes of the local oscillator output signal in real time and outputting a corrected phase value. This corrected phase value is output at intervals equal to the PLL's update period, typically once per millisecond. However, the sampling rate of the received baseband signal is much higher, typically hundreds of millions of times per second. Therefore, the corrected phase value needs to be aligned with the symbol timing information of the received signal. The symbol timing information is provided by the baseband processor, indicating the start boundary of each symbol.

[0051] Linear interpolation is performed on the corrected phase values ​​to generate a phase compensation sequence that corresponds one-to-one with the sampling points of the received baseband signal. The interpolation factor for linear interpolation is determined by the ratio of the symbol rate to the phase-locked loop (PLL) update rate. For example, if the symbol rate is 2 gigabits per second and the PLL update rate is 1000... Therefore, each update cycle contains 2 million symbol sampling points, and the interpolation factor is 2 million. The linear interpolation formula is:

[0052]

[0053] in, For the first The corrected phase value output by the secondary phase-locked loop The number of symbol sampling points in each update cycle. This is the index of the current baseband sampling point. This interpolation generates a continuous, smooth phase compensation sequence for subsequent interference cancellation.

[0054] In step S5, the phase compensation signal and the received baseband signal undergo joint inter-symbol interference cancellation processing, outputting a demodulated data stream after interference suppression. This process first constructs a time-varying channel state matrix. Each row of this time-varying channel state matrix is ​​composed of the phase compensation sequence at the current symbol time and the estimated phase perturbation values ​​of the preceding and following symbols. The estimated phase perturbation values ​​are obtained by local differential or prediction of the phase compensation sequence, reflecting the residual phase error between adjacent symbols. The dimension of the time-varying channel state matrix is... ,in To balance the length of the symbol blocks being processed, In this embodiment, the width of the front and rear symbol windows is half. =3, therefore the number of columns in the matrix is ​​7.

[0055] The time-varying channel state matrix and the received baseband signal vector are subjected to minimum mean square error (MSE) equalization. The goal of MSE equalization is to minimize the mean square error between the equalized output and the ideal transmitted symbol. The weight coefficients of the equalizer are updated online using a recursive least squares algorithm. The forgetting factor of the recursive least squares algorithm is set to 0.995 to balance the weights of historical data and new observation data. The initial covariance matrix is ​​set to the identity matrix multiplied by 1000 to ensure high adaptive sensitivity in the early stages of the algorithm.

[0056] In each iteration, the prediction error is first calculated, which is the difference between the received signal and the predicted value under the current weights. Then, the gain vector is calculated based on the prediction error and the covariance matrix. Finally, the covariance matrix and the equalizer tap coefficients are updated. The equalizer has 7 taps, covering the time window of the current symbol and the three symbols before and after it, effectively suppressing interference between symbols caused by phase noise. The equalization output is the demodulated data stream after interference suppression, and its bit error rate is significantly lower than that of the traditional fixed bandwidth scheme.

[0057] The network communication chip is integrated into fifth-generation mobile communication terminal equipment or vehicle-mounted units of the Internet of Vehicles, and is manufactured using a 28-nanometer complementary metal-oxide-semiconductor process. All functional units—including the phase noise monitoring unit, channel dynamic parameter estimation unit, phase-locked loop bandwidth control unit, phase compensation generation unit, and inter-symbol interference joint cancellation unit—are implemented within a single chip, requiring no external processor intervention, and possessing engineering advantages such as low latency, high integration, and strong robustness.

[0058] At the system level, the network communication chip signal interference suppression processing system includes a phase noise monitoring unit, a channel dynamic parameter estimation unit, a phase-locked loop bandwidth control unit, a phase compensation generation unit, and an inter-symbol interference joint cancellation unit. The phase noise monitoring unit, as previously described, consists of a high-resolution time-to-digital converter and a phase difference calculation module. The channel dynamic parameter estimation unit is configured to perform a sliding window Fourier transform, identify the main lobe width, and calculate the estimated Doppler frequency shift. The phase-locked loop bandwidth control unit has a built-in closed-loop bandwidth mapping table and connects an on-chip programmable current source and an adjustable RC network to update physical parameters. The phase compensation generation unit includes a symbol timing alignment module, a linear interpolation module, and a phase sequence output buffer to ensure that the phase compensation sequence is synchronized with baseband sampling. The inter-symbol interference joint cancellation unit includes a time-varying channel state matrix construction module, a seven-tap least mean square error equalizer, and a recursive least squares weight update module to complete the final interference suppression.

[0059] In addition, the system also includes a Doppler frequency shift smoothing filter module, which adopts a third-order Butterworth low-pass filter structure with a cutoff frequency of 50 Hz. It connects the channel dynamic parameter estimation unit and the phase-locked loop bandwidth control unit to improve the stability of bandwidth control.

[0060] In summary, this embodiment constructs a complete millimeter-wave communication interference suppression mechanism through five core steps: real-time phase noise monitoring, high-precision Doppler frequency shift estimation, dynamic reconstruction of phase-locked loop bandwidth, phase compensation sequence generation, and joint inter-symbol interference cancellation. In a high-speed mobile scenario of 300 km / h, the measured bit error rate is lower than [percentage missing]. It meets the requirements of the fifth-generation mobile communication standard, reducing bandwidth by more than two orders of magnitude compared to traditional fixed-bandwidth solutions. The entire processing flow is completed in a closed loop within the chip, with a response latency of less than 1 millisecond, making it suitable for high-dynamic vehicle-to-everything (V2X) and mobile broadband applications.

Claims

1. A method for signal interference suppression processing of a network communication chip, characterized in that, The application relates to a method for dynamically adjusting the closed-loop bandwidth of a phase-locked loop (PLL) based on the Doppler shift estimation value. The method comprises the following steps: Real-time acquisition of the phase jitter sequence of the local oscillator output signal by a phase noise monitoring unit integrated in the network communication chip; Calculation of the current channel coherence time and the Doppler shift estimation value based on the phase jitter sequence, which comprises the following steps: Sliding window Fourier transform of the phase jitter sequence to obtain the phase noise power spectral density; Identification of the frequency offset corresponding to the main lobe width in the phase noise power spectral density; Back calculation of the current relative motion speed by substituting the frequency offset into the Doppler shift formula; Calculation of the channel coherence time reciprocal based on the relative motion speed and the carrier center frequency, and taking the channel coherence time reciprocal as the Doppler shift estimation value; Dynamic adjustment of the closed-loop bandwidth parameters of the phase-locked loop according to the Doppler shift estimation value; Phase tracking and correction of the carrier signal by using the adjusted phase-locked loop to generate a phase compensation signal; Joint inter-symbol interference cancellation processing of the phase compensation signal and the received baseband signal to output the interference-suppressed demodulation data stream, which comprises the following steps: Construction of a time-varying channel state matrix, each row of the time-varying channel state matrix being composed of the phase compensation sequence at the current symbol time and the phase disturbance estimation values of the forward symbol and the backward symbol; Minimum mean square error equalization operation of the time-varying channel state matrix and the received baseband signal vector; The weight coefficient of the minimum mean square error equalization operation is updated online by using the recursive least square algorithm, and the forgetting factor is set to 0.995; 2. The network communication chip signal interference suppression processing method of claim 1, wherein The equalization output result is the interference-suppressed demodulation data stream. The phase noise monitoring unit comprises a high-resolution time-to-digital converter and a phase difference calculation module; the high-resolution time-to-digital converter quantizes the zero-crossing time difference between the local oscillator output signal and the reference clock signal at a rate not lower than 10 billion times per second to generate an original time error sequence; 3. The method of claim 2, wherein the method further comprises: The phase difference calculation module performs first-order difference operation on the original time error sequence to obtain the phase jitter sequence.

4. The method of claim 3, wherein the method further comprises: Before the dynamic adjustment of the closed-loop bandwidth parameters of the phase-locked loop according to the Doppler shift estimation value, the Doppler shift estimation value is subjected to a smoothing filtering process; the smoothing filtering process adopts a third-order Butterworth low-pass filter, and the cutoff frequency is set to 50 Hz. The dynamic adjustment of the closed-loop bandwidth parameters of the phase-locked loop according to the Doppler shift estimation value comprises the following steps: Preparation of a closed-loop bandwidth mapping table which defines the corresponding relationship among the Doppler shift estimation value, the charge pump current of the phase-locked loop, the resistance and capacitance parameters of the loop filter; When the Doppler shift estimation value changes, the corresponding charge pump current value, resistance value and capacitance value are found out from the closed-loop bandwidth mapping table; The physical parameters of the phase-locked loop are updated to the found parameter values by using the on-chip programmable current source and the adjustable resistance-capacitance network, so that the closed-loop bandwidth is dynamically reconstructed.

5. The method of claim 4, wherein the method further comprises: The phase-locked loop comprises a voltage-controlled oscillator, a phase detector, a charge pump, a loop filter and a frequency divider; the working frequency band of the voltage-controlled oscillator covers 28 GHz to 39 GHz; the phase detector adopts a digital time-to-digital conversion type structure, and the phase detection resolution reaches 10 picoseconds; the loop filter is composed of a programmable resistance array and a switchable capacitance array, wherein the resistance array comprises 16 metal oxide semiconductor field effect transistor switch resistance units connected in parallel, and the resistance of each unit is 500 ohms; and the capacitance array comprises 32 metal-insulator-metal capacitance units connected in parallel, and the capacitance of each unit is 20 femtofarad.

6. The method of claim 5, wherein the method further comprises: The phase-locked loop is used for phase tracking and correction of the carrier signal, and generates a phase compensation signal, comprising: aligning the corrected phase value output by the adjusted phase-locked loop with the symbol timing information of the received signal; performing linear interpolation on the corrected phase value to generate a phase compensation sequence corresponding to the sampling points of the received baseband signal one by one; the interpolation factor of the linear interpolation is determined by the ratio of the symbol rate to the update rate of the phase-locked loop.

7. The method of claim 6, wherein the method further comprises: The initial covariance matrix of the recursive least square algorithm is set to a unit matrix multiplied by 1000; in each iteration, the prediction error is calculated first, then the gain vector is updated, and finally the covariance matrix and the equalizer tap coefficient are updated; the number of equalizer taps is 7, covering a time window of the current symbol and each of the three symbols before and after the current symbol.

8. The method of claim 1, wherein the method further comprises: The network communication chip is integrated in a fifth generation mobile communication terminal device or a vehicle internet of vehicles on-board unit; the chip is manufactured by using a 28 nanometer complementary metal oxide semiconductor process; the local oscillator is a voltage-controlled oscillator based on a transformer feedback structure, and the phase noise of the local oscillator is lower than -155 db / Hz at a frequency offset of 100 kHz.

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