Extended data link width for host ribbon chip module connectors in alternate mode

Abstract

Aspects relate to an extended data link width for a chip connection. In one example, a sideband transmitter of a module of a first die is configured to transmit an extended data link width enable request over a sideband of a die-to-die connection to a module partner to set an extended data link width of a primary bus of the die-to-die connection. The extended data link width includes data lines of the primary bus and redundant data lines of the primary bus that are reconfigured as data lines. A sideband receiver of the module is configured to receive an extended data link width enable response from the module partner over the sideband to set the extended data link width of the primary bus. A primary bus transmitter is configured to communicate data with the module partner over the primary bus using the extended data link width.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to non-provisional patent application serial number 18 / 352,600, filed July 14, 2023, with the United States Patent and Trademark Office, the entire contents of which are fully set forth herein as in their entirety and incorporated herein for all applicable purposes. Technical Field

[0003] All aspects of this disclosure relate to data communication between integrated circuit chip modules in general, and specifically to operation using extended data link width in alternative data transmission modes. Background Technology

[0004] As integrated circuit (IC) chips become increasingly smaller, it has become possible to package multiple chips into a single package. Each chip can be optimized for the cost, materials, manufacturing process, and size best suited for a specific function. In such a package, the central processing unit (CPU) can be manufactured separately from the graphics processor, dedicated processor, volatile memory, non-volatile memory, input / output controllers, or other components. Different components can be packaged together to meet different needs without redesigning any of the individual components. By placing these different chips into a single package, the entire system including the package can be made smaller. Similar principles apply to printed circuit board systems and subsystems. Furthermore, connections between different chips can be made faster and at a lower cost. In some cases, smaller chips (e.g., memory, dedicated processors, or interfaces) are referred to as chiplets; however, any chip can be called a chiplet.

[0005] The Universal Chipset Fast Interconnect (UCIe) specification version 1.0 (UCIe 1.0) defines the physical parameters and protocols for data transfer between chips or between two chipsets. Connections can be direct or via packages. Interconnects can be within a single package or across a circuit board between two different packages. UCIe 1.0 is designed to support interoperability between chipsets from different manufacturers and designers. A UCIe 1.0 interconnect includes a main band as the primary data transfer connector and a side band as the primary initialization and control connector. A series of state transitions are defined to allow the interconnect to initialize from the side band to the main band to the link to the active state, and back to the standby and reset states.

[0006] UCIe 1.0 defines standard and advanced packages. The advanced package version of UCIe 1.0 uses a main channel stripe with 64 data channels, four redundant data channels, two clock channels, one track channel, one active channel, one redundant clock channel, and one redundant active channel. The advanced package version is designed for connectors with smaller bump pitch (e.g., 25 microns to 55 microns) and shorter distances (e.g., less than 2 mm), which may be found within the package. The advanced package also supports different data transfer modes through its Flow Control Unit (FLIT) data channels with different sizes and different protocols. As examples, there are raw mode, streaming mode, Peripheral Component Fast Interconnect (PCIe) 6 mode, and various different Compute Fast Link (CXL) modes. New versions and modes may evolve over time. Summary of the Invention

[0007] The following content presents an overview of one or more specific implementations to provide a basic understanding of such implementations. This overview is not an exhaustive summary of all anticipated implementations, nor is it intended to identify key or essential elements of all implementations, nor to depict the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0008] In one example, an apparatus includes a sideband transmitter for a first die module, configured to transmit an extended data link width enable request to a module partner via a die-to-die connector sideband to set the extended data link width of the main band of the die-to-die connector. The extended data link width includes the data lines of the main band and redundant data lines of the main band reconfigured as data lines. A sideband receiver for the module is configured to receive an extended data link width enable response from the module partner via the sideband to set the extended data link width of the main band. A main band transmitter is configured to communicate data with the module partner via the main band using the extended data link width.

[0009] In one example, a method includes transmitting an extended data link width enable request to a module partner via a die-to-die connector sideband to set an extended data link width for the main band of the die-to-die connector, wherein the extended data link width includes the main band's data lines and redundant data lines of the main band reconfigured as data lines. An extended data link width enable response is received from the module partner via the sideband to set the extended data link width for the main band, and data is transmitted with the module partner via the main band using the extended data link width.

[0010] In another example, a non-transitory computer-readable medium has instructions stored therein for causing a processor of an interconnect link to perform the operations described above.

[0011] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the described embodiments are intended to cover all such aspects and their equivalents. Attached Figure Description

[0012] Figure 1 This is a block diagram of modules and module partners applicable to various aspects of this disclosure, which are coupled together using 64 data channels die-to-die connectors.

[0013] Figure 2 This is a block diagram of modules and module partners applicable to various aspects of this disclosure, which are coupled together using 68 data channels die-to-die connectors.

[0014] Figure 3 This is a diagram of the connection operation state machine according to various aspects of this disclosure.

[0015] Figure 4 This is a diagram of the master-band initialization state machine based on various aspects of this disclosure.

[0016] Figure 5 It is a signaling diagram of messages between modules and module partners according to various aspects of this disclosure for initializing the main band to extend the data link width.

[0017] Figure 6 It is a block diagram of the configuration registers according to various aspects of this disclosure.

[0018] Figure 7 It is a signaling diagram of messages between modules and module partners according to various aspects of this disclosure for initializing the main band in order to reduce the data link width.

[0019] Figure 8 It is a block diagram of a modular die according to various aspects of this disclosure.

[0020] Figure 9 This is a flowchart illustrating various aspects of operating the die-to-die connector to extend the data link width according to various aspects of this disclosure. Detailed Implementation

[0021] The detailed descriptions following, illustrated with reference to the accompanying drawings, are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed descriptions include specific details. However, these concepts can be practiced without these specific details. In some instances, to avoid ambiguity regarding such concepts, well-known structures and components are shown in block diagram form.

[0022] The term "die-to-die connector" as used herein can refer to a connection between any two dies (including chips or chiplets). A die can be considered any integrated circuit formed on a wafer and then cut, removed, or otherwise extracted from the wafer. The wafer can be silicon, glass, gallium nitride, or any other suitable material used to form the integrated circuit. For a die-to-die connector, each die includes a module. In UCIe 1.0, a module includes a die-to-die adapter processor, PHY (physical) logic, and a PHY interface. The interface includes a transmitter and a receiver for each line. A die can have multiple modules that can be coupled to modules of different dies or to the same die. Although examples are presented in the context of UCIe 1.0, this interface specification is not required. The die-to-die connectors described herein can also be used to connect two packages across a printed circuit board.

[0023] Die-to-die connectors can provide a bidirectional mainband with high data rates by using multiple data channels and multiple clock channels. As used herein, each channel consists of a transmit line and a receive line. These lines are inversely related, because a transmit line viewed from one module's perspective is a receive line viewed from another module's perspective, and vice versa. In other words, the line is coupled to the module's transmitter at one end and to the module's receiver at the other end.

[0024] Die-to-die connectors have a fixed number of available data channels, which can be used to transfer bits from one end of the connector to the other. When using data channels to support different protocols and different data transmission modes, a mismatch may occur between the number of physical data channels in the die-to-die connector and the number of data bytes in the FLIT of the selected protocol and data transmission mode. As an example, PCIe is configured for 4, 8, 16, 32, 64, 128, or 256 data channels. When correctly configured, the UCIe Advanced Package can use its 64 main channels with data channels to send or receive four FLITs, each containing 16 bytes, in a single transmission. Alternatively, four transmissions can be used to send or receive a single 256-byte FLIT. CXL offers several different modes, but the main mode has a 68-byte FLIT. In the case of 64 data channels, two transmissions are used to send or receive a 68-byte FLIT. As an example, 64 bytes can be transmitted in the first transmission, and the remaining 4 bytes in the second transmission. These bytes can then be reassembled into 68-byte packets by the receiver. In this description, MainBand and SideBand refer to the corresponding structures as defined in UCIe, while main band and sideband refer to any die-to-die connector having bands as described herein.

[0025] As described herein, the mainband data channels of a die-to-die connector can be reconfigured from a data link width (e.g., 64 data channels) to an extended data link width (e.g., 68 data channels) to accommodate larger FLITs (e.g., 68 bytes for CXL) using alternative data transmission modes. Die-to-die connectors can also be reconfigured to a reduced data link width (e.g., 64 channels) to accommodate smaller FLITs (e.g., 64 bytes for PCIe). The data link width can be reconfigured by sending an extended data link width enable request from the module to the module partner to set the mainband data link width of the die-to-die connector. For larger FLITs (e.g., 68-byte CXL FLIT), the extended data link width can include the mainband data channels as well as redundant data channels of the mainband that are reconfigured as data channels. Data is communicated with the module partner via the extended data link width that includes redundant data channels.

[0026] By adding four redundant data channels to 64 data channels, a 68-data-channel interconnect is obtained. The described method can be applied to UCIe mainband interconnects using PCIe and CXL, or to other mainband interconnects between IC chip modules with multiple data channels and alternative modes. In this description, sidebands are used to configure the mainband, for example, by exchanging configuration parameters during mainband initialization. Training can then be performed to configure the mainband.

[0027] Figure 1 This is a block diagram showing a first die 101 having module 103 and a second die 102 having module partner 104 coupled together using a 64-channel die-to-die connector 100 (e.g., UCIe Advanced Package Interconnect). Module 103 has a main band transmitter 110 connected to a transmit section 132 of the main band 130. Each die may have many other components (not shown) to generate, process, store, or transmit data, or supply or regulate power, or perform operational, management, or administrative functions, depending on the nature of the die. The first die 101 has module 103, and the second die 102 has module partner 104. Module 103 and module partner 104 may have the same or different structures and may include additional components (not shown), including transmitters, receivers, interfaces, adapters, logic devices, buffers, etc.

[0028] The connection is symmetrical because module 103 has a main-band transmitter 110, while module partner 104 has a main-band transmitter 122. Both transmitters perform the same functions and operations in opposite directions using the same protocol. Similarly, module 103 has a main-band receiver 112, and module partner 104 has a main-band receiver 120. This description relates to the modules and their construction and operation, but the description applies equally to module partner 104 in the same manner. Repair or training can be initiated on either side, and parameter and configuration changes can be initiated on either side. Module 103 has a sideband transmitter 114 and a sideband receiver 116. Module partner 104 also has a sideband receiver 124 and a transmitter 126.

[0029] UCIe 1.0 features a layered protocol with a physical layer and die-to-die adapters. The physical layer can consist of all types of current packaging options from different manufacturers and manufacturing processes. Examples include 2D packaging, 2.5D packaging, 3D packaging, and other methods such as silicon bridges, embedded multi-die interconnect bridges (EMIB), interposer-based chip-on-substrate (CoWoS) and fan-out chip-on-substrate (FOCoS) interposer packages, and any other connections between two dies or two packages on the same substrate. Optical or electrical connections can be made between packages and other components. UCIe may be extended in future revisions to connect dies or packages across rack-based components.

[0030] Connector 100 has a main band 130 and a side band 136. The main band has a transmitting section 132 as viewed from module 103 and a receiving section 134 as viewed from module 103. 64 transmit data channels each have data lines in the transmitting section 132 and data lines in the receiving section 134, with 64 lines in each direction. The side band 136 also has transmitting and receiving sections, each having side band data lines and side band clock lines.

[0031] Transmitter section 132 includes 64 transmit data lines, one clock P line, one clock N line, one active line, and one track line. The advanced package mainband transmitter section 132 also includes four redundant data lines (RDS data), one redundant clock line (RD clock), and one redundant active line (RD active). The redundant lines are configured for use in case of failure of one or more of the primary data or clock lines. Transmitter section 132 is coupled to mainband receiver 120 of module partner 104. Module 103 has a mainband receiver 112 connected to receiver section 134 of mainband 130. Receiver section 134 includes 64 receive data lines, one clock P line, one clock N line, one active line, one track line, four redundant data lines, one redundant clock line, and one redundant active line. Receiver section 134 is coupled to mainband transmitter 122 of module partner 104.

[0032] Redundant clock channels are provided as a two-way repair mechanism in case of a failure in one of the clock channels. A failure in either clock channel P or N will result in the configuration of a redundant clock channel to replace the failed clock channel. If the other clock channel fails, the track channel can also be remapped as a clock channel. Similarly, redundant active channels are provided as a two-way repair mechanism in case of a failure in the active channel.

[0033] Four redundant data lines in each direction of the mainband can be used in the event of a data line failure. Up to four data lines in each direction may fail without affecting data throughput. However, in many implementations, data line failures are extremely unlikely. If no data line failure occurs, the redundant data lines will always be idle. As described below, by reusing four redundant mainband data lines and combining them with the existing 64 functional mainband data lines, a 68-line data connector with extended data link width is created for mainband data transmission. If a data line failure occurs, the configuration can revert to a different state where data transmission requires fewer than all 68 data lines.

[0034] Within the context of UCIe 1.0, a specific number of lines is provided as an example, and different numbers of lines can be used to accommodate different die-to-die connectors. Multiple extended data link widths can exist using different numbers of redundant data lines. Multiple reduced data link widths can exist using different numbers of data lines. An extended data link width can exist where one redundant data line is used to replace a faulty data line and another redundant data line is used to extend the data link width.

[0035] The UCIe 1.0 protocol layer operates above the physical layer and shares many characteristics with Peripheral Component Fast Interconnect (PCIe), Compute Fast Link (CXL), and other pre-existing protocols. The PCIe protocol offers broad interoperability and flexibility. The CXL protocol provides low-latency and high-throughput connections. UCIe 1.0 can be extended in future revisions to include other protocols and further modifications beyond PCIe and CXL. The architecture and approach presented herein are described in the context of UCIe 1.0 but are adaptable to future versions of UCIe under any name and other connection configurations with multiple clock channels. PCIe has multiple data transfer modes configured as multiples of 8. Therefore, a FLIT in PCIe can be 8B, 16B, 32B, 64B, 128B, or 256B. 64 data channels correspond to a single 64B FLIT, allowing a single FLIT to be transmitted entirely in a single data transfer. For other data transfer modes, 8, 4, or 2 FLITs are transmitted in a single data transfer, or a single FLIT is carried using 1, 2, or 4 data transfers.

[0036] Figure 2This is a block diagram showing a first die 201 having module 203 and a second die 202 having module partner 204 coupled together using a 64-channel die-to-die connector 200 (e.g., UCIe Advanced Package Interconnect). Module 203 has a main band transmitter 210 connected to a transmit section 232 of the main band 230. The transmit section 232 includes 68 transmit data lines, one clock P line, one clock N line, one active line, and one track line. The Advanced Package main band transmit section 232 also includes 0 redundant data lines, one redundant clock line, and one redundant active line. The redundant data lines, along with the 64 data lines, are reconfigured for simultaneous use of the 68 active data lines. The transmit section 232 is coupled to a main band receiver 220 of module partner 204. Module 203 has a main band receiver 212 connected to a receive section 234 of the main band 230. The receiver section 234 includes 68 receive data lines, one clock P line, one clock N line, one active line, one track line, 0 redundant data lines, one redundant clock line, and one redundant active line. The receiver section 234 is coupled to the main band transmitter 222 of module partner 204.

[0037] The module also includes a sideband transmitter 214, which is coupled to a sideband receiver 224 of the module partner 204 via a sideband 236 of the die-to-die connector 200. The sideband 236 can be used with... Figure 1 The sideband example is the same or similar. Module 203 has a sideband receiver 216, which is coupled to the sideband transmitter 226 of module partner 204 via a sideband 236 of die-to-die connector 200. The sideband has a bidirectional data channel and a bidirectional clock channel.

[0038] Redundant data lines in each direction are reconfigured as data lines to extend the main data link width to an extended data link width. Transmit and receive data lines can be configured differently. For example, the data link width can be 68 lines in the transmit direction and 64 lines in the receive direction, or vice versa. This may be suitable, for example, when there is more data traffic in one direction than in the other. The CXL has a main mode with a 68-byte FLIT. In the case of 64 data channels, a 68-byte FLIT is transmitted or received in two transmissions. However, when the extended data link width is set to 68 lines, the extended data link width corresponds to the CXL's 68-byte FLIT. Therefore, the entire FLIT can be transmitted in a single data transmission. In the context of UCIe 1.0, a specific number of lines is provided as an example, and different numbers of lines can be used to accommodate different die-to-die connections.

[0039] In the UCIe 1.0 Advanced Package, 64 main channels with data channels are used for data transmission. Therefore, a maximum of 64 bytes of data can be transmitted in a single data transfer. The default FLIT used in CXL2.0 transmission is the 68-byte FLIT. FLIT alignment does not perfectly match the number of physical data channels. The remaining 4 bytes of the first 68 bytes are shifted to the next consecutive data transfer. This allows only 60 bytes of the 68 bytes in the second FLIT to be transmitted with the second data transfer. Then, 8 bytes of the 68 bytes are shifted to the third data transfer. This process continues, with each consecutive FLIT having an additional 4 bytes shifted to the next data transfer. When the transmitter of a module or module partner has no more FLITs to transmit, it terminates the data stream using, for example, a Data Stream Stop (PDS) token and two subsequent transmissions of all-zero data. The two subsequent transmissions of all-zero data give the receiver of the module partner or module at least two 64-byte transmissions to reset the receive byte shifter. Using 68 main channels with data channels allows for the transmission of a complete 68-byte FLIT in a single data transfer, eliminating shifting.

[0040] Figure 3 This is a state machine diagram of state machine 300 based on some aspects of the connection operation state machine. The state machine is related to the link layer form of the physical layer connection (e.g., 100, 200 described above). As described above, the same state machine can be used for UCIe advanced mode or other configurations with adaptability to accommodate channel differences. In UCIe 1.0, as part of the main channel band link training, modules and module partners must go through various stages of link initialization. First, the link is in the reset state 302. The link is held in the reset state 302 for at least 4ms to allow the phase-locked loop (PLL) and other link transmitter and receiver components to stabilize. The link progresses through the secondary channel band initialization state 304 (called SBINIT), the main channel band initialization state 306 (called MBINIT), the main channel band training state 308 (called MBTRAIN), and the link initialization state 310 (called LINKINIT) to enter the active state 312 (called ACTIVE). In the UCIe advanced package, the MBINIT state initializes the clock P channel, clock N channel, clock RD channel, track channel, and active channel.

[0041] consider Figure 3 The state machine 300 begins with a reset state 302, which can be obtained at startup, upon recovery from a deep sleep or low-power state (e.g., L2 state 314), or upon recovery from a fault. The reset state 302 can also be entered via a command from a higher-level layer of the die (e.g., a command to switch to a different masterband data link width).

[0042] The state machine transitions from reset state 302 to sideband initialization state 304. The sideband is the low-speed, high-reliability section of the die-to-die connector. It is configured to be easily initialized even in the presence of other faults or challenging environmental conditions. After sideband initialization state 304, the state machine can proceed to mainband initialization state 306.

[0043] The main band initialization state 306 includes the main band redundant data line initialization (MBRD INIT) sub-state 320. Data link width support, enable, and configuration parameters can be exchanged in sideband messages during the main band initialization state 306, or as part of the main band redundant data line initialization sub-state 320, and these parameters can be stored in the link configuration register.

[0044] After completing the main band initialization state 306, the state machine advances to the main band training state 308. During training in the link startup phase (i.e., when the physical layer transitions from the RESET state), the hardware is allowed to attempt training multiple times. The main band training state 308 includes training on redundant data lines (if present) that have been reconfigured as data lines.

[0045] After the master training state 308, state machine 300 advances to the link initialization state 310. Link initialization state 310 refers to the connection between the module and its module partner. After link initialization state 310, the state machine moves to the active state 312 for data communication between the module and its module partner. The state machine remains in the active state 312 until an event requires a transition.

[0046] One type of transition is to PHY retraining state 316. PHY retraining state 316 allows the PHY layer of the connection to be retrained in the event of errors or changes in the environment or conditions on the connection. As an example, a failure of the data line or a loss of the clock line might cause the state machine to transition to PHY retraining state 316 during active state 312. A new configuration of the data line or clock line can be trained in PHY retraining state 316. After PHY retraining state 316, the state machine returns to master band training state 308 to train the new master band configuration, then returns to link initialization state 310, and finally returns to active state 312, which has been recovered from PHY retraining state 316.

[0047] The mainband training state 308 can be entered on various other triggers. As an example, the software application can write the start UCIe link training bit into the UCIe link control. This allows the state machine to transition to the PHY retraining state 316. The die-to-die adapter can trigger mainband training based on the state of the physical adapter at the die or module partner, a sideband signal fault, or a new cold start initialization.

[0048] Another type of transition is to L1 / L2 state 314. L1 / L2 state 314 includes two different low-power or standby conditions to accommodate inactivity on the die-to-die connector. To reduce power consumption, heat generation, and / or wear on the die or connector components, state machine 300 can transition to L1 standby, which disables many connected components, especially those across the mainband section. State machine 300 transitions from L1 standby in L1 / L2 state 314 to mainband training state 308. From mainband training state 308, the state machine transitions to link initialization state 310 and returns to active state 312. L2 standby is a deeper standby involving more components, including clock shutdown to save more power. Starting from L2 standby, state machine 300 transitions from L1 / L2 state 314 to reset state 302. From reset state 302, the complete process of state machine transitions is executed to reach active state 312. There may be more or fewer standby or low-power states than L1 standby and L2 standby to suit different specific implementations.

[0049] Another state is the training error state 318, which is reached as a transition from the reset state 302. This state is dead and results in an inoperable connection. If the module is restarted, it re-enters the reset state 302 and can be initialized or returned to the training error state 318.

[0050] Figure 4 Based on some aspects of the main band initialization state machine 400, which provides additional details about the main band initialization state 306, including the main band redundant data line initialization sub-state 320. The main band initialization state machine 400 transitions from the main band initialization state to a parameter state 402, during which parameters for die-to-die connection operation are shared between the module and its module partners. Next, the main band redundant data line initialization state 404 includes transmitting an enable request via sideband to enable extended data link width for die-to-die connections and receiving an enable response via sideband to enable extended data link width.

[0051] The primary redundancy data line initialization sub-state 404 may also include transmitting a support request for extended data link width via sideband and receiving a support response for extended data link width. In some examples, the support request may only be made once during initialization, or support may be pre-configured. An enable request may be transmitted in response to receiving a support request in the primary redundancy data line initialization state 404 or during another state. The primary redundancy data line initialization state 404 also includes setting parameters in the link configuration register to support extended data link width.

[0052] After the main band redundant data line initialization state 404, the system enters calibration state 406 to calibrate the link using the selected clock and data channels. Repair clock state 408 follows calibration state 406 and allows the transmission and reception of training patterns between modules to test the clock connection between the module and its module partner. Repair valid state 410 is used to train valid channels for framing data on the data lines. A valid signal is a type of clock signal.

[0053] Reversing the master band state 412 allows testing the master band to determine whether the reversal should be applied to the master band's data channels. Using the reversal, channel 15 or channel 63 becomes channel 0, and the channel designation continues counting up to channel 0, which becomes channel 15 or channel 63.

[0054] The master band repair state 414 is a training state for master band data communication, in which a known pattern is transmitted on the data lines to test the correct operation of each data channel. Each data channel is tested on both the transmit and receive data lines. If a faulty data line is detected in either direction via master band repair state 414, the data link width can be modified to exclude the faulty data line. This test allows the availability of redundant data lines to be determined. A request to enable extended data link width is made in response to testing the data lines and testing redundant data lines. If both the data lines and redundant data lines are functional, the data link width can be extended to include the redundant data lines. After completing the operation of the master band initialization state machine 400, the link training state machine then transitions from the master band initialization state 306 to the master band training state 308, as follows. Figure 3 As shown.

[0055] In UCIe 1.0, utilizing correct and valid framing on valid channels and the forwarding clock, the UCIe module tests the data channels while repairing the main band state, transmitting 128 iterations of the per-channel ID pattern (LSB priority) on all N main channels with data channels. N is 68 (64 data + 4 RD) for the Advanced Package interface and 16 for the Standard Package interface. The UCIe module partner performs per-channel comparisons on its receivers on all N channels. If at least 16 consecutive iterations of the per-channel ID pattern are detected, the detection on the channel is considered successful. The UCIe module partner records the detection results on the receive line. After transmitting 128 iterations of the per-channel ID pattern, the UCIe module stops transmitting patterns and transmits an MBINIT.REVERSALMB result request sideband message to obtain the recorded results. The UCIe module partner stops comparing and responds with an MBINIT.REVERSALMB result response sideband message with N bits per channel result (68 for the Advanced Package interface and 16 for the Standard Package interface).

[0056] Figure 5 This is a signaling diagram of messages between module 502 of the first die and module partner 504 of the second die for initializing the main band using the extended data link width of the main band. When the die-to-die adapter processor... Figure 3 Signaling 500 can be used when the module moves from reset state 302. This can occur, for example, during startup or during a transition from L2 state 314. In some examples, a higher layer sends a request to the module to switch from a first data transmission mode with a smaller FLIT (e.g., 32 or 64 bytes) to a second data transmission mode with a larger FLIT (e.g., 68 bytes). Signaling 500 begins after sideband initialization is performed. The module and its module partner transmit a message indicating sideband initialization is complete (512). This corresponds to... Figure 3 The sideband initialization state 304 ends. Module 502 then sends a main band initialization parameter request 514 to module partner 504. Module partner 504 responds with a main band initialization parameter response 516. These are achieved through the initialized sideband exchange.

[0057] Module 502 and module partner 504 can use this response and request to include an extended data link width handshake. The extended data link width handshake can be used to determine whether extended data link width is supported by including a data link width support parameter in the main band initialization parameter request 514 and a variable link with a support parameter configuration response in the main band initialization parameter response 516. A data link width enable parameter can also be included in the main band initialization parameter request 514 and the main band initialization parameter response 516. The parameter can include any other suitable extended data link width parameter, or support and enable can be communicated in another way. The parameter can then be stored in the link configuration register. In one example, extended data link width support is part of the initial configuration and not part of the extended data link width handshake. In another example, enable is part of the initial configuration and not part of the extended data link width handshake.

[0058] UCIe 1.0 provides a more concrete example of parameter exchange. An exchange called MBINIT.PARAM exists. Parameters used to support and enable extended data link width can be exchanged during this exchange or during different operations. In UCIe 1.0, for both standard and advanced encapsulations, the main channel band initialization request message is called the MBINIT.PARAM configuration request. This is a sideband request to exchange parameters with the UCIe module partner. This request includes the parameters. The response from the module partner is called the MBINIT.PARAM configuration response, and is also a sideband message.

[0059] Then, module 502 initiates master band clock training 518. This can begin with an enable request via a sideband to module partner 504 to initiate master band clock training. Module partner 504 responds with a master band clock training enable response, instructing the module partner to prepare to receive iterations of the clock training pattern. Iterations of the clock training pattern are transmitted on each transmit line, and after the training pattern is completed, the module partner transmits a report of the results to the module. The same process is then repeated in the opposite direction, with iterations of the training pattern transmitted from the module partner to the module on each receive line. In UCIe 1.0, the clock repair process on each line consists of 128 iterations of the clock repair pattern (referred to as CLKREPAIR or “Per Lane ID” pattern). The module partner receiver needs to detect at least 16 iterations of the training pattern to determine that the training pattern has been successfully received.

[0060] At 520, module 502 and module partner 504 optionally perform data transfer mode negotiation. The data transfer mode determines the size of the FLIT or data link width transmitted between the module and module partner. As an example, several data transfer modes are compute fast link modes. CXL 2.0 includes CXL 68-byte FLIT mode, CXL 68-byte enhanced FLIT mode, and CXL 256-byte FLIT mode. PCIe 6.0 has a variety of different data transfer modes, including 64-byte FLIT mode, 128-byte FLIT mode, and 256-byte FLIT mode. The data transfer mode may also be compute fast link mode, peripheral component fast interconnect mode, streaming protocol mode, or any other suitable data transfer mode. Alternatively, the data transfer mode can be pre-configured or determined during master band initialization.

[0061] In response to data transmission mode negotiation 520 (if present), at 522, module 502 transmits a mode parameter configuration request via a sideband to module partner 504 to initialize the main band for the first data transmission mode. At 524, module 502 receives a mode parameter configuration response via a sideband from module partner 504 to initialize the main band for the first mode. The first mode can be any of the data transmission modes described above, such as PCIe 64-byte FLIT or CXL 68-byte FLIT or any other mode.

[0062] At 510, extended data link width can be enabled or disabled in response to the data transmission mode set by mode parameter configuration request 522 and response 524. At 526, in response to receiving a mode parameter configuration response, the module transmits an extended data link width enable request to module partner 504 via a sideband. In some examples, this request sets the extended data link width of the main band from die to die connector. The extended data link width includes the main band's data lines and any redundant data lines of the main band that have been reconfigured as data lines. In some examples, this request sets a reduced data link width that does not include any redundant data lines. The extended data link width enable request can switch the main band from a reduced data link width to an extended data link width, or vice versa.

[0063] At 528, module 502 receives an extended data link width enable response 528 from module partner 504 via the sideband to set the extended data link width of the main band. At 530, the module and module partner set the data link width in response to the extended data link width enable. In some aspects, the extended data link width is set by configuring transmit data lines and configuring transmit redundant data lines for data. Similarly, receive data lines and receive redundant data lines are set for data. In some examples, the link width parameter has a transmit link width different from the receive link width, and the data link is configured for two different link widths, one in each direction.

[0064] After enabling extended data link width at 510, training is performed on the configured main band data line at 532. Any suitable data line can be used for training, and its corresponding... Figure 3 The main band training state is 308. Link initialization 540 corresponds to... Figure 3 The link initialization state is 310. In the case of main band initialization, signaling continues to use extended data link width 542 to communicate data with module partners via main band data communication. This is consistent with... Figure 3 The activity status 312 corresponds to this.

[0065] Figure 6This is an example of configuration register 602 applicable to extended data link widths as described herein. Configuration register 602 is an example of a link configuration register (referred to herein as config_reg) that can be configured to support extended data link widths for the master band (e.g., the master channel band of an Advanced Package or a Standard Package). Configuration register 602 includes a transmit redundancy configuration register 604 and a receive redundancy register 606. The transmit redundancy configuration register may include additional registers 622, and the receive redundancy register 606 may include additional registers 624 that can be used for any of the other parameters described herein. Additional registers 626 may be added to accommodate more link variants and other connector configurations.

[0066] In some respects, the value in each position is set to zero by default and at startup. During the main band initialization state 306 described above, and specifically during the main band redundant data line initialization sub-state 320, a sideband support request is transmitted to the module partner to support extended data link width for the main band data lines. This may be part of the main band initialization parameter request 514 and may include support parameters. Upon receiving a sideband support response from the module partner (shown as main band initialization parameter response 516, which may include support parameters), a support bit may be added to the configuration register.

[0067] Configuration register 602 may include a support bit TX_RD_Support 612 for transmit data lines and a support bit RX_RD_Support 616 for receive data lines. In the example, when all support bits are "1" or high, both dies support extended data link widths for both transmit and receive data lines. In the example, when all are "0" or low, neither dies supports extended data link widths for either transmit or receive data lines.

[0068] Upon receiving a sideband enable response (shown as Extended Data Link Width Enable Response 528) from a module partner, the extended data link width can be configured. Figure 6 The configuration parameters for enabling these parameters are as follows. Specifically, TX_RD_Enable 614 indicates whether to enable extended data link width for the main band transmit data lines. RX_RD_Enable 618 indicates whether to enable extended data link width for the main band receive data lines. Alternatively, a single enable bit can be used for both transmit and receive lines, allowing both directions to be processed identically. Figure 6 The register settings allow the main redundant data channel to be aggregated with the module's functional data channel for data transmission.

[0069] The configuration register can be used to determine the use of redundant channels. This can be set during the main band redundant data line initialization sub-state 320. When the TX_RD_Enable bit is set to 1, the four transmit redundant channels are used along with the 64 main band active data lines for data transmission. When the TX_RD_Enable bit is set to 0, the four transmit redundant data lines are not used along with the 64 main band active data lines for transmission. Similarly, when the RX_RD_Enable bit is set to 1, the four receive redundant channels are used along with the 64 main band active data lines for data transmission.

[0070] Figure 7 This is a signaling diagram between module 702 of the first die and module partner 704 of the second die for initializing the main band during the transition from extended data link width to reduced data link width. When the die-to-die adapter processor... Figure 3 Signaling 700 can be used when the module moves from reset state 302. This can occur, for example, during startup or during a transition from L2 state 314. Signaling 700 begins after sideband initialization is performed. The module and its partner transmit a message indicating sideband initialization is complete 712. This corresponds to... Figure 3 The sideband initialization state 304 ends. Module 702 then sends a main band initialization parameter request 714 to module partner 704. Module partner 704 responds with a main band initialization parameter response 716. These are achieved through the initialized sideband exchange.

[0071] Module 702 and module partner 704 can use this response and request to include an extended data link width handshake. The extended data link width handshake can be used to determine whether extended data link width is supported by including a data link width support parameter in the main band initialization parameter request 714 and a variable link with a support parameter configuration response in the main band initialization parameter response 716. A data link width enable parameter can also be included in the main band initialization parameter request 714 and the main band initialization parameter response 716. The parameters can include any other suitable extended data link width parameters, or support and enable can be communicated in another manner. The parameters can then be stored in the link configuration register. In one example, extended data link width support is part of the initial configuration and not part of the extended data link width handshake. In another example, enable is part of the initial configuration and not part of the extended data link width handshake.

[0072] Then, module 702 initiates master band clock training 718. At 720, module 702 and module partner 704 optionally perform data transmission mode negotiation to determine the size of the FLIT transmitted between the module and module partner. In this example, the data link width will change from an extended data link width (e.g., 68 bytes) to a reduced data link width (e.g., 64 bytes). This could be due to a change in data transmission mode or due to a failure of one of the data lines or a redundant data line in a redundant data line.

[0073] In response to data transmission mode negotiation 720 (if present), at 722, module 702 transmits a mode parameter configuration request via sideband to module partner 704 to initialize the main band for the second data transmission mode. The second data transmission mode will have a reduced FLIT compared to the first data transmission mode, or will operate with a reduced data link width due to physical or other considerations. At 724, module 702 receives a mode parameter configuration response via sideband from module partner 704 to initialize the main band for the first mode.

[0074] At 710, the extended data link width can be disabled in response to the data transmission mode set by mode parameter configuration request 722 and response 724. At 726, in response to receiving the mode parameter configuration response, the module transmits an extended data link width disable request to module partner 704 via the sideband. In this example, the request sets a reduced data link width that does not include any redundant data lines. Redundant data lines are reconfigured as redundant, rather than being part of the die-to-die connector data link. Disabling the extended data link width can switch the main band from an extended data link width to a reduced data link width.

[0075] At 728, module 702 receives an extended data link width disable response from module partner 704 via the sideband to set a reduced data link width for the main band. At 730, the module and module partner set the data link width in response to the extended data link width disable. This is a reduction in the data link width, as shown in the figure. The reduced data link width is set by configuring the transmit data lines and configuring redundant transmit data lines as redundant. In some examples, one or more data lines have failed, and redundant data lines are reconfigured for use as data lines, but the data link width is not extended beyond, for example, a standard of 64 data lines. The link width parameter can have a transmit link width different from the receive link width, and the data link is set for two different link widths, one in each direction.

[0076] After disabling the extended data link width at 710, train 732 on the configured main band data line. Any suitable data line can be used for training, and its corresponding... Figure 3 The main band training state is 308. Link initialization 740 corresponds to... Figure 3 The link initialization state is 310. In the case of main band initialization, signaling continues to communicate data with the module partner via main band data communication using reduced data link width 742. This is consistent with... Figure 3 The activity status 312 corresponds to this.

[0077] Figure 8 This is a block diagram of an example of a hardware implementation for die 800 (e.g., a central processing unit, graphics processor, dedicated processor, volatile memory, non-volatile memory, input / output controller, or any other suitable component having a die-to-die connector 810 with sidebands and a mainband). In this example, the die has a processor 820 and a memory 805 for performing the main operations of the die. The die has a module 814 for supporting the die-to-die connector 810 with die-to-die adapter processor 804, computer-readable medium 806, PHY logic 812, PHY receive block 816, and PHY transmit block 818. The die-to-die adapter processor 804 performs the operations described above to serve the die-to-die connector 810 between die 800 and one or more other dies (not shown).

[0078] According to various aspects of this disclosure, module 814 can be used to implement elements, any part of elements, or any combination of elements. Examples of module 814 include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic elements, discrete hardware circuitry, and other suitable hardware configured to control die-to-die connector 810 and clock modes as described throughout this disclosure. In various examples, die 800 can be configured to perform any one or more of the functions described herein. The die contains other components (not shown) configured to perform other functions of the die, as applicable to the type of die.

[0079] In this example, the module has a processor 820, a memory 805, and a computer-readable medium 806 for performing the main operations of the module. A die-to-die adapter processor 804 performs the operations described above to serve the interconnect between module 814 and a module partner or another module. According to various aspects of this disclosure, module 814 may be used to implement elements or any part of elements or any combination of elements. Examples of processors include central processing units, graphics processors, dedicated processors, memory controllers, and input / output controllers. Examples of die-to-die adapter processor 804 include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware configured to control die-to-die connections and clock modes as described throughout this disclosure. In various examples, module 814 may be configured to perform any one or more of the functions described herein. The module contains other components (not shown) configured to perform other functions of the module, as applicable to the type of die.

[0080] In this example, die 800 can be implemented using a bus architecture (typically represented by bus 802). Bus 802 may include any number of interconnect buses and bridges, depending on module 814, the specific application of die 800, and overall design constraints. Bus 802 communicatively couples together various circuits including processor 820, die-to-die adapter processor 804, memory 805, and a computer-readable medium (typically represented by computer-readable medium 806) storing instructions thereon. Bus 802 may also link various other circuits, such as timing sources, peripherals, data buffers, modules, power management circuitry, and other processing cores, which are not further described. Bus interface 808 provides an interface between bus 802 and other optional external interfaces, such as control interface 830 and data interface 832. Processor 820 is at a higher level relative to die-to-die adapter processor 804 and is coupled to die-to-die adapter processor via bus 802. Processor 820 may communicate operation, management, or management control with die-to-die adapter processor 804, or die-to-die adapter processor 804 may operate autonomously. In some examples, the die-to-die adapter receives requests from a higher layer (e.g., processor 820) to extend or reduce the data link width of the main band. The higher layer may also transmit requests to switch from a first data transmission mode to a second data transmission mode.

[0081] Control interface 830 can be used to provide a communication interface or component for communicating with various other devices and equipment (e.g., other devices housed within the same package or system) via an internal bus or external transmission medium, such as command and control interfaces for power regulation, power-on testing, and other purposes. Data interface 832 can be used to provide data connectivity to other types of components within the package or system, in addition to die-to-die connector 810. Control interface 830 and data interface 832 can be connected to higher layers to receive reset and configuration commands that can switch the die-to-die processor to single-clock mode.

[0082] Module 814 includes a PHY receiver block 816 corresponding to the sideband and mainband receivers described above, and a PHY transmitter block 818 corresponding to the sideband and mainband transmitters described above. The PHY receiver block 816 and the PHY transmitter block 818 are coupled to a die-to-die connector 810, which corresponds to the physical portions of the sideband 136 and mainband 130 channels described above, which are coupled to a first die 101 and a second die 102 via pins on corresponding die connectors. The module also includes a PHY logic element 812, which may include link logic to control data applied to each line and the state machine described above, under the control of a die-to-die adapter processor. The PHY logic element 812 may also include a clock generator coupled to a clock source to generate the sideband and mainband clock signals as described above.

[0083] The die-to-die adapter processor 804 is responsible for managing the PHY logic unit 812 and interface processing, including executing software stored on the computer-readable medium 806. When executed by the die-to-die adapter processor 804, the software causes module 814 to perform various functions described below for any particular device. The computer-readable medium 806 and memory 805 can also be used to store data manipulated by the die-to-die adapter processor 804 during software execution.

[0084] The die-to-die adapter processor 804 may be part of one or more other processor cores (not shown) of the processor 820 or die 800, and performs operations by means of the processor core executing software stored on the computer-readable medium 806, or the die-to-die adapter processor 804 may be independent of any other processing resources of the die 800 to execute software stored on the computer-readable medium 806 using its own processing resources. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software dies, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description languages, or others. The software may reside on the computer-readable medium 806. The die-to-die adapter processor 804 controls operations performed by a state machine, such as... Figure 3 and Figure 4 Those operations, and cause signaling 500, 700 of the signaling diagram, and cause the clock repair training mode to be sent and received.

[0085] Computer-readable medium 806 may be a non-transitory computer-readable medium. By way of example, non-transitory computer-readable media include magnetic storage devices, flash memory devices, random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, and any other suitable medium for storing software and / or instructions accessible and readable by a controller. Computer-readable medium 806 may reside in another part of module 814 or die 800. Computer-readable medium 806 may be embodied in firmware for the operation of a state machine or parameters of an ASIC. Those skilled in the art will recognize that the optimal implementation of the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system.

[0086] Die 800 can be configured to perform any one or more of the operations described herein. In some aspects of this disclosure, such as the die-to-die adapter processor 804 utilized in die 800, circuitry configured for various functions may be included. Die-to-die adapter processor 804 is coupled to memory 805 via bus 802. Memory 805 includes parameter and configuration register 815, which may include functions for... Figure 6 The parameters for the different data link widths of the data channels shown are displayed. Any other parameters and configuration values ​​can also be stored, including those for mainband operations or CXL operations in PCIe.

[0087] The die-to-die adapter processor 804 may include Extended Data Link Width (EDLW) support circuitry 841 to request and receive responses for transmitting EDLW for supporting the mainband data channel using a module partner and setting support parameters in the link configuration register of the parameter and configuration register 815. The EDLW support circuitry 841 may include one or more hardware components providing a physical structure that performs various processes related to the request and receive responses for transmitting EDLW support using a module partner and setting support parameters. The EDLW support circuitry 841 may include components for transmitting an EDLW support request to a module partner, components for receiving an EDLW support response for supporting the mainband data channel from the module partner via a sideband, and components for setting support parameters in the link configuration register of the parameter and configuration register 815. The EDLW support circuitry 841 may be further configured to execute EDLW support instructions 851 included on a computer-readable medium 806 to implement the EDLW support described herein.

[0088] The die-to-die adapter processor 804 may include an EDLW enable circuit 842 configured to transmit and receive EDLW enable and disable requests to and from a module partner via a sideband, and to receive EDLW enable and disable responses from the module partner. As discussed herein, an enable request is to enable the use of Extended Data Link Width (EDLW) from the receiver (e.g., the module partner) to the transmitter (e.g., the module). The EDLW enable circuit 842 may include functions for responding to, for example... Figure 6 The EDLW enable circuitry provides the functionality of components that infer EDLW activation via commands or tables, and transmit and receive requests and responses to enable EDLW. Commands may be received from a higher layer (e.g., processor 820) or via control interface 830 to switch from a first data transmission mode to a second data transmission mode. The EDLW enable circuitry may further set parameters, enable bits, and additional parameters for operating the EDLW in a link configuration register. The EDLW enable circuitry 842 may also be configured to execute EDLW enable instructions 852 included on computer-readable medium 806 to implement one or more of the functions described herein.

[0089] Module 814 and die-to-die adapter processor 804 may include link initialization circuitry 843 configured to perform operations as discussed herein to initialize the main band with a specified transmit data link width and a specified receive data link width. Link initialization circuitry 843 may include functionality for initializing the link, and may also include functionality for main band clock training and main band data line training. Link initialization circuitry 843 may include functionality for receiving automatic results in response to initialization of iterations of the training mode on the clock line. Link initialization circuitry 843 may also be configured to execute link initialization instructions 853 included on computer-readable medium 806 to implement one or more of the functions described herein.

[0090] The die-to-die adapter processor 804 may include data communication circuitry 844 configured to communicate data with another module via the main band of the die-to-die connector 810 using an initialized main band with a clock training process, as discussed herein. Data communication circuitry 844 may include functionality for communicating data with another module via the main band. Data communication circuitry 844 may be further configured with parameters for communicating via the main band using an extended or reduced data link width. Data communication circuitry 844 may also be configured to execute data communication instructions 854 included on the computer-readable medium 806 to implement one or more of the functions described herein.

[0091] The circuit architecture described in this article can be implemented on one or more ICs, chips, chiplets, modules, interposers, packages, system printed circuit boards (PCBs), etc. The circuit architecture described in this article can also be manufactured using various process technologies, such as complementary metal-oxide-semiconductor (CMOS), NMOS, PMOS, bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0092] Figure 9 This is an example of using a die-to-die connector (such as, Figure 1 and Figure 2 A flowchart illustrating an example of a method for extending the data link width of the main data channel using a connector (such as a connector). This method can... Figure 8 die to die adapter processor 804 or other circuits and such in Figure 8This is executed within the software described in the context of [the software described in the original text]. Method 900 optionally begins at block 902 by transmitting a data link width support parameter configuration request via a sideband to a module partner to indicate that the module supports extended data link width. The transmission of the support request may be performed during mainband initialization. Alternatively, the die may be configured to support extended data link width without any handshake of the support parameters.

[0093] In response to the request message, the module partner may optionally transmit a response. Method 900 continues in block 904, optionally receiving a data link width support parameter configuration response via sideband to indicate that the module partner supports extended data link width.

[0094] In block 906, optionally, a mode parameter configuration request can be transmitted to the module partner via the sideband to initialize the main band for the first mode. Then, in block 908, the module can receive a mode parameter configuration response from the module partner via the sideband. The mode parameter configuration request may include an identifier of the data transmission mode, which includes the protocol used for the data transmission mode and the size of the FLIT used for the data transmission mode. The mode parameters can be used to set the data link width and also to configure buffers and other parts of the physical connection between the module and the module partner. In some examples, an extended data link width corresponds to a CXL data transmission mode with a 68-byte FLIT, and a reduced data link width corresponds to a PCIe data transmission mode with a 64-byte FLIT.

[0095] In block 910, the module executes an extended data link width enable request to the module partner via a die-to-die connector sideband to set the extended data link width of the main band in the die-to-die connector. The extended data link width may include the main band's data lines and redundant data lines of the main band that have been reconfigured as data lines. The link width parameter may be a single bit indicating an on or off state, or it may have multiple bits indicating one or more different extended data link widths. In block 912, the module executes receiving an extended data link width enable response from the module partner via a sideband to set the extended data link width of the main band. The data link width enable request and data link width enable response may be transmitted during main band initialization.

[0096] After the extended data link width enable bit is set and optionally stored in the configuration register along with the support and enable parameters, the main band data lines of the die-to-die connector can be configured for use. In block 914, extended data link width is used to communicate data with the module partner via the main band. In some examples, extended data link width disable requests and responses can be transmitted, causing the module partner to communicate via the main band using a reduced data link width corresponding to a FLIT for a different data transmission mode, which has a different data link width than the second data transmission mode FLIT. In some examples, the reduced data link width FLIT corresponds to the main band data lines that do not include redundant data lines.

[0097] As used herein, “or” is intended to be interpreted as inclusive unless otherwise explicitly stated. For example, “a or b” could include only a, only b, or a combination of a and b. As used herein, the phrase “at least one of” or “one or more of” a list of items refers to any combination of those items, including a single member. For example, “at least one of a, b, or c” is intended to cover the following examples: only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, and a combination of a, b, and c.

[0098] The various exemplary components, logic components, logic blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the specific embodiments disclosed herein can be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. This interchangeability of hardware, firmware, and software has been generally described in terms of its functionality and exemplified in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall system.

[0099] The various exemplary logic blocks, modules, and circuits described in conjunction with the exemplary aspects disclosed herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic component, discrete hardware component, or any combination thereof. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0100] In one or more exemplary aspects, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code stored on a computer-readable medium or transmitted as one or more instructions or code stored on a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Combinations of the above should also be included within the scope of computer-readable media.

[0101] The following provides an overview of various embodiments of this disclosure.

[0102] Example 1: An apparatus comprising: a sideband transmitter for a first die module, the sideband transmitter being configured to transmit an extended data link width enable request to a module partner via a die-to-die connector sideband to set an extended data link width for a main band of the die-to-die connector, wherein the extended data link width includes data lines of the main band and redundant data lines of the main band reconfigured as data lines; a sideband receiver for the module, the sideband receiver being configured to receive an extended data link width enable response from the module partner via the sideband to set the extended data link width of the main band; and a main band transmitter, the main band transmitter being configured to communicate data with the module partner via the main band using the extended data link width.

[0103] Example 2: According to the apparatus of Example 1, the apparatus further includes a control interface for receiving a request from a higher layer to switch from a first data transmission mode to a second data transmission mode, wherein transmitting the extended data link width enable request is performed in response to the request to switch to the second mode.

[0104] Example 3: The apparatus according to Example 1 or 2, wherein the extended data link width corresponds to the Flow Control Unit (FLIT) of the second data transmission mode.

[0105] Example 4: According to the apparatus of Example 3, wherein the main band transmitter is further configured to transmit data to the module partner via the main band using a reduced data link width corresponding to FLIT of the second data transmission mode.

[0106] Example 5: The apparatus according to any one or more of Examples 1 to 4, the apparatus further includes a configuration register configured to store Extended Data Link Width Enable in response to receiving the Extended Data Link Width Enable response.

[0107] Example 6: A method comprising: transmitting an extended data link width enable request to a module partner via a die-to-die connector sideband to set an extended data link width of a main band of the die-to-die connector, wherein the extended data link width includes data lines of the main band and redundant data lines of the main band reconfigured as data lines; receiving an extended data link width enable response from the module partner via the sideband to set the extended data link width of the main band; and communicating data with the module partner via the main band using the extended data link width.

[0108] Example 7: According to the method described in Example 6, the extended data link width corresponds to the flow control unit (FLIT) of the data transmission mode.

[0109] Example 8: According to the method described in Example 7, the data transmission mode includes a computational fast link mode with 68-byte FLIT.

[0110] Example 9: According to the method of Example 6 or 7, the method further includes receiving a request from a higher layer to switch from a first data transmission mode to a second data transmission mode, and wherein transmitting the extended data link width enable request is performed in response to the request to switch to the second data transmission mode.

[0111] Example 10: The method according to any one or more of Examples 6 to 9, wherein the extended data link width corresponds to the FLIT of the second data transmission mode, the method further includes transmitting data with the module partner through the main band using a reduced data link width corresponding to the FLIT of the first data transmission mode, wherein the FLIT of the first data transmission mode has a different data link width than the FLIT of the second data transmission mode.

[0112] Example 11: According to the method of Example 10, the data link width of the first data transmission mode FLIT corresponds to the data line of the main band excluding the redundant data line.

[0113] Example 12: The method according to Example 10 or 11, wherein conveying the data includes transmitting a second data transmission mode FLIT in a single data transmission via the main band.

[0114] Example 13: The method according to any one or more of Examples 10 to 12, the method further comprising: detecting a faulty data line of the main band; and transmitting an extended data link width disable request to the module partner via the sideband to initialize the main band to the reduced data link width, wherein the reduced data link width excludes the faulty data line and reconfigures redundant data lines as data lines, the reduced data link width corresponding to the FLIT less than the second data transmission mode.

[0115] Example 14: The method according to any one or more of Examples 6 to 13, wherein transmitting the extended data link width enable request includes transmitting the extended data link width enable request during main band initialization.

[0116] Example 15: The method according to any one or more of Examples 6 to 14, wherein transmitting the extended data link width enable request includes transmitting a receive data link width to identify the data link width of the receive data line and transmitting a transmit data link width to identify the data link width of the transmit data line.

[0117] Example 16: The method according to any one or more of Examples 6 to 15, the method further comprising training the main band with the extended data link width in response to receiving the extended data link width enable response.

[0118] Example 17: According to the method described in Example 16, training the main band includes training the data lines and the redundant data lines of the main band.

[0119] Example 18: The method according to any one or more of Examples 6 to 17, the method further comprising: testing the main band data line; and testing the redundant data line of the main band, wherein transmitting the extended data link width enable request is performed in response to testing the data line and testing the redundant data line.

[0120] Example 19: The method according to any one or more of Examples 6 to 18, the method further comprising storing Extended Data Link Width Enable in a configuration register in response to receiving the Extended Data Link Width Enable response.

[0121] Example 20: The method according to any one or more of Examples 6 to 19, the method further comprising: transmitting a mode parameter configuration request to the module partner via the sideband to initialize the main band for a first mode; and receiving a mode parameter configuration response from the module partner via the sideband to initialize the main band for the first mode, wherein transmitting the extended data link width enable request is performed in response to receiving the mode parameter configuration response.

[0122] Example 21: According to the method of Example 20, transmitting the mode parameter configuration request includes transmitting the mode parameter configuration request during main band initialization.

[0123] Example 22: The method according to any one or more of Examples 6 to 21, the method further comprising, before transmitting the mode parameter configuration request: transmitting a data link width support parameter configuration request to the module partner via the sideband to indicate that the module supports extended data link width; and receiving a data link width support parameter configuration response via the sideband to indicate that the module partner supports the extended data link width.

[0124] Example 23: According to the method described in Example 22, the method further includes storing data link width support parameters in a configuration register.

[0125] Example 24: A non-transitory computer-readable medium storing instructions for causing a processor of a die to perform operations including: transmitting an extended data link width enable request to a module partner via a die-to-die connector sideband to set the extended data link width of the main band of the die-to-die connector, wherein the extended data link width includes data lines of the main band and redundant data lines of the main band reconfigured as data lines; receiving an extended data link width enable response from the module partner via the sideband to set the extended data link width of the main band; and communicating data with the module partner via the main band using the extended data link width.

[0126] Example 25: According to the medium described in Example 24, the operation further includes: transmitting an extended data link width enable request to a module partner via a die-to-die connector sideband to set the extended data link width of the main band of the die-to-die connector, wherein the extended data link width includes the data lines of the main band and redundant data lines of the main band reconfigured as data lines; receiving an extended data link width enable response from the module partner via the sideband to set the extended data link width of the main band; and transmitting data to the module partner via the main band using the extended data link width.

Claims

1. An apparatus, the apparatus comprising: The link initialization circuit of the first die module is configured to initialize the sideband of the die-to-die connector between the module and a module partner. The sideband has receive data lines and transmit data lines. The sideband has high reliability and low data rate compared to the main band of the die-to-die connector. The main band includes multiple data lines and multiple redundant data lines. Each of the multiple redundant data lines is configured to replace the faulty data line in response to a faulty data line among the multiple data lines. The module's sideband transmitter is configured to transmit a sideband initialization complete message via the sideband's transmit data line. The link initialization circuit is configured to initialize the main band in response to the initialization complete message; The sideband transmitter is configured to transmit an extended data link width enable request message, including an enable parameter, to the module partner via the transmit data line of the sideband to set the extended data link width of the main band, wherein the extended data link width includes the data line of the plurality of data lines and at least one redundant data line of the plurality of redundant data lines. The module's sideband receiver is configured to receive an extended data link width enable response message, including the enable parameter, from the module partner via the sideband's receive data line, to set the extended data link width of the main band. The link initialization circuit is configured to initialize the at least one redundant data line as a main band line in response to receiving the extended data link width enable response message, and to use the extended data link width to train the main band. and A mainband transmitter, configured to communicate data with the module partner via the mainband using the extended data link width.

2. The apparatus of claim 1, further comprising a control interface for receiving a request from a higher layer to switch from a first data transmission mode to a second data transmission mode, wherein transmitting the extended data link width enable request is performed in response to the request to switch to the second data transmission mode.

3. The apparatus of claim 1, wherein the extended data link width corresponds to the flow control unit FLIT of the second data transmission mode.

4. The apparatus of claim 3, wherein the main band transmitter is further configured to transmit data to the module partner via the main band using a reduced data link width corresponding to FLIT of the second data transmission mode.

5. The apparatus of claim 1, further comprising a configuration register configured to store extended data link width enabling parameters in response to receiving the extended data link width enabling response.

6. A method, the method comprising: The sideband of the die-to-die connector between the module and its module partner is initialized. The sideband has receive data lines and transmit data lines. The sideband has high reliability and low data rate compared to the main band of the die-to-die connector. The main band includes multiple data lines and multiple redundant data lines. Each of the multiple redundant data lines is configured to replace the faulty data line in response to a fault among the multiple data lines. The sideband initialization completion message is transmitted via the data transmission line of the sideband. The main band is initialized in response to the initialization complete message; The extended data link width enable request message, including enable parameters, is transmitted to the module partner via the transmit data line of the sideband to set the extended data link width of the main band, wherein the extended data link width includes the data line among the plurality of data lines and at least one redundant data line among the plurality of redundant data lines. The extended data link width enable response message, including the enable parameter, is received from the module partner via the receive data line of the sideband to set the extended data link width of the main band; In response to receiving the extended data link width enable response message, the at least one redundant data line is initialized as a main band line; The main band is trained using the extended data link width; as well as The extended data link width is used to communicate data with the module partner via the main band.

7. The method of claim 6, wherein the extended data link width corresponds to the flow control unit FLIT of the data transmission mode.

8. The method of claim 7, wherein the data transmission mode includes a computationally fast link mode with 68-byte FLIT.

9. The method of claim 6, further comprising receiving a request from a higher layer to switch from a first data transmission mode to a second data transmission mode, wherein transmitting the extended data link width enable request message is performed in response to the request to switch to the second data transmission mode.

10. The method of claim 6, wherein the extended data link width corresponds to the FLIT of the second data transmission mode, the method further comprising transmitting data to the module partner via the main band using a reduced data link width corresponding to the FLIT of the first data transmission mode, the FLIT of the first data transmission mode having a different data link width than the FLIT of the second data transmission mode.

11. The method of claim 10, wherein the data link width of the first data transmission mode FLIT corresponds to the data line of the main band excluding the redundant data line.

12. The method of claim 10, wherein conveying the data includes transmitting a second data transmission mode FLIT in a single data transmission via the main band.

13. The method of claim 10, further comprising: Detect faulty data lines on the main unit; as well as The sideband transmits an extended data link width disable request message, including a disable parameter, to the module partner to initialize the main band to the reduced data link width, wherein the reduced data link width excludes the faulty data lines and reconfigures redundant data lines as data lines, and the reduced data link width corresponds to the FLIT, which is less than the second data transmission mode.

14. The method of claim 6, wherein transmitting the extended data link width enable request message includes transmitting the extended data link width enable request message during the initialization of the main band.

15. The method of claim 6, wherein transmitting the extended data link width enable request message includes transmitting a receive data link width as a parameter included in the extended data link width enable request message to identify the data link width of the receive data line, and transmitting a transmit data link width to identify the data link width of the transmit data line.

16. The method of claim 6, further comprising negotiating with the module partner a data transmission mode including the extended data link width.

17. The method of claim 16, wherein transmitting the Extended Data Link Width Enable Request message and receiving the Extended Data Link Width Enable Response message are performed in a MBINIT.PARAM exchange of General Purpose Chipset Fast Interconnect.

18. The method according to claim 6, further comprising: Test the mainband data cable; and Test the redundant data lines of the main unit. The transmission of the extended data link width enable request message is in response to testing the data line and testing the redundant data line.

19. The method of claim 6, further comprising storing extended data link width enable parameters in a configuration register in response to receiving the extended data link width enable response message.

20. The method according to claim 6, further comprising: The sideband transmits a mode parameter configuration request message to the module partner to initialize the main band for the first mode; as well as The sideband receives a mode parameter configuration response message from the module partner to initialize the main band used for the first mode. The transmission of the extended data link width enable request message is performed in response to receiving the mode parameter configuration response message.

21. The method of claim 20, wherein transmitting the mode parameter configuration request message includes transmitting the mode parameter configuration request message during main band initialization.

22. The method of claim 20, further comprising, before transmitting the mode parameter configuration request message: The module transmits a data link width support parameter configuration request message to the module partner via the sideband to indicate that the module supports extended data link width; and The sideband receives a data link width support parameter configuration response message to indicate that the module partner supports the extended data link width.

23. The method of claim 22, further comprising storing a data link width support parameter in a configuration register.

24. A non-transitory computer-readable medium storing instructions for causing a processor of a die to perform operations including: The sideband of the die-to-die connector between the module and its module partner is initialized. The sideband has receive data lines and transmit data lines. The sideband has high reliability and low data rate compared to the main band of the die-to-die connector. The main band includes multiple data lines and multiple redundant data lines. Each of the multiple redundant data lines is configured to replace the faulty data line in response to a fault among the multiple data lines. The sideband initialization completion message is transmitted via the data transmission line of the sideband. The main band is initialized in response to the initialization complete message; The extended data link width enable request message, including enable parameters, is transmitted to the module partner via the transmit data line of the sideband to set the extended data link width of the main band, wherein the extended data link width includes the data line among the plurality of data lines and at least one redundant data line among the plurality of redundant data lines. The extended data link width enable response message, including the enable parameter, is received from the module partner via the receive data line of the sideband to set the extended data link width of the main band; In response to receiving the extended data link width enable response message, the enable parameters are stored in the configuration register of the module; In response to receiving the extended data link width enable response message, the at least one redundant data line is initialized as a main band line; The main band is trained using the extended data link width; as well as The extended data link width is used to communicate data with the module partner via the main band.

25. The medium of claim 24, further comprising: The sideband transmits a mode parameter configuration request message to the module partner to initialize the main band for the first mode; as well as The sideband receives a mode parameter configuration response message from the module partner to initialize the main band used for the first mode. The transmission of the extended data link width enable request message is performed in response to receiving the mode parameter configuration response message.

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