Chip segmentation auxiliary structure and method for improving bonding interface quality

Abstract

Integrated circuit (IC) structures, electronic modules, and methods of manufacture are described in which direct bonding interfaces are removed at corners or edges to counteract the likelihood of non-bonding or delamination. This may be accomplished during singulation with side recesses formed through the entire thickness of the electronic component and into the directly bonded die followed by a final singulation of the IC structure.

Description

[0001] Related patent applications

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 508,830, filed June 16, 2023, and U.S. Patent Application No. 18 / 598,938, filed March 7, 2024, each of which is incorporated herein by reference. Background Technology Technical Field

[0005] The implementation schemes described herein relate to semiconductor packaging, and more specifically, to the molding of direct bonding structures. Background of the Invention

[0007] Current market demands for portable and mobile electronic devices, such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, augmented reality / virtual reality (AR / VR) headsets, gaming devices, and other mobile devices, require the integration of more performance and features into increasingly smaller spaces. As a result, various multi-die packaging solutions, such as system-in-package (SiP) and package-out-of-package (PoP), have become more prevalent to meet the need for higher die / component density devices.

[0008] There are many different possibilities for arranging multiple dies in a SiP (System-in-Package). For example, vertical integration of dies in a SiP structure has evolved into 2.5D and 3D solutions. In a 2.5D solution, multiple dies can be flip-chip bonded to an interposer, which may include vias and fan-out wiring. Various 3D solutions exist. In one specific implementation, multiple dies can be stacked on top of each other on a SiP substrate and connected with external lead bonding or solder bumps. Other conventional 3D solutions utilize hybrid bonding using either Wafer-on-Wafer (WoW) or CoW (CoW) technologies. In a WoW solution, the top and bottom device area dimensions are precisely matched, and each layer is confined to a technology node. In a CoW solution, multiple top dies (chips) can be integrated onto the same bottom die with a defined area and technology node.

[0009] Hybrid bonding, including metal-metal and oxide-oxide bonding, is generally used as a suitable technology for the mass production of high-density input / output (I / O) chips with ultra-small pad pitches. A conventional hybrid bonding sequence involves three main operations: initial oxide-oxide bonding at room temperature, heating to close the recessed gaps, and subsequent further heating to compress the metal-metal bond. Following the hybrid bonding process, subsequent processing and device completion operations may occur, depending on the specific application. Modern integrated circuit (IC) manufacturing technologies typically utilize gap-filling materials, such as dielectric materials (e.g., chemical vapor-deposited oxides or nitrides) or epoxy molding compounds, to encapsulate hybrid-bonded dies for various reasons, including protecting brittle materials from mechanical damage and smoothing the surface to facilitate downstream wafer-level processing. Summary of the Invention

[0010] Integrated circuit (IC) structures, electronic modules, and manufacturing methods are described, in which direct bonding interfaces can be removed in high-risk areas that are unbonded or delaminated, such as at die corners or edges. This can be achieved by dicing methods, and particularly by a combination of grooving (e.g., laser, plasma, stealth etching) and mechanical sawing. In embodiments, the IC structure includes electronic components (e.g., dies, interposers, etc.) and one or more dies directly bonded to the electronic components. The dies directly bonded to the electronic components can themselves be single-layer dies or multi-stacked dies (bonded dies). Side grooves are formed in at least one die and extend through the entire thickness of the electronic component and into the die. In embodiments, the side grooves define groove sidewalls extending through the entire thickness of the electronic component and groove tops within the die, and the groove tops intersect with the outermost lateral sidewall of the die such that the outermost lateral sidewall is outside the groove sidewalls. Variations of the grooving process can form one or more local cavities that extend through the electronic component and into the die interior to the outer edge of the segmented IC structure. In this case, the local cavity can be further placed within the die, and is not limited to application to die corners and / or edges. Side recesses and / or local cavities can be filled before the IC structure is split, or optionally filled in downstream assembly processes. Attached Figure Description

[0011] Figure 1A It is a schematic top view of an electronic module including an IC structure according to an implementation scheme, the IC structure having a die directly bonded to electronic components.

[0012] Figure 1B It is according to the implementation plan along Figure 1A A schematic cross-sectional side view of line XX.

[0013] Figures 2A to 2CIt is a schematic top view illustration of an IC structure with various die arrangements according to the implementation plan.

[0014] Figure 3 This is a schematic top view of the molded IC structure prior to the segmentation of the implementation plan.

[0015] Figure 4 It is according to the implementation plan along Figure 3 A schematic cross-sectional side view of line XX.

[0016] Figure 5 This is a schematic top view of the molded IC structure after being divided according to the implementation plan.

[0017] Figure 6A It is according to the implementation plan along Figure 5 A schematic cross-sectional side view of line XX.

[0018] Figure 6B It is according to the implementation plan along Figure 5 A schematic cross-sectional side view of the line YY.

[0019] Figure 6C It is a schematic cross-sectional side view of the recessed configuration according to the implementation scheme, wherein the outer edge of the segment of the IC structure corresponds to the outer edge of the gap filling material.

[0020] Figure 6D It is a schematic cross-sectional side view of the recessed configuration formed by plasma and saw cutting according to the implementation scheme.

[0021] Figure 6E It is a schematic cross-sectional side view of a recessed configuration formed by plasma and saw cutting according to the implementation scheme, wherein the outer edge of the segment of the IC structure corresponds to the outer edge of the gap filling material.

[0022] Figure 6F This is a schematic cross-sectional side view of a recessed configuration formed in a multi-device stack according to the implementation scheme.

[0023] Figures 7A to 7E This is a schematic cross-sectional side view illustration of a method for forming an IC structure with side grooves according to an implementation scheme.

[0024] Figure 8A This is a schematic top view illustration of a molded IC structure with side grooves and a segmented gap-filling material according to the implementation scheme.

[0025] Figure 8B This is a schematic top view illustration of a molded IC structure with side grooves and a segment passing through the die, according to the implementation scheme.

[0026] Figure 8C This is a schematic top view illustration of a molded IC structure with a segment passing through the die, according to the implementation scheme.

[0027] Figure 9 It is a schematic top view of the molded IC structure including the dummy chiplet before partitioning, according to the implementation scheme.

[0028] Figure 10 It is a schematic top view of a molded IC structure including dummy chips after segmentation, according to the implementation plan.

[0029] Figure 11A It is according to the implementation plan along Figure 10 The schematic cross-sectional side view of line AA is shown, in which a side groove is formed in the dummy chip.

[0030] Figure 11B It is according to the implementation plan along Figure 10 The schematic cross-sectional side view of line AA is shown, in which the side groove is not formed in the dummy chip.

[0031] Figure 12 It is according to the implementation plan along Figure 10 A schematic cross-sectional side view of line BB.

[0032] Figure 13 It is a schematic top view of the molded IC structure, including the dummy chiplet before partitioning, according to the implementation scheme.

[0033] Figure 14 It is a schematic top view of a molded IC structure including dummy chips after segmentation, according to the implementation plan.

[0034] Figure 15 It is a schematic top view illustration of a molded IC structure including one or more local cavities according to the implementation scheme.

[0035] Figure 16 This is a schematic cross-sectional side view of an IC structure including a local cavity formed by plasma etching, according to an implementation scheme.

[0036] Figure 17 This is a schematic cross-sectional side view of an IC structure including a local cavity formed by laser etching, according to an implementation scheme.

[0037] Figures 18 to 19 It is a schematic top view illustration of a cutting sequence including selective segmentation of non-directly bonded surfaces according to the implementation scheme.

[0038] Figures 20A to 20F This is a schematic cross-sectional side view of an IC structure with various side grooves and double-sided molding according to the implementation scheme.

[0039] Figures 21A to 21M This is a schematic cross-sectional side view illustration of a method for forming an IC structure with side grooves and a double-sided molded part according to the implementation scheme.

[0040] Figures 22A to 22B This is a schematic top-view diagram illustrating the segmentation paths for the three-die IC structure and the location of high-stress corner areas according to the implementation plan.

[0041] Figures 23A to 23B This is a schematic top-view diagram illustrating the segmentation paths for the three-die IC structure and the location of high-stress corner areas according to the implementation plan.

[0042] Figure 24 This is a schematic top-view diagram illustrating a two-die IC structure with chamfered die corners in a non-segmented corner, according to the implementation plan. Detailed Implementation

[0043] The embodiments describe integrated circuit (IC) structures, electronic modules, and manufacturing methods. In one embodiment, the IC structure includes an electronic component and a die, the electronic component including a first bonding surface, and the die including a second bonding surface directly bonded to the first bonding surface (e.g., using hybrid bonding or fusion bonding). A side recess extends through the entire thickness of the electronic component and into the die, defining a recess sidewall extending through the entire thickness of the electronic component and a recess top within the die. According to the embodiment, the recess top intersects with the outermost lateral sidewall of the die, such that the outermost lateral sidewall is outside the recess sidewall. The recess top may further extend through a gap-filling material (e.g., molding compound) that laterally surrounds the die.

[0044] In one respect, it has been observed that molding compound materials such as epoxy molding compounds (EMCs) have a much lower elastic modulus and a higher coefficient of thermal expansion (CTE) than the die they encapsulate, and this change in elastic modulus and CTE from the bonded die to the surrounding EMC can lead to high stress concentrations near the die edges and corners at the bonding interface. In particular, high peel stress concentrations can form when the bonded structure attempts to bend due to thermal or mechanical loads, such as by utilizing the expansion of EMC at high temperatures. Additionally, high shear stress concentrations can form when the bonded structure attempts to shrink or expand together with other package and system components, such as substrates, printed circuit boards, etc.

[0045] On the other hand, it has been observed that incoming dies may have a degree of inherent warpage due to residual stress in the back-end process (BEOL) stacking structure and the bonding interface layer material used for fusion or hybrid bonding. It has also been observed that flattening die edges and corners during direct bonding processes such as fusion bonding and hybrid bonding can be challenging.

[0046] According to the implementation plan, bonding interfaces can be removed in high-risk areas, such as die corners and edges. This can be achieved through cutting methods, and particularly through a combination of grooving (e.g., laser, plasma, stealth etching) and mechanical sawing to remove unbonded or delaminated high-risk areas.

[0047] Various embodiments are described with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and constructions. In the following description, numerous specific details, such as particular configurations, dimensions, and processes, are set forth to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. The phrase "an embodiment" as used throughout the specification means that a particular feature, structure, construction, or characteristic described in connection with an embodiment is included in at least one embodiment. Therefore, the repeated use of the phrase "in an embodiment" throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, construction, or characteristic may be combined in any suitable manner in one or more embodiments.

[0048] As used herein, the terms “above,” “on top of,” “to,” “between,” “across,” and “on top of” can refer to the relative position of one layer with respect to other layers. A layer being “above,” “on top of,” “across,” or “on top of” another layer, or being “to” another layer, or being “in contact” with another layer, can mean directly contacting other layers or having one or more intervening layers. A layer being “between” multiple layers can mean directly contacting those multiple layers or having one or more intervening layers.

[0049] Now for reference Figures 1A to 1B , Figure 1A It is a schematic top view of an electronic module including an IC structure according to an implementation scheme, the IC structure having a die directly bonded to electronic components; Figure 1B It is according to the implementation plan along Figure 1AThe figure shows a schematic cross-sectional side view taken by line XX. As shown, the electronic module 100 may include a module substrate 102 (such as a printed circuit board (PCB), intermediate components, etc.) and an integrated circuit (IC) structure 110 mounted on the module substrate 102. Additional electronic components 120 may also be mounted on the module substrate 102.

[0050] The IC structure 110 according to the embodiments may include a plurality of dies 112, which may be the same or different types. Various exemplary dies 112 include systems-on-a-chip (SoC), graphics processing units (GPUs), central processing units (CPUs), artificial intelligence (AI) logic, machine learning logic, radio frequency (RF) baseband processors, radio frequency (RF) antennas, signal processors, power management integrated circuits (PMICs), logic components, memory, photonics, biochips, low-speed and / or high-speed input / output (HSIO) caches, silicon interconnects, and any combination thereof. The dies 112 according to the embodiments may be active or passive and may be intermediates. According to the embodiments, the dies 112 may be directly bonded to electronic components 114, which may also be die or intermediate structures. For example, direct bonding may be accompanied by fusion bonding (dielectric-dielectric bonding) or hybrid bonding (metal-metal bonding and dielectric-dielectric bonding). Electronic components 114 may include electrical wiring (including die-to-die wiring) and vertical wiring from the dies 112 to the module substrate 102. The electronic components may optionally include a variety of passive or active devices. In a particular embodiment, die 112 includes multiple CPUs and GPUs co-bonded with intermediate electronic components 114. IC structure 110 may be connected to multiple memory packages that serve as electronic components 120 and is interconnected via module substrate 102.

[0051] exist Figure 1B In the illustrated exemplary embodiment, module substrate 102 includes a top surface 104 and a bottom surface 106, the bottom surface including a plurality of contact pads 108 on which a plurality of solder bumps 105 are placed. Electronic component 120 (such as a dynamic random access memory (DRAM) package) includes, for example, a stacked DRAM chip 122 connected to package substrate 124 via wire bonding 126. DRAM chip 122 and wire bonding 126 may be encapsulated in molding compound 128 on top of package substrate 124. Electronic component 120 may be mounted to module substrate 102 and solder bumps 125.

[0052] According to an embodiment, the IC structure 110 includes an electronic component 114 and a die 112. The electronic component has a first bonding surface 116, and the die includes a second bonding surface 118 directly bonded to the first bonding surface 116. A side recess 130 is formed in the IC structure 110 such that the side recess extends through the entire thickness of the electronic component 114 and into the die 112. Specifically, the side recess 130 may define a recess sidewall 132 extending through the entire thickness of the electronic component 114 and a recess top 134 within the die 112. The recess top 134 further intersects with the outermost lateral sidewall 131 of the die 112, such that the outermost lateral sidewall is outside the recess sidewall 132. The recess top may be tapered, depending on the method of forming the side recess 130. An underfill material 136 (e.g., epoxy resin, etc.) may be additionally applied between the IC structure 110 and the top surface 104 of the module substrate 102. In the implementation scheme, the bottom filling material 136 fills the side groove 130.

[0053] The die 112 may be encapsulated in a gap filler material 135 (such as an oxide or molding compound (e.g., epoxy resin)). In some embodiments, the gap filler material 135 may optionally be removed (at least partially) from one or more sides of the IC structure 110 during the formation of the recess sidewalls 132 and the splitting, as will be described in further detail.

[0054] The segmented IC structure 110 according to an embodiment may include a multi-die chipset, wherein a gap filler material 135 laterally fills the space between dies 112 and optionally surrounds one or more edges of the dies 112, depending on whether the side notches and slits are made through the dies 112 or the gap filler material 135. According to some embodiments, the outermost lateral sidewalls 131 of two dies (e.g., formed after the side notches 130 and slits) are parallel to each other, thereby forming opposite edges of the segmented IC structure 110. In other embodiments, the outermost lateral sidewalls 131 of two dies may be orthogonal to each other when on opposite sides of a corner of the segmented IC structure, or may share the same plane when forming the same edge of the segmented IC structure 110.

[0055] Still referencing Figure 1B According to the embodiment, die 112 may each include a semiconductor layer 138 and a back-end process (BEOL) stack-up structure 140 on the semiconductor layer. Semiconductor layer 138 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, etc., and may have an epitaxial device layer on the bulk silicon. Silicon is exemplary, and other semiconductor substrate materials may be used. BEOL stack-up structure 140 may include conventional electrical wiring and a metal sealing structure (e.g., a sealing ring) to act as a physical barrier against moisture and impurities entering both, and to provide mechanical integrity.

[0056] The electronic component may also include a semiconductor layer 144 and a BEOL stack structure 142. The BEOL stack structure 142 may include electrical wiring and optionally include die-to-die wiring between dies 112. A plurality of vias 146 (e.g., through-silicon vias) may extend through the semiconductor layer 144 and the back-side dielectric layer 148 to contact terminals (e.g., contact pads) 150 on which solder bumps 125 may be placed.

[0057] It should be understood that Figures 1A to 1B The specific die 112 arrangement within the illustrated IC structure 110 is exemplary, and the implementation is not limited thereto. Figures 2A to 2C This is a schematic top view illustration of an IC structure with various die arrangements according to the implementation scheme. Specifically, Figures 2A to 2C The illustrated implementation scheme illustrates the molding configuration prior to segmentation. Various alternative configurations are envisioned.

[0058] Now for reference Figures 3 to 4 , Figure 3 This is a schematic top view of the molded IC structure prior to the segmentation of the implementation plan. Figure 4 It is according to the implementation plan along Figure 3 The diagram shows a schematic cross-sectional side view of line XX. For clarity, a dual-core system is illustrated, but implementations are not limited to this. Figure 3 As shown, die 112 includes a sealing ring 160 structure within its original periphery 161 (edge). A gap-filling material is then formed between and around the dies on top of the electronic component 114, and optionally on top of the dies. Figure 3 In the specific embodiment shown, a high-stress region 164 is identified near the corner of die 112. For example, the high-stress region 164 may be identified during product development and modeling. According to the embodiment, these high-stress regions 164 may be removed during side groove formation and segmentation. The dashed line along path 166 illustrates the coverage of the edge segmentation. In this embodiment, the IC structure segmentation may extend through the edges of both dies 112.

[0059] Now for reference Figure 4In the illustrated embodiment, the BEOL stack structure 140 of die 112 includes a dielectric bonding layer 152 and metal bonding pads 154, both of which are exposed along the bonding surface 118. Similarly, the BEOL stack structure 142 of electronic component 114 may include a dielectric bonding layer 156 and metal bonding pads 158, both of which are exposed along the bonding surface 116. In a hybrid bonding configuration, the metal bonding pads 54, 158 may be bonded together using metal-to-metal bonding, and the dielectric bonding layers 152, 156 may be bonded together using dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding).

[0060] Now for reference Figures 5 to 6A A schematic top view and a cross-sectional side view of the molded IC structure 110 after being segmented along path 166, according to an embodiment, are provided, wherein Figure 6A It is along Figure 5 The line XX is cut. As shown in the figure, a portion passes through the bottom core 112. According to the implementation scheme, the grooving operation can be performed before the grooving. Figure 6A The resulting structure includes a side recess 130 extending through the entire thickness of the electronic component 114 and into the die 112. The side recess 130 defines a recess sidewall 132 extending through the entire thickness of the electronic component and a recess top 134 within the die 112. The recess top 134 further intersects with the outermost lateral sidewall 131 of the die 112, such that the outermost lateral sidewall 131 is outside the recess sidewall 132. (As shown in...) Figures 7A to 7E As further described in the process flow, the segmentation may include a first operation (such as laser etching (grooving), plasma etching, stealth etching, etc.) for forming the side groove 130, followed by a second operation (such as sawing) for segmentation, wherein the outermost lateral sidewall 131 is defined. Therefore, the depth (d1) of the side groove 130 may be primarily determined by the first operation, and the depth / thickness (d2) of the outermost lateral sidewall is the remainder. Figure 6A The specific embodiment illustrated may indicate laser etching in which a curved groove top 134 may be formed.

[0061] Figure 6B It is according to the implementation plan along Figure 5A schematic cross-sectional side view of the line YY is shown. As illustrated, the side groove 130 may optionally extend into the gap filler material 135. While the side groove 130 may be selectively formed along the die 112, it may also be formed along the entire length of the split edge of the IC structure. In this configuration, the side groove 130 may span a portion of the gap filler material 135, where the depth d1 may be greater than the depth within the die 112 because the laser can etch the gap filler material 135 at a faster rate than the material of the die 112. Therefore, the depth profile of the side groove 130 along the outer edge of the split of the IC structure may vary depending on the material, where the depth d1 through the region of the gap filler material 135 is deeper than that of the die 112.

[0062] Although the side groove 130 can be formed into the die 112 to remove the risky bonding interface area, the partition of the IC structure 110 is not required to also pass through the die 112. Figure 6C It is a schematic cross-sectional side view of the recessed configuration according to the embodiment, wherein the outer edge of the segment of the IC structure corresponds to the outer edge 139 of the gap filling material 135.

[0063] The dimensions of the side recesses can indicate the formation method. For example, laser etching can create a tapered transition within the recess top 134 between the recess sidewall 132 and the outer edge of the segmented IC structure. Laser etching can also produce sloping recess sidewalls 132, depending on the laser grooving process. Other manufacturing techniques may produce different side recess dimensions. Figure 6D This is a schematic cross-sectional side view illustration of a recess configuration formed by plasma and / or sawing according to an embodiment. In such embodiments, the top 134 of the recess may be substantially flat and may be orthogonal to the sidewall 132 of the recess. For example, any combination of plasma and sawing may be used to form it. Figure 6D The structure can be divided into IC structures, such as by plasma etching to form side recesses 130, followed by plasma etching or mechanical sawing to divide the IC structure 110. Alternatively, mechanical sawing can be used for both operations, in which a larger blade is used to form the side recesses 130, and then a narrower blade is used to divide within the opening of the side recesses. Figure 6E It is a schematic cross-sectional side view of a recessed configuration formed by plasma and saw cutting according to the embodiment, wherein the outer edge of the segment of the IC structure corresponds to the outer edge 139 of the gap filling material 135.

[0064] To date, embodiments of the structure comprising a single electronic component 114 and a die 112 directly bonded together have been described. These embodiments are applicable to a variety of three-dimensional (3D) structures. Figure 6FThis is a schematic cross-sectional side view illustrating a recessed configuration formed in a multi-device stack according to an embodiment. As shown, the configuration may include multiple electronic components 114A, 114B, etc. For example, this could be a 3D IC die stack with various through-hole configurations 146. Therefore, a side recess 130 may be formed to an appropriate depth through one or more of the electronic components. Depth d1 and the recess top 134 may therefore optionally terminate within the electronic components of such a stack, rather than within the top die 112. Any embodiment of the embodiments described herein can be implemented using such a multi-device stack, which may include additional electronic components or dies.

[0065] Figures 7A to 7E This is a schematic cross-sectional side view illustrating a method for forming an IC structure with side grooves according to an embodiment. Figure 7A As shown, the sequence may begin with direct bonding (e.g., fusion bonding, hybrid bonding) of die 112 to electronic component substrate 114S, which may be wafer-level. Die 112 may then be encapsulated on electronic component substrate 114S using gap filler material 135 (such as molding compound). Die 112 and gap filler material 135 may then be optionally thinned using a polishing method, after which solder bumps 105 are applied to electronic component substrate 114S. Tape 173 (e.g., ball grid tape) may then be applied to solder bumps 105 and transferred to frame 172, as... Figure 7B As shown. Reference Figure 7C Multiple side grooves 130 are then formed through the entire thickness of the electronic component substrate 114S and into the die 112, wherein the side grooves define groove sidewalls 132 and groove tops 134 within the die 112. Notably, the groove tops 134 may also extend in a gap-filling material 135. In embodiments, laser drilling or grooving can be used to form the side grooves 130. Other techniques, such as plasma etching, stealth etching, etc., may also be used.

[0066] Then, as Figure 7D The diagram illustrates a sawing operation where sawing is performed through side groove 130 to divide the IC structure 110. In an illustrated embodiment, sawing may be performed through a portion of die 112 to create the outermost lateral sidewall of the die. In other embodiments, sawing may be performed through gap filler material 135, such that after division, a portion of gap filler material 135 remains around the edge of the original die 112. After division, tape 173 can be removed, followed by mounting the IC structure 110 onto the module substrate 102, for example, as... Figure 7E As shown.

[0067] In relation to Figure 7CThe side groove 130 formed in the described operation can be used to remove high-risk areas for debonding across the direct bonding interface between the die 112 and the electronic component 114. Regarding Figure 7D The described subsequent mechanical sawing operation is used to divide the IC structure 110 and can be applied to different locations. Figure 8A This is a schematic top view illustration of a molded IC structure 110 with side grooves and a segment extending through a gap filler material 135, according to an embodiment. In such an embodiment, the top of the groove 134 spans both the semiconductor layer of the die 112 and the gap filler material 135, and the side groove 130 also extends into the gap filler material 135. Therefore, the outer edge of the IC structure 110 corresponds to the outer edge 139 of the gap filler material 135, rather than the outermost lateral sidewall 131 of the die 112. The top of the groove 134 may have a smooth transition between the semiconductor layer 138 of the die and the gap filler material 135, or a notch as shown, wherein the material removal rate of the semiconductor layer 138 is faster, resulting in a greater depth d1 through the gap filler material 135 within the same side groove 130. Figure 8B This is a schematic top view of a molded IC structure 110 with side grooves and a segment passing through the die 112, according to an embodiment. Similar to the previously described embodiment, the outermost lateral sidewall 131 of the die 112 also corresponds to the outer edge of the IC structure 110. Figure 8C This is a schematic top view illustration of a molded IC structure with a segment passing through the die, according to an embodiment. Such embodiments can be achieved using only mechanical sawing (if required), or in combination with laser drilling, plasma etching, stealth etching, etc.

[0068] Briefly return to the reference Figure 3 and Figure 5 In the illustrated embodiment, the segmentation path 166 extends through the die 112 and through the gap filler material 135 that laterally surrounds adjacent dies 112. According to the embodiment, the dummy chip may also be fused-bonded or co-bonded to the electronic component 114 to aid in the mechanical sawing operation and to distribute stress evenly during sawing.

[0069] Figure 9 This is a schematic top view of a molded IC structure 110 including a dummy chiplet 170 prior to partitioning, according to an embodiment. For example, the dummy chiplet may be a silicon body layer and fused bonded by dielectric-dielectric bonding, or optionally hybrid bonded by adding dummy metal bonding pads. As can be seen, partitioning path 166 extends through the dummy chiplet 170. Figure 10 It is based on the implementation plan. Figure 9A schematic top view illustration of a molded IC structure including segmented virtual chiplets 170. In this configuration, the saw cut is formed primarily across a semiconductor material (e.g., silicon), cutting only through the gap-filling material 135 between the semiconductor elements. In this embodiment, the shared outer edge of the IC structure 110 may be formed by, for example... Figures 11A to 11B The outer edge 171 of the dummy chip 170 formed during sawing, as shown, and as Figure 12 The outermost transverse sidewall 131 of the core 112, which is also formed during the same sawing operation, is defined by both. Figure 11A In the illustrated embodiment, the side recess 130 may be formed across the entire outer edge of the IC structure 110 and within the dummy chiplet 170. Figure 11B In the illustrated embodiment, the side recess 130 may be selectively formed below the die 112, rather than below the dummy chip 170. (Comparison) Figure 11A and Figure 12 Due to different materials and material removal rates, the depth d1 of the side recess 130 can differ within the dummy chip 170 and the die 112. For example, the depth d1 in the dummy chip can be less than the depth within the die 112. The depth d1 can be greater over a short distance of the gap filler material 135 between the die 112 and the dummy chip, wherein the side recess 130 is formed across the entire outer edge of the IC structure 110. Therefore, the profile of the depth d1 can vary along the outer edge of the IC structure.

[0070] According to the implementation, the area occupied by the electronic component 114 can be an area determined for the IC structure 110. More specifically, the location of the sealing ring 162 can determine the location where the side recess 130 and the split can occur, since cutting through the sealing ring 162 provides a conduit for moisture and impurities to enter. Therefore, the planar layout according to the implementation can take into account the location of the corresponding sealing ring. Residual overlay markings associated with the placement of the die 112 can also indicate the integration process. Furthermore, in some implementations, it can be determined that the split path 166 does not need to travel through the silicon on all sides, and the bonding interfaces can be removed only on some sides of the IC structure 110.

[0071] Figure 13 This is a schematic top view of the molded IC structure, including the dummy chip 170 prior to partitioning, according to the implementation scheme. Figure 13 A cover mark 174 on the outer corner of die 112 is also shown. For example, the cover mark 174 may be formed on electronic component 114 for alignment of die 112 during direct bonding. In the particular embodiment illustrated, various structural features are shown together, although they do not necessarily need to be combined. Initially, Figure 13The illustrated splitting path 166 travels only along the two side edges of the IC structure 110 through the die 112. Splitting can be performed along the other edges through the bottom electronics 114 and the covering gap filler 135. Where the occupied area of ​​the die 112 is typically smaller than the area within the sealing ring 162 of the electronics, the corner cover mark 174 of the die 112 can typically be located within the outline of the sealing ring 162. However, in cases where the edge of the die 112 is cut during splitting according to an embodiment, the associated cover mark 174 of the edge with the split can also be split and removed from the final IC structure 110. This is due to... Figure 13 The cover mark 174 outside the segmentation path 166 is shown. Therefore, the resulting structure can be a cover mark 174 near one edge of the die 112 excluding the side groove 130, wherein the cover mark 174 is not located near the edge of the side groove 130 of the die 112 because a portion of the bonding interface has been removed.

[0072] Figure 14 It is a molded IC structure, including dummy chips after segmentation, according to the implementation plan (such as...). Figure 13 A schematic top view of the molded IC structure is shown. Furthermore, a close-up view provides additional details of the corresponding sealing rings 160, 162, the location of the overlay mark 174, and the chamfered corner 178 of the die 112 and the corresponding chamfer of the sealing ring 160 of the die 112. First, the overlay mark 174 may be located outside the sealing ring 162 of the electronic component 114 and may be completely removed along the dividing edge of the IC structure, including the outermost lateral sidewall 131 of the die 112. Furthermore, the die 112 may not include the chamfered corner 178 along such dividing edge, or at least the chamfered corner 178 may be incomplete.

[0073] To date, various configurations have been described in which high-risk, non-bonded areas at direct-bonded interfaces are removed through edge-cutting techniques, and particularly through a combination of grooving operations and subsequent segmentation operations. Implementations are not limited to applying such techniques across the entire edge or corner, but can apply grooving operations at selective locations to alleviate positioning stress. Figure 15 This is a schematic top view illustration of a molded IC structure including one or more partial cavities 180 according to an embodiment. The partial cavity 180 may be formed similarly to the side recess 130, although in this case it may be confined from the inside. The partial cavity can be of various shapes, depending on the stress to be alleviated. Exemplary structures include circular, L-shaped, rectangular, chamfered, and combinations thereof.

[0074] Figure 16 This is a schematic cross-sectional side view of an IC structure including a local cavity 180 formed by plasma etching, according to an embodiment. Figure 17This is a schematic cross-sectional side view of an IC structure including a local cavity 180 formed by laser etching, according to an embodiment. It should be understood that the specific structural arrangement may depend on the etching process. Figure 16 In the specific embodiments illustrated, plasma etching technology can produce a flat cavity top 184 and straight or tapered sidewalls 182. Figure 17 In the specific embodiment illustrated, laser etching technology can produce a conical cavity top 184 and straight or conical sidewalls 182. Associated with the specific etching technology... Figures 16 to 17 The illustrated flat and curved sidewalls and top can also coexist with any of the side recesses 130 described herein, as similar etching techniques can be used. When mounting the IC structure 110 to the module substrate 102 (such as...) Figure 1B After being applied to the illustrated module substrate, the bottom filler material 136 may penetrate and partially or completely fill the local cavity 180. Alternatively, the local cavity 180 may be substantially filled with one or more layers of cavity filler material (e.g., molding compound) and may include a protective liner layer (similar to the layer described above). Figures 20A to 20E (As described in the embodiments). For example, essentially filling may include complete filling, such as subtracting any volume occupied by an optional protective padding layer.

[0075] To date, implementations in which the final partitioning operation is performed on a global scale using mechanical blades or other methods have been described. Selective etching and partitioning can also be performed. Figures 18 to 19 This is a schematic top view illustration of a cutting sequence including selective segmentation of non-directly bonded surfaces according to an embodiment. As shown, when using cutting solutions such as laser etching and plasma etching, the resulting cut edges of IC structure 110 are not limited to straight lines. According to an embodiment, etching techniques such as plasma cutting and / or stealth cutting are used to substantially remove non-directly bonded interfaces in IC structure 110. Two exemplary die (or chipset) arrangements are illustrated before and after segmentation. As shown, a multi-die 112 system can be etched using selective methods achieved by laser or plasma etching, wherein the amount of gap filler material 135 is limited.

[0076] Figures 20A to 20E This is a schematic cross-sectional side view illustration of an IC structure with various side grooves and double-sided molding according to an embodiment. Specifically, Figures 20A to 20E The IC structure is similar to those previously described herein, with the addition of some processing (such as the encapsulation of electronic component 114), which may optionally be incorporated according to the implementation.

[0077] Similar to previous embodiments, the IC structure may include an electronic component 114 having a first bonding surface 116, and one or more dies 112, each die 112 including a second bonding surface 118 directly bonded to the first bonding surface 116. A side recess 130 may be formed to extend through the entire thickness of the electronic component 114 and optionally extend into the die 112. The side recess 130 may define a recess sidewall 132 extending through the entire thickness of the electronic component 114 and a recess top 134 within the die 112. The recess top 134 may additionally intersect with the outermost lateral sidewall 131 of the die 112, such that the outermost lateral sidewall 131 is outside the recess sidewall 132. In some embodiments, the recess top 134 may extend into a gap-filling material 135 (e.g., molding compound). According to embodiments, the side recess 130 may extend to various depths. As shown, the side recess 130 may extend beyond the second bonding surface 118 and into the die 112. For example, the side groove may extend into or beyond the stacked structure 140 and into the semiconductor layer 138.

[0078] according to Figures 20A to 20E In the illustrated embodiment, the IC structure 110 may be double-molded (or otherwise filled), including a gap filler material 135 (e.g., a first molding compound layer) and one or more additional recess filler material layers 186 (e.g., molding compound layers) within the side recesses 130. The gap filler material 135 and the one or more additional recess filler material layers 186 may be the same or different materials to address issues such as warpage, stress, and cost.

[0079] Now for reference Figure 20A Electronic component 114 may be similar to those previously described. For example, electronic component 114 may be a die, a dielectric, etc. As shown, the electronic component may include a first bonding surface 116, a plurality of metal bonding pads 158, and a dielectric bonding layer 156. Similarly, one or more dies 112 may each include a second bonding surface 118, a plurality of metal bonding pads 154, and a dielectric bonding layer 152. Electronic component 114 may also include a semiconductor layer 144 (which may also be a bulk layer not formed of silicon) and a BEOL stack structure 142. Alternatively, the semiconductor layer 144 may be replaced by another bulk material (such as glass). The BEOL stack structure 142 may include electrical wiring and optionally include die-to-die wiring between dies 112. Multiple vias 146 (e.g., through-silicon vias) may extend through the semiconductor layer 144 and the back-side dielectric layer 148 to contact the terminal 150, on which solder bumps (which may also be solder tips) 125 may be placed.

[0080] exist Figure 20AIn the illustrated specific embodiment, the side recess 130 may be filled with one or more optional padding layers 188 (conformal to the profile) and form the profile of the recess sidewalls 132 and the recess top 134 (e.g., having a substantially uniform thickness along the recess sidewalls and the recess top). The padding layers 188 may conform to the profile and form the profile along the recess sidewalls and the recess top of the side recess, wherein the padding layers are between one or more recess filling material layers and the side recess. The remaining portion of the side recess 130 may be filled with one or more recess filling material layers 186 (e.g., molding compound material).

[0081] Still referencing Figure 20A In the illustrated embodiment, passivation layer 190 may be deposited over one or more recess-fill material layers 186, pad layers 188, and semiconductor layers 144 (or other body layers, etc.) (e.g., over their planarized surfaces). Thus, passivation layer 190 may span beneath one or more recess-fill material layers 186 and electronic component 114. A plurality of terminals 150 may additionally be formed beneath the passivation layer. Both pad layers 188 and passivation layer 190 may be formed of a suitable material (e.g., silicon nitride) to act as barrier layers, such as to prevent the ingress of moisture or the diffusion of other materials. A solder mask layer 192 may optionally be formed beneath passivation layer 190 to facilitate the formation of terminals 150. Figure 20A In the particular embodiment illustrated, the IC structure 110 includes sidewalls 194 spanning a gap filler 135, a liner layer 188, one or more recess filler layers 186, and a passivation layer 190. Figure 20A In the particular embodiment illustrated, the side recess 130 includes multiple recess layers with different depths and widths. This can be attributed to multiple etching operations, such as a first etching operation that partially or completely penetrates the electronic component 114, and a second etching operation that penetrates the hybrid bonding interface formed by the metal bonding pads 154, 158 and the dielectric bonding layers 152, 156.

[0082] Now for reference Figure 20B An example of IC structure 110 (similar to...) Figure 20A One difference in the IC structure is that the side recess 130 may have been formed by a single etching operation, with a single-layer top 134. Figure 20C The illustrated implementation scheme is similar to Figure 20B One difference in the implementation is that the package separation may include cutting through the edge of die 112. In the illustrated implementation, the sidewall 194 of IC structure 110 spans the outermost lateral sidewall 131 of die 112, the pad layer 188, one or more recess filler material layers 186, and the passivation layer 190. Figure 20D The illustrated implementation scheme is similar to Figure 20AIn one embodiment, a plurality of groove-filling material layers 186A, 186B fill the side groove 130. As shown, the first groove-filling material layer 186A may partially or completely fill the upper region 130B of the side groove 130 (e.g., formed by a second etching operation), and the second groove-filling material layer 186B may partially or completely fill the lower region 130A of the side groove (e.g., formed by a first etching operation). Figure 20E The illustrated implementation scheme is similar to Figure 20B In one embodiment, a first groove-filling material layer 186A and a second groove-filling material layer 186B fill the side groove 130. According to the embodiment, the first and second gap-filling material layers may be formed of the same or different materials.

[0083] Now for reference Figure 20F This illustrates yet another variation. In this illustrated embodiment, the side recess 130 may extend entirely through the thickness of the die 112. In such an embodiment, an optional liner layer 188 may span the entire outermost lateral sidewall 131 of the die 112 (which will also correspond to the recess sidewall 132). One or more recess-filling material layers 186 may then be deposited to fill the side recess 130. The IC structure 110 may then be segmented through the passivation layer 190 and the one or more recess-filling material layers 186.

[0084] Figures 21A to 21M This is a schematic cross-sectional side view illustrating a method for forming an IC structure with side grooves and a double-sided molded part according to an embodiment. Specifically, regarding... Figure 20A The IC structure provides Figures 21A to 21M The illustrated process sequence is provided, but it should be understood that various process variations can be incorporated to manufacture other IC structures, such as... Figures 20B to 20F The IC structures illustrated herein. Figure 21A As shown, the sequence may begin with directly bonding the die 112 to the electronic component substrate 114S (e.g., fusion bonding, hybrid bonding), which can be at the wafer level. The die 112 can then be encapsulated on the electronic component substrate 114S using a gap-filling material 135 (such as molding compound), as... Figure 21B As shown. Then, optionally, a thinning operation can be performed thereafter, in which the back side of the gap filler 135 and optionally the die 112 is ground back to form a planarized surface 137. The molded structure can then be flipped, wherein the planarized surface 137 is attached to the carrier substrate 196, for example, using an adhesive layer, as shown. Figure 21C As shown. Then, an optional polishing operation can be performed afterwards to reduce the thickness of the electronic component substrate 114S. Figure 21DIn the particular configuration illustrated, the semiconductor layer 144 (or other body layer) may be thinned. If the through-silicon vias 146 are pre-formed, they may optionally not be exposed during this operation.

[0085] Now for reference Figure 21E A first etching operation can be performed to pattern the lower region 130A of the sidewall recess 130 through the semiconductor layer 144 of the electronic component substrate 114S. For example, this may optionally remove exclusion zone (KOZ) silicon regions. Further etching can then be performed as follows: Figure 21F The second etching operation shown further and completely removes the KOZ hybrid bonding layer and forms the upper region 130B of the sidewall recess 130. A suitable etching technique, such as plasma etching, can be selected based on the material. It should be understood that this multi-operation etching sequence is optional, and a single etching operation can be performed to form the sidewall recess 130.

[0086] like Figure 21G As shown, a liner layer 188 (conformal to the profile) may optionally be formed, and the profiles of the recess sidewalls 132 and the recess top 134 may be formed (e.g., having a substantially uniform thickness along the recess sidewalls and the recess top). The liner layer 188 may be a single layer (e.g., SiN). x (1) or multiple layers. In an embodiment, the liner layer comprises SiN x SiO2, SiN x The layers are stacked sequentially. The padding layer 188 may be substantially conformal to the profile and form the profile of the groove sidewall 132 and groove top 134 of the sidewall groove (e.g., having a substantially uniform thickness along the groove sidewall and groove top).

[0087] After depositing the optional backing layer 188, one or more groove-filling material layers 186 (e.g., molding compound material) may be applied, such as Figure 21H As shown. For example, this can be achieved through a molding operation in which molding compound material is applied within the sidewall recess 130 and optionally over an optional padding layer 188 that spans the patterned electronic component substrate and is within the sidewall recess 130. Further processing can then be performed as follows: Figure 21I The polishing operation shown creates a planarized surface 187 spanning the recess-filling material layer 186, the padding layer 188, and the electronic component substrate 114S. For example, the polishing operation may thin the semiconductor layer 144 until the via 146 is exposed along the planarized surface 187.

[0088] A passivation layer 190 may then be deposited on the planarized surface 187. The passivation layer 190 may be formed of a suitable material (e.g., silicon nitride) to act as a barrier layer, such as to prevent the ingress of moisture or the diffusion of other materials. A solder mask layer 192 may optionally be formed on the passivation layer 190, and the solder mask layer and the passivation layer may then be patterned, for example by electroplating, to facilitate the formation of the terminals 150 and the solder bumps 125.

[0089] At this point, the patterned structure can be removed from the carrier substrate 196 and attached to the frame 172, for example, using adhesive tape. Figure 21L As shown, solder reflow is then performed and the circuit is divided into multiple IC structures 110, as follows. Figure 21M As shown, the bond can then be unbonded from frame 172.

[0090] According to embodiments, mechanical sawing can be performed for package dicing, in which the sawing path 166 can travel through the semiconductor layer, gap filler 135, and recess filler layer 186 and / or pad layer 188 of the die 112. Alternatively, other techniques such as plasma cutting can be used to form the sawing path. Furthermore, it has been observed that high-stress regions can be located along the corner regions of the die 112. According to some embodiments, these high-stress regions can be removed during side recess formation and dicing. A dummy chiplet 170 can also be included to facilitate the sawing process. In some embodiments, the planar layout of the die 112 within the IC structure 110 can be an asymmetrical arrangement so that the sawing path 166 cuts through as many corners and edges of the die 112 as possible, thereby reducing the number of potentially unbonded and high-stress regions in the IC structure 110.

[0091] Figures 22A to 22B This is a schematic top plan view illustrating the location of the slicing paths and high-stress corner regions for the three die 112 IC structures according to the implementation scheme. As shown, the sawing path 166 does not pass through the die 112 corners annotated with solid lines. A single sawing path 166 extends through the die 112 corners annotated with dashed lines, and two sawing paths 166 extend through the die 112 corners annotated with stars. Now refer to Figure 22A In the layout, in the first arrangement, the dummy chiplet 170 can be arranged along the edge of the IC structure, such that the sawing path 166 travels through the chiplet 170 in a limited number of directions. This arrangement results in four die corners 112 not being sawed and potentially being high-stress locations. Figure 22BIn this arrangement, the identical dies 112 have been rearranged such that the sawing path 166 preferentially travels through the dies 112, while only a single sawing path 166 extends through the dummy chip 170 between the dies. Furthermore, the multiple dummy chips 170 have been reduced to a single, larger dummy chip 170. As shown, this arrangement results in two die 112 corners not being sawed, which could potentially be high-stress areas. Overall, Figures 22A to 22B The illustrated rearrangement changes from two double-cut corners (star shape) to four double-cut corners (star shape), retains six single-cut corners (dashed circles), and changes four uncut corners (solid circles) to two uncut corners (solid circles). In addition, the number of sawn edges of the core 112 changes from five edges to seven edges.

[0092] Figures 23A to 23B This is a schematic top-view diagram illustrating the segmentation paths for the three-die IC structure and the location of high-stress corner areas according to the implementation plan. Figures 23A to 23B The arrangement illustrates a similar concept used to increase the number of bends and edges of the sawn core. As shown in the figure, in Figure 23A In the middle, four dummy chips 170 are positioned along the corners of the IC structure 110 to be segmented. Figure 23B In the illustrated implementation, four dummy chips 170 can be combined into two larger dummy chips 170, allowing the sawing path 166 to travel along more of the die 112 corners and edges.

[0093] In general, Figures 23A to 23B The illustrated rearrangement changes from zero double-cut corners (star shape) to two double-cut corners (star shape), retains eight single-cut corners (dashed circles), and changes four uncut corners (solid circles) to two uncut corners (solid circles). In addition, the number of sawn edges of the core 112 changes from four edges to six edges.

[0094] It should be understood that Figures 22A to 23B The arrangement shown is compatible with any of the IC structures in IC structure 110 described herein, and these principles can also be applied to IC structures with a greater number of dies. Furthermore, it should be understood that the sawing path 166 may optionally travel within the sidewall recess 130 described herein or in the absence of the sidewall recess 130.

[0095] Although Figures 22A to 23B The illustrated principle can be used to reduce the number of undivided (unsaved) die corners 112, but eliminating undivided die corners using IC structure 110 may not be feasible. According to the implementation, these potentially high-stress areas can be chamfered to reduce stress. Figure 24This is a schematic top plan view of a two-die IC structure 110 with a chamfered corner 178 according to an implementation scheme. The chamfered corner is not divided along with the IC structure. The chamfered corner 178 can be straight, such as... Figure 14 As shown, or optionally circular, such as Figure 24 As shown. It should be understood that although a two-die arrangement 112 is illustrated, the chamfered corner 178 may be internally integrated within the IC die structure 110 to reduce stress at the non-segmented die corners, which could otherwise be potentially high-stress areas.

[0096] When utilizing various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming integrated circuit structures with side grooves. Although the embodiments have been described in language specific to structural features and / or methodological behavior, it should be understood that the appended claims are not necessarily limited to the specific features or behaviors described. Rather, the specific features and behaviors disclosed should be understood as embodiments of the claims for illustrative purposes.

Claims

1. An integrated circuit structure, comprising: an electronic component including a first bonding surface; a die including a second bonding surface directly bonded to the first bonding surface; a side recess extending through an entire thickness of the electronic component and into the die; wherein the side recess defines a recess sidewall extending through the entire thickness of the electronic component and a recess top within the die; and wherein the recess top intersects an outermost lateral sidewall of the die such that the outermost lateral sidewall is outside of the recess sidewall.

2. The integrated circuit structure of claim 1, wherein the first bonding surface and the second bonding surface are hybrid bonded or fusion bonded together.

3. The integrated circuit structure of claim 2, wherein the die includes: a semiconductor layer; and a back end of line (BEOL) build-up structure on the semiconductor layer; wherein the recess top is in the semiconductor layer.

4. The integrated circuit structure of claim 3, further comprising: a second die including a third bonding surface directly bonded to the first bonding surface; and a gap fill material laterally between the first die and the second die.

5. The integrated circuit structure of claim 4, further comprising: a second side recess extending through the entire thickness of the electronic component and into the second die; wherein the second side recess defines a second recess sidewall extending through the entire thickness of the electronic component and a second recess top within the second die; and wherein the second recess top intersects a second outermost lateral sidewall of the second die such that the second outermost lateral sidewall is outside of the second recess sidewall.

6. The integrated circuit structure of claim 5, wherein the second outermost lateral sidewall of the second die is parallel to the outermost lateral sidewall of the first die.

7. The integrated circuit structure of claim 4, further comprising a small chip including a fourth bonding surface directly bonded to the first bonding surface, wherein the gap fill material is laterally between the small chip and both the second die and the first die.

8. The integrated circuit structure of claim 7, wherein the side recess does not extend into the small chip.

9. The integrated circuit structure of claim 8, wherein: the electronic component includes a first BEOL build-up structure; the first BEOL build-up structure includes a first seal ring adjacent to the recess sidewall; the die includes a second BEOL build-up structure; and the second BEOL build-up structure includes a second seal ring adjacent to the recess sidewall; wherein the first seal ring extends below the small chip.

10. The integrated circuit structure of claim 4, wherein the die comprises one or more chamfered corners, and the side recess does not comprise a chamfered corner along the outermost lateral side wall of the die.

11. The integrated circuit structure of claim 10, wherein the die comprises a seal ring adjacent to the recess side wall, wherein the seal ring comprises a chamfered corner adjacent to the recess side wall.

12. The integrated circuit structure of claim 3, further comprising a gap fill material laterally surrounding the die, wherein the side recess extends into the gap fill material, and the recess top is additionally formed in the gap fill material.

13. The integrated circuit structure of claim 3, wherein the electronic component is selected from the group consisting of a die and an interposer.

14. The integrated circuit structure of claim 1 : further comprising a local cavity extending through the entire thickness of the electronic component and into the die; wherein the local cavity defines a cavity side wall extending through the entire thickness of the electronic component and a cavity top within the die; and wherein the local cavity is completely surrounded by the electronic component and the die.

15. The integrated circuit of claim 14, wherein the local cavity is substantially filled with one or more layers of cavity fill material.

16. The integrated circuit of claim 1, further comprising one or more layers of recess fill material substantially filling the side recess.

17. The integrated circuit of claim 16, further comprising a liner layer spanning the side recess, the liner layer conforming to the profile and forming an outer shape along the recess side wall and the recess top of the side recess, wherein the liner layer is between the one or more layers of recess fill material and the side recess.

18. The integrated circuit of claim 16, further comprising: a passivation layer spanning below the one or more layers of recess fill material and the electronic component; and a plurality of terminals below the passivation layer.

19. An electronic module, comprising: a module substrate; an integrated circuit structure mounted on the module substrate, the integrated circuit structure comprising: an electronic component comprising a first bonding surface; a die comprising a second bonding surface directly bonded to the first bonding surface; a side recess extending through an entire thickness of the electronic component and into the die; wherein the side recess defines a recess side wall extending through the entire thickness of the electronic component and a recess top within the die; and wherein the recess top intersects an outermost lateral side wall of the die such that the outermost lateral side wall is outside of the recess side wall. ​ 20. The electronic module of claim 19, further comprising an underfill material between the integrated circuit structure and the module substrate, wherein the underfill material fills the side recess.

21. The electronic module of claim 20, further comprising a gap fill material laterally surrounding the die, wherein the side recess extends into the gap fill material.

22. The electronic module of claim 20, wherein the first bonding surface and the second bonding surface are mixedly bonded or fusion bonded together.

23. The electronic module of claim 20: further comprising a partial cavity extending through the entire thickness of the electronic component and into the die; wherein the partial cavity defines a cavity sidewall extending through the entire thickness of the electronic component and a cavity top within the die; wherein the partial cavity is completely surrounded by the electronic component and the die; and wherein the underfill material fills the partial cavity.

24. The electronic module of claim 19, further comprising: one or more recess fill material layers that substantially fill the side recess; and an underfill material between the integrated circuit structure and the module substrate; wherein the underfill material does not intrude inside the side recess.

25. The electronic module of claim 19: further comprising a partial cavity extending through the entire thickness of the electronic component and into the die; an underfill material between the integrated circuit structure and the module substrate; wherein the partial cavity defines a cavity sidewall extending through the entire thickness of the electronic component and a cavity top within the die; wherein the partial cavity is completely surrounded by the electronic component and the die; and wherein the partial cavity is substantially filled with one or more cavity fill material layers and the underfill material does not intrude inside the partial cavity.

26. A method of forming an integrated circuit structure, the method comprising: directly bonding a die to an electronic component substrate; encapsulating the die on the electronic component substrate with a gap fill material; forming a side recess through an entire thickness of the electronic component substrate and into the die, wherein the side recess defines a recess sidewall extending through the entire thickness of the electronic component substrate and a recess top within the die; and sawing through the side recess to singulate the electronic component, wherein the recess top intersects an outermost lateral sidewall of the die such that the outermost lateral sidewall is outside the recess sidewall.

27. The method of claim 26, wherein forming the side recess comprises laser drilling.

28. The method of claim 27, wherein directly bonding the die to the electronic component substrate comprises mixedly bonding or fusion bonding.

29. The method of claim 26, further comprising: One or more recess fill material layers are deposited in the side recess prior to sawing through the side recess to separate the electronic component.

30. An integrated circuit structure, comprising: an electronic component including a first bonding surface; a die including a second bonding surface directly bonded to the first bonding surface; a partial cavity extending through an entire thickness of the electronic component and into the die; wherein the partial cavity defines a cavity sidewall extending through the entire thickness of the electronic component and a cavity top within the die; and wherein the partial cavity is completely surrounded by the electronic component and the die.

31. The integrated circuit structure of claim 30, wherein the electronic component includes a first sealing ring and the die includes a second sealing ring, and the partial cavity extends through the electronic component and into the die outside of the first sealing ring and the second sealing ring.

32. The integrated circuit structure of claim 30, wherein the first bonding surface and the second bonding surface are hybrid bonded or fusion bonded together.

33. The integrated circuit structure of claim 32, wherein the die includes: a semiconductor layer; and a back end of line (BEOL) build-up structure on the semiconductor layer; wherein the cavity top is in the semiconductor layer.

34. The integrated circuit structure of claim 30, wherein the partial cavity is substantially filled with one or more cavity fill material layers.

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