Frequency converter service life prediction method and system

Abstract

The invention discloses a frequency converter service life prediction method and system, and relates to the technical field of frequency converter prediction.The frequency converter service life prediction system comprises a state detection module, three-phase imbalance detection is conducted on electric energy output by a frequency converter module, and when three-phase imbalance occurs, a micro-control module controls a power module to be powered off and stops inversion and frequency conversion work of the frequency converter module; meanwhile, six groups of driving signals are sequentially output, and the output time of each group of driving signals in the six groups of driving signals is the same, so that three groups of upper half switching tubes and three groups of lower half switching tubes of the frequency converter module are driven to be independently conducted; and the control state detection module carries out saturation conduction voltage drop detection on the frequency converter module and carries out frequency converter service life prediction according to a set detection threshold value. The method and system can reduce the detection complexity of the frequency converter, can automatically complete the state detection and life prediction of the frequency converter, and improve the detection efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of frequency converter prediction, and specifically relates to a frequency converter life prediction method and system. BACKGROUND

[0002] A frequency converter is an electronic device that can invert and convert the input DC power and drive a three-phase motor to work. The frequency converter is generally composed of six groups of IGBTs. In the prior art, in order to detect the working state of the IGBTs in the frequency converter in real time, avoid the factors of IGBT aging and short circuit, and prevent voltage imbalance or phase breakage of three-phase power, which affects the working efficiency of surrounding elements. In the prior art, a plurality of voltage and current detection devices are used to individually detect the working state of the six groups of IGBTs and predict the service life of the frequency converter, or relevant personnel use relevant voltage and current detection devices to individually detect the working state of the six groups of IGBTs and predict the service life of the frequency converter. The detection cost is high and the detection means is complex, and thus needs to be improved. SUMMARY

[0003] The present application provides a frequency converter life prediction method and system to solve the problems in the background art.

[0004] According to the present application, a frequency converter life prediction system is provided, which comprises:

[0005] A power module is used to connect DC power and control power transmission.

[0006] A frequency converter module is connected with the power module and the micro-control module, and is used to control the DC power to be inverted and converted and output three-phase power by controlling the conduction state of three groups of upper half switch tubes and three groups of lower half switch tubes. When six groups of the same type of driving signals output by the micro-control module are sequentially received, the three groups of upper half switch tubes and the three groups of lower half switch tubes are controlled to be individually conducted in sequence.

[0007] A state detection module is connected with the frequency converter module, and is used to detect three-phase imbalance of the three-phase power and output a first detection signal when the three-phase imbalance occurs, detect saturation conduction voltage drop, and output a second detection signal when the detected signal is greater than a set first detection threshold, and output a third detection signal when the second detection signal is greater than a set second detection threshold.

[0008] The micro-control module is connected with the state detection module, the power supply module and the detection control module, is used for driving the conduction state of the three groups of upper half switch tubes and the three groups of lower half switch tubes of the frequency converter module and controlling the frequency converter module to perform inversion and frequency conversion, when receiving the first detection signal, stopping driving the frequency converter module to perform inversion and frequency conversion and controlling the power supply module to stop power transmission, and sequentially providing six groups of same type driving signals for the frequency converter module and the detection control module, receiving the first detection signal, the second detection signal and the third detection signal;

[0009] The detection control module is connected with the frequency converter module and the state detection module, is used for selecting a signal transmission path according to the six groups of driving signals output by the micro-control module, controlling the connection state of the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module and the state detection module and controlling the connection state of the three groups of upper half switch tubes and the three groups of lower half switch tubes and the ground end, and controlling the state detection module to perform saturation conduction voltage drop detection on the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module according to the connection state of the three groups of upper half switch tubes and the three groups of lower half switch tubes and the state detection module and the ground end.

[0010] As a further scheme of the present application, the state detection module comprises an unbalance detection unit and a single detection unit;

[0011] Preferably, the unbalance detection unit is connected with the micro-control module, is used for performing three-phase unbalance detection on three-phase power and outputting the first detection signal when three-phase unbalance occurs, and the first detection signal is received by the micro-control module;

[0012] The single detection unit is connected with the micro-control module and the detection control module, is used for performing saturation conduction voltage drop detection on the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module connected by the detection control module, and outputting the second detection signal when the detected signal is greater than a set first detection threshold value, and outputting the third detection signal when the detected signal is greater than a set second detection threshold value, and the second detection signal and the third detection signal are received by the micro-control module.

[0013] As a further scheme of the present application, the detection control module comprises a first detection unit and a second detection unit;

[0014] Preferably, the first detection unit is connected with the micro-control module, the frequency converter module and the state detection module, is used for selecting a signal transmission path according to three groups of driving signals in the six groups of driving signals output by the micro-control module, controlling the connection state of the three groups of upper half switch tubes in the frequency converter module and the state detection module and the ground end, and controlling the state detection module to perform saturation conduction voltage drop detection on the three groups of upper half switch tubes in the frequency converter module;

[0015] The second detecting unit is connected with the micro-control module, the frequency converter module and the state detecting module, and is used for selecting a signal transmission path according to three groups of driving signals in the six groups of driving signals output by the micro-control module, controlling the connection state of three groups of lower half switch tubes in the frequency converter module and the state detecting module and the ground, and controlling the state detecting module to detect the saturation conduction voltage drop of the three groups of lower half switch tubes in the frequency converter module.

[0016] As a further scheme of the present application, the power supply module comprises a power supply port, a first MOS tube, a first resistor, a first switch tube, a first diode and a second diode; the micro-control module comprises a first controller;

[0017] Preferably, the first end of the power supply port is connected with the drain of the first MOS tube and connected with the gate of the first MOS tube and the collector of the first switch tube through the first resistor, the emitter of the first switch tube is grounded, the base of the first switch tube is connected with the cathode of the first diode and the cathode of the second diode, and the anode of the first diode and the anode of the second diode are respectively connected with the IO7 end and the IO8 end of the first controller.

[0018] As a further scheme of the present application, the frequency converter module comprises a first power tube, a second power tube, a third power tube, a fourth power tube, a fifth power tube, a sixth power tube and an output port;

[0019] Preferably, the collector of the first power tube is connected with the collector of the third power tube, the collector of the fifth power tube and the source of the first MOS tube, the emitter of the first power tube is connected with the collector of the second power tube and the first end of the output port, the emitter of the third power tube is connected with the collector of the fourth power tube and the second end of the output port, the emitter of the fifth power tube is connected with the collector of the sixth power tube and the third end of the output port, the emitter of the second power tube is connected with the emitter of the fourth power tube, the emitter of the sixth power tube and the second end of the power supply port, and the gate of the first power tube, the gate of the second power tube, the gate of the third power tube, the gate of the fourth power tube, the gate of the fifth power tube and the gate of the sixth power tube are respectively connected with the IO1 end, the IO2 end, the IO3 end, the IO4 end, the IO5 end and the IO6 end of the first controller.

[0020] As a further scheme of the present application, the first detecting unit comprises a first analog switch, a first logic device, a second logic device and a third logic device;

[0021] Preferably, the third end, the eighth end, the tenth end and the first end of the first analog switch are connected to the emitter of the first power tube, the emitter of the third power tube, the emitter of the fifth power tube and the emitter of the second power tube respectively, the twelfth end, the sixth end and the fifth end of the first analog switch are connected to the Y end of the first logic, the Y end of the second logic and the Y end of the third logic respectively, the B end of the first logic is connected to the B end of the second logic, the B end of the third logic and the IO8 end of the first controller, the A end of the first logic, the A end of the second logic and the A end of the third logic are connected to the IO5 end, the IO3 end and the IO1 end of the first controller respectively, the fourth end, the ninth end, the eleventh end and the second end of the first analog switch are grounded, and the thirteenth end of the first analog switch is connected to the IO7 end of the first controller.

[0022] As a further scheme of the present application, the second detection unit comprises a second analog switch, a fourth logic, a fifth logic and a sixth logic.

[0023] Preferably, the eleventh end, the second end, the fourth end and the ninth end of the second analog switch are connected to the emitter of the first power tube, the emitter of the third power tube, the emitter of the fifth power tube and the collector of the first power tube respectively, the sixth end of the second analog switch is connected to the IO8 end of the first controller, the twelfth end, the thirteenth end and the fifth end of the second analog switch are connected to the Y end of the fourth logic, the Y end of the fifth logic and the Y end of the sixth logic respectively, the A end of the fourth logic is connected to the B end of the fifth logic, the A end of the sixth logic and the IO7 end of the first controller, the B end of the fourth logic, the A end of the fifth logic and the B end of the sixth logic are connected to the IO2 end, the IO4 end and the IO6 end of the first controller respectively, and the eighth end of the second analog switch is connected to the tenth end, the first end and the third end of the second analog switch.

[0024] As a further scheme of the present application, the single detection unit comprises a second resistor, a third resistor, a first capacitor, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode, a second capacitor, a fourth resistor, a fifth resistor, a first voltage stabilizer, a first operational amplifier, a first reference power supply, a second reference power supply, a first comparator and a second comparator.

[0025] Preferably, the cathode of the third diode is connected to one end of the second resistor and the third end of the second analog switch, and the other end of the second resistor, the anode of the fifth diode, the cathode of the fourth diode, one end of the first capacitor and one end of the third resistor are connected through the second capacitor, the other end of the first capacitor is connected to the anode of the sixth diode, the cathode of the seventh diode and the other end of the third resistor, the anode of the third diode is connected to the anode of the fourth diode and the non-inverting terminal of the first operational amplifier and is connected to the first voltage source and one end of the fourth resistor through the fifth resistor, the other end of the fourth resistor is connected to the inverting terminal of the first operational amplifier and the anode of the seventh diode, the output terminal of the first operational amplifier is connected to the non-inverting terminal of the first comparator and the non-inverting terminal of the second comparator, the inverting terminal of the first comparator and the inverting terminal of the second comparator are respectively connected to the first reference power supply and the second reference power supply, and the output terminal of the first comparator and the output terminal of the second comparator are respectively connected to the IO9 terminal and the IO10 terminal of the first controller.

[0026] As a further scheme of the present application: the unbalance detection unit comprises a mutual inductor device, a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a third operational amplifier, a first processing device, a second processing device, a third comparator, a fourth comparator, a third reference power supply and a fourth reference power supply.

[0027] Preferably, the first detection end, the second detection end and the third detection end of the mutual inductor device detect the first end, the second end and the third end of the output port respectively, the first output end, the second output end and the third output end of the mutual inductor device are respectively connected to the non-inverting terminal of the second operational amplifier, the input terminal of the first processing device and the input terminal of the second processing device, the inverting terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier and is connected to one end of the seventh resistor, the inverting terminal of the third operational amplifier, the output terminal of the first processing device and the output terminal of the second processing device through the sixth resistor, the non-inverting terminal of the third operational amplifier is connected to ground through the eighth resistor, the output terminal of the third operational amplifier is connected to the other end of the seventh resistor, the inverting terminal of the third comparator and the non-inverting terminal of the fourth comparator, the non-inverting terminal of the third comparator and the inverting terminal of the fourth comparator are respectively connected to the third reference power supply and the fourth reference power supply, and the output terminal of the third comparator and the output terminal of the fourth comparator are respectively connected to the IO11 terminal and the IO12 terminal of the first controller.

[0028] In addition, in order to achieve the above-mentioned purpose, the present application further provides a frequency converter life prediction method, and the control method is applied to the frequency converter life prediction system, and the steps of the method comprise:

[0029] Acquiring the three-phase unbalance condition detected by the state detection module;

[0030] When detecting three-phase imbalance, stop the inverter and frequency conversion of the frequency converter module and control the state detection module to switch the signal transmission path, control the connection state of the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module and the state detection module and the ground, and control the state detection module to detect the saturation conduction voltage drop of the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module in turn.

[0031] The saturation conduction voltage drop state and aging degree of the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module detected by the state detection module are obtained, and the frequency converter life is predicted.

[0032] Compared with the prior art, the frequency converter life prediction method and system can detect three-phase imbalance of the power output by the state detection module, stop the inverter and frequency conversion of the frequency converter module when three-phase imbalance occurs, and control the power module to stop power supply by the micro control module. At the same time, six groups of driving signals are output in turn, and the output time of each group of driving signals in the six groups of driving signals is the same, so as to drive the three groups of upper half switch tubes and the three groups of lower half switch tubes of the frequency converter module to conduct individually. The detection control module controls the state detection module to detect the saturation conduction voltage drop of the frequency converter module according to the conduction state of the switch tube of the frequency converter module, and predicts the frequency converter life according to the set detection threshold. The detection complexity of the frequency converter is reduced, and the frequency converter state detection and life prediction can be automatically completed, and the detection efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creating laborious work.

[0034] Figure 1 A principle block diagram of a frequency converter life prediction system provided by the embodiment of the present application.

[0035] Figure 2 A principle block diagram of a state detection module provided by the embodiment of the present application.

[0036] Figure 3 A principle block diagram of a detection control module provided by the embodiment of the present application.

[0037] Figure 4 A circuit diagram of a frequency converter life prediction system provided by the embodiment of the present application.

[0038] Figure 5 A circuit diagram of a single detection unit provided by the embodiment of the present application.

[0039] Figure 6 The circuit diagram of the unbalance detection unit provided for the embodiment of the present application.

[0040] Figure 7 The flow chart of the frequency converter life prediction method provided for the embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0042] In one embodiment, referring to Figure 1 , Figure 2 and Figure 3 , a frequency converter life prediction system comprises:

[0043] Specifically, the power module 1 is configured to access direct current power and control power transmission.

[0044] The frequency converter module 2 is connected with the power module 1 and the micro-control module 4, and is configured to control the direct current power to be invertered and frequency-converted and output three-phase power by controlling the conduction states of three groups of upper half switch tubes and three groups of lower half switch tubes, and control the three groups of upper half switch tubes and the three groups of lower half switch tubes to be individually conducted in turn when six groups of driving signals of the same type output by the micro-control module 4 are received in turn.

[0045] The state detection module 3 is connected with the frequency converter module 2, and is configured to detect three-phase unbalance of the three-phase power and output a first detection signal when the three-phase unbalance occurs, detect saturation conduction voltage drop and output a second detection signal when the detected signal is greater than a set first detection threshold, and output a third detection signal when the second detection signal is greater than a set second detection threshold.

[0046] The micro-control module 4 is connected with the state detection module 3, the power module 1 and the detection control module 5, and is configured to drive the conduction states of the three groups of upper half switch tubes and the three groups of lower half switch tubes of the frequency converter module 2 and control the frequency converter module 2 to be invertered and frequency-converted, stop driving the frequency converter module 2 to be invertered and frequency-converted and control the power module 1 to stop power transmission when the first detection signal is received, and provide six groups of driving signals of the same type for the frequency converter module 2 and the detection control module 5 in turn and in a timing manner, and receive the first detection signal, the second detection signal and the third detection signal.

[0047] The detection control module 5 is connected with the frequency converter module 2 and the state detection module 3, and is used for selecting a signal transmission path according to the six groups of driving signals output by the micro control module 4, controlling the on-off state of the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module 2 and the state detection module 3, and controlling the on-off state of the three groups of upper half switch tubes and the three groups of lower half switch tubes and the ground end, according to the on-off state of the three groups of upper half switch tubes and the three groups of lower half switch tubes and the state detection module 3 and the ground end, and controlling the state detection module 3 to detect the saturation conduction voltage drop of the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module 2.

[0048] Further, the state detection module 3 includes an unbalance detection unit 301 and a single detection unit 302.

[0049] Specifically, the unbalance detection unit 301 is connected with the micro control module 4, and is used for detecting three-phase unbalance of three-phase electric energy and outputting a first detection signal when the three-phase unbalance occurs, which is received by the micro control module 4.

[0050] The single detection unit 302 is connected with the micro control module 4 and the detection control module 5, and is used for detecting the saturation conduction voltage drop of the three groups of upper half switch tubes and the three groups of lower half switch tubes in the frequency converter module 2 connected by the detection control module 5, and outputting a second detection signal when the detected signal is greater than a first detection threshold, and outputting a third detection signal when the detected signal is greater than a second detection threshold, which are received by the micro control module 4.

[0051] Further, the detection control module 5 includes a first detection unit 501 and a second detection unit 502.

[0052] Specifically, the first detection unit 501 is connected with the micro control module 4, the frequency converter module 2 and the state detection module 3, and is used for selecting a signal transmission path according to three groups of driving signals in the six groups of driving signals output by the micro control module 4, controlling the on-off state of the three groups of upper half switch tubes in the frequency converter module 2 and the state detection module 3, and controlling the state detection module 3 to detect the saturation conduction voltage drop of the three groups of upper half switch tubes in the frequency converter module 2.

[0053] The second detection unit 502 is connected with the micro control module 4, the frequency converter module 2 and the state detection module 3, and is used for selecting a signal transmission path according to three groups of driving signals in the six groups of driving signals output by the micro control module 4, controlling the on-off state of the three groups of lower half switch tubes in the frequency converter module 2 and the state detection module 3, and controlling the state detection module 3 to detect the saturation conduction voltage drop of the three groups of lower half switch tubes in the frequency converter module 2.

[0054] In specific embodiments, the power module 1 described above can adopt a power circuit composed of a power port, a field effect tube, a triode, etc., can access direct current and control the transmission of direct current; the frequency converter module 2 described above can adopt a frequency converter circuit composed of six groups of IGBTs, which can be three groups of upper half switching tubes and three groups of lower half switching tubes, can perform inversion and frequency conversion processing on the input direct current and output three-phase power, and can also be controlled by the micro control module 4 and work individually; the state detection module 3 described above can adopt a state detection circuit composed of a diode, a comparator, an operational amplifier, a reference power supply, etc., can perform saturation conduction voltage drop detection processing on the frequency converter module 2 connected when the detection control module 5 is turned on, and perform signal size comparison according to the set first detection threshold and second detection threshold, the first detection threshold is smaller than the second detection threshold and can be used as a limit for predicting IGBT aging, and can also perform three-phase balance detection on the three-phase power output by the frequency converter module 2 and judge three-phase imbalance according to the voltage size compared with the set imbalance threshold; the micro control module 4 described above can adopt a micro control circuit composed of a single-chip microcomputer, integrates many components such as an operator, a controller, a memory, and an input-output device, and realizes functions such as signal processing, data storage, module control, and timing control; the detection control module 5 described above can adopt a detection control circuit composed of an analog switch and a logic device, can switch the transmission path of the signal according to the individual conduction of the three groups of upper half switching tubes and the three groups of lower half switching tubes of the frequency converter module 2, or through the six groups of driving signals output by the micro control module 4, control the saturation conduction voltage drop detection of the collector of the three groups of upper half switching tubes and the three groups of lower half switching tubes connected by the state detection module 3, and control the connection state of the emitter of the three groups of upper half switching tubes and the three groups of lower half switching tubes to the ground.

[0055] In this embodiment, please refer to Figure 4 , Figure 5 and Figure 6 , the power module 1 includes a power port, a first MOS tube M1, a first resistor R1, a first switching tube V1, a first diode D1 and a second diode D2; the micro control module 4 includes a first controller U1;

[0056] Specifically, the first end of the power port is connected to the drain of the first MOS tube M1 and connected to the gate of the first MOS tube M1 and the collector of the first switching tube V1 through the first resistor R1, the emitter of the first switching tube V1 is grounded, the base of the first switching tube V1 is connected to the cathode of the first diode D1 and the cathode of the second diode D2, and the anode of the first diode D1 and the anode of the second diode D2 are connected to the IO7 terminal and the IO8 terminal of the first controller U1 respectively.

[0057] In specific embodiments, the first MOS transistor M1 can be an N-channel field effect transistor; the first switch V1 can be an NPN triode; and the first controller U1 can be an STM32 single-chip microcomputer.

[0058] Further, the frequency converter module 2 includes a first power tube Q1, a second power tube Q2, a third power tube Q3, a fourth power tube Q4, a fifth power tube Q5, a sixth power tube Q6, and an output port.

[0059] Specifically, the collector of the first power tube Q1 is connected to the collector of the third power tube Q3, the collector of the fifth power tube Q5, and the source of the first MOS transistor M1; the emitter of the first power tube Q1 is connected to the collector of the second power tube Q2 and the first end of the output port; the emitter of the third power tube Q3 is connected to the collector of the fourth power tube Q4 and the second end of the output port; the emitter of the fifth power tube Q5 is connected to the collector of the sixth power tube Q6 and the third end of the output port; the emitter of the second power tube Q2 is connected to the emitter of the fourth power tube Q4, the emitter of the sixth power tube Q6, and the second end of the power supply port; and the gates of the first power tube Q1, the second power tube Q2, the third power tube Q3, the fourth power tube Q4, the fifth power tube Q5, and the sixth power tube Q6 are respectively connected to the IO1 end, the IO2 end, the IO3 end, the IO4 end, the IO5 end, and the IO6 end of the first controller U1.

[0060] In specific embodiments, the first power tube Q1, the second power tube Q2, the third power tube Q3, the fourth power tube Q4, and the fifth power tube Q5 can all be IGBTs.

[0061] Further, the first detection unit 501 includes a first analog switch U2, a first logic device J1, a second logic device J2, and a third logic device J3.

[0062] Specifically, the third end, the eighth end, the tenth end, and the first end of the first analog switch U2 are respectively connected to the emitter of the first power tube Q1, the emitter of the third power tube Q3, the emitter of the fifth power tube Q5, and the emitter of the second power tube Q2; the twelfth end, the sixth end, and the fifth end of the first analog switch U2 are respectively connected to the Y end of the first logic device J1, the Y end of the second logic device J2, and the Y end of the third logic device J3; the B end of the first logic device J1 is connected to the B end of the second logic device J2, the B end of the third logic device J3, and the IO8 end of the first controller U1; the A end of the first logic device J1, the A end of the second logic device J2, and the A end of the third logic device J3 are respectively connected to the IO5 end, the IO3 end, and the IO1 end of the first controller U1; the fourth end, the ninth end, the eleventh end, and the second end of the first analog switch U2 are all grounded; and the thirteenth end of the first analog switch U2 is connected to the IO7 end of the first controller U1.

[0063] In specific embodiments, the first analog switch U2 can be selected from a CD4066 chip; the first analog switch U2, the second analog switch U3, and the third analog switch can be selected from an AND gate.

[0064] Further, the second detection unit 502 includes a second analog switch U3, a fourth logic J4, a fifth logic J5, and a sixth logic J6;

[0065] Specifically, the eleventh end, the second end, the fourth end, and the ninth end of the second analog switch U3 are connected to the emitter of the first power tube Q1, the emitter of the third power tube Q3, the emitter of the fifth power tube Q5, and the collector of the first power tube Q1, respectively; the sixth end of the second analog switch U3 is connected to the IO8 end of the first controller U1; the twelfth end, the thirteenth end, and the fifth end of the second analog switch U3 are connected to the Y end of the fourth logic J4, the Y end of the fifth logic J5, and the Y end of the sixth logic J6, respectively; the A end of the fourth logic J4 is connected to the B end of the fifth logic J5, the A end of the sixth logic J6, and the IO7 end of the first controller U1; the B end of the fourth logic J4, the A end of the fifth logic J5, and the B end of the sixth logic J6 are connected to the IO2 end, the IO4 end, and the IO6 end of the first controller U1, respectively; the eighth end of the second analog switch U3 is connected to the tenth end, the first end, and the third end of the second analog switch U3.

[0066] In specific embodiments, the second analog switch U3 can be selected from a CD4066 chip; the fourth logic J4, the fifth logic J5, and the sixth logic J6 can be selected from an AND gate.

[0067] Further, the single cell detection unit 302 includes a second resistor R2, a third resistor R3, a first capacitor C1, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a seventh diode D7, a second capacitor C2, a fourth resistor R4, a fifth resistor R5, a first voltage stabilizing source VCC1, a first operational amplifier OP1, a first reference power supply VF1, a second reference power supply VF2, a first comparator A1, and a second comparator A2.

[0068] Specifically, the cathode of the third diode D3 is connected to one end of the second resistor R2 and the third terminal of the second analog switch U3, and is connected to the other end of the second resistor R2, the anode of the fifth diode D5, the cathode of the fourth diode D4, one end of the first capacitor C1 and one end of the third resistor R3 through the second capacitor C2, the other end of the first capacitor C1 is connected to the anode of the sixth diode D6, the cathode of the seventh diode D7 and the other end of the third resistor R3, the anode of the third diode D3 is connected to the anode of the fourth diode D4 and the non-inverting terminal of the first operational amplifier OP1 and is connected to the first voltage reference VCC1 and one end of the fourth resistor R4 through the fifth resistor R5, the other end of the fourth resistor R4 is connected to the inverting terminal of the first operational amplifier OP1 and the anode of the seventh diode D7, the output terminal of the first operational amplifier OP1 is connected to the non-inverting terminal of the first comparator A1 and the non-inverting terminal of the second comparator A2, the inverting terminal of the first comparator A1 and the inverting terminal of the second comparator A2 are connected to the first reference voltage VF1 and the second reference voltage VF2 respectively, and the output terminal of the first comparator A1 and the output terminal of the second comparator A2 are connected to the IO9 terminal and the IO10 terminal of the first controller U1 respectively.

[0069] In specific embodiments, the first operational amplifier OP1 can be OP07 operational amplifier; the first reference voltage VF1 and the second reference voltage VF2 provide the first detection threshold and the second detection threshold respectively, and are used for early aging and late aging judgment; the first comparator A1 and the second comparator A2 can be LM358 comparators.

[0070] Further, the unbalance detection unit 301 includes a mutual inductor device, a second operational amplifier OP2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a third operational amplifier OP3, a first processing device, a second processing device, a third comparator A3, a fourth comparator A4, a third reference voltage VF3 and a fourth reference voltage VF4.

[0071] Specifically, the first detection end, the second detection end and the third detection end of the mutual inductor device detect the first end, the second end and the third end of the output port respectively, the first output end, the second output end and the third output end of the mutual inductor device are connected with the non-inverting terminal of the second operational amplifier OP2, the input end of the first processing device and the input end of the second processing device respectively, the inverting terminal of the second operational amplifier OP2 is connected with the output end of the second operational amplifier OP2 and one end of the seventh resistor R7 through the sixth resistor R6, the output end of the third operational amplifier OP3, the output end of the first processing device and the output end of the second processing device, the non-inverting terminal of the third operational amplifier OP3 is connected with the ground through the eighth resistor R8, the output end of the third operational amplifier OP3 is connected with the other end of the seventh resistor R7, the inverting terminal of the third comparator A3 and the non-inverting terminal of the fourth comparator A4, the non-inverting terminal of the third comparator A3 and the inverting terminal of the fourth comparator A4 are connected with the third reference voltage VF3 and the fourth reference voltage VF4 respectively, and the output end of the third comparator A3 and the output end of the fourth comparator A4 are connected with the IO11 end and the IO12 end of the first controller U1 respectively.

[0072] In specific embodiments, the mutual inductor device can be composed of three groups of current transformers, signal conversion circuits, voltage division circuits and filters to perform current detection, current signal conversion to voltage signal, signal voltage division and filtering processing, the center end of the three groups of current transformers passes through the lines at the first end, the second end and the third end of the output port to complete the current detection work; the second operational amplifier OP2 can be an OP07 operational amplifier for signal following processing; the circuit composition structure of the first detection device and the circuit composition structure of the second detection device are the same as the voltage composition structure of the second operational amplifier OP2 and the sixth resistor R6; the third operational amplifier OP3 can be an OP07 operational amplifier for addition calculation with the seventh resistor R7 and the eighth resistor R8; the third comparator A3 and the fourth comparator A4 can be LM358 comparators; the fourth reference voltage VF4 provides an unbalance threshold value, and the third reference voltage VF3 provides a negative value state unbalance threshold value, so that the third comparator A3 and the fourth comparator A4 perform three-phase unbalance judgment on the output signal of the third operational amplifier OP3.

[0073] In this embodiment, please refer to Figure 7 The application further provides a frequency converter life prediction method, the control method is applied to the frequency converter life prediction system, and the steps of the method comprise:

[0074] S100, acquiring the three-phase unbalance condition detected by the state detection module 3;

[0075] S200, when detecting three-phase imbalance, stop the inverter module 2 and frequency conversion work and timing control state detection module 3 switch signal transmission path, control the connection state of three groups of upper half switch tube and three groups of lower half switch tube in the frequency converter module 2 and the state detection module 3 and the ground, control the state detection module 3 to detect the saturation conduction voltage drop of three groups of upper half switch tube and three groups of lower half switch tube in the frequency converter module 2 in turn;

[0076] S300, obtain the saturation conduction voltage drop state and aging degree of three groups of upper half switch tube and three groups of lower half switch tube in the frequency converter module 2 detected by the state detection module 3 and predict the frequency converter life.

[0077] In the frequency converter life prediction system, DC power is accessed by the power port, the IO1 end to the IO6 end of the first controller U1 drives the on-off state of the first power tube Q1, the second power tube Q2, the third power tube Q3, the fourth power tube Q4, the fifth power tube Q5 and the sixth power tube Q6, respectively, inverts and frequency-converts the DC power and outputs three-phase power, which is received by the output port. The current sampling, signal conversion, voltage division and filtering of the three-phase power input to the output port are performed by the mutual inductor device, and the processed signals are subjected to signal following processing by the second operational amplifier OP2, the sixth resistor R6, the first processing device and the second processing device, respectively, and are subjected to addition processing by the third operational amplifier OP3, the seventh resistor R7 and the eighth resistor R8. When the three-phase is balanced, the third operational amplifier OP3 outputs zero potential. When unbalanced, if the signal output by the third operational amplifier OP3 is less than the negative value state imbalance threshold provided by the third reference power source VF3 or greater than the positive value state imbalance threshold provided by the fourth reference power source VF4, the third comparator A3 or the fourth comparator A4 will output the first detection signal, which is received by the IO11 end and the IO12 end of the first controller U1, respectively. At this time, the first controller U1 will stop driving the frequency converter module 2 to invert and frequency-convert, and will output six groups of driving signals in a timed manner, i.e. the IO1 end of the first controller U1 outputs a group of driving signals in a timed manner, and then the IO4 end outputs a group of driving signals in a timed manner, and so on, to control the output of driving signals by the IO5 end, the IO2 end, the IO4 end and the IO6 end in turn, so as to drive the first power tube Q1, the third power tube Q3, the fifth power tube Q5, the second power tube Q2, the fourth power tube Q4 and the sixth power tube Q6 in turn. At the same time, during the output of driving signals by the IO1 end, the IO4 end and the IO5 end, the IO8 end of the first controller U1 will provide a high level to control the eighth end and the ninth end of the second analog switch U3 to be conductive, the first switch tube V1 is conductive, and the first power tube Q1 is cut off. When the IO1 end outputs the driving signal, the Y end of the third logic device J3 triggers the fourth end and the third end of the first analog switch U2 to be conductive, so that the emitter of the first power tube Q1 is grounded, so that the first operational amplifier OP1 cooperates with the second resistor R2, the third resistor R3, the first capacitor C1, the third diode D3, the fourth diode D4, the fifth diode D5, the sixth diode D6, the seventh diode D7, the second capacitor C2, the fourth resistor R4, the fifth resistor R5 and the first voltage stabilizing source VCC1 to detect the saturation conduction voltage drop of the first power tube Q1. When the detected signal is greater than the first detection threshold set by the first reference power source VF1, the first comparator A1 outputs a high level signal, i.e. a second detection signal, indicating that the aging is in the early stage. When the detected signal is greater than the second detection threshold set by the second reference power source VF2, the second comparator A2 outputs a high level signal, i.e. a third detection signal, indicating that the aging is in the late stage. Similarly, when the IO3 end outputs the driving signal, the second logic device J2 triggers the eighth end and the ninth end of the first analog switch U2 to be conductive,The monomer detection unit 302 performs aging detection on the third power tube Q3, and outputs a driving signal from the IO5 terminal to perform aging detection on the fifth power tube Q5. After the driving signal is output from the IO1 terminal, the IO3 terminal and the IO5 terminal, the first controller U1 outputs the driving signal from the IO2 terminal, the IO4 terminal and the IO6 terminal in turn in a timing manner, and during this period, the IO7 terminal of the first controller U1 controls the first terminal and the second terminal of the first analog switch U2 to be conductive, the emitter of the second power tube Q2, the emitter of the fourth power tube Q4 and the emitter of the sixth power tube Q6 are grounded, the first MOS tube M1 is cut off, and the aging degree of the second power tube Q2, the fourth power tube Q4 and the sixth power tube Q6 is detected according to the state of the driving signal output from the IO2 terminal, the IO4 terminal and the IO6 terminal, and the IO9 terminal and the IO10 terminal of the first controller U1 receive.

[0078] It is apparent to those skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and that the present application can be carried out in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, it is to be understood that the embodiments are to be considered in all respects as illustrative and not restrictive, and the scope of the present application is indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein. No limitation is intended to the scope of the claims based on any embodiment illustrated in the drawings.

[0079] Further, it should be understood that although the present specification describes only one independent technical solution for each embodiment, the specification is described in this way only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. A frequency converter life prediction system, characterized in that, The circuit includes: The power module is used to receive DC power and control power transmission; The inverter module, connected to the power supply module and the microcontroller module, is used to control the conduction state of three sets of upper half-switches and three sets of lower half-switches to control DC power for inversion and frequency conversion and output three-phase power. When it receives six sets of the same type of drive signals from the microcontroller module in sequence, it controls the three sets of upper half-switches and three sets of lower half-switches to conduct individually in sequence. The status detection module is connected to the inverter module and is used to detect three-phase imbalance of three-phase power. When there is three-phase imbalance, it outputs a first detection signal, performs saturation conduction voltage drop detection, and outputs a second detection signal when the detected signal is greater than a set first detection threshold. When the detected signal is greater than the set second detection signal, it outputs a third detection signal. The microcontroller module, connected to the status detection module, power supply module, and detection control module, is used to drive the conduction state of the three sets of upper half-switches and three sets of lower half-switches of the inverter module and control the inverter module to perform inversion and frequency conversion. When the first detection signal is received, it stops driving the inverter module to perform inversion and frequency conversion and controls the power supply module to stop power transmission. It also sequentially provides six sets of the same type of drive signals to the inverter module and the detection control module at regular intervals, and receives the first detection signal, the second detection signal, and the third detection signal. The detection and control module, connected to the inverter module and the status detection module, is used to select the signal transmission path based on the six sets of drive signals output by the microcontroller module, control the connection status of the three sets of upper half-switches and three sets of lower half-switches in the inverter module with the status detection module, and control the connection status of the three sets of upper half-switches and three sets of lower half-switches with ground. Based on the connection status of the three sets of upper half-switches and three sets of lower half-switches with the status detection module and ground, the status detection module is controlled to perform saturation conduction voltage drop detection on the three sets of upper half-switches and three sets of lower half-switches in the inverter module.

2. The inverter life prediction system according to claim 1, characterized in that, The state detection module includes an imbalance detection unit and a single-unit detection unit; The imbalance detection unit, connected to the microcontroller module, is used to detect three-phase imbalance of three-phase power and output a first detection signal when three-phase imbalance occurs, which is received by the microcontroller module. The individual detection unit is connected to the microcontroller module and the detection control module. It is used to detect the saturation conduction voltage drop of the three sets of upper half-switches and three sets of lower half-switches in the inverter module connected to the detection control module. When the detected signal is greater than the set first detection threshold, it outputs a second detection signal. When it is greater than the set second detection signal, it outputs a third detection signal. The second and third detection signals are received by the microcontroller module.

3. The inverter life prediction system according to claim 2, characterized in that, The detection control module includes a first detection unit and a second detection unit; The first detection unit is connected to the microcontroller module, the inverter module, and the status detection module. It is used to select the signal transmission path based on three of the six sets of drive signals output by the microcontroller module, control the connection status of the three sets of upper half-switches in the inverter module with the status detection module and the ground, and control the status detection module to perform saturation conduction voltage drop detection on the three sets of upper half-switches in the inverter module. The second detection unit is connected to the microcontroller module, the inverter module, and the status detection module. It is used to select the signal transmission path based on three of the six sets of drive signals output by the microcontroller module, control the connection status of the three sets of lower half-switches in the inverter module with the status detection module and the ground terminal, and control the status detection module to perform saturation conduction voltage drop detection on the three sets of lower half-switches in the inverter module.

4. The inverter life prediction system according to claim 3, characterized in that, The power module includes a power port, a first MOSFET, a first resistor, a first switch, a first diode, and a second diode; the microcontroller module includes a first controller. The first end of the power port is connected to the drain of the first MOS transistor and is connected to the gate of the first MOS transistor and the collector of the first switching transistor through the first resistor. The emitter of the first switching transistor is grounded. The base of the first switching transistor is connected to the cathode of the first diode and the cathode of the second diode. The anode of the first diode and the anode of the second diode are respectively connected to the IO7 and IO8 terminals of the first controller.

5. The inverter life prediction system according to claim 4, characterized in that, The frequency converter module includes a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a fifth power transistor, a sixth power transistor, and an output port; The collector of the first power transistor is connected to the collector of the third power transistor, the collector of the fifth power transistor, and the source of the first MOSFET. The emitter of the first power transistor is connected to the collector of the second power transistor and the first terminal of the output port. The emitter of the third power transistor is connected to the collector of the fourth power transistor and the second terminal of the output port. The emitter of the fifth power transistor is connected to the collector of the sixth power transistor and the third terminal of the output port. The emitter of the second power transistor is connected to the emitters of the fourth and sixth power transistors and the second terminal of the power supply port. The gates of the first, second, third, fourth, fifth, and sixth power transistors are respectively connected to the IO1, IO2, IO3, IO4, IO5, and IO6 terminals of the first controller.

6. The inverter life prediction system according to claim 5, characterized in that, The first detection unit includes a first analog switch, a first logic unit, a second logic unit, and a third logic unit; The third, eighth, tenth, and first terminals of the first analog switch are respectively connected to the emitters of the first, third, fifth, and second power transistors. The twelfth, sixth, and fifth terminals of the first analog switch are respectively connected to the Y terminals of the first, second, and third logic devices. The B terminal of the first logic device is connected to the B terminals of the second and third logic devices and the IO8 terminal of the first controller. The A terminals of the first, second, and third logic devices are respectively connected to the IO5, IO3, and IO1 terminals of the first controller. The fourth, ninth, eleventh, and second terminals of the first analog switch are all grounded. The thirteenth terminal of the first analog switch is connected to the IO7 terminal of the first controller.

7. The inverter life prediction system according to claim 6, characterized in that, The second detection unit includes a second analog switch, a fourth logic unit, a fifth logic unit, and a sixth logic unit; The eleventh, second, fourth, and ninth terminals of the second analog switch are connected to the emitter of the first power transistor, the emitter of the third power transistor, the emitter of the fifth power transistor, and the collector of the first power transistor, respectively. The sixth terminal of the second analog switch is connected to the IO8 terminal of the first controller. The twelfth, thirteenth, and fifth terminals of the second analog switch are connected to the Y terminals of the fourth, fifth, and sixth logic devices, respectively. The A terminal of the fourth logic device is connected to the B terminal of the fifth logic device, the A terminal of the sixth logic device, and the IO7 terminal of the first controller. The B terminal of the fourth logic device, the A terminal of the fifth logic device, and the B terminal of the sixth logic device are connected to the IO2, IO4, and IO6 terminals of the first controller, respectively. The eighth terminal of the second analog switch is connected to the tenth, first, and third terminals of the second analog switch.

8. The inverter life prediction system according to claim 7, characterized in that, The single-unit detection unit includes a second resistor, a third resistor, a first capacitor, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode, a second capacitor, a fourth resistor, a fifth resistor, a first voltage regulator, a first operational amplifier, a first reference power supply, a second reference power supply, a first comparator, and a second comparator. The cathode of the third diode is connected to one end of the second resistor and the third terminal of the second analog switch, and is connected to the other end of the second resistor, the anode of the fifth diode, the cathode of the fourth diode, one end of the first capacitor, and one end of the third resistor through the second capacitor. The other end of the first capacitor is connected to the anode of the sixth diode, the cathode of the seventh diode, and the other end of the third resistor. The anode of the third diode is connected to the anode of the fourth diode and the non-inverting input of the first operational amplifier, and is connected to the first voltage regulator and one end of the fourth resistor through the fifth resistor. The other end of the fourth resistor is connected to the inverting input of the first operational amplifier and the anode of the seventh diode. The output terminal of the first operational amplifier is connected to the non-inverting input of the first comparator and the non-inverting input of the second comparator. The inverting input of the first comparator and the inverting input of the second comparator are respectively connected to the first reference power supply and the second reference power supply. The output terminals of the first comparator and the second comparator are respectively connected to the IO9 and IO10 terminals of the first controller.

9. The inverter life prediction system according to claim 8, characterized in that, The imbalance detection unit includes a current transformer device, a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a third operational amplifier, a first processing device, a second processing device, a third comparator, a fourth comparator, a third reference power supply, and a fourth reference power supply; The first, second, and third detection terminals of the current transformer device detect the first, second, and third terminals of the output port, respectively. The first, second, and third output terminals of the current transformer device are connected to the non-inverting input of the second operational amplifier, the input terminal of the first processing device, and the input terminal of the second processing device, respectively. The inverting input of the second operational amplifier is connected to the output terminal of the second operational amplifier and is connected to one end of the seventh resistor, the inverting input of the third operational amplifier, the output terminal of the first processing device, and the output terminal of the second processing device through the sixth resistor. The non-inverting input of the third operational amplifier is grounded through the eighth resistor. The output terminal of the third operational amplifier is connected to the other end of the seventh resistor, the inverting input of the third comparator, and the non-inverting input of the fourth comparator. The non-inverting input of the third comparator and the inverting input of the fourth comparator are connected to the third reference power supply and the fourth reference power supply, respectively. The output terminals of the third comparator and the fourth comparator are connected to the IO11 and IO12 terminals of the first controller, respectively.

10. A method for predicting the lifespan of a frequency converter, characterized in that, The control method is applied to the inverter life prediction system according to claims 1-9, and includes the following steps: The status detection module detects three-phase imbalance. When a three-phase imbalance is detected, the inverter module stops its inverter and frequency conversion operations and periodically controls the status detection module to switch the signal transmission path. It controls the connection status of the three sets of upper half-switches and three sets of lower half-switches in the inverter module with the status detection module and the ground terminal. The status detection module then performs saturation conduction voltage drop detection on the three sets of upper half-switches and three sets of lower half-switches in the inverter module in sequence. The system acquires the saturation conduction voltage drop status and aging degree of the three sets of upper half-switches and three sets of lower half-switches in the inverter module detected by the status detection module, and predicts the lifespan of the inverter.

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