Integrated circuit fault analysis system and method based on machine vision

Abstract

The invention relates to the technical field of integrated circuit fault analysis, in particular to an integrated circuit fault analysis system and method based on machine vision, and the method combines layout design data and multi-mode image data of an integrated circuit to analyze the physical integrity of interconnection lines. The abnormal condition of the electrical connectivity of the interconnection line is analyzed; analyzing the connection state between the interconnection line and the function module and the abnormal risk of signal transmission by combining electroluminescence data, infrared heat distribution data and layout design data of the integrated circuit; the overall function failure degree of the integrated circuit is comprehensively evaluated; and performing fault early warning on the integrated circuit based on the overall function failure degree evaluation result of the integrated circuit. Therefore, the accuracy and comprehensiveness of fault diagnosis are improved. Accurate research and judgment on the overall failure risk of the integrated circuit are realized, and the reliability level of the integrated circuit is remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of dialysis process monitoring, and particularly relates to an integrated circuit fault analysis system and method based on machine vision. BACKGROUND

[0002] As the core cornerstone of modern electronic systems, the performance reliability and functional integrity of integrated circuits directly determine the quality level and service life of the entire electronic device. During the manufacturing and service process of integrated circuits, not only will they be affected by process fluctuations, leading to physical defects in the microstructure, but also the long-term effects of electrical stress and thermal stress will cause physical defects to evolve from initial micro-deformation to intermediate parameter drift and then to late functional failure. If the evolution path of the defects is not identified in a timely manner, it may cause serious faults such as signal transmission errors and logic function disorders, not only causing abnormal device functions, but also leading to system-level failures. Traditional integrated circuit fault analysis relies on electrical testing and manual microscopy, which is not only inefficient, but also difficult to fully cover the detection of internal hidden defects and intermittent faults. Using machine vision technology for analysis can accurately capture micro-defects on the surface and inside of the chip, including metal interconnection line fractures, interlayer short circuits and other hidden dangers that are difficult for humans to find, breaking through the limitations of traditional detection and significantly improving the efficiency and accuracy of fault analysis.

[0003] However, the prior art does not deeply correlate the physical topography defects of the interconnection lines with their actual signal transmission characteristics when performing machine vision detection on integrated circuits. For example, when a high-speed interconnection line has a slight deformation, it is difficult to accurately determine the actual impact of the deformation on signal integrity without considering its impedance continuity, signal reflection and other characteristics under high-speed signal transmission, thereby leading to misjudgment of the defect hazard degree. At the same time, the prior art also lacks quantitative evaluation of the functional impact of interconnection line defects in the overall circuit system, making it difficult for the detection results to accurately reflect the impact of interconnection line faults on system performance, and unable to provide a comprehensive basis for signal integrity protection. Especially in high-frequency and high-speed application scenarios, slight physical defects of interconnection lines may cause serious signal quality problems, and the existing methods often ignore the internal correlation between physical defects and electrical performance, leading to evaluation results that are inconsistent with actual application requirements.

[0004] To solve these problems, the present application designs an integrated circuit fault analysis system and method based on machine vision. SUMMARY

[0005] In order to overcome the defects and deficiencies existing in the prior art, the application provides a machine vision-based integrated circuit fault analysis system and method, which collects multi-modal data of an integrated circuit through a multi-source machine vision sensor, combines layout design information, sequentially performs interconnection line physical integrity analysis, electrical connectivity abnormality diagnosis and functional module connection state evaluation, and finally realizes precise evaluation and fault warning of overall functional failure degree through multi-index fusion.

[0006] In order to achieve the above purpose, the application adopts the following technical solutions: In a first aspect, the embodiment of the application provides a machine vision-based integrated circuit fault analysis method, including the following steps: S1, synchronously collecting multi-modal image data, infrared thermal distribution data and electroluminescence data of an integrated circuit through a multi-source machine vision sensor, and acquiring layout design data of the integrated circuit; S2, combining the layout design data and the multi-modal image data of the integrated circuit, analyzing the physical integrity of the interconnection line; thereby analyzing the electrical connectivity abnormality of the interconnection line; S3, combining the electroluminescence data, the infrared thermal distribution data and the layout design data of the integrated circuit, analyzing the connection state and signal transmission abnormality risk between the interconnection line and the functional module; S4, based on the analysis results of the electrical connectivity abnormality of the interconnection line and the analysis results of the connection state and signal transmission abnormality risk, comprehensively evaluating the overall functional failure degree of the integrated circuit; S5, based on the evaluation results of the overall functional failure degree of the integrated circuit, performing fault warning on the integrated circuit.

[0007] As an implementation manner of the application, in step S2, the physical integrity of the interconnection line is analyzed by combining the layout design data and the multi-modal image data of the integrated circuit, including the following specific steps: S21, generating an ideal graph of the interconnection line based on the layout design data, and registering the actual interconnection line image in the multi-modal image data with the ideal graph; S22, calculating the effective connection area ratio of the registered area, the effective connection area ratio being the proportion of the area of the overlapping part of the actual interconnection line image and the ideal graph to the total area of the ideal graph; S23, calculating the shape consistency degree between the edge of the actual interconnection line and the edge of the ideal graph; S24, performing weighted summation on the effective connection area ratio and the shape consistency degree to obtain the physical integrity of the interconnection line; a preset physical integrity threshold value is provided, and when the physical integrity of the interconnection line is less than the physical integrity threshold value, fault warning is performed on the integrated circuit.

[0008] As an implementation manner of the present application, the analysis on the electrical connectivity abnormality of the interconnection line in step S2 comprises the following specific steps: S25, when the physical integrity of the interconnection line is greater than or equal to the physical integrity threshold, abstracting the interconnection line network in the layout design data into a graph structure, wherein the node represents the connection point and the edge represents the metal line segment; S26, traversing each edge in the graph structure, when the effective connection area ratio corresponding to an edge is lower than a first preset threshold, determining that the edge has an open circuit risk; S27, detecting adjacent patterns isolated from each other in the layout design data, when the effective connection area ratio of the gap region of the adjacent patterns is higher than a second preset threshold, determining that the theoretical gap region has a conductive bridging defect; S28, based on steps S26-27, extracting the number of edges in the graph structure that are determined to have an open circuit risk, and the number of original node pairs that are at risk of short circuit due to the conductive bridging defect of the theoretical gap region; analyzing the electrical connectivity abnormality of the interconnection line.

[0009] As an implementation manner of the present application, the analysis on the connection state and signal transmission abnormal risk between the interconnection line and the functional module in step S3 in combination with the electroluminescence data, the infrared thermal distribution data and the layout design data of the integrated circuit comprises the following specific steps: S31, extracting the boundary of the functional module and the connection point information of the functional module and the interconnection line from the layout design data; S32, spatially superimposing the electroluminescence data and the infrared thermal distribution data on the layout design data to construct a feature vector set for each functional module, the feature vector set comprising abnormal luminescence intensity, abnormal heating temperature within the module region and layout context attributes of the module; S33, processing the feature vector set by using an unsupervised learning-based anomaly detection model to calculate the connection and transmission abnormal risk of each functional module; S34, weighting and summing the connection and transmission abnormal risks of each functional module to obtain the connection state and signal transmission abnormal risk between the interconnection line and the functional module.

[0010] As an implementation manner of the present application, the comprehensive evaluation on the overall functional failure degree of the integrated circuit based on the electrical connectivity abnormality analysis result of the interconnection line and the connection state and signal transmission abnormal risk analysis result in step S4 comprises the following specific steps: S41, extracting the electrical connectivity abnormality analysis result of the interconnection line and the connection state and signal transmission abnormal risk analysis result between the interconnection line and the functional module; S42, the electrical connectivity abnormal situation analysis result and the connection state are weighted and summed with the signal transmission abnormal risk analysis result, and the overall function failure degree of the integrated circuit is obtained.

[0011] As an implementation manner of the present application, the fault early warning of the integrated circuit based on the overall function failure degree evaluation result of the integrated circuit in step S5 comprises the following specific steps: S51, the overall function failure degree of the integrated circuit is extracted. S52, a function failure threshold is preset, when the overall function failure degree of the integrated circuit is greater than the function failure threshold, the fault early warning of the integrated circuit is performed, and when the overall function failure degree of the integrated circuit is less than or equal to the function failure threshold, it is determined that the integrated circuit function is normal.

[0012] In a second aspect, the embodiments of the present application also provide an integrated circuit fault analysis system based on machine vision, comprising: A data acquisition module is configured to synchronously acquire multi-modal image data, infrared thermal distribution data and electroluminescence data of the integrated circuit through a multi-source machine vision sensor, and acquire layout design data of the integrated circuit. An interconnection line abnormality analysis module is configured to analyze the physical integrity of the interconnection line in combination with the layout design data and the multi-modal image data of the integrated circuit, so as to analyze the electrical connectivity abnormality of the interconnection line. A circuit transmission abnormality detection module is configured to analyze the connection state and signal transmission abnormal risk between the interconnection line and the functional module in combination with the electroluminescence data, the infrared thermal distribution data and the layout design data of the integrated circuit. A function failure quantification module is configured to comprehensively evaluate the overall function failure degree of the integrated circuit based on the electrical connectivity abnormality analysis result of the interconnection line and the connection state and signal transmission abnormal risk analysis result. A fault early warning module is configured to perform fault early warning of the integrated circuit based on the overall function failure degree evaluation result of the integrated circuit.

[0013] Compared with the prior art, the present application has the following advantages and beneficial effects: 1. The present application converts the physical defects detected by vision into quantifiable electrical performance indicators by correlatively analyzing the physical integrity and electrical connectivity abnormality of the interconnection line, realizes the leap from topography observation to function prediction, and improves the accuracy of fault diagnosis. 2. The present application can identify intermittent faults and performance degradation problems that are difficult to find by traditional methods by analyzing the abnormal risk of the connection state of the functional module through multi-source data fusion and machine learning algorithm, and improves the comprehensiveness of fault detection. 3、The application establishes a comprehensive evaluation system from physical defects to system functions, realizes accurate judgment of the overall failure risk of integrated circuits, provides a scientific basis for product quality control and preventive maintenance, and significantly improves the reliability level of integrated circuits. BRIEF DESCRIPTION OF DRAWINGS

[0014] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, read in conjunction with the accompanying drawings: Figure 1 The overall flowchart of the integrated circuit fault analysis method based on machine vision of the present application is shown in the figure. Figure 2 The work flowchart of analyzing the physical integrity of the interconnection line in step S2 of the integrated circuit fault analysis method based on machine vision of the present application is shown in the figure. Figure 3 The work flowchart of step S3 of the integrated circuit fault analysis method based on machine vision of the present application is shown in the figure. Figure 4 The structural schematic diagram of the integrated circuit fault analysis system based on machine vision of the present application is shown in the figure. DETAILED DESCRIPTION

[0015] The technical solutions of the present application will be described in detail below by means of the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments and the embodiments can be combined with each other.

[0016] Embodiment 1 As shown in the figure, the present embodiment provides an integrated circuit fault analysis method based on machine vision, which specifically includes the following steps: Figure 1 ​S1. Multimodal image data, infrared thermal distribution data, and electroluminescence data of the integrated circuit are simultaneously acquired using multi-source machine vision sensors, and the layout design data of the integrated circuit is obtained. In the actual operation of this embodiment, the acquisition of multimodal image data is carried out using a high-resolution optical microscope equipped with an electric platform and an autofocus system. A full-area scan is performed in 0.5-micrometer increments, acquiring 256 frames of images for each scan area. A complete image of the bare die surface is generated using an image stitching algorithm. The image resolution is set to 0.1 micrometers per pixel to ensure clear differentiation of interconnect structures with a minimum linewidth of 0.5 micrometers. The acquisition of infrared thermal distribution data needs to be performed under the condition that the integrated circuit is subjected to its rated operating voltage. A liquid nitrogen-cooled infrared focal plane array detector is used, dividing the chip surface into 32×32 grid points. Thermal radiation data is acquired for 30 seconds at each point. The thermal radiation intensity is converted into temperature values ​​through blackbody radiation calibration to establish a temperature distribution map, with a temperature resolution of 0.1 degrees Celsius and a spatial resolution of 5 micrometers. Electroluminescence data was acquired using a back-illuminated EMCCD detector. Under a bias of 1.2 times the rated voltage applied to the chip, a 60-second exposure was performed, covering a wavelength range of 400-1100 nanometers. The luminescence intensity of each pixel was recorded using photon counting mode. Layout design data was obtained by parsing GDSII format design files, extracting geometric data of each process layer and their corresponding network attributes, and establishing a complete database containing transistor-level netlists and physical layout hierarchical relationships. In this embodiment, multimodal image data provides the foundation for physical defect detection, infrared thermal distribution data reflects abnormal heating points under operating conditions, electroluminescence data captures photon emission generated by microscopic defects such as gate oxide leakage, and layout design data provides circuit-level explanations for all observed phenomena. This strategy of simultaneous acquisition of multi-source data not only enables comprehensive detection from physical morphology to electrical characteristics but, more importantly, establishes a bridge between defect phenomena and circuit function, providing a rich data foundation for subsequent root cause analysis of faults. S2. By combining the layout design data of the integrated circuit with multimodal image data, the physical integrity of the interconnects is analyzed; thereby analyzing abnormal electrical connectivity of the interconnects. S3. Combining the electroluminescence data, infrared thermal distribution data, and layout design data of the integrated circuit, analyze the connection status and signal transmission anomaly risks between interconnects and functional modules; S4. Based on the analysis results of abnormal electrical connectivity of interconnects and the analysis results of abnormal connection status and signal transmission risks, a comprehensive assessment of the overall functional failure degree of integrated circuits is conducted. S5. Based on the overall functional failure assessment results of integrated circuits, provide early warning of integrated circuit failures.

[0017] In this embodiment, as shown in Figure 2 The layout design data of the integrated circuit is combined with the multi-modal image data in step S2 to analyze the physical integrity of the interconnection line, including the following specific steps: S21, generating an ideal pattern of the interconnection line based on the layout design data, and registering the actual interconnection line image in the multi-modal image data with the ideal pattern; S22, calculating the effective connection area ratio of the registered region, which is the proportion of the area of the overlapping part of the actual interconnection line image and the ideal pattern to the total area of the ideal pattern; S23, calculating the shape consistency degree between the actual interconnection line edge and the ideal pattern edge; specifically, a series of sampling points are set on the ideal pattern edge after registration according to a preset sampling interval; for each sampling point, the nearest Euclidean distance from each sampling point to the actual interconnection line edge is calculated to obtain a sequence of shortest distances; the nearest Euclidean distance of each sampling point to the actual interconnection line edge in the sequence of shortest distances is divided by a preset maximum allowed shape deviation threshold to obtain a distance deviation degree, wherein when the distance deviation degree of a sampling point is greater than 1, the distance deviation degree of the sampling point is taken as 1; the arithmetic mean of the distance deviation degrees of all sampling points is obtained as the shape difference degree between the actual interconnection line edge and the ideal pattern edge, and the difference between the value 1 and the shape difference degree of the interconnection line is taken as the shape consistency degree between the actual interconnection line edge and the ideal pattern edge; wherein the value range of the shape consistency degree is 0 to 1, and the closer the value is to 1, the higher the shape consistency of the actual contour and the ideal contour of the interconnection line; S24, weighted sum of the effective connection area ratio and the shape consistency degree to obtain the physical integrity of the interconnection line; a preset physical integrity threshold is set, and when the physical integrity of the interconnection line is less than the physical integrity threshold, a fault warning is given to the integrated circuit.

[0018] In this embodiment, the electrical connectivity abnormality of the interconnection line is analyzed in step S2, including the following specific steps: S25, when the physical integrity of the interconnection line is greater than or equal to the physical integrity threshold, the interconnection line network in the layout design data is abstracted into a graph structure, wherein the nodes represent the connection points and the edges represent the metal line segments; S26, traversing each edge in the graph structure, when the effective connection area ratio of a certain edge is lower than a first preset threshold, it is determined that there is an open circuit risk in the certain edge; S27, detecting mutually isolated adjacent patterns in the layout design data, when the effective connection area ratio of the gap region of the adjacent patterns is higher than a second preset threshold, it is determined that there is a conductive bridging defect in the theoretical gap region; specifically including: S271, based on the layout design data of the integrated circuit, identify all adjacent conductive patterns in the publication map that are electrically isolated from each other and belong to different signal networks. The conductive patterns include but are not limited to metal interconnection lines, polysilicon gates, and active area diffusion layers; S272, extract the minimum design spacing area between adjacent conductive patterns, defined as the theoretical gap area to be detected; wherein the boundary of the theoretical gap area is determined by the design outer boundary of the adjacent patterns; S273, accurately map all identified theoretical gap areas to the actual chip surface image through coordinate transformation. Analyze whether there is an abnormal conductive material image feature in the theoretical gap area that should not exist, wherein the abnormal conductive material image feature is characterized by brightness, texture and contrast consistent with the adjacent conductive pattern material; S274, for each theoretical gap area, calculate the total area of the abnormal conductive material image feature appearing inside it; and calculate the ratio of the total area of the abnormal conductive material image feature to the total area of the theoretical gap area, to obtain the effective connection area ratio of each theoretical gap area: S275, when the effective connection area ratio of the theoretical gap area is higher than the second preset threshold, it is determined that the theoretical gap area has a conductive bridging defect; S28, based on steps S26-27, extract the number of all edges in the graph structure that are determined to have an open circuit risk, and the number of all original node pairs that face a short circuit risk due to the existence of conductive bridging defects in the theoretical gap area; analyze the electrical connectivity abnormality of the interconnection line, which specifically includes: taking the ratio of the number of edges with open circuit risk to the total number of edges in the graph structure as the edge abnormality index, taking the ratio of the number of original node pairs facing a short circuit risk due to the existence of conductive bridging defects in the theoretical gap area to the total number of node pairs in the graph structure as the node abnormality index, and adding the edge abnormality index and the node abnormality index to obtain the electrical connectivity abnormality of the interconnection line.

[0019] It should be noted that in step S2, the physical integrity analysis starts from image registration, adopts a feature point-based registration algorithm, first extracts corner features in the ideal pattern, matches through SIFT feature descriptors in the actual image, then uses the RANSAC algorithm to remove mismatched points, and finally realizes sub-pixel level accuracy registration through affine transformation, with a registration error controlled within 0.05 pixels. The calculation of the effective connection area ratio adopts a pixel-level comparison method, performs a logical AND operation on the registered binary images, and calculates the ratio of the number of overlapping pixels to the total number of ideal pattern pixels. This parameter can intuitively reflect the loss or redundancy of interconnection line material. The evaluation of the shape consistency degree is more detailed, sampling points are set on the edge of the ideal pattern after registration at an interval of 0.2 microns, the nearest Euclidean distance from each sampling point to the actual edge is calculated, and the maximum allowed shape deviation threshold is set to 20% of the line width according to the process capability. The distance deviation of all sampling points is normalized and then the arithmetic mean is calculated to obtain a shape consistency evaluation value in the range of 0 to 1. The comprehensive score of physical integrity is obtained by weighted calculation, wherein the weight of the effective connection area ratio is set to 0.7 by default in this embodiment, and the weight of the shape consistency degree is set to 0.3 by default. Specifically, in this embodiment, the weight allocation is based on regression analysis of historical data to determine that the area factor has a more significant impact on electrical performance. The physical integrity threshold is determined by statistical analysis method, the physical integrity scores of 1000 known good samples are collected, the mean value minus three times the standard deviation is taken as the threshold, and it is ensured that 99.7% of the good products can pass the detection. In the electrical connectivity abnormality analysis, the open circuit risk is determined based on the comparison of the effective connection area ratio and the first preset threshold, and the first preset threshold is obtained by statistical analysis of samples with open circuit failure in the accelerated life test; the short circuit risk is detected by analyzing the abnormal material bridge in the theoretical gap region, and the second preset threshold is determined by considering the process fluctuation level, and the mean value plus three times the standard deviation is taken as the threshold by statistical analysis of the gap region of good products in different process batches. The calculation of the edge abnormality index and the node abnormality index adopts a normalization method to ensure the comparability of circuit networks of different sizes. This complete analysis system can accurately identify physical defects in interconnection lines and map these defects to electrical connectivity abnormalities, providing accurate input parameters for subsequent system-level evaluation. Its advantage lies in converting visual detection results into quantifiable electrical performance indicators, realizing the leap from physical morphology to functional impact.

[0020] In this embodiment, as shown in Figure 3 The connection state and signal transmission abnormality risk between the interconnection line and the functional module are analyzed in step S3 in combination with the electroluminescence data, infrared thermal distribution data and layout design data of the integrated circuit, including the following specific steps: S31, extracting the boundary of the functional module and the connection point information of the functional module and the interconnection line from the layout design data; S32, spatially superimpose the electroluminescence data and the infrared thermal distribution data with the layout design data, and construct a feature vector set for each functional module, the feature vector set including abnormal light emission intensity, abnormal heat emission temperature in the module area, and layout context attributes of the module; S33, processing the feature vector set by using an unsupervised learning-based anomaly detection model, and calculating connection and transmission anomaly risks of each functional module; specifically including: S331, obtaining a training data set containing a plurality of known good integrated circuit samples; for each good sample, performing steps S31 and S32 to construct a feature vector set for each functional module; and aggregating the feature vector sets of all functional modules in all good samples to form a model training data set; S332, randomly selecting a feature vector subset of a plurality of functional modules from the model training data set; randomly selecting a feature dimension in the feature vector, and randomly selecting a split value between the minimum value and the maximum value of the feature dimension to divide the feature vector subset into two subspaces; S333, recursively repeating the above splitting process until any of the following conditions is met: The subspace contains only one feature vector; All feature vectors in the subspace are identical in the selected feature dimension; The preset tree depth limit is reached; S334, constructing a plurality of isolation trees by the above process to form an isolation forest model; S335, for any functional module of the integrated circuit under test, inputting the feature vector of any functional module into the trained isolation forest model to calculate the connection and transmission anomaly risk of any functional module, the specific steps being as follows: For each isolation tree in the isolation forest, calculate the path length of the feature vector of any functional module from the root node to the leaf node; Calculate the arithmetic mean of the path lengths of the feature vectors in all isolation trees, and divide the arithmetic mean by a benchmark path length value normalized for a specific sample number as a normalized path length ratio value; wherein the specific sample number refers to the number of samples contained in a non-replacement subsample set randomly extracted from the global training data set when each isolation tree in the isolation forest is constructed, which is determined by the subsampling size; the calculation process of the benchmark path length value specifically includes: calculating the natural logarithm value of the specific sample number minus one; adding the natural logarithm value to Euler-Mascheroni constant to obtain a harmonic number estimate value; calculating the difference between twice the sample number and 1; multiplying the harmonic number estimate value by two minus the difference between twice the sample number and 1 as the dividend, and the sample number as the divisor to perform division operation, and taking the division operation result as the benchmark path length value; The power operation result with 2 as the base number and the negative number of the normalized path length ratio as the index is taken as the connection and transmission abnormality risk of any function module; In S34, the connection and transmission abnormality risks of the function modules are weighted and summed to obtain the connection state and signal transmission abnormality risk between the interconnection lines and the function modules.

[0021] It should be noted that in step S3, the analysis of the connection state between the interconnection line and the functional module and the abnormal risk of signal transmission needs to build a multi-feature fusion evaluation model. When extracting the boundary of the functional module from the layout design data, a hierarchical processing method is adopted, first, the basic logic gate in the standard cell library is identified, then the module level boundary is constructed according to the netlist connection relationship, and finally the coordinates of the connection points of each module and the interconnection line are extracted. The integrity of these connection points is directly related to the quality of signal transmission. In this embodiment, the construction of the feature vector set contains three dimensions of features: the abnormal emission intensity feature is obtained by counting the number of photon emission points in each functional module area that exceeds three times the standard deviation of background noise; the abnormal heating temperature feature calculates the difference between the 95% quantile of the temperature value in the module area and the average temperature of the chip; the layout context attribute includes the driving strength, load capacitance and clock domain of the module, which can be directly extracted from the netlist. Specifically, the training of the isolation forest model in this embodiment uses 200 isolated trees, and the subsample size is set to 256. The grid search is used to determine the calculation complexity while ensuring the detection performance. The calculation of the benchmark path length value uses the exact algorithm to ensure the consistency of the path length standardization. The calculation of the abnormal risk divides the average path length of each functional module feature vector in all isolated trees by the benchmark path length value, and then converts it to an abnormal risk in the range of 0 to 1 through exponential operation. The final connection state between the interconnection line and the functional module and the abnormal risk of signal transmission are obtained by weighted sum of the abnormal risks of all functional modules, and the weights are allocated according to the importance of the modules in the circuit. Specifically, the allocation of the weight of the functional module is based on its functional importance and topological criticality in the circuit system, and the accurate weight allocation is realized through a multi-dimensional quantitative evaluation system. In the specific implementation of this embodiment, first, the electrical characteristics and connection relationship of each functional module are extracted from the circuit netlist in the layout design data, and an evaluation system containing four dimensions of timing criticality, signal driving ability, network centrality and functional importance is established. The timing criticality is obtained through static timing analysis, the frequency of the module on the critical path and its influence on the setup time and hold time margin are calculated, and the modules on the clock path and high-speed data path are given higher weight, and the specific value is obtained by normalizing the path margin. In this embodiment, if the timing margin of a module on the critical path is less than 10% of the total clock period, its timing criticality score is 1.0, and its timing criticality score decreases by 0.2 for every 10% increase in margin. The signal driving ability evaluation is based on the fan-out load and driving strength of the module, and the ratio of the equivalent capacitance load of the module output terminal to the standard driving capacity is determined. The network centrality is calculated by the betweenness centrality algorithm in graph theory, which analyzes the hub degree of the module in the global signal transmission network, and the ratio of the number of shortest paths passing through the module to the total number of paths is quantified, and the value is scaled by logarithm to map to the range of 0-1.The function importance evaluation divides the modules into core processing units, memory control units, peripheral interfaces and other categories according to the chip architecture design document, and is scored by domain experts according to the system function requirements. After obtaining the scores of the four dimensions, the final weight is obtained by weighted fusion, which can reflect the actual importance of the module. The weights of all modules are finally normalized to ensure that the total weight is 1, avoiding the excessive influence of individual modules on the overall evaluation result. In practical applications, the weight allocation scheme of the embodiment also supports dynamic adjustment according to specific application scenarios, for example, appropriately increasing the weight proportion of timing criticality in applications that emphasize real-time performance, and enhancing the weight setting of power management modules in low-power consumption applications. This fine-grained weight allocation mechanism ensures that the final calculated connection state and signal transmission abnormal risk can accurately reflect the actual impact of different module faults on system function, providing reliable quantitative basis for subsequent fault warning and diagnosis, and making the evaluation result have good explainability and engineering guidance value.

[0022] Based on the above, the embodiment can find intermittent faults and performance degradation problems that are difficult to identify by traditional detection methods, and provide more comprehensive connection state evaluation through multi-dimensional feature analysis. Its innovation lies in establishing a quantitative correlation between the physical phenomena observed by machine vision and the circuit function performance, providing more abundant basis for fault warning.

[0023] In the embodiment, based on the electrical connectivity abnormality analysis result of the interconnection line and the connection state and signal transmission abnormal risk analysis result in step S4, the overall function failure degree of the integrated circuit is comprehensively evaluated, including the following specific steps: S41, extract the electrical connectivity abnormality analysis result of the interconnection line, and the connection state and signal transmission abnormal risk analysis result between the interconnection line and the functional module; S42, weighted sum of the electrical connectivity abnormality analysis result and the connection state and signal transmission abnormal risk analysis result, to obtain the overall function failure degree of the integrated circuit.

[0024] It should be noted that in step S4, the comprehensive evaluation of the overall function failure degree of the integrated circuit needs to establish a multi-index fusion model. The abnormality analysis result of electrical connectivity comes from the output of step S2, including edge abnormality index and node abnormality index, reflecting the structural integrity of the interconnection network. The connection state and signal transmission abnormality risk analysis result comes from the output of step S3, which is a risk index after standardization processing, reflecting the working state of the functional module level. The comprehensive evaluation adopts a linear weighting model, and in this embodiment, the weight of the abnormality of electrical connectivity is set to 0.6 by default, and the weight of the connection state and signal transmission abnormality risk is set to 0.4 by default. Specifically, the weight distribution in this embodiment is determined by principal component analysis, reflecting the decisive role of structural integrity on overall function. This embodiment effectively fuses the detection results at different levels, considering both the structural integrity of the interconnection line and the dynamic working state of the functional module, providing a comprehensive and systematic fault evaluation. Thus, a complete mapping relationship from physical defects to functional failure is established, so that the detection results based on machine vision can be directly used for function state judgment, providing a reliable basis for subsequent early warning decision.

[0025] In this embodiment, based on the overall function failure degree evaluation result of the integrated circuit in step S5, the integrated circuit is given a fault warning, including the following specific steps: S51, extracting the overall function failure degree of the integrated circuit; S52, presetting a function failure threshold, when the overall function failure degree of the integrated circuit is greater than the function failure threshold, the integrated circuit is given a fault warning; when the overall function failure degree of the integrated circuit is less than or equal to the function failure threshold, it is determined that the integrated circuit is normal. Illustratively, the setting of the function failure threshold in this embodiment is based on statistical analysis of a large amount of historical data, collecting the evaluation results of 500 known fault samples and 500 good samples, determining the threshold position by finding the best classification boundary, and ensuring that the classification accuracy on the validation set is above 95%.

[0026] Embodiment 2 As shown in Figure 4 , the present embodiment provides an integrated circuit fault analysis system based on machine vision, comprising: a data acquisition module for synchronously acquiring multi-modal image data, infrared thermal distribution data and electroluminescence data of the integrated circuit through multi-source machine vision sensors, and acquiring layout design data of the integrated circuit; an interconnection line abnormality analysis module for analyzing the physical integrity of the interconnection line in combination with the layout design data and multi-modal image data of the integrated circuit; thereby analyzing the abnormality of electrical connectivity of the interconnection line; The circuit transmission anomaly detection module is configured to analyze the connection state and signal transmission anomaly risk between the interconnection lines and the functional modules in combination with the electroluminescence data, the infrared thermal distribution data and the layout design data of the integrated circuit. The functional failure quantification module is configured to comprehensively evaluate the overall functional failure degree of the integrated circuit based on the electrical connectivity anomaly analysis result of the interconnection lines and the connection state and signal transmission anomaly risk analysis result. The fault early warning module is configured to perform fault early warning on the integrated circuit based on the overall functional failure degree evaluation result of the integrated circuit.

[0027] The steps of implementing the respective functions of the parameters and the unit modules in the above-mentioned machine vision-based integrated circuit fault analysis system of the present application can refer to the parameters and steps in the above-mentioned machine vision-based integrated circuit fault analysis method embodiments, and will not be repeated here.

[0028] Each of the embodiments in the present application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments mainly describes the differences from other embodiments. In particular, the IoT device and medium embodiments are basically similar to the method embodiments, and thus are described simply. The relevant parts can refer to the descriptions of the method embodiments.

[0029] The system and medium provided by the embodiments of the present application are one-to-one corresponding to the method, and thus the system and medium also have similar beneficial technical effects to the method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the system and medium will not be repeated here.

[0030] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0031] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0032] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0033] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0034] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0035] Computer-readable media include both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0036] It is also to be noted that the terms "comprising", "including", and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0037] The above embodiments are only used to illustrate the present application, but not to limit it. Instead of the above, various modifications and changes can be made to the application by those skilled in the art. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the application shall fall into the scope of claims of the application.

Claims

1. A machine vision-based integrated circuit fault analysis method, characterized in that, Includes the following steps: S1. Synchronously acquire multimodal image data, infrared thermal distribution data and electroluminescence data of integrated circuits through multi-source machine vision sensors, and obtain layout design data of integrated circuits. S2. By combining the layout design data of the integrated circuit with multimodal image data, the physical integrity of the interconnects is analyzed; thereby analyzing abnormal electrical connectivity of the interconnects. S3. Combining the electroluminescence data, infrared thermal distribution data, and layout design data of the integrated circuit, analyze the connection status and signal transmission anomaly risks between interconnects and functional modules; S4. Based on the analysis results of abnormal electrical connectivity of interconnects and the analysis results of abnormal connection status and signal transmission risks, a comprehensive assessment of the overall functional failure degree of integrated circuits is conducted. S5. Based on the overall functional failure assessment results of integrated circuits, provide early warning of integrated circuit failures.

2. The integrated circuit fault analysis method based on machine vision according to claim 1, characterized in that, Step S2, which combines the layout design data of the integrated circuit with multimodal image data, analyzes the physical integrity of the interconnects, including the following specific steps: S21. Generate an ideal graphic of interconnecting lines based on the layout design data, and register the actual interconnecting line images in the multimodal image data with the ideal graphic; S22. Calculate the effective connection area ratio of the registered region, wherein the effective connection area ratio is the ratio of the area of ​​the overlapping part of the actual interconnection image and the ideal graphic to the total area of ​​the ideal graphic; S23. Calculate the degree of morphological consistency between the actual interconnect edge and the ideal graphic edge; S24. The effective connection area ratio and the degree of morphological consistency are weighted and summed to obtain the physical integrity of the interconnect. A preset physical integrity threshold is set, and when the physical integrity of the interconnect is less than the physical integrity threshold, a fault warning is issued for the integrated circuit.

3. The integrated circuit fault analysis method based on machine vision according to claim 2, characterized in that, The analysis of abnormal electrical connectivity of the interconnecting lines in step S2 includes the following specific steps: S25. When the physical integrity of the interconnect is greater than or equal to the physical integrity threshold, the interconnect network in the layout design data is abstracted into a graph structure, where nodes represent connection points and edges represent metal line segments. S26. Traverse each edge in the graph structure. When the effective connection area ratio of an edge is lower than the first preset threshold, determine that the edge has an open-circuit risk. S27. Detect adjacent graphics that are isolated from each other in the layout design data. When the effective connection area ratio of the gap area of ​​the adjacent graphics is higher than the second preset threshold, it is determined that there is a conductive bridging defect in the theoretical gap area. S28. Based on steps S26-27, extract the number of all edges in the graph structure that are determined to have open circuit risk, and the number of all source node pairs that face short circuit risk due to conductive bridging defects in the theoretical gap region. Analyze abnormal electrical connectivity of interconnects.

4. The integrated circuit fault analysis method based on machine vision according to claim 3, characterized in that, Step S3 combines the electroluminescence data, infrared thermal distribution data, and layout design data of the integrated circuit to analyze the connection status and signal transmission anomaly risks between interconnects and functional modules, including the following specific steps: S31. Extract the boundary information of the functional modules and the connection point information between the functional modules and the interconnection lines from the layout design data; S32. Spatially overlay the electroluminescence data and the infrared thermal distribution data with the layout design data to construct a feature vector set for each functional module. The feature vector set includes the abnormal luminescence intensity, abnormal heating temperature and layout context attributes of the module within the module area. S33. The feature vector set is processed using an anomaly detection model based on unsupervised learning to calculate the connection and transmission anomaly risk of each functional module. S34. The connection and transmission anomaly risks of each functional module are weighted and summed to obtain the connection status and signal transmission anomaly risks between the interconnection line and the functional module.

5. The integrated circuit fault analysis method based on machine vision according to claim 4, characterized in that, Step S4, based on the analysis results of abnormal electrical connectivity of interconnects and the analysis results of abnormal connection status and signal transmission risks, comprehensively evaluates the overall functional failure level of the integrated circuit, including the following specific steps: S41. Extract the analysis results of abnormal electrical connectivity of interconnecting lines, as well as the analysis results of abnormal connection status and signal transmission risk between interconnecting lines and functional modules; S42. The results of the electrical connectivity anomaly analysis and the connection status analysis are weighted and summed with the results of the signal transmission anomaly risk analysis to obtain the overall functional failure degree of the integrated circuit.

6. The integrated circuit fault analysis method based on machine vision according to claim 5, characterized in that, Step S5, based on the overall functional failure assessment results of the integrated circuit, provides fault warning for the integrated circuit, including the following specific steps: S51. Extract the overall functional failure level of the integrated circuit; S52. A preset functional failure threshold is set. When the overall functional failure level of the integrated circuit is greater than the functional failure threshold, a fault warning is issued for the integrated circuit. When the overall functional failure level of the integrated circuit is less than or equal to the functional failure threshold, the integrated circuit is judged to be functioning normally.

7. A machine vision-based integrated circuit fault analysis system, implemented based on any one of claims 1-6, characterized in that, The system includes: The data acquisition module is used to synchronously acquire multimodal image data, infrared thermal distribution data and electroluminescence data of integrated circuits through multi-source machine vision sensors, and to obtain the layout design data of integrated circuits. The interconnect anomaly analysis module is used to analyze the physical integrity of interconnects by combining integrated circuit layout design data and multimodal image data; thereby analyzing abnormal electrical connectivity of interconnects. The circuit transmission anomaly detection module is used to analyze the connection status and signal transmission anomaly risks between interconnects and functional modules by combining electroluminescence data, infrared thermal distribution data and layout design data of integrated circuits. The functional failure quantification module is used to comprehensively evaluate the overall functional failure level of integrated circuits based on the analysis results of electrical connectivity anomalies and connection status and signal transmission anomaly risks. The fault warning module is used to provide fault warnings for integrated circuits based on the overall functional failure assessment results.

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