Self-biased band-gap reference current circuit

Abstract

The invention relates to the technical field of band-gap reference circuits, in particular to a self-biased band-gap reference current circuit, which comprises a current mirror circuit comprising a plurality of PMOS (P-channel Metal Oxide Semiconductor) transistors, grids of the PMOS transistors are connected together, and sources of the PMOS transistors are connected with a power supply; the differential amplifier circuit comprises a differential pair transistor, a load transistor and a bias transistor; the temperature compensation circuit comprises at least two bipolar transistors and a plurality of resistors; the self-biased starting circuit comprises at least one capacitor and at least one transistor. The reference current source does not need an external bias circuit, has a high power supply rejection ratio and a low temperature coefficient, and meets the requirement for a high-performance reference source in analog integrated circuit design.

Description

Technical Field

[0001] This invention relates to the field of bandgap reference circuit technology, and in particular to a self-biased bandgap reference current circuit. Background Technology

[0002] With the rapid development of integrated circuit technology, especially in applications such as the Internet of Things, wearable devices, medical instruments, and high-precision sensors, the performance requirements for reference sources in analog integrated circuits are increasing. As an important component of analog integrated circuits, the reference source provides a stable reference voltage or current for the system, and its performance directly affects the accuracy and reliability of the entire system.

[0003] In traditional analog integrated circuit design, bandgap reference circuits are widely used because they can provide reference values ​​that are insensitive to temperature changes. However, existing bandgap reference circuits typically face the following technical challenges:

[0004] First, temperature stability is insufficient. Although traditional bandgap reference circuits are designed based on the combination of PN junction forward voltage (negative temperature coefficient) and thermal voltage (positive temperature coefficient), in practical applications, especially over a wide temperature range (e.g., -40°C to 125°C), they often fail to achieve ideal temperature compensation. This is because the temperature characteristics of semiconductor devices exhibit high-order nonlinearities, making it difficult for a simple linear combination to completely offset the effects of temperature changes. This results in the output reference value drifting with temperature variations, reducing system accuracy.

[0005] Secondly, there is the issue of startup reliability. Bandgap reference circuits often have multiple steady-state operating points, including a zero-current "dead zone" state. When the power supply is turned on, the circuit may remain in the zero-current state and fail to start normally, which requires an additional startup circuit. However, most existing startup circuits are complex in design and continue to consume power even after the circuit is operating normally, which not only increases system complexity but also reduces energy efficiency.

[0006] Third, it is sensitive to power supply variations. With the proliferation of portable devices and low-power applications, power supply conditions have become more complex and variable, such as battery voltage decay over time and increased power supply noise interference. Traditional bandgap reference circuits have limited ability to suppress power supply fluctuations (Power Supply Rejection Ratio, PSRR), making the output reference value susceptible to power supply variations and unable to meet the requirements of high-precision applications.

[0007] Fourth, external bias dependency. Many existing bandgap reference circuits require external bias circuits to provide a stable operating current, which not only increases the complexity of system design but also increases chip area and power consumption. In resource-constrained small devices, how to eliminate the dependency on external bias has become an urgent problem to be solved.

[0008] Finally, the chip area is too large. In integrated circuit design, chip area directly affects cost. Traditional bandgap reference circuits often require a large number of passive components (such as resistors and capacitors) and complex bias networks, occupying a significant amount of chip area. As integrated circuits develop towards higher integration and lower cost, how to reduce chip area while ensuring performance has become a major challenge for designers.

[0009] To address the aforementioned issues, researchers have proposed various improvement schemes. For example, curvature compensation techniques are used to improve temperature stability; one-time startup circuits are designed to reduce static power consumption; and cascaded structures are used to improve power supply rejection ratio (PSRR). However, these schemes are typically optimizations for single problems, making it difficult to solve all issues simultaneously, and often at the cost of increased circuit complexity and chip area. Therefore, there is an urgent need for a novel bandgap reference circuit design scheme that can simultaneously address multiple aspects such as temperature stability, self-starting reliability, PSRR, and chip area, meeting the comprehensive requirements of modern integrated circuit design. Summary of the Invention

[0010] To address the technical problems existing in the prior art, this invention provides a self-biased bandgap reference current circuit scheme, aiming to realize a reference current source with high power supply rejection ratio and low temperature coefficient without the need for external bias circuit, thus solving the demand for high-performance reference sources in analog integrated circuit design.

[0011] The present invention discloses a self-biased bandgap reference current circuit, which consists of four key functional modules working in concert: a current mirror circuit, a differential amplifier circuit, a temperature compensation circuit, and a self-biased startup circuit.

[0012] The current mirror circuit is constructed using multiple PMOS transistors. The gates of these PMOS transistors are interconnected to form a common-gate structure, and their sources are all connected to the power supply. This structure ensures that the gate-source voltages of each PMOS transistor are equal, thereby generating a proportionally determined current based on the same control voltage. In a specific implementation, these PMOS transistors include M12, M1, M0, M8, and M7, which form a current replication and distribution network, replicating the reference current to different parts of the circuit.

[0013] A differential amplifier circuit consists of differential pair transistors, load transistors, and bias transistors. The differential pair transistors (such as M2 and M3) receive the input signal from the temperature compensation circuit, the load transistors (such as M5 and M6) provide the load impedance required for amplification, and the bias transistor (such as M4) provides the appropriate operating current. The differential amplifier circuit achieves precise voltage control by comparing the voltage difference between two critical nodes (node ​​A and node B) in the temperature compensation circuit and using negative feedback to bring these two node voltages to near equality.

[0014] The temperature compensation circuit comprises at least two bipolar transistors (e.g., Q0, Q1) and multiple resistors (e.g., R1, R2, R3, R4). This circuit forms the core of the entire bandgap reference, and its operating principle is based on the characteristic that the forward voltage of the PN junction of a bipolar transistor has a negative temperature coefficient (decreases with increasing temperature), while the thermal voltage has a positive temperature coefficient (increases with increasing temperature). Through the circuit structure and resistor ratio designed in this invention, these two voltage components with opposite temperature coefficients cancel each other out, generating a reference current that is insensitive to temperature changes.

[0015] The self-biased startup circuit consists of at least one capacitor (e.g., C1) and at least one transistor (e.g., M10, M11). This circuit solves the self-starting problem of the bandgap reference circuit, preventing the circuit from falling into a zero-current steady-state point. When the power supply is turned on, the characteristic that the voltage across the capacitor cannot change instantaneously causes the control transistor (e.g., M10) to conduct, providing initial bias current for the current mirror circuit and the differential amplifier circuit. As the circuit reaches its normal operating point, the self-biased startup circuit automatically turns off and no longer participates in subsequent operations.

[0016] The cooperation among these four functional modules during operation is as follows: First, the self-biased startup circuit ensures that the circuit starts correctly from a zero state; second, the differential amplifier circuit uses a negative feedback mechanism to make the voltages at the key nodes of the temperature compensation circuit equal, thus constructing a precise combination of the thermal voltage (positive temperature coefficient) and the PN junction voltage (negative temperature coefficient) of the bipolar transistor; finally, the current mirror circuit replicates the temperature-compensated current and provides a stable output, while using the differential structure to effectively suppress power supply fluctuations.

[0017] According to a self-biased bandgap reference current circuit of the present invention, specifically, the current mirror circuit includes a first to a fifth PMOS transistor (M12, M1, M0, M8, M7), the gates of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) and the drain of a second PMOS transistor (M1) are connected together, and the sources of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) are connected to a power supply; wherein, each of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) has the same width-to-length ratio, and the total width-to-length ratio of the PMOS transistors M12, M1, M8, and M7 is equal, for realizing the current mirror function.

[0018] It is understood that this scheme specifically defines the structure of the current mirror circuit, including the first to fifth PMOS transistors (M12, M1, M0, M8, M7). The gates of these transistors are connected together, and their sources are connected to the power supply. Furthermore, the width-to-length ratios of the first PMOS transistor (M12), the fifth PMOS transistor (M7), and the fourth PMOS transistor (M8) are equal. This specific current mirror design achieves the following technical effects: First, the common-gate structure ensures that these PMOS transistors are controlled by the same gate-source voltage, forming a voltage-controlled current source array. Second, the individual widths and lengths of all five PMOS transistors (M12, M1, M0, M8, M7) are identical. This comprehensive size matching not only ensures that the current flowing through M12, M7, and M8 maintains a precise proportional relationship but also ensures that the bias currents provided by M1 and M0 have the same temperature characteristics and process sensitivity, thereby improving the matching accuracy and stability of the entire current mirror network. This comprehensive transistor matching design offers significant advantages over partial matching: it improves the overall accuracy of the current mirror, reduces the impact of process variations on circuit performance, enhances the balance between branches of the temperature compensation circuit, and improves the stability of the differential amplifier's bias current. During circuit operation, M12 provides the reference current output, while M7 and M8 provide equal bias currents to the two branches of the temperature compensation circuit, respectively. This precise current distribution ensures balanced operation of the two critical nodes (node ​​A and node B) in the temperature compensation circuit, providing stable input conditions for the differential amplifier. Simultaneously, M1 and M0, as key bias units, provide operating current for the differential amplifier and the temperature compensation network. M0 specifically provides a common-mode current source for the differential pair transistors (M2 and M3), ensuring the linear operating region of the differential amplifier. This current mirror structure exhibits high output impedance characteristics during operation, effectively suppressing the impact of load variations on current accuracy. Furthermore, its symmetrical design enhances the circuit's reliability against process fluctuations and temperature changes, providing a stable and reliable current foundation for the entire self-biased bandgap reference circuit.

[0019] According to a self-biased bandgap reference current circuit of the present invention, specifically, the differential amplifier circuit includes:

[0020] The source of the differential pair transistors (M2, M3) is connected to the drain of the third PMOS transistor (M0);

[0021] Load transistors (M5, M6), wherein the drain of M5 is connected to the drain of M2, the drain of M6 is connected to the drain of M3, and the gate of M5 is connected to the gate and drain of M6.

[0022] The gate of the bias transistor (M4) is connected to the drain of M2 and the drain of M5.

[0023] The sources of the load transistors (M5, M6) and the bias transistor (M4) are both grounded; the width-to-length ratio of the first transistor (M2) and the second transistor (M3) in the differential pair transistors is equal; the width-to-length ratio of the first load transistor (M5) and the second load transistor (M6) in the load transistors is equal, which is used to form a balanced differential amplifier structure.

[0024] As can be understood, this scheme defines in detail the structure of the differential amplifier circuit, including the differential pair transistors (M2, M3), load transistors (M5, M6), and bias transistor (M4), as well as their connection relationships and size matching requirements. This differential amplifier structure achieves the following technical effects: First, the source of the differential pair transistors is connected to the drain of the PMOS transistor M0, forming a current-source biased differential input stage. M0 provides a constant bias current, enabling the differential pair to operate in the high-gain region while possessing good common-mode rejection capability. Second, the load transistors M5 and M6 form an active load in a common-gate connection, improving the voltage gain of the differential amplifier, and their drains are connected to the drains of M2 and M3 respectively, forming a high-gain node. The gate of the bias transistor M4 is connected to the drains of M2 and M5, forming a self-biasing loop, enabling the circuit to automatically establish a suitable operating point. Of particular note is that M2 and M3 have the same width-to-length ratio, and M5 and M6 have the same width-to-length ratio. This symmetrical design ensures the balance on both sides of the differential amplifier, improving the common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR). In actual operation, when a slight difference occurs in the voltages of node A and node B in the temperature compensation circuit, the differential pair amplifies this difference and adjusts the bias current of the current mirror through feedback, making the voltages of nodes A and B tend to be equal. This differential amplifier structure not only provides high-gain voltage comparison functionality but also possesses excellent common-mode rejection characteristics, significantly suppressing power supply noise as a common-mode signal and further improving the stability of the reference current. Simultaneously, the design of grounding all transistor sources simplifies the bias network, reducing circuit area and power consumption.

[0025] According to a self-biased bandgap reference current circuit of the present invention, specifically, it further includes a first capacitor (C0) and a first resistor (R0). One end of the first resistor (R0) is connected to the drain and gate of the second PMOS transistor (M1), and the other end is connected to the positive terminal of the first capacitor (C0) and the drain of the bias transistor (M4). The negative terminal of the first capacitor (C0) is connected to the drain of the first transistor (M2) in the differential pair transistor. The voltages of the two differential input nodes (A, B) of the differential amplifier circuit are equal when the circuit is operating stably. A high power supply rejection ratio is achieved through the differential amplifier structure, and the drain current of the fourth PMOS transistor (M8) is equal to the drain current of the fifth PMOS transistor (M7).

[0026] As can be understood, this scheme introduces the configuration of a first capacitor (C0) and a first resistor (R0), and details their connection relationship and the voltage characteristics of the differential input nodes (A, B). This configuration achieves the following technical effects: First, resistor R0 is connected between the drains of M1 and M4, forming a current feedback path. This path, together with capacitor C0, constitutes a compensation network, improving the phase margin of the circuit and preventing high-frequency oscillations. Second, the positive terminal of C0 is connected to the drain of M4, and the negative terminal is connected to the drain of M2, forming a Miller compensation structure, providing a feedforward path in the high-frequency band and improving the stability of the circuit. During circuit operation, when the power supply voltage fluctuates, this fluctuation is conducted to the differential amplifier through the current mirror structure. However, due to the high common-mode rejection ratio of the differential amplifier, the power supply fluctuation as a common-mode signal is largely suppressed. At the same time, the differential amplifier maintains the voltages of nodes A and B equal through a negative feedback mechanism, further reducing the impact of power supply fluctuations on the reference current. The RC network configuration plays a crucial role in the frequency domain: at low frequencies, it maintains the high-gain characteristics of the differential amplifier, ensuring precise voltage matching between nodes A and B; at high frequencies, it provides negative feedback compensation, preventing system instability. This design not only improves the circuit's transient response performance but also enhances its ability to suppress power supply noise, enabling the reference current to maintain high stability under various operating conditions. Specifically, the fact that the drain current of the fourth PMOS transistor (M8) is equal to that of the fifth PMOS transistor (M7) ensures current balance in the two critical branches (nodes A and B) of the temperature compensation circuit. This precise current matching further improves the accuracy of temperature compensation, reduces temperature coefficient deviations caused by branch imbalances, and enhances the temperature stability of the reference current.

[0027] According to a self-biased bandgap reference current circuit of the present invention, specifically, the temperature compensation circuit includes:

[0028] First bipolar transistor (Q1);

[0029] Second bipolar transistor (Q0);

[0030] The second to fifth resistors (R1, R2, R3, R4);

[0031] Wherein, one end of the second resistor (R1) is connected to the emitter of the first bipolar transistor (Q1), and the other end of the second resistor (R1) is connected to the third resistor (R2), the gate of the first transistor (M2) in the differential pair transistor, and the drain of the fourth PMOS transistor (M8).

[0032] One end of the fourth resistor (R3) is connected to the emitter of the second bipolar transistor (Q0), the gate of the second transistor (M3) in the differential pair transistor, the drain of the fifth PMOS transistor (M7), and the drain of the PMOS transistor (M9).

[0033] The other end of the third resistor (R2) is connected to the base of the fourth resistor (R3), the fifth resistor (R4), and the first and second bipolar transistors (Q0, Q1);

[0034] The collectors of the first and second bipolar transistors (Q0, Q1) and the other end of the fifth resistor (R4) are grounded;

[0035] The third resistor (R2) and the fourth resistor (R3) have the same W / L value, forming a symmetrical structure for the temperature compensation circuit.

[0036] As can be understood, this scheme details the structure of the temperature compensation circuit, including the connection relationships and symmetry requirements of the bipolar transistors (Q1, Q0) and multiple resistors (R1, R2, R3, R4). This temperature compensation circuit achieves the following technical effects: First, the emitters of bipolar transistors Q1 and Q0 are connected to different resistor networks and the gates of the differential pair transistors, respectively, forming a temperature-sensitive voltage source; the bases of Q1 and Q0 are connected together, forming a bandgap reference core; the collector is grounded, enabling the transistors to operate in the forward active region. Second, the resistor network (R1, R2, R3, R4) constructs a precise current distribution path, where the W / L values ​​of R2 and R3 are equal, ensuring the symmetry of the temperature compensation circuit. During operation, the core principle of the temperature compensation circuit lies in utilizing two voltage components with opposite temperature coefficients: the base-emitter voltage VQ0_BE of Q0 has a negative temperature coefficient (approximately -2mV / °C), while the thermal voltage VT (related to the proportion of bipolar transistors) has a positive temperature coefficient (approximately +0.085mV / °C). Through the resistor network designed in this invention, these two components with opposite temperature coefficients are combined in an appropriate ratio to cancel each other out the temperature effect. R1 and R3 are connected to the gates of differential pair transistors M2 and M3, transmitting the temperature-sensitive voltage to the differential amplifier, forming a closed-loop control system. The differential amplifier adjusts the current mirror output through a negative feedback mechanism, making the voltages at nodes A and B equal. This balanced state ensures that the current distribution of the two branches meets the temperature compensation requirements. R4 is connected to the bases of Q0 and Q1 and ground, providing a base current path to ensure that the bipolar transistors operate at the correct bias point. This temperature compensation circuit structure achieves temperature compensation for the reference current through precise control of current distribution and voltage balance, keeping the output current highly stable over a wide temperature range. Meanwhile, its symmetrical design enhances the circuit's resistance to process fluctuations and improves the accuracy and consistency of the reference current.

[0037] According to a self-biased bandgap reference current circuit of the present invention, specifically, the ratio of the number of the first bipolar transistor (Q1) to the number of the second bipolar transistor (Q0) is 1:8; the resistance ratio of the second resistor (R1) to the fourth resistor (R3) is 8:1. The output reference current does not change with temperature through the combination of these two ratios.

[0038] It is understandable that this scheme specifies key proportional relationships: the ratio of the first bipolar transistor (Q1) to the second bipolar transistor (Q0) is 1:8; the resistance ratio of the second resistor (R1) to the fourth resistor (R3) is 8:1. These specific proportional relationships achieve the following technical effects: First, the 1:8 ratio of Q1 to Q0 physically means that Q0 consists of eight parallel transistors of the same size, while Q1 has only one. This configuration makes the emitter current density of Q0 eight times smaller than that of Q1. According to the physical characteristics of bipolar transistors, the base-emitter voltage difference between the two is VT·ln8, where VT is the thermal voltage, which has a positive temperature coefficient. Second, the 8:1 resistance ratio of R1 to R3 complements the Q1:Q0 ratio, which is the core of the temperature compensation principle. In actual operation, these two precisely set ratios work together: when the temperature rises, the VBE voltage of Q0 decreases (negative temperature coefficient), while VT·ln8 increases (positive temperature coefficient). By using a design ratio of R1:R3=8:1 (however, the ratio of R1 to R3 will be affected by the actual process parameters, and the design ratio may be too large or too small to some extent), the components of these two opposite temperature coefficients are made to cancel each other out, which is mathematically expressed as: This precise mathematical balance makes the output reference current Iref insensitive to temperature changes, achieving a low temperature coefficient reference current source. It is worth noting that the precise setting of this proportional relationship directly determines the temperature stability of the reference current; any deviation will weaken the temperature compensation effect. Therefore, in actual circuit design and layout, special measures need to be taken to ensure the precise realization of these proportional relationships, such as using matched layout techniques and gradient arrangements, to reduce the impact of process variations and environmental factors. Through this designed proportional relationship, the circuit can maintain an extremely low temperature coefficient (typically less than 100 ppm / °C) over a wide temperature range (typically -40°C to 125°C), meeting the requirements of high-precision analog circuits.

[0039] According to a self-biased bandgap reference current circuit of the present invention, specifically, the self-biased startup circuit includes:

[0040] The sixth NMOS transistor (M11) has its gate connected to the power supply and its source grounded.

[0041] The second capacitor (C1) has its positive terminal connected to the power supply and its negative terminal connected to the drain of the sixth NMOS transistor (M11);

[0042] The seventh NMOS transistor (M10) has its drain connected to the gate of the second PMOS transistor (M1), its source grounded, and its gate connected to the drain of the sixth NMOS transistor (M11).

[0043] The gates of the eighth PMOS transistor (M13) and the ninth NMOS transistor (M14) are connected to the drain of the sixth NMOS transistor (M11);

[0044] The tenth PMOS transistor (M9) has its source connected to the power supply. The gate of the tenth PMOS transistor (M9) is connected to the drain of the eighth PMOS transistor (M13) and the ninth NMOS transistor (M14). The drain of the tenth PMOS transistor (M9) is connected to one end of the fourth resistor (R3).

[0045] During the circuit startup phase, the voltage across the second capacitor (C1) in the self-biased startup circuit cannot change abruptly, causing the seventh NMOS transistor (M10) to conduct and start the current mirror circuit. As the circuit reaches a stable operating point, the seventh NMOS transistor (M10) automatically turns off, achieving the self-start function.

[0046] As can be understood, this scheme details the structure and working principle of the self-biased startup circuit, including the connection relationship between multiple transistors (M11, M10, M13, M14, M9) and capacitor C1. This self-biased startup circuit achieves the following technical effects: First, the circuit solves the inherent startup problem of bandgap reference circuits—bandgap circuits typically have two steady-state operating points, one being the desired normal operating point, and the other a zero-current "dead zone" state. Without a startup circuit, the circuit may remain in the zero-current state and fail to operate normally. Second, this startup circuit employs a self-biasing mechanism based on capacitive coupling, eliminating the need for continuous static power consumption. The working process is as follows: When the power supply is turned on, the voltage across capacitor C1 cannot change instantaneously; its initial negative terminal voltage is close to the power supply voltage, resulting in a higher gate voltage for NMOS transistor M10, which then conducts. After M10 conducts, it pulls down the common gate of the current mirror (the gate of M1), activating the current mirror circuit. Simultaneously, the gate of M11 is connected to the power supply, and its source is grounded, forming a conducting state. Its drain begins to discharge to the negative terminal of C1, causing the voltage of the negative terminal of C1 to gradually decrease. The gates of M13 and M14 are connected to the drain of M11. When the power supply is turned on, M14 conducts, and the gate of M9 is at a low level. As the gate voltage of M9 decreases, M9 conducts and injects auxiliary startup current into the R3 branch of the temperature compensation circuit. This extra current ensures that the bipolar transistor Q0 can quickly establish the correct emitter bias condition during the startup phase, accelerate the establishment of the node B voltage, and provide stable input conditions for the differential amplifier, thereby improving the reliability and speed of startup. As the circuit gradually reaches the normal operating point, the negative terminal voltage of C1 is low enough to turn off M10 and M14, turn on M13, and turn off M9. At this time, the circuit has entered a self-sustaining state, and the startup circuit automatically exits operation, no longer consuming additional power. This one-time startup mechanism based on capacitive coupling not only ensures the reliability of circuit startup but also avoids the disadvantage of continuous power consumption in traditional startup circuits, improving energy efficiency. Furthermore, the startup circuit is designed to withstand various extreme operating conditions, such as low temperature, low power supply voltage, and slow start-up. By appropriately adjusting the size of M11 and the capacitance of C1, reliable startup under various conditions is ensured. This self-biased startup method also reduces reliance on external bias circuits, lowers system complexity and cost, and saves chip area.

[0047] According to a self-biased bandgap reference current circuit of the present invention, specifically, the reference current generated by the temperature compensation circuit is:

[0048]

[0049] in, The base-emitter voltage difference of the second bipolar transistor (Q0) The reference current is a thermal voltage, and R1 and R3 are the resistance values ​​of the second resistor (R1) and the fourth resistor (R3), respectively. The temperature stability of the reference current is achieved by canceling out the two components with opposite temperature coefficients.

[0050] As can be understood, this scheme describes the mathematical expression for the reference current and explains the principle behind temperature stability. This mathematical expression reveals the following technical effects: First, the reference current Iref consists of two key components, the first term... This term reflects the contribution of the base-emitter voltage of the bipolar transistor Q0 to the reference current; it has a negative temperature coefficient. The second term... This reflects the contribution of the thermal voltage difference generated by the bipolar transistor ratio (Q1:Q0=1:8) to the reference current, and this term has a positive temperature coefficient. Secondly, the formula clearly shows the regulating effect of resistors R1 and R3 on the output current, providing a precise mathematical basis for circuit design. In actual operation, these two opposing temperature coefficient components interact: when the temperature rises, VQ0_BE decreases (approximately -2mV / °C), causing the first term to decrease; simultaneously, VT increases (approximately +0.085mV / °C), causing the second term to increase. By designing the ratio of R1 to R3 (R1:R3=8:1), these two opposing trends cancel each other out, making the total current Iref insensitive to temperature. The importance of this mathematical expression lies in its provision of the theoretical foundation for bandgap reference circuits, enabling designers to accurately calculate the required resistance values ​​and transistor parameters according to specific application requirements. For example, by adjusting the absolute values ​​of R1 and R3 (while maintaining the R1:R3 ratio of 8:1), the required reference current can be set; by fine-tuning the proportional relationship, the shape of the temperature profile can be adjusted, such as achieving zero temperature coefficient at a specific temperature point or high-order compensation of the temperature profile. Furthermore, this expression also indicates the path of influence of process parameter fluctuations on the reference current, providing guidance for reliable circuit design.

[0051] According to a self-biased bandgap reference current circuit of the present invention, specifically, the temperature dependence of the reference current satisfies:

[0052]

[0053] in, Let be the partial derivative of the thermal voltage VT with respect to temperature T. The base-emitter voltage difference of the second bipolar transistor (Q0) The partial derivative with respect to temperature T; the temperature coefficient of the reference current Iref is made zero by using this temperature partial derivative equation to ensure the stability of the reference current over a wide temperature range.

[0054] As can be understood, this scheme proposes a mathematical expression for the temperature dependence of the reference current and explains in detail the condition that the temperature coefficient is zero. This mathematical expression achieves the following technical effects: First, it rigorously proves the temperature stability condition of the reference current in theory, providing a precise mathematical basis for circuit design. The expression sets the partial derivative of the reference current Iref with respect to temperature T to zero, meaning that Iref is insensitive to temperature changes, thus achieving temperature compensation. Second, the expression clarifies the temperature dependence of each physical quantity: This represents the partial derivative (positive value) of the thermal voltage VT with respect to temperature. This represents the negative partial derivative of the base-emitter voltage of Q0 with respect to temperature. In practical applications, when the ambient temperature changes, the base-emitter voltage VQ0_BE of the bipolar transistor Q0 changes with temperature at a rate of approximately -2mV / °C (negative temperature coefficient), while the thermal voltage VT changes with temperature at a rate of approximately +0.085mV / °C (positive temperature coefficient). Substituting these known physical parameters into the equation and considering ln8≈2.08, we can derive the key condition for achieving temperature compensation: R1 / R3 ≈ 8. This rigorous derivation of the mathematical condition not only provides theoretical guidance for circuit design but also reveals the essence of the temperature compensation mechanism—precisely canceling the voltage components of the positive and negative temperature coefficients in the current domain through precisely controlled resistance ratios. It is worth noting that this equation considers first-order temperature compensation, i.e., the cancellation of the linear temperature coefficient. In high-precision applications, higher-order temperature nonlinearities must also be considered, which is typically achieved by introducing an additional curvature compensation network. This mathematical expression has significant engineering implications: it not only provides a precise basis for resistor ratio design but also identifies key parameters affecting temperature stability, enabling designers to optimize circuits in a targeted manner to achieve reference current sources with extremely low temperature coefficients (typically as low as tens of ppm / °C). Furthermore, this expression provides a theoretical framework for testing and analyzing temperature performance, facilitating the evaluation of temperature compensation effects in practical circuits.

[0055] According to a self-biased bandgap reference current circuit of the present invention, specifically, it further includes an output current mirror structure for providing high-precision output current, the output current mirror structure comprising:

[0056] The second PMOS output transistor (MO2) has its source connected to a power supply and its drain providing an enhancement-mode reference current output (Iref_out).

[0057] The self-biased bandgap reference current circuit has a dual-output structure, including the original reference current output (Iref) provided by the drain of the first PMOS transistor (M12) and the enhanced reference current output (Iref_out) provided by the drain of the second PMOS output transistor (MO2). Both can be used simultaneously to meet different application requirements.

[0058] It is understood that this scheme describes an output current mirror structure for providing high-precision output current, including a second PMOS output transistor (MO2) and a dual-output design. This output current mirror structure achieves the following technical effects: First, by replicating the reference current of the core circuit through an independent PMOS current mirror (MO2), an additional isolation layer is provided, reducing the impact of load effects on the core circuit; MO2, as an output transistor, provides an enhanced reference current output Iref_out. Second, the dual-output design (retaining the Iref output from the original M12 drain while simultaneously providing the Iref_out output from the MO2 drain) increases the application flexibility of the circuit, meeting the needs of different scenarios. In practical applications, this structure has multiple advantages:

[0059] 1. Improved output current accuracy: Through an independent output current mirror, the core circuit is isolated from the load, avoiding reference distortion caused by load changes feeding back to the core circuit.

[0060] 2. Enhanced load regulation capability: Output transistor MO2 provides higher output impedance, making the output current less sensitive to changes in load voltage and improving load regulation.

[0061] 3. Functional Flexibility: The dual-output design allows the circuit to meet different performance requirements simultaneously. The Iref output (M12 drain) remains compatible with the original circuit and is suitable for applications sensitive to area and power consumption; the Iref_out output (MO2 drain) provides higher performance characteristics and is suitable for scenarios with high precision and drive capability requirements.

[0062] It should be noted that all current outputs must mirror the current at the drain of M1, and the current at the drain of M1 is the source of the mirrored current. Changing the ratio of the number of MO2 to M1 transistors can change the output current at the drain of MO2. The output current at the drain of MO2 will not affect the core circuit and will not add any additional circuitry to nodes A and B. Except for circuitry that can be turned off after startup, the current flowing into the drain of the PMOS transistors at nodes A and B is equal.

[0063] According to a self-biased bandgap reference current circuit of the present invention, specifically, it further includes a capacitor compensation structure for enhancing output filtering, comprising:

[0064] The output filter capacitor (C_filt) has one end connected to the drain of the second PMOS output transistor (MO2) and the other end grounded, and is used to filter out high-frequency noise in the enhanced reference current output (Iref_out);

[0065] The capacitor compensation structure ensures the output current quality of the self-biased bandgap reference current circuit.

[0066] Understandably, this solution adds an output filter capacitor (C_filt). This capacitor compensation structure achieves the following technical effects: the output filter capacitor C_filt is connected between the enhanced reference current output Iref_out and ground, forming a low-pass filter that effectively suppresses high-frequency noise and ripple.

[0067] In actual work process

[0068] The noise suppression mechanism of C_filt is as follows: Bandgap reference circuits inevitably generate or conduct various noises, including thermal noise, flicker noise, and power supply coupling noise. C_filt and the equivalent resistance at the Iref_out output (mainly determined by the output impedance of MO2) form an RC low-pass filter with a cutoff frequency of fc = 1 / (2πR·C_filt). A properly designed C_filt can set the cutoff frequency within the desired frequency band (typically several kHz to hundreds of kHz), effectively filtering out high-frequency noise components while maintaining responsiveness to slow load changes. This filtering characteristic is crucial for applications requiring high signal-to-noise ratios, such as high-precision ADCs and low-noise amplifiers.

[0069] Furthermore, C_filt provides additional power supply rejection, particularly for high-frequency power supply noise, further improving PSRR performance at high frequencies. Experimental results show that the addition of C_filt can reduce output current noise by 5-10 dB, significantly improving signal quality.

[0070] The technical effects that the self-biased bandgap reference current circuit of the present invention aims to achieve include:

[0071] First, the self-biasing characteristic is achieved. Through the design of the self-biased startup circuit, utilizing the characteristic that the voltage of capacitor C1 cannot change abruptly, at the instant the power is supplied, the voltage at the negative terminal of C1 approaches the power supply voltage, causing the control transistor M10 to conduct. This provides the initial operating voltage to the gate of the current mirror MOS (M1, M0, M8, M7), and the differential circuit begins to operate, driving M4 with its output voltage. The self-biasing path, through M1, R0, and M4, generates a bias voltage at the drain of M1, resulting in a current output from the drain of M1. This current is mirrored to M0, forming a feedback path that stabilizes the circuit. As the circuit gradually stabilizes, the differential amplifier circuit forms a self-stabilizing feedback. The negative terminal of C1 discharges completely through M11, reaching zero voltage, and M10 automatically turns off, allowing the circuit to enter normal operation. This design eliminates the dependence on external bias circuits, reducing system complexity and area.

[0072] Secondly, temperature stability is achieved. Under the negative feedback of the differential amplifier, the voltages at nodes A and B in the temperature compensation circuit are equal. When the ratio of bipolar transistors Q1 to Q0 is 1:8, a thermal voltage term VTln8 is generated, which has a positive temperature coefficient; simultaneously, the base-emitter voltage VQ0_BE of Q0 has a negative temperature coefficient. By designing the ratio of resistors R1 to R3 to be 8:1, the reference current is... The two opposing components of the temperature coefficient in the equation exactly cancel each other out, that is... This ensures the stability of the reference current to temperature.

[0073] Secondly, a high power supply rejection ratio is achieved. The common-mode rejection characteristic of the differential amplifier circuit effectively suppresses power supply noise as a common-mode signal; simultaneously, the high output impedance characteristic of the current mirror structure further reduces the impact of power supply variations on the output current. Through the negative feedback of the differential amplifier, disturbances caused by power supply fluctuations are automatically compensated, making the output reference current highly stable relative to power supply changes.

[0074] Finally, the chip area is reduced. Due to the self-biased design, the circuit does not require a separate bias power supply circuit. At the same time, the functional modules are tightly integrated, which significantly reduces the chip area, improves the integration level, and reduces the cost.

[0075] In summary, this invention achieves a reference current source with high power supply rejection ratio and low temperature coefficient without the need for an external bias circuit by organically combining self-biased startup mechanism, temperature compensation balancing technology and differential amplifier negative feedback principle, thus solving the need for high-performance reference sources in analog integrated circuit design. Attached Figure Description

[0076] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0077] Figure 1 This is a circuit design structure diagram of Embodiment 1 of the present invention;

[0078] Figure 2 This is a circuit design structure diagram of Embodiment 2 of the present invention. Detailed Implementation

[0079] To more clearly illustrate the technical solution of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments described in this section are intended to illustrate the present invention by way of example, and are not intended to limit the present invention. Those skilled in the art, under the guidance of the present invention, can make various modifications or additions to the following embodiments, and such modifications or additions should all fall within the protection scope of the present invention.

[0080] Example 1

[0081] like Figure 1 As shown, this embodiment provides a self-biased bandgap reference current circuit, which solves the problem that traditional bandgap reference circuits require an additional bias circuit, while achieving a high power supply rejection ratio and a low temperature coefficient for reference current output.

[0082] Regarding the circuit structure, the self-biased bandgap reference current circuit in this embodiment mainly includes four parts: current mirror circuit, differential amplifier circuit, temperature compensation circuit, and self-biased startup circuit.

[0083] 1. Current Mirror Circuit: The current mirror circuit includes first to fifth PMOS transistors (M12, M1, M0, M8, M7). The gates of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) and the drain of the second PMOS transistor (M1) are connected together. The sources of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) are connected to the power supply VDD. Each of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) has the same width-to-length ratio, and the total width-to-length ratio of PMOS transistors M12, M1, M8, and M7 is equal, which is used to implement the current mirror function. With this structural design, the current mirror circuit can accurately replicate the current, while the drain of the first PMOS transistor (M12) provides a reference current output Iref.

[0084] 2. Differential Amplifier Circuit: The differential amplifier circuit includes differential pair transistors (M2, M3), load transistors (M5, M6), and bias transistor (M4). The sources of the differential pair transistors (M2, M3) are connected to the drain of the third PMOS transistor (M0). The drain of the load transistor M5 is connected to the drain of M2, and the drain of M6 is connected to the drain of M3. The gate of M5 is connected to the gate and drain of M6. The gate of the bias transistor (M4) is connected to the drains of M2 and M5. The sources of both the load transistors (M5, M6) and the bias transistor (M4) are grounded. The circuit also includes a first capacitor (C0) and a first resistor (R0). One end of the first resistor (R0) is connected to the drain and gate of the second PMOS transistor (M1), and the other end is connected to the positive terminal of the first capacitor (C0) and the drain of the bias transistor (M4). The negative terminal of the first capacitor (C0) is connected to the drain of the first transistor (M2) in the differential pair transistors. M2 and M3 in the differential pair transistors have equal width-to-length ratios, and M5 and M6 in the load transistors have equal width-to-length ratios. This design forms a balanced differential amplifier structure, ensuring that the voltages of the two differential input nodes (A, B) of the differential amplifier are equal when the circuit is operating stably. This differential amplifier structure achieves a high power supply rejection ratio, and the drain currents of the fourth PMOS transistor (M8) and the fifth PMOS transistor (M7) are equal.

[0085] 3. Temperature Compensation Circuit: The temperature compensation circuit includes a first bipolar transistor (Q1), a second bipolar transistor (Q0), and second to fifth resistors (R1, R2, R3, R4). One end of the second resistor (R1) is connected to the emitter of the first bipolar transistor (Q1), and the other end is connected to the third resistor (R2), the gate of the first transistor (M2) in the differential pair transistor, and the drain of the fourth PMOS transistor (M8). One end of the fourth resistor (R3) is connected to the emitter of the second bipolar transistor (Q0), the gate of the second transistor (M3) in the differential pair transistor, the drain of the fifth PMOS transistor (M7), and the drain of the PMOS transistor (M9). The other end of the third resistor (R2) is connected to the fourth resistor (R3), the fifth resistor (R4), and the bases of the first and second bipolar transistors (Q0, Q1). The collectors of the first and second bipolar transistors (Q0, Q1) and the other end of the fifth resistor (R4) are grounded. To achieve temperature compensation, the W / L values ​​of the third resistor (R2) and the fourth resistor (R3) are equal, forming a symmetrical structure for the temperature compensation circuit. Specifically, the ratio of the number of the first bipolar transistor (Q1) to the number of the second bipolar transistor (Q0) is 1:8, and the resistance ratio of the second resistor (R1) to the fourth resistor (R3) is 8:1. The combination of these two ratios ensures that the output reference current does not change with temperature.

[0086] 4. Self-Biased Startup Circuit: The self-biased startup circuit includes a sixth NMOS transistor (M11), a second capacitor (C1), a seventh NMOS transistor (M10), eighth and ninth PMOS transistors (M13, M14), and a tenth PMOS transistor (M9). The gate of the sixth NMOS transistor (M11) is connected to the power supply, and its source is grounded. The positive terminal of the second capacitor (C1) is connected to the power supply, and its negative terminal is connected to the drain of the sixth NMOS transistor (M11). The drain of the seventh NMOS transistor (M10) is connected to the gate of the second PMOS transistor (M1), its source is grounded, and its gate is connected to the drain of the sixth NMOS transistor (M11). The gates of the eighth PMOS transistor (M13) and the ninth NMOS transistor (M14) are connected to the drain of the sixth NMOS transistor (M11). The source of the tenth PMOS transistor (M9) is connected to the power supply, the gate of the tenth PMOS transistor (M9) is connected to the drain of the eighth PMOS transistor (M13) and the ninth NMOS transistor (M14), and the drain of the tenth PMOS transistor (M9) is connected to one end of the fourth resistor (R3).

[0087] Regarding the working principle, the self-biased bandgap reference current circuit in this embodiment works as follows:

[0088] 1. Startup Phase: After power-on, the voltage across the second capacitor (C1) cannot change abruptly. The negative terminal voltage of C1 is VDD, NMOS transistor M10 turns on, and the drain-source terminals of current sources M12, M1, M0, M7, and M8 are turned on. The M7-R3-R4 path and the M8-R2-R4 path are opened. Since the voltages at nodes A and B are lower than the drain voltage of M0, the differential pairs M2 and M3 are turned on. The gate voltage of M4 is higher than the turn-on voltage of NMOS transistor M4, so M4 is turned on. M1, R0, and M4 form a circuit, and the self-biasing voltage of the drain of M1 gradually rises to the quiescent operating point voltage of the circuit. At the same time, the gate of M11 is connected to the power supply, the drain-source terminal of M11 turns on, the negative terminal voltage of C1 gradually decreases, and M10 turns off. This achieves self-biasing of the differential operational amplifier, eliminating the need for an additional bias circuit and reducing the chip area.

[0089] 2. Stable Operation Phase: During stable operation, the differential amplifier circuit maintains equal voltages at the two critical nodes A and B in the temperature compensation circuit. Because nodes A and B are connected to different components, especially with a Q1 to Q0 ratio of 1:8, maintaining equal node voltages generates a voltage component proportional to and inversely proportional to temperature. These two voltage components with opposite temperature coefficients cancel each other out through a specific resistor ratio (R1 / R3 = 8), forming a reference current Iref that does not change with temperature.

[0090] 3. Reference Current Formation: The reference current generated in this embodiment can be described as follows:

[0091]

[0092] in, The base-emitter voltage difference of the second bipolar transistor (Q0) The voltage is the thermal voltage, and R1 and R3 are the resistance values ​​of the second resistor (R1) and the fourth resistor (R3), respectively.

[0093] As can be seen from the above formula, the reference current consists of two parts: the first part It has a negative temperature coefficient, Part Two It has a positive temperature coefficient. When these two temperature coefficients cancel each other out, the reference current can remain unchanged with temperature.

[0094] Specifically, the dependence of the reference current on temperature can be expressed as follows:

[0095]

[0096] When R1 / R3 = 8, the above equation holds true, achieving a zero temperature coefficient for the reference current Iref and ensuring the stability of the reference current over a wide temperature range.

[0097] The self-biased bandgap reference current circuit of this embodiment has the following technical advantages: 1. Self-biasing function: Through ingenious startup circuit design, the circuit achieves self-biasing functionality, eliminating the need for an additional bias circuit and reducing chip area and power consumption. 2. Low temperature coefficient: By designing a temperature compensation circuit and using specific device size ratios, two voltage components with opposite temperature coefficients cancel each other out, achieving low sensitivity of the reference current to temperature changes and ensuring the stability of the reference current over a wide temperature range. 3. High power supply rejection ratio: Employing a differential amplifier structure and utilizing its common-mode rejection characteristics, the circuit's ability to suppress power supply fluctuations is significantly improved, reducing the impact of power supply noise on the reference current. 4. Simple and efficient circuit: Through the organic combination of multiple functional modules, a simple yet powerful reference current circuit is achieved, suitable for various applications in integrated circuits requiring a stable current source.

[0098] Example 2

[0099] Based on the self-biased bandgap reference current circuit of Embodiment 1, this embodiment provides a further enhanced design, such as... Figure 2 As shown. While retaining the basic structure and working principle of Embodiment 1, Embodiment 2 adds an enhanced structure to further improve circuit performance.

[0100] Specifically, to provide high-precision output current, this embodiment adds an output current mirror structure, including a second PMOS output transistor (MO2):

[0101] The source of the second PMOS output transistor (MO2) is connected to the power supply, and its drain provides an enhancement-mode reference current output (Iref_out). All current outputs must mirror the current at the drain of M1. Changing the ratio of MO2 to M1 transistors alters the output current at the drain of MO2.

[0102] With this design, the circuit has a dual-output structure, including the original reference current output (Iref) provided by the drain of the first PMOS transistor (M12) and the enhanced reference current output (Iref_out) provided by the drain of the second PMOS output transistor (MO2), both of which can be used simultaneously to meet different application requirements.

[0103] 3. Capacitor compensation structure.

[0104] To enhance output filtering, this embodiment adds a capacitor compensation structure, including:

[0105] The output filter capacitor (C_filt) has one end connected to the drain of the second PMOS output transistor (MO2) and the other end grounded. It is used to filter out high-frequency noise in the enhanced reference current output (Iref_out).

[0106] The output filter capacitor (C_filt) acts as a low-pass filter, filtering out high-frequency noise components in the output current and providing a cleaner DC reference current.

[0107] Regarding the technical effects of Embodiment 2, based on Embodiment 1, Embodiment 2 achieves the following enhanced effects by adding an output current mirror structure and a capacitor compensation structure:

[0108] 1) Flexibility of the dual-output structure. The original Iref output is retained to maintain compatibility, while an Iref_out output with higher performance characteristics is added, which can meet the needs of different application scenarios in the system at the same time.

[0109] 2) Reduced output noise. The output filter capacitor effectively filters out high-frequency noise, providing a cleaner DC reference current and improving the signal-to-noise ratio of downstream circuits.

[0110] In summary, Embodiment 2 provides a comprehensively enhanced self-biased bandgap reference current circuit that not only retains all the advantages of the original design but also achieves significant improvements in output current characteristics, stability, and noise performance, forming a more complete solution that is more suitable for high-performance analog integrated circuit design.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A self-biased bandgap reference current circuit, comprising: The current mirror circuit includes multiple PMOS transistors, the gates of which are connected together and the sources are connected to a power supply. A differential amplifier circuit includes a differential pair transistor, a load transistor, and a bias transistor; A temperature compensation circuit, comprising at least two bipolar transistors and multiple resistors; A self-biased startup circuit includes at least one capacitor and at least one transistor; The self-biased startup circuit turns on the control transistor through capacitive coupling when the power supply is turned on, thereby starting the current mirror circuit and the differential amplifier circuit. After the circuit reaches the stable operating point, the control transistor automatically turns off. The differential amplifier circuit maintains the voltages of the two key nodes in the temperature compensation circuit equal, causing the bipolar transistor in the temperature compensation circuit to generate a voltage component proportional to temperature and an inversely proportional voltage component. These two voltage components with opposite temperature coefficients cancel each other out through a specific resistor ratio. The current mirror circuit replicates and outputs the temperature-compensated current, while utilizing the common-mode rejection characteristic of the differential amplifier circuit to improve the suppression capability of power supply fluctuations, thereby generating a reference current with high power supply rejection ratio and low temperature coefficient without the need for an external bias circuit.

2. The self-biased bandgap reference current circuit according to claim 1, characterized in that, The current mirror circuit includes first to fifth PMOS transistors (M12, M1, M0, M8, M7), the gates of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) and the drain of the second PMOS transistor (M1) are connected together, and the sources of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) are connected to the power supply; wherein, each of the first to fifth PMOS transistors (M12, M1, M0, M8, M7) has the same width-to-length ratio, and the total width-to-length ratio of PMOS transistors M12, M1, M8, and M7 is equal, for the purpose of realizing the current mirror function.

3. The self-biased bandgap reference current circuit according to claim 2, characterized in that, The differential amplifier circuit includes: The source of the differential pair transistors (M2, M3) is connected to the drain of the third PMOS transistor (M0); Load transistors (M5, M6), wherein the drain of M5 is connected to the drain of M2, the drain of M6 is connected to the drain of M3, and the gate of M5 is connected to the gate and drain of M6. The gate of the bias transistor (M4) is connected to the drain of M2 and the drain of M5. The sources of the load transistors (M5, M6) and the bias transistor (M4) are both grounded; the width-to-length ratio of the first transistor (M2) and the second transistor (M3) in the differential pair transistors is equal; the width-to-length ratio of the first load transistor (M5) and the second load transistor (M6) in the load transistors is equal, which is used to form a balanced differential amplifier structure.

4. The self-biased bandgap reference current circuit according to claim 3, characterized in that, It also includes a first capacitor (C0) and a first resistor (R0). One end of the first resistor (R0) is connected to the drain and gate of the second PMOS transistor (M1), and the other end is connected to the positive terminal of the first capacitor (C0) and the drain of the bias transistor (M4). The negative terminal of the first capacitor (C0) is connected to the drain of the first transistor (M2) in the differential pair transistor. The voltages of the two differential input nodes (A, B) of the differential amplifier circuit are equal when the circuit is operating stably. A high power supply rejection ratio is achieved through the differential amplifier structure. The drain current of the fourth PMOS transistor (M8) is equal to the drain current of the fifth PMOS transistor (M7).

5. The self-biased bandgap reference current circuit according to claim 2, characterized in that, The temperature compensation circuit includes: First bipolar transistor (Q1); Second bipolar transistor (Q0); The second to fifth resistors (R1, R2, R3, R4); Wherein, one end of the second resistor (R1) is connected to the emitter of the first bipolar transistor (Q1), and the other end of the second resistor (R1) is connected to the third resistor (R2), the gate of the first transistor (M2) in the differential pair transistor, and the drain of the fourth PMOS transistor (M8). One end of the fourth resistor (R3) is connected to the emitter of the second bipolar transistor (Q0), the gate of the second transistor (M3) in the differential pair transistor, the drain of the fifth PMOS transistor (M7), and the drain of the PMOS transistor (M9). The other end of the third resistor (R2) is connected to the base of the fourth resistor (R3), the fifth resistor (R4), and the first and second bipolar transistors (Q0, Q1); The collectors of the first and second bipolar transistors (Q0, Q1) and the other end of the fifth resistor (R4) are grounded; The third resistor (R2) and the fourth resistor (R3) have the same W / L value, forming a symmetrical structure for the temperature compensation circuit.

6. The self-biased bandgap reference current circuit according to claim 5, characterized in that, The ratio of the number of the first bipolar transistor (Q1) to the number of the second bipolar transistor (Q0) is 1:8; the ratio of the resistance of the second resistor (R1) to the resistance of the fourth resistor (R3) is 8:

1. By coordinating these two ratios, the output reference current does not change with temperature.

7. The self-biased bandgap reference current circuit according to claim 5, characterized in that, The self-biased startup circuit includes: The sixth NMOS transistor (M11) has its gate connected to the power supply and its source grounded. The second capacitor (C1) has its positive terminal connected to the power supply and its negative terminal connected to the drain of the sixth NMOS transistor (M11); The seventh NMOS transistor (M10) has its drain connected to the gate of the second PMOS transistor (M1), its source grounded, and its gate connected to the drain of the sixth NMOS transistor (M11). The gates of the eighth PMOS transistor (M13) and the ninth NMOS transistor (M14) are connected to the drain of the sixth NMOS transistor (M11); The tenth PMOS transistor (M9) has its source connected to the power supply. The gate of the tenth PMOS transistor (M9) is connected to the drain of the eighth PMOS transistor (M13) and the ninth NMOS transistor (M14). The drain of the tenth PMOS transistor (M9) is connected to one end of the fourth resistor (R3). During the circuit startup phase, the voltage across the second capacitor (C1) in the self-biased startup circuit cannot change abruptly, causing the seventh NMOS transistor (M10) to conduct and start the current mirror circuit. As the circuit reaches a stable operating point, the seventh NMOS transistor (M10) automatically turns off, achieving the self-start function.

8. The self-biased bandgap reference current circuit according to claim 5, characterized in that, The reference current generated by the temperature compensation circuit is ； in, The base-emitter voltage difference of the second bipolar transistor (Q0) The reference current is a thermal voltage, and R1 and R3 are the resistance values ​​of the second resistor (R1) and the fourth resistor (R3), respectively. The temperature stability of the reference current is achieved by canceling out the two components with opposite temperature coefficients.

9. The self-biased bandgap reference current circuit according to claim 8, characterized in that, The temperature dependence of the reference current satisfies: ； in, Let be the partial derivative of the thermal voltage VT with respect to temperature T. The base-emitter voltage difference of the second bipolar transistor (Q0) The partial derivative with respect to temperature T; the temperature coefficient of the reference current Iref is made zero by using this temperature partial derivative equation to ensure the stability of the reference current over a wide temperature range.

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