Indoor space automatic layout and rendering method and system based on design knowledge graph

Abstract

The application relates to the field of knowledge graph data processing, and discloses an indoor space automatic layout and rendering method and system based on a design knowledge graph, which comprises the following steps: maintaining an entity knowledge graph containing a variation path, and discretizing a continuous geometric space into an environment topology graph; performing node mapping based on subgraph isomorphism and resource topology handshake verification; in response to a mapping deadlock, triggering recursive topology rewriting along the variation path to reconstruct a query subgraph, and generating a configuration instruction; the application converts continuous geometric search into discrete graph isomorphism and attribute propagation, reduces the high-dimensional space layout calculation complexity, solves the deadlock problem under over-constrained conditions by using a recursive variation mechanism, and ensures the logical rigor and engineering compliance of the layout scheme.

Description

Technical Field

[0001] This invention relates to an automatic layout and rendering method and system for interior spaces based on design knowledge graphs, belonging to the field of knowledge graph data processing technology. Background Technology

[0002] Currently, existing automated technologies for interior space design typically employ parametric methods based on geometric constraints or template matching methods based on pre-defined rule bases. Geometric constraint solving relies on high-dimensional numerical calculations and entity collision detection in continuous Euclidean space, iteratively searching for solutions that satisfy size and position constraints. Template matching methods are based on rigid rule mapping of static database floor plan features. However, these technical approaches suffer from computational efficiency bottlenecks when faced with non-standard irregular spaces or real-world conditions with multiple complex constraints. Interior layout involves the optimization of combinations between multiple entities, and searching for the optimal solution in continuous geometric space is a combinatorial optimization problem with exponentially increasing computational complexity. As the number of spatial entities increases, relying solely on geometric calculations leads to a surge in computational power consumption and a decrease in convergence speed. Geometric solvers struggle to directly handle privacy-level and access logic constraints that are not geometrically semantic, resulting in geometrically collision-free but logically non-compliant calculation results. Simply increasing the size of the rule base leads to rule conflicts and deadlocks, and cannot adapt to dynamically changing spatial topologies.

[0003] This dual problem of computational efficiency and adaptability stems from the fact that existing technological approaches often overemphasize the geometric representation and visual rendering of physical space, while neglecting the effective abstraction and deduction of the deep logical semantics of space. For example, Chinese invention patent CN119091027B discloses a BIM-based method and system for simulating and displaying interior decoration. Although this solution integrates structured lighting simulation and texture mapping analysis technologies and attempts to assist in the display by calculating lighting coefficients through complex physical rendering equations, the core layout logic remains at a shallow computational level based on geometric distance (Zd, Zc) and collision detection. Essentially, it involves iterative searches based on visual posterior in a continuous space, lacking the ability to graphically represent implicit design knowledge such as privacy, accessibility, and compliance with engineering resources.

[0004] Therefore, the technical problem to be solved by this invention is how to break away from the dependence on geometric calculations, process spatial semantic constraints through discretized data structures, and realize a deterministic and compliant layout generation automatic processing mechanism under limited computing resources. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: An automatic layout and rendering method for interior space based on design knowledge graph, comprising the following steps:

[0006] Maintain an entity knowledge graph in a graph database. The entity knowledge graph contains entity nodes connected by logical edges. Entity nodes define topological interface attributes and resource request tag sets. Logical edges define relative spatial constraint parameters between entities and unidirectional mutation paths pointing to degraded replacement nodes.

[0007] In response to the input continuous geometric space data, spatial boundary features are extracted and the continuous geometric space data is discretized into an environmental topology map composed of multiple spatial slot nodes. The spatial slot nodes are written with capacity attribute data describing their geometric carrying capacity and a set of resource supply labels describing the physical resource supply status.

[0008] Perform a primary mapping based on the maximum common subgraph isomorphism, construct the target entity nodes to be processed in the entity knowledge graph into a query subgraph, and search the environment topology graph for a set of candidate slots that are topologically isomorphic to the query subgraph and satisfy the capacity attribute data.

[0009] Perform resource topology handshake verification on the candidate slot set, perform inclusion logic operation on the resource request tag set of the target entity node and the resource supply tag set of the spatial slot node, and dynamically insert relay nodes into the query subgraph to reconstruct the connection relationship based on the compensation logic in the entity knowledge graph when the operation result is false.

[0010] In response to a deadlock state caused by failure of primary mapping or resource topology handshake verification, a recursive topology rewriting along a one-way mutation path is triggered, replacing conflicting nodes in the query subgraph with degraded replacement nodes and updating the topology interface attributes. The rewritten mutated query subgraph is then used to re-execute the isomorphic search until the ownership mapping relationship is established.

[0011] Based on the established attribution mapping relationship and the relative spatial constraint parameters of logical edges, the local coordinate transformation matrix of each node is calculated and structured configuration instructions are generated.

[0012] Preferably, the step of generating the environmental topology graph further includes establishing discrete mapping logic for non-geometric field attributes, constructing an undirected connected graph with the spatial slot node corresponding to the entry position of the continuous geometric spatial data as the root node; traversing the undirected connected graph and calculating the betweenness centrality value and the shortest path hop count relative to the root node for each spatial slot node; mapping the betweenness centrality value to accessibility attribute data, mapping the shortest path hop count to privacy attribute data, and writing the accessibility attribute data and privacy attribute data to the corresponding spatial slot node; correspondingly, performing the primary mapping based on the maximum common subgraph isomorphism includes: verifying whether the preset logical requirements of the target entity node and the accessibility attribute data or privacy attribute data of the spatial slot node satisfy the preset logical inclusion relationship.

[0013] Preferably, in the step of performing resource topology handshake verification, the inclusion logic operation follows the following set determination rule: extract the resource request tag set of the target entity node. The resource supply tag set corresponding to the slot node in the candidate slot set If the result of set operations If the result is true, the resource topology handshake verification is considered successful; if the set operation result is false, the difference set is identified. The system identifies missing resource items in the query subgraph and retrieves compensation relay nodes from the entity knowledge graph that are capable of providing missing resource items. When a compensation relay node successfully inserts into the query subgraph and establishes a new logical connection, the resource topology handshake verification is considered successful.

[0014] Preferably, the logical edges include a necessity weight attribute, and the recursive topology rewriting step also includes weighted pruning logic based on the minimum spanning tree. In response to the query subgraph not establishing a valid belonging mapping relationship in the environment topology graph, a weighted connected graph is constructed based on the query subgraph; reverse minimum spanning tree pruning is performed on the weighted connected graph according to the necessity weight attribute, prioritizing disconnecting the logical edge with the lowest weight or removing the entity node with the lowest weight to generate a corrected query subgraph; the subgraph isomorphic search is re-executed using the corrected query subgraph, and the pruned logical edges or entity nodes are marked as residual items to be processed and written into the structured configuration instructions.

[0015] Preferably, the construction steps of the environment topology graph also include virtual slot derivation logic triggered by the main anchor point, defining the master-slave dependency relationship between the parent node and the subordinate child node in the entity knowledge graph; in response to the parent node being successfully mapped to the first spatial slot node in the environment topology graph, using the coordinate data of the first spatial slot node as a reference and combining the relative spatial constraint parameters in the logical edge, dynamically creating a set of virtual derived slot nodes in the environment topology graph; directly mapping the subordinate child node to the virtual derived slot node, and locking the logical connection relationship between the parent node and the subordinate child node, no longer performing a global isomorphic search on the subordinate child node.

[0016] Preferably, the unidirectional mutation path defines a degradation replacement relationship from the source node to the target node. The degradation replacement relationship includes the reduction of entity size, the deletion of functional components, or the simplification of the topological connection structure. Recursive topological rewriting is performed until a belonging mapping relationship is established or the traversal depth of the unidirectional mutation path reaches a preset threshold.

[0017] Preferably, the step of generating the environmental topology map further includes attribute injection based on environmental potential energy. In response to the window or noise source location features in the continuous geometric spatial data, the environmental potential energy value of each region in the space is calculated based on a preset distance decay function. The environmental potential energy value is quantified into a hierarchical label, and the hierarchical label is written as an environmental attribute into the data structure of the corresponding spatial slot node. Accordingly, the entity nodes in the entity knowledge graph contain environmental demand attributes, and the primary mapping step includes verifying the matching degree between the environmental attributes of the spatial slot node and the environmental demand attributes of the target entity node.

[0018] Preferably, the entity knowledge graph adopts a two-layer heterogeneous graph architecture. The bottom layer is an environmental topology graph composed of spatial slot nodes, which is used to represent the discretized attributes of physical space. The upper layer is a logical entity graph composed of entity nodes, which is used to encapsulate the co-dependent relationships between design rules and entities. The attribution mapping relationship is implemented by embedding the nodes in the logical entity graph into the corresponding nodes in the environmental topology graph.

[0019] Preferably, the structured configuration instructions are JSON format data files containing unique object identifiers, relative transformation matrices, and material references. The data files are used to drive the rendering engine to generate a 3D scene. The method also includes deadlock detection and rollback steps. When the traversal depth in the recursive topology rewriting step reaches a preset threshold and no ownership mapping relationship is established, it is determined to be an unsolvable deadlock state. A state rollback operation is performed to restore the previous successful primary mapping state, and the conflict area that caused the unsolvable deadlock state is marked, and an exception report containing conflict area information is generated.

[0020] An automatic layout and rendering system for interior spaces based on a design knowledge graph, comprising:

[0021] The graph maintenance module is used to maintain entity knowledge graphs in the graph database. The entity knowledge graph contains entity nodes connected by logical edges. Entity nodes define topological interface attributes and resource request tag sets. Logical edges define relative spatial constraint parameters between entities and unidirectional mutation paths pointing to degraded replacement nodes.

[0022] The spatial discretization module is used to extract spatial boundary features in response to the input continuous geometric spatial data and discretize the continuous geometric spatial data into an environmental topology map composed of multiple spatial slot nodes. The spatial slot nodes are written with capacity attribute data describing geometric carrying capacity and a set of resource supply tags describing physical resource supply status.

[0023] The isomorphic mapping module is used to perform primary mapping based on the maximum common subgraph isomorphism, constructing the target entity nodes to be processed in the entity knowledge graph into a query subgraph, and searching in the environment topology graph for a set of candidate slots that are topologically isomorphic to the query subgraph and satisfy the capacity attribute data.

[0024] The resource handshake verification module is used to perform resource topology handshake verification on the candidate slot set, perform inclusion logic operation on the resource request tag set of the target entity node and the resource supply tag set of the space slot node, and dynamically insert relay nodes into the query subgraph to reconstruct the connection relationship based on the compensation logic in the entity knowledge graph when the operation result is false.

[0025] The recursive topology rewriting module is used to respond to deadlock caused by failure of primary mapping or resource topology handshake verification. It triggers recursive topology rewriting along a one-way mutation path, replaces conflicting nodes in the query subgraph with degraded replacement nodes and updates the topology interface attributes. It then uses the rewritten mutated query subgraph to re-execute isomorphic search until the ownership mapping relationship is established.

[0026] The configuration instruction generation module is used to calculate the local coordinate transformation matrix of each node and generate structured configuration instructions based on the established attribution mapping relationship and the relative spatial constraint parameters of logical edges.

[0027] Compared with the prior art, the beneficial effects of the present invention are:

[0028] 1. In the automatic layout and rendering of indoor spaces, a discrete mapping mechanism from physical space features to environmental topology is constructed. Design rules are encapsulated as entity knowledge graph interface definitions and logical edges. The geometric search and collision detection based on continuous Euclidean space are transformed into a problem of graph database subgraph isomorphism and attribute propagation. The discrete attributes of spatial slot nodes are used to directly lock the entity's affiliation. The relative position is triggered by constant-level deduction through logical edge dependencies, avoiding nondeterministic iterative optimization and backtracking calculations in high-dimensional geometric spaces. This data processing paradigm shift enables the generation of layout schemes in milliseconds based on graph topology without relying on expensive physical simulation computing power when processing large-scale complex house types or non-standard irregular spaces. Based on deterministic graph interface matching logic, common logical errors in geometric calculations such as object overlap and functional deviation are eliminated from the bottom layer of the data structure, ensuring the stability of the generated scheme according to engineering specifications.

[0029] 2. Graph centrality algorithms and potential energy discretization mapping enable the digitization of physical field semantics. The construction of the environmental topology graph introduces a mechanism based on betweenness centrality calculation and shortest path hop count analysis of undirected connected graphs. Combined with a preset potential energy decay function, continuous physical field information such as illumination and noise, as well as implicit spatial semantics of privacy and accessibility, are translated into discretized attribute labels for slot nodes. The habitability and functional attributes of the space are directly quantified through graph theory algorithms, without the need to run high-performance graphics rendering algorithms such as ray tracing or line-of-sight analysis. The layout combinations that meet the environmental potential energy constraints are automatically filtered during the graph matching stage, solving the technical problem of traditional geometric layout methods in handling non-geometric environmental constraints at low cost. Through multi-dimensional attribute Boolean logic operations, a direct data mapping between physical environmental characteristics and design logic requirements is established, ensuring that the layout results comply with both physical comfort and functional logic.

[0030] 3. The weighted logical pruning and ontology recursive mutation mechanism is based on the adaptive solution capability of graph reasoning. It establishes necessary weighted logical connections and defines degradation replacement path ontology mutation edges in the entity knowledge graph. It constructs an automatic resolution mechanism for graph matching deadlock. When faced with space constraints or demand conflicts, it performs weighted edge dynamic pruning or triggers node recursive ontology replacement along the mutation path based on the minimum spanning tree algorithm. It automatically reconstructs the topology of the query subgraph, transforming the value trade-off and scheme adjustment logic of designers with limited resources into a graph algorithm weight optimization and path walking process. It ensures that the system does not fail due to the inability to find a fully matching subgraph under extreme house types or strict requirements. It outputs a solution that retains the core design value and has a complete and effective topology structure, improving the usability and generalization ability of the automatic layout system in real and complex scenarios. Attached Figure Description

[0031] Figure 1 This is a flowchart of the automatic layout and rendering method for indoor space that combines a recursive topology rewriting mechanism according to the present invention.

[0032] Figure 2 This is a comparison chart of the computation time of the method of this invention and the simulated annealing algorithm under different spatial entity sizes;

[0033] Figure 3 This is a logical architecture diagram of the automatic layout and rendering system for indoor spaces based on design knowledge graphs, as described in this invention. Detailed Implementation

[0034] The present invention will be described in detail below with reference to specific embodiments. It should be noted that the following embodiments are only used to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0035] This embodiment discloses an automatic layout and rendering method and system for interior spaces based on a design knowledge graph, including four core processing stages: entity knowledge graph maintenance, environmental topology graph generation, slot assignment matching, and rendering command generation. In the entity knowledge graph construction stage, the system maintains the entity knowledge graph in a graph database, containing entity nodes connected by logical edges. Each entity node defines a topology interface attribute, specifying the port type, normal direction, and dimensional tolerance for physical connections within the space. Entity nodes also define a set of resource request tags. This set enumerates the types of physical resources required for the normal operation of entities, such as power interfaces, network interfaces, or water supply and drainage interfaces. The logical edges connecting each entity node define the relative spatial constraint parameters between entities, including relative distance intervals, relative angles, and alignment methods. The logical edges also define unidirectional mutation paths pointing to degraded replacement nodes. These paths specify the sequence of replacement nodes used to replace the current node when it cannot meet the spatial constraints, either by reducing its size or simplifying its function. The logical edges also contain necessity weight attributes to guide the priority of constraint relaxation in over-constrained states. In the environmental topology generation stage, the system responds to the input continuous geometric spatial data, extracting the spatial boundary features of walls, doors, windows, and openings. The system discretizes the continuous geometric spatial data into an environmental topology consisting of multiple spatial slot nodes according to the preset sampling precision. The spatial slot nodes are written with capacity attribute data describing geometric bearing capacity and a set of resource supply labels describing the physical resource supply status. In the discretization construction of the environmental topology map, the geometric carrying capacity attribute data of spatial slot nodes is not defined solely by the area dimension, but is determined through shape compactness metric screening. The physical area of ​​each independent candidate region formed by the aggregation of continuous geometric spatial discretization grids is calculated. and geometric perimeter According to the formula Solve the region shape compactness index The database is used to access a pre-stored standard furniture model library. The distribution data of the aspect ratio of the minimum bounding rectangle of the entity to be laid out is statistically analyzed, and the compactness value corresponding to the 5th percentile of this distribution is set as the geometric validity threshold. When generating the final environment topology graph, the inequality will be satisfied. Region mapping is a spatial slot node with capacity attribute. During the map construction stage, regions that meet the physical area requirements but cannot accommodate entities due to excessively narrow or distorted geometric shapes are automatically removed.

[0036] To process implicit spatial semantics, the system establishes a discrete mapping logic for non-geometric field attributes. The system uses the spatial slot node corresponding to the entry point of the continuous geometric spatial data as the root node, constructing an undirected connected graph based on spatial adjacency relationships. The system traverses this undirected connected graph, using graph theory algorithms to calculate the betweenness centrality value and the shortest path hop count relative to the root node for each spatial slot node. The system maps the betweenness centrality value to accessibility attribute data, representing the transportation hub status of the area; and maps the shortest path hop count to privacy attribute data, representing the privacy level of the area. These two attribute data are written to the corresponding spatial slot nodes. Furthermore, in response to the window or noise source location characteristics in the continuous geometric spatial data, the system calculates the spatial area based on a preset distance decay function. The system calculates the environmental potential energy value of the domain and quantifies it into hierarchical labels, which are then written into the data structure of the corresponding spatial slot node as environmental attributes. During the initial mapping phase based on the maximum common subgraph isomorphism, the system parses the design requirements and constructs a query subgraph from the target entity nodes in the entity knowledge graph. The system performs isomorphic search in the environmental topology graph to find a set of candidate slots that are topologically isomorphic to the query subgraph and satisfy the capacity attribute data. During this process, the system verifies whether the preset logical requirements of the target entity nodes and the accessibility, privacy, and environmental attributes of the spatial slot nodes satisfy the preset logical inclusion relationship. To ensure project compliance, the system performs resource topology handshake verification on the candidate slot set and extracts the resource request label set of the target entity nodes. The resource supply tag set corresponding to the slot node in the candidate slot set In the resource topology handshake verification logic operation of the candidate slot set, the inclusion determination of the resource supply tag set follows a physical port concurrent occupancy locking mechanism. Each resource supply node in the environment topology graph is initialized with a fixed maximum load capacity integer. Integers are directly extracted from the physical interface quantity attribute of the electromechanical facility elements corresponding to the input geometric space data, such as the standard two-hole wall socket. Single-port network panel corresponding When the graph matching engine performs resource supply and demand verification, it maintains and reads the current occupancy counter of each resource supply node in real time. When the target entity's resource request type matches the supply tag and meets the real-time constraints... When the output verification passes the Boolean truth value, it is synchronously triggered. The update operation internalizes the physical hardware concurrent access limit as a graph matching boundary condition, ensuring that the generated layout scheme has logical connectivity while strictly complying with the physical load-bearing limits of the on-site electromechanical facilities. The system performs a set inclusion logical operation, and if the set operation result... If the result is true, the resource topology handshake verification is considered successful; if the result is false, the system identifies the difference set. The system identifies the missing resource item in the query subgraph and retrieves a compensation relay node from the entity knowledge graph that is capable of providing the missing resource item, such as a power strip or extension cord node. When the compensation relay node is successfully inserted into the query subgraph and a new logical connection is established, the system determines that the resource topology handshake verification has passed.

[0037] To address deadlock caused by over-constraints, the system triggers a recursive topology rewrite along a unidirectional mutation path. In response to a failure in the primary mapping or resource topology handshake verification, the system locks conflicting nodes in the query subgraph. Following the unidirectional mutation path, the system replaces these conflicting nodes with degraded replacement nodes and simultaneously updates the topology interface attributes. Degraded replacement relationships involve reducing entity size, removing functional components, or simplifying the topology connection structure. The system re-executes isomorphic search using the rewritten mutated query subgraph. This process is recursive until a ownership mapping relationship is established or the traversal depth of the unidirectional mutation path reaches a preset threshold. If the problem remains unresolved after reaching the threshold, the system determines it as a deadlock and processes it using weighted pruning logic based on minimum spanning trees. The system constructs a weighted connected graph based on the query subgraph and performs reverse minimum spanning tree pruning based on necessity weight attributes, prioritizing disconnecting the logical edge with the lowest weight or removing the entity node with the lowest weight. A corrected query subgraph is generated for re-searching, and pruned items are marked as pending residual items. For island layout scenarios, the system executes virtual slot derivation logic triggered by the main anchor point, and the system identifies entity knowledge graphs. The master-slave dependency relationship between parent nodes and subordinate child nodes is established in response to the successful mapping of the parent node to the first spatial slot node in the environment topology graph. Using the coordinate data of the first spatial slot node as a reference, and combining the relative spatial constraint parameters in the logical edges, the system dynamically creates a set of virtual derived slot nodes in the environment topology graph. The system directly maps subordinate child nodes to these virtual derived slot nodes and locks the logical connection relationship between the parent node and subordinate child nodes, no longer performing a global isomorphic search on the subordinate child nodes. During the configuration instruction generation phase, based on the established attribution mapping relationship and the relative spatial constraint parameters of the logical edges, the system calculates the local coordinate transformation matrix of each node. The system generates a structured configuration instruction containing a unique object identifier, a relative transformation matrix, and material references. This instruction is typically a JSON data file used to drive the rendering engine to generate a 3D scene. If the traversal depth in the recursive topology rewriting step reaches a preset threshold without establishing an attribution mapping relationship, the system determines it to be in an unsolvable deadlock state, performs a state rollback operation to restore the previous successful primary mapping state, and generates an exception report containing conflict area information.

[0038] Example 1: In a renovation project of an irregularly shaped old residential bedroom (6 square meters) with a load-bearing wall corner, there was a serious over-constraint layout challenge. The user required the simultaneous placement of a 1.5-meter-wide double bed, a standard-sized bedside table, a desk, and a wardrobe within this limited space. The room had only a few fixed-location power outlets. Conventional rectangular layout algorithms could not accommodate all furniture while avoiding the load-bearing wall corner, and were highly likely to render desks and other electrical appliances unusable due to their distance from outlets, resulting in a double failure of the layout scheme at both the geometric and engineering levels. To address this situation, the system executed an automatic layout process based on a design knowledge graph. The system extracted the spatial features of the room's walls, doors, windows, and power outlets, discretized them into an environmental topology graph composed of multiple spatial slot nodes, and mapped the power outlet locations to resource supply tags for the corresponding slot nodes. The system constructs a query subgraph containing all target furniture entities and attempts to search for candidate slots that meet geometric constraints during the initial mapping stage. Due to the rigidity of the physical dimensions of the space, a standard-sized double bed and a bedside table cannot coexist while retaining the minimum passage width, causing the initial mapping to fail and triggering a deadlock state.

[0039] In response to this deadlock, the system activates a recursive topology rewriting mechanism, locking the standard-sized bedside table node causing the geometric conflict. Based on a predefined unidirectional mutation path in the entity knowledge graph, it replaces the bedside table node with a smaller, floating side table node, and simultaneously updates the topology interface attributes. This ontology-based degradation operation eliminates hard conflicts in the geometric dimension, allowing the reconstructed mutation query subgraph to be successfully mapped to the environment topology graph. While establishing the geometric mapping, the system performs a resource topology handshake check. The system detects that the area mapped to the desk node lacks power resources, i.e., the desk node's resource request tag. Resource supply tags not included in the corresponding slot node In the process, the inclusion logic operation result is false. To resolve this engineering contradiction, the system automatically retrieves the entity knowledge graph and dynamically inserts a power extension line compensation relay node between the desk node and the nearest power socket node, thereby reconstructing the logical connection relationship and enabling the resource topology handshake verification to pass. Finally, the system outputs a layout scheme that takes into account both functional requirements and engineering specifications. This scheme uses the dynamic reconstruction capability of the discrete graph to resolve spatial geometric conflicts and solves the electromechanical resource gap through logical deduction of resource attributes, achieving an effective layout in extremely constrained spaces.

[0040] Example 2: To quantitatively verify the effectiveness and stability of the present invention under complex working conditions, this example constructs a highly realistic automated test platform for interior design based on the Plan5D-G dataset. 500 real-world apartment layout samples containing irregular spaces and multiple constraint conflicts are selected and run on a workstation configured with an Intel Core i9-10900K processor, 64GB DDR4 memory, and an NVIDIA RTX 3080 graphics card. The experimental design includes a multi-dimensional control system with gradient pressure. Control group A uses a traditional geometric constraint solving algorithm based on simulated annealing; control group B uses an expert system matching method based on static rule templates; control group C (partially missing) uses the graph mapping architecture of the present invention but removes the recursive topology rewriting module; the present invention sample group uses a complete technical solution including recursive topology rewriting and resource topology handshake verification. The core monitoring indicators are set as layout generation success rate and average computation time. The experiment is conducted in a standard rectangular room. Under normal operating conditions, the power of each component exceeded 98%. The system gradually increased the irregularity of the apartment layout and the density of constraint conflicts, entering the extreme test stage. As the complexity of the problem increased, the success rate of control group B dropped rapidly, indicating that the static template could not adapt to topological mutations. Although control group A maintained a certain success rate, the computation time increased exponentially and it was prone to getting trapped in local optima. When facing over-constrained operating conditions, the success rate of control group C was lower than that of the sample group of this invention, confirming the key role of the recursive mutation mechanism in handling deadlock. The sample group of this invention showed stability under extreme operating conditions, with the success rate remaining at a high level and the average time only increasing slightly. Key intermediate data showed that the system triggered an average of 2.3 recursive mutation operations when encountering deadlock, resolving the vast majority of geometric conflicts. In addition, for a specific test set containing electromechanical resource gaps, the sample group of this invention achieved a high resource conflict resolution rate through a resource topology handshake mechanism, while control groups A and B had a large number of electromechanical resource conflicts (see Table 1).

[0041] Table 1: Specific performance data under extreme overconstraint conditions;

[0042]

[0043] The above data shows that the present invention, through graph mutation and resource handshake mechanism, has adaptive solution capability and engineering stability in dealing with extreme problems such as irregular spaces and over-constrained deadlock.

[0044] Example 3: This example combines Figures 1 to 3 This section describes a method and system for automatic layout and rendering of interior spaces based on design knowledge graphs, such as... Figure 1As shown, in response to continuous geometric spatial data containing boundary features such as walls, doors, windows, and holes, the spatial discretization module generates an environmental topology map, calculates capacity attributes, and injects potential energy. The map then enters the isomorphic mapping module, which interacts with the graph maintenance module to obtain the topology interface. It performs a primary mapping search based on the maximum common subgraph isomorphism. The generated candidate set enters the resource handshake verification module. During this process, the graph maintenance module provides compensation logic to support resource supply and demand inclusion calculations and dynamic insertion of relay nodes. After verification, the logic judgment stage begins. If the verification passes and there is no deadlock, the configuration instruction generation module calculates the local coordinate transformation matrix and generates structured configuration instructions in JSON format. The final output is instruction data used to drive the rendering engine to generate a 3D scene. If the judgment result is negative, indicating a deadlock or conflict, the recursive topology rewriting module is triggered. This module, based on the mutation path retrieved by the graph maintenance module, replaces nodes along the unidirectional mutation path and updates the topology interface to reconstruct the query subgraph. The reconstructed subgraph is then fed back to the isomorphic mapping module to re-execute the search until a closed-loop logic is formed.

[0045] like Figure 2 As shown, the horizontal axis represents the spatial scale, specifically quantified by the number of entities, covering four test nodes: small space (5 entities), medium space (15 entities), large space (30 entities), and ultra-large space (50 entities). The vertical axis represents the computation time in milliseconds (ms), displayed on a logarithmic scale. The figure contains two data sequences: the dashed line represents the simulated annealing geometry solution method, and the solid line represents the method of this invention. Observing the data trend, it can be seen that as the spatial scale increases from 5 entities to 50 entities, the computation time of the simulated annealing geometry solution increases exponentially, surging from 100ms to over 10,000ms. In contrast, the computation time of the method of this invention increases gradually, remaining in a lower range, and even in the ultra-large space condition, the computation time is still below 300ms. Figure 3 As shown, the user interaction layer includes designer terminal devices and front-end interactive applications, responsible for inputting spatial scanning data and communicating with the core layer via HTTPS / WebSocket protocol, as well as receiving 3D rendering scenes. The core computing service layer integrates spatial discretization services, isomorphic mapping engines, resource handshake verification services, and configuration instruction generation services, and embeds a recursive topology rewriting mechanism to handle deadlock detection and degradation along mutation paths. This layer interacts bidirectionally with the knowledge data layer through the isomorphic mapping engine and rewriting mechanism. The knowledge data layer consists of a graph database cluster, internally storing entity knowledge graphs, specifically including logical edge definitions, unidirectional mutation paths, and resource request tag data. This layer provides data support to the core layer and supports subgraph reconstruction when rewriting is triggered. All layers work together to achieve fully automated processing from data input to instruction generation.

[0046] Example 4: To address the potential black-box problems of algorithm paths and parameter thresholds in complex irregular spaces and under dynamic constraints, this example provides an adaptive parameter tuning and path decision-making mechanism based on dynamic feedback. By embedding pseudocode-level operation flow descriptions and constructing parameter setting principles and adaptive logic, the system ensures decision transparency and reproducibility in non-deterministic environments. For the core path decision in the layout algorithm, the system embeds a clear input-processing-output operation flow. In the initial mapping stage, the system no longer relies on fuzzy heuristic search but performs deterministic priority ranking based on topological centrality. The system calculates the topological importance of all entities to be laid out. This value is defined as the weighted sum of the degree and betweenness centrality of an entity node in the logical entity graph, based on the system's... The entities to be laid out are sorted in descending order to form a deterministic layout sequence. For each entity in the sequence, the system performs a candidate slot search based on the maximum common subgraph isomorphism in the environment topology graph. If the search result is empty, the system triggers a backtracking mechanism based on the minimum conflict set to identify and remove low-priority entities that cause conflicts, rather than randomly retrying. This ensures that each step of the layout decision has a clear algorithmic basis and eliminates the path black box caused by randomness.

[0047] Secondly, addressing the parameter / threshold black box problem, this embodiment constructs parameter adaptive setting logic based on environmental complexity, using the mutation depth threshold in recursive topology rewriting. For example, this parameter is no longer set to a fixed empirical value, but rather based on the complexity of the environmental topology graph. Perform dynamic calculations. Defined as the ratio of the number of nodes to the number of edges in the environmental topology graph, with a system-preset baseline threshold. And according to the formula Calculate the current mutation depth threshold, where The system automatically increases the mutation depth threshold as a preset adjustment coefficient when the environmental complexity is high, providing greater solution space search capability; conversely, it lowers the threshold to reduce computational overhead. This mechanism is not only based on the system's adaptive capability under different operating conditions, but also elevates parameter settings from empirical values ​​to principle-driven deterministic logic through explicit calculation formulas. Finally, to ensure transparency of the model's working mechanism, the system introduces a three-stage lifecycle explanation. In the model initialization stage, the system explicitly loads the pre-trained entity knowledge graph and environmental feature extractor. In the model running stage, the system monitors the state changes during the layout generation process in real time, including the current constraint satisfaction rate, the number of resource conflicts, and the size of the remaining solution space. Once a deadlock trend is detected, i.e., no effective solution is generated after several consecutive iterations, the system triggers the aforementioned adaptive parameter tuning or backtracking mechanism. In the model termination stage, the system outputs the final layout scheme and detailed decision logs, including entity selection, slot matching results, and mutation operation records for each step. This transparent management throughout the entire lifecycle ensures the traceability and interpretability of system behavior, avoiding the trust crisis caused by the model black box.

[0048] Example 5: To construct an entity knowledge graph with deterministic logic and eliminate the subjectivity of parameter setting, the system performs an offline parameter calibration procedure based on large-scale synthetic samples before deployment. The system loads a training sample set containing multi-dimensional spatial constraints and uses the Monte Carlo tree search algorithm to perform iterative layout solving. During this process, the system records the frequency statistical distribution of successful solutions resulting from the disconnection of specific logical edges or node replacement operations. Based on this statistical result, the system quantifies and sets the necessity weight attribute of logical edges. Edges that can effectively resolve deadlocks by frequently disconnecting are marked with low weight. Simultaneously, the system establishes a unidirectional mutation path based on the functional similarity vector space analysis of entity nodes. When the functional similarity between the target node and the source node exceeds a safety threshold... Furthermore, mutation connections are only established when the space occupancy reduction rate meets the preset efficiency standard, so that the setting of the graph topology and parameter weights is based on the objective solution probability distribution.

[0049] For accurate mapping of non-geometric field properties, the system executes the on-site environmental benchmark calibration procedure during the initialization phase. The system sets the geometric centroid of the space to be laid out as the calibration zero point, and virtually sets a known intensity at the window or noise source location. Using a standard signal source, the system samples the field intensity at multiple discrete grid points in space to obtain measured attenuation curves. By fitting the measured values ​​to the theoretical propagation model using the least squares method, the system calculates the distance attenuation coefficient applicable to the current physical scenario. and environmental potential energy gain factor These calibrated parameters are written into the property configuration file of the space slot node, enabling the environmental labels stored in the node to... The layout generation stage can strictly reflect the physical field distribution characteristics of the site.

[0050] Example 6: To resolve the trade-off between search efficiency and convergence of the recursive topology rewriting mechanism under different problem scales, this example constructs a set of dynamic search boundary adaptive constraint procedures based on problem scale. The system quantifies the complexity coefficient of the current layout task by parsing the input environment topology graph and query subgraph. This coefficient is defined as the product of the number of slot nodes in the environmental space and the number of entity nodes to be deployed, and is used to characterize the theoretical size of the solution space. The system is based on a linear mapping function. Calculate and lock the maximum recursive search depth threshold for the current task in real time. ,in and As a preset adjustment constant, during the recursive search process, once the current search depth reaches this threshold and no valid belonging mapping relationship is established, the system immediately determines that the current search path is an invalid path and forcibly terminates the recursion, activating the weighted pruning logic based on the minimum spanning tree, ensuring that the system can automatically limit the depth of invalid search when dealing with large-scale or extreme over-constraint problems.

[0051] To address the geometric data quality issues in the environmental topology map generation process, the system incorporates a standardized geometric preprocessing and accuracy calibration procedure before the discretization step. The system performs vector closure checks on the input continuous geometric space data and calculates the gap value between disconnected endpoints using the Euclidean distance formula. If this gap value is less than a preset tolerance threshold... The system performs endpoint merging to construct a closed physical boundary. It retrieves the minimum bounding box size of all target entity nodes to be processed in the entity knowledge graph, extracts the minimum value as a benchmark, and sets the discretization sampling step size based on a predetermined multiple of this benchmark value, such as 0.5 times. This ensures that the generated spatial slot nodes can effectively filter out meaningless geometric noise while having the capacity to support the minimum physical entity.

[0052] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An indoor space automatic layout and rendering method based on a design knowledge graph, characterized in that, The method comprises the following steps: maintaining an entity knowledge graph in a graph database, the entity knowledge graph comprising entity nodes connected by logical edges, the entity nodes being defined with topology interface attributes and a set of resource request tags, the logical edges being defined with relative spatial constraint parameters between entities and a one-way variation path pointing to a degraded substitute node; in response to input continuous geometric spatial data, extracting spatial boundary features and discretizing the continuous geometric spatial data into an environmental topology graph composed of a plurality of spatial slot nodes, the spatial slot nodes being written with capacity attribute data describing their geometric carrying capacity and a set of resource supply tags describing the physical resource supply state; performing a primary mapping based on maximum common subgraph isomorphism, constructing a target entity node to be processed in the entity knowledge graph into a query subgraph, and searching for a candidate slot set in the environmental topology graph that is topologically isomorphic to the query subgraph and meets the capacity attribute data; performing resource topology handshake verification on the candidate slot set, performing an inclusive logical operation on the resource request tag set of the target entity node and the resource supply tag set of the spatial slot node, and when the operation result is false, dynamically inserting a relay node into the query subgraph based on compensation logic in the entity knowledge graph to reconstruct the connection relationship; in response to a deadlock state caused by failure of the primary mapping or the resource topology handshake verification, triggering recursive topology rewriting along the one-way variation path, replacing conflict nodes in the query subgraph with degraded substitute nodes and updating the topology interface attributes, and re-executing isomorphic search using the rewritten variation query subgraph until a home mapping relationship is established; based on the established home mapping relationship and the relative spatial constraint parameters of the logical edges, calculating the local coordinate transformation matrix of each node and generating a structured configuration instruction.

2. The indoor space automatic layout and rendering method based on a design knowledge graph according to claim 1, characterized in that, The step of generating the environmental topology graph further comprises establishing discrete mapping logic for non-geometric field attributes, taking a spatial slot node corresponding to an entry position of the continuous geometric spatial data as a root node to construct an undirected connected graph; traversing the undirected connected graph and calculating the betweenness centrality value of each spatial slot node and the shortest path hop count relative to the root node; mapping the betweenness centrality value to accessibility attribute data and the shortest path hop count to privacy attribute data, and writing the accessibility attribute data and the privacy attribute data into the corresponding spatial slot node; Correspondingly, performing the primary mapping based on maximum common subgraph isomorphism comprises verifying whether the preset logical requirements of the target entity node and the accessibility attribute data or the privacy attribute data of the spatial slot node meet the preset logical inclusion relationship.

3. The indoor space automatic layout and rendering method based on a design knowledge graph according to claim 1, characterized in that, In the step of performing the resource topology handshake verification, the inclusive logical operation follows the following set determination rule: extracting the resource request tag set of the target entity node and the resource supply tag set of the corresponding slot node in the candidate slot set ; if the set operation result is true, it is determined that the resource topology handshake verification is passed; if the set operation result is false, the missing resource item in the difference set is identified, and a compensation relay node with the ability to provide the missing resource item in the entity knowledge graph is searched; when the compensation relay node successfully inserts the query subgraph and establishes a new logical connection, it is determined that the resource topology handshake verification is passed.

4. The indoor space automatic layout and rendering method based on a design knowledge graph according to claim 1, characterized in that, The logical edge contains a necessity weight attribute, and the recursive topology rewriting step further comprises a weighted pruning logic based on a minimum spanning tree, in response to the query subgraph not establishing an effective home mapping relationship in the environmental topology graph, constructing a weighted connected graph based on the query subgraph; performing reverse minimum spanning tree pruning on the weighted connected graph according to the necessity weight attribute, preferentially disconnecting the logical edge with the lowest weight or removing the entity node with the lowest weight to generate a modified query subgraph; re-executing subgraph isomorphism search using the modified query subgraph, and marking the pruned logical edge or entity node as a to-be-processed residual item and writing it into the structured configuration instruction.

5. The indoor space automatic layout and rendering method based on a design knowledge graph according to claim 1, characterized in that, The construction step of the environment topology map further includes virtual slot derivation logic triggered based on the master anchor point, and a master-slave dependency relationship between a parent node and a subordinate node is defined in the entity knowledge graph; In response to successful mapping of the parent node to the first spatial slot node in the environment topology map, a group of virtual derived slot nodes is dynamically created in the environment topology map based on the coordinate data of the first spatial slot node and in combination with the relative spatial constraint parameters in the logical edge; The subordinate node is directly mapped to the virtual derived slot node, and the logical connection relationship between the parent node and the subordinate node is locked, and the global isomorphic search is no longer performed on the subordinate node.

6. The indoor space automatic layout and rendering method based on a design knowledge graph according to claim 1, characterized in that, The one-way variant path defines a degradation replacement relationship from the source node to the target node, and the degradation replacement relationship includes reduction of entity size, reduction or simplification of functional components, or simplification of topology connection structure; the recursive topology rewriting is executed until the ownership mapping relationship is established or the traversal depth of the one-way variant path reaches a preset threshold.

7. The indoor space automatic layout and rendering method based on a design knowledge graph according to claim 1, characterized in that, The step of generating the environment topology map further includes attribute injection based on environmental potential, and in response to window or noise source position features in the continuous geometric space data, the environmental potential values of each region in the space are calculated based on a preset distance decay function; the environmental potential values are quantized into hierarchical labels, and the hierarchical labels are written into the data structure of the corresponding spatial slot node as environmental attributes; accordingly, the entity nodes in the entity knowledge graph contain environmental demand attributes, and the primary mapping step includes verifying the matching degree of the environmental attributes of the spatial slot node and the environmental demand attributes of the target entity node.

8. The indoor space automatic layout and rendering method based on a design knowledge graph according to claim 1, characterized in that, The entity knowledge graph adopts a double-layer heterogeneous graph architecture, the bottom layer is an environment topology map composed of spatial slot nodes, used to represent the discretization attributes of the physical space; the upper layer is a logical entity graph composed of entity nodes, used to encapsulate the design rules and the accompanying dependency relationship between entities; The ownership mapping relationship is realized by embedding the nodes in the logical entity graph into the corresponding nodes in the environment topology map.

9. The indoor space automatic layout and rendering method based on a design knowledge graph according to claim 1, characterized in that, The structured configuration instruction is a JSON format data file containing the unique identifier of the object, the relative transformation matrix and the material reference, and the data file is used to drive the rendering engine to generate a three-dimensional scene, and the method further includes a deadlock detection and rollback step; when the traversal depth in the recursive topology rewriting step reaches the preset threshold and the ownership mapping relationship is still not established, it is determined that it is an unsolvable deadlock state; a state rollback operation is performed to restore to the last successful primary mapping state, and the conflict area causing the unsolvable deadlock state is marked, and an exception report containing the conflict area information is generated.

10. An indoor space automatic layout and rendering system based on a design knowledge graph, for implementing the method of claim 1, characterized in that, Comprise: A graph maintenance module is used to maintain an entity knowledge graph in a graph database, the entity knowledge graph comprises entity nodes connected by logical edges, the entity nodes are defined with topology interface attributes and a resource request label set, and the logical edges are defined with relative spatial constraint parameters between entities and one-way variant paths pointing to degraded alternative nodes; A spatial discretization module is used to respond to input continuous geometric space data, extract spatial boundary features, and discretize the continuous geometric space data into an environment topology map composed of a plurality of spatial slot nodes, and the spatial slot nodes are written into capacity attribute data describing geometric bearing capacity and resource supply label sets describing physical resource supply state; The isomorphism mapping module is configured to perform a primary mapping based on maximum common subgraph isomorphism, construct a query subgraph of a target entity node to be processed in an entity knowledge graph, and search a candidate slot set in an environment topology graph that is topologically isomorphic to the query subgraph and satisfies capacity attribute data; The resource handshake verification module is configured to perform resource topology handshake verification on the candidate slot set, perform an inclusive logical operation on a resource request label set of the target entity node and a resource supply label set of the spatial slot node, and when the operation result is false, dynamically insert a relay node into the query subgraph based on compensation logic in the entity knowledge graph to reconfigure a connection relationship; The recursive topology rewriting module is configured to, in response to a deadlock state caused by failure of the primary mapping or the resource topology handshake verification, trigger recursive topology rewriting along a unidirectional variation path, replace a conflict node in the query subgraph with a degraded replacement node and update a topology interface attribute, and re-execute isomorphic search using a rewritten variation query subgraph until a home mapping relationship is established; The configuration instruction generation module is configured to calculate a local coordinate transformation matrix of each node and generate a structured configuration instruction based on the established home mapping relationship and a relative spatial constraint parameter of a logical edge.

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