Overvoltage protection in flyback power converters

Abstract

The embodiment of the invention relates to overvoltage protection in a flyback power converter. Techniques for trough detection in flyback power converters. In an example, circuitry implementing the techniques is configured to generate a first indication (613) of an over voltage protection (OVP) condition of a flyback power converter using a switch terminal signal (601) of the flyback power converter. The circuitry is further configured to generate a second indication of an input voltage surge condition of the flyback power converter using the switch terminal signal of the flyback power converter (615). The circuitry is further configured to suppress the first indication (615) in response to generating the second indication.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of Indian (IN) Provisional Patent Application No. 202441059286, filed on August 6, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] This specification relates to power converters, and more specifically, to overvoltage protection in flyback power converters. Background Technology

[0004] A flyback power converter is a switch-mode power supply that converts an AC or DC input voltage into one or more regulated DC output voltages. A flyback converter topology typically includes an input capacitor, a primary-side switching element (e.g., a metal-oxide-semiconductor field-effect transistor, or MOSFET), a coupling inductor called a flyback transformer, an output diode or rectifier, and an output capacitor. The transformer allows for energy storage, energy transfer, and current isolation between the input and any output. The turns ratio between the primary and secondary windings of the transformer can be configured such that the output voltage is lower or higher than the input voltage. In operation, when the primary-side switching element is closed (on-time, or TON), the primary winding of the transformer is connected to the input voltage and the primary-side current ramps up, thus storing energy in the transformer's gaps or core. During this on-time, the output diode is reverse-biased and off, and the output capacitor supplies the load current. When the primary-side switching element is open (off-time, or TOFF), the current in the transformer moves to the secondary and flows through the now forward-biased output diode, thereby replenishing the output capacitor and supplying the load current. During this process, the secondary current ramps down as the transformer core demagnetizes. Some flyback converters use auxiliary transformer windings for trough sensing and overvoltage protection, and generate a low-voltage bias supply. Several significant issues remain with flyback power converters. Summary of the Invention

[0005] In one example, a circuit includes: a first comparator configured to use a switching terminal signal of a flyback power converter to generate a first indication of an overvoltage protection (OVP) condition of the flyback power converter; a second comparator configured to use the switching terminal signal of the flyback power converter to generate a second indication of an input voltage surge condition of the flyback power converter; and logic circuitry configured to suppress the first indication from the first comparator in response to the second indication from the second comparator.

[0006] In another example, a circuit includes: a first circuit configured to scale a switching terminal signal of a flyback power converter by a scaling factor to generate a scaled version of the switching terminal signal; a second circuit configured to determine an operating average input voltage of the flyback power converter based on the scaled version of the switching terminal signal; and a third circuit configured to use the operating average input voltage to determine whether both an overvoltage protection (OVP) condition and an input voltage surge condition exist in the flyback power converter, and to suppress an indication of the OVP condition in response to the presence of the input voltage surge condition.

[0007] In another example, a method includes: comparing VIN+N*VOUT with VIN(AVG)+N*VREF, where VIN corresponds to the input voltage of the flyback power converter, VIN(AVG) corresponds to the operating average input voltage of the flyback power converter, N corresponds to the turns ratio of the flyback power converter, VOUT corresponds to the output voltage of the flyback power converter, and VREF corresponds to the voltage limit of the flyback power converter; and in response to VIN+N*VOUT being greater than VIN(AVG)+N*VREF, comparing VIN(AVG) with a sample of the voltage-adjusted operating average input voltage; indicating an input voltage surge condition in response to VIN(AVG) being greater than the sample of the voltage-adjusted operating average input voltage; and indicating an overvoltage protection condition in response to VIN(AVG) not being greater than the sample of the voltage-adjusted operating average input voltage. Attached Figure Description

[0008] Figure 1 A block diagram of a flyback power converter system with overvoltage protection (OVP) circuitry is shown in the example.

[0009] Figure 2 Example signals of the switching terminals of a flyback power converter are shown.

[0010] Figure 3 Example shown Figure 1 The block diagram of the OVP circuit of the system.

[0011] Figure 4A Example shown Figure 1 and 3 A schematic diagram of the OVP circuit of the system.

[0012] Figure 4B Example shown Figure 4A A schematic diagram of the VIN(AVG) processing circuit of the OVP circuit.

[0013] Figure 4C Example shown Figure 4A A schematic diagram of the delay circuit of the OVP circuit.

[0014] Figure 4D Example shown Figure 4A A schematic diagram of the leakage ringing filter circuit of the OVP circuit.

[0015] Figure 5A and 5B Each shows an instance of... Figure 1 A diagram of the signals generated by the system.

[0016] Figure 6 A flowchart illustrating an example of a method for overvoltage protection in a flyback power converter is shown.

[0017] Figure 7 The diagram shows a block diagram of a system comprising a flyback power converter configured for overvoltage protection without the use of an auxiliary winding. Detailed Implementation

[0018] This document describes a technique for overvoltage protection in flyback power converters. This technique allows the power converter to detect overvoltage conditions using signals at the switching node or terminal of the flyback power converter, and can be implemented without auxiliary transformer windings. The technique further allows differentiation between overvoltage conditions and input voltage surge conditions, which can cause erroneous overvoltage indications. In an example, the circuitry implementing this technique is configured to detect the operating average of the input voltage of the flyback power converter and compare the operating average input voltage with a sample of the average input voltage adjusted to reflect surge conditions. The sample adjusted to reflect surge conditions effectively represents a surge condition reference level and can be taken, for example, when the circuitry detects an overvoltage condition. In an example case, if the operating average input voltage is greater than the surge condition reference level, an input voltage surge condition can be indicated while temporarily suppressing the overvoltage condition indication to allow the input voltage surge condition to be acknowledged or subside. If the surge condition subsides, the associated but erroneous OVP indication will also subside. The duration of the surge condition check cycle can be inversely proportional to the average operating input voltage (e.g., 40 μs for a 400-volt input voltage and 120 μs for a 60-volt input voltage). Therefore, the aforementioned technology and circuitry enable a high-confidence surge-aware declaration of overvoltage conditions.

[0019] General Overview

[0020] As described above, flyback power converters still present several significant challenges. More specifically, existing flyback power converter topologies utilize an auxiliary winding of the flyback transformer to facilitate functions such as sensing overvoltage conditions. This auxiliary-based sensing may further require additional discrete components (e.g., high-voltage linear regulators) and separate package pins. The auxiliary winding, additional discrete components, and pins increase the converter's overall cost and footprint. Therefore, eliminating the auxiliary winding, additional discrete components, and pins would be beneficial. However, doing so necessitates a novel approach to overvoltage protection. One possible method is to use signals at the switching terminals of the flyback power converter to detect overvoltage conditions. To detect overvoltage conditions from the switching terminal signals, values ​​for the input voltage, output voltage, and the flyback transformer turns ratio are required. Furthermore, while input voltage surges do not transfer to the auxiliary winding, they do manifest on the switching terminal signals. A sudden rise in input voltage caused by a surge condition can lead to false indications of overvoltage conditions. Therefore, a given auxiliary-free overvoltage protection method should be surge-sensing.

[0021] Therefore, this document describes a technique for providing overvoltage protection in a flyback power converter topology without the use of an auxiliary winding. In an example, this technique can be implemented using a circuit system configured to perform surge-sensing overvoltage protection using the switching terminal signals (sometimes referred to as switching node signals) of the flyback power converter. The switching terminal signals may include a leakage reset section, a leakage ringing section, and a magnetizing ringing (or resonant) section. To detect overvoltage conditions, the circuit system is configured to obtain the input and output voltages of the flyback power converter from the switching terminal signals. Given these voltage values ​​and the turns ratio of the flyback transformer, the circuit system is further configured to determine when an overvoltage condition exists and confirm that the overvoltage condition is not an input surge condition. In this way, transient surge conditions are not mistakenly indicated as overvoltage conditions.

[0022] In this example, the circuit system includes a first comparator, a second comparator, and logic circuitry. The first comparator is configured to use a switching terminal signal of the flyback power converter to indicate an overvoltage protection (OVP) condition of the flyback power converter. The second comparator is configured to use the switching terminal signal to indicate an input voltage surge condition of the flyback power converter. The logic circuitry is configured to suppress the first comparator's indication of an OVP condition in response to the second comparator's indication of an input voltage surge condition. As described above, the circuit system is configured to obtain the input and output voltages of the flyback power converter from the switching terminal signals. In this example: the first comparator is configured to compare VIN+N*VOUT with VIN(AVG)+N*VREF, and indicates an OVP condition in response to VIN+N*VOUT being greater than VIN(AVG)+N*VREF; and the second comparator is configured to compare VIN(AVG) with a sample of the operating average input voltage adjusted to provide a surge reference voltage, and indicates an input voltage surge condition in response to VIN(AVG) being greater than the surge reference voltage. In these examples, VIN corresponds to the instantaneous input voltage of the flyback power converter, VIN(AVG) corresponds to the operating average input voltage of the flyback power converter, N corresponds to the turns ratio of the flyback power converter, VOUT corresponds to the output voltage of the flyback power converter, and VREF corresponds to the voltage limit of the flyback power converter. See below for reference. Figure 3 , 4A Examples of circuit systems for obtaining these various input and output voltage values ​​are described in sections 4D, 5A, 5B, and 6. In some examples, the input voltage of the power converter is in a high-voltage domain (e.g., greater than 25 volts), and the circuit system includes scaling circuitry configured to reduce the switching terminal signal of the flyback power converter by a scaling factor to obtain a scaled (low-voltage) version of the switching terminal signal, scaling each of the values ​​obtained for VIN(AVG), VIN+N*VOUT, and the surge reference voltage by the scaling factor.

[0023] Circuit architecture

[0024] Figure 1A block diagram of a flyback power converter system 100 with overvoltage protection (OVP) circuitry is shown in the example. As illustrated, system 100 includes an integrated circuit (IC) 101, a flyback transformer 111, an output diode DOUT, an output capacitor COUT, a feedback circuit 113, an electromagnetic interference (EMI) filter 115, and a rectifier 117. In this example, the flyback power converter system 100 converts an AC input voltage (VAC) to a DC input voltage (VIN), which is then converted by system 100 into a regulated DC output voltage (VOUT). In other examples, the DC input voltage VIN is obtained directly, rather than from the AC input voltage VAC.

[0025] As further illustrated, IC 101 includes surge sensing OVP detection circuitry 103, control circuitry 105, driver 107, sensing circuitry 108, and switching element 109, all of which can be filled on a given substrate, such as on or part of an integrated circuit die within an integrated circuit package (e.g., leaded ceramic flat package, dual in-line package, ball grid array, pin grid array, planar grid array, leaded chip carrier, quad flat no lead, to name a few), or on or part of a printed circuit board (e.g., single-sided, double-sided, multilayer, flexible, to name a few), or on or part of any other suitable substrate on which a circuit system can be formed and / or filled. In this example, each of the flyback transformer 111, DOUT, COUT, feedback circuitry 113, EMI filter 115, and rectifier 117 is shown external to IC 101, but in other examples, any one or more of these components or circuits may be integrated within IC 101. The electronic system to be powered may also be coupled between the VOUT terminal of system 100 and the ground terminal. The electronic system (referred to herein as load current (ILOAD)) can be configured to suit any number of applications (e.g., automotive systems, computing systems, communication systems, gaming systems, home appliances and consumer electronics systems, mobile electronic systems such as smartphones, or any other application utilizing regulated power). Other instances of the flyback power converter system 100 may include additional components not shown and / or be configured differently, and any of these systems can benefit from the techniques described herein.

[0026] EMI filter 115 removes unwanted noise from the line voltage, and rectifier 117 rectifies the AC input. Any suitable EMI filter and rectifier circuitry can be used. Other examples may apply VIN directly, rather than obtaining it from an AC source as shown. In these cases, system 100 may not include VAC, EMI filter 115, and rectifier 117. Transformer 111 allows for energy storage, energy transfer, and current isolation between the input VIN and output VOUT. The turns ratio between the primary winding 111p and the secondary winding 111s can be set such that VOUT is below or above VIN. Any suitable flyback transformer can be used. In this example, flyback transformer 111 does not include any auxiliary windings for overvoltage protection. Other examples may include one or more auxiliary windings, for example, to provide an alternative for OVP and / or for providing trough sensing and / or bias power.

[0027] Switching element 109 can be any suitable switching element technology, such as a gallium nitride field-effect transistor (GaNFET) or other power FETs, or a power bipolar junction transistor (BJT). In this example, switching element 109 is coupled between the SW terminal of IC 101 and the ground terminal via its current terminals (e.g., the source / drain terminals of the FET, or the emitter / collector terminals of the BJT), wherein sensing circuitry 108 is coupled between switching element 109 and ground. Control terminals of switching element 109 (e.g., the gate terminal of the FET, or the base terminal of the BJT) are coupled to the output of driver 107. When switching element 109 is closed (on-time, or TON), primary winding 111p is connected to the input voltage VIN and the primary-side current ramps up, thus storing energy in the core of transformer 111. During this on-time, diode DOUT is reverse biased and off, and capacitor COUT supplies load current. When switching element 109 is turned off (off time, or TOFF), the energy stored in the core of transformer 111 is transferred to the secondary winding 111s, and current flows through diode DOUT (now forward biased), thereby replenishing capacitor COUT and supplying the load current ILOAD. During this process, the secondary current ramps down as the core of transformer 111 demagnetizes. The closing and opening of switching element 109 (including for overvoltage protection) is controlled by IC 101, as explained further below.

[0028] Sensing circuit 108 senses the primary-side peak current IPK and provides this current information (which may be a scaled version of the actual primary-side peak current IPK) to control circuit 105. The primary-side peak current IPK depends on ILOAD and input line conditions. Any suitable current sensing circuit system that allows control circuit 105 to receive or otherwise determine the primary-side peak current IPK can be used, such as a resistor-based current sensing circuit that includes a sensing FET or BJT as a scaled-down replica of the switching element 109. In some instances, sensing circuit 108 may also compare IPK for a given switching cycle with a reference current, and if IPK exceeds the reference current, generate a current limit signal. In these cases, the current limit signal may be provided to control circuit 105, which may then initiate one or more remedial actions (e.g., asserting a current clamping circuit, shutting down the converter, disconnecting VIN, etc.). Feedback circuit system 113 senses the output voltage and provides a feedback voltage VFB signal to control circuit 105. The VFB signal may be, for example, a scaled-down version of VOUT. Any suitable feedback circuit system that allows the control circuit 105 to receive or otherwise determine VOUT can be used, such as resistive voltage dividers and / or optocoupler feedback circuits sometimes used in flyback topologies.

[0029] As further illustrated, an input voltage VIN is applied to one terminal of the primary winding, and the other terminal of the primary winding is coupled to the switching node (SW) terminal of IC 101, causing IC 101 to receive a switching node voltage (VSW) signal. Additionally, system ground (GND) is coupled to the ground terminal of IC 101, the IPK signal generated by sensing circuit 108 is coupled to the current sensing (CS) terminal of IC 101, and the VFB signal generated by feedback circuit 113 is coupled to the feedback (FB) terminal of IC 101. Furthermore, a power supply voltage VDD can be generated on IC 101 or received via another terminal of IC 101 and can be used to power the circuitry therein as needed. Other embodiments may be configured differently and / or include other components, and any of these configurations may benefit from the techniques described herein.

[0030] In a typical operation, the surge-sensing OVP detection circuit 103 receives a VSW signal from the SW terminal and turns ratio (N) information from the control circuit 105, and generates one or more surge-sensing OVP detection signals. A given OVP signal identifies when the current value of VOUT exceeds a given OVP threshold. The OVP threshold can be fixed or variable, depending on the application. The control circuit 105 receives a VFB signal at its FB input terminal, an IPK signal at its CS terminal, and one or more OVP detection signals at its voltage sensing (VS) input terminal, and provides a corresponding drive voltage (VDRV) signal at its DRV output terminal. The VDRV signal (which can be, for example, a pulse-width modulation (PWM) signal) is applied to the control terminal of the switching element 109 via the driver 107 and can be configured by the control circuit 105 to stop switching upon sensing an OVP condition (indicated by one or more OVP detection signals). In some instances, the control circuit 105 further configures the VDRV signal for valley switching.

[0031] Figure 2 Example signals of the switching terminals (or switching nodes, or switch nodes, which are used interchangeably herein) of a flyback power converter are shown. Figure 1 In example system 100, the signal can be, for example, the VSW signal at the SW terminal of IC 101. The signal is not intended to be drawn to scale, but is provided to illustrate various illustrative aspects of the signal, and the signal may vary from example to example. As shown, a single switching cycle of the signal includes an on-time (TON) portion and an off-time (TOFF) portion. The TOFF portion includes a demagnetizing (TDEMAG) portion and a resonant or no-load time (TDEAD) portion. The TDEMAG portion includes a leakage reset (TRESET) portion and a leakage ringing portion. The TDEAD portion includes a magnetizing ringing portion, which includes multiple troughs (V1, V2, ...). In this example, switching occurs on the second trough V2, and a new switching cycle begins. Other examples may switch on the first trough V1 or a later trough (e.g., V3, V4, etc.). In other examples, a trough switching scheme is not used.

[0032] exist Figure 2 On the right, VCLAMP and VFETMAX are shown. VCLAMP is the clamping voltage (which can be, for example, generated by...). Figure 7 The snubber 710 is provided in the middle. VCLAMP can be calculated as follows:

[0033] VCLAMP = Tolerance% * VFETMAX – VINMAX (Equation 1)

[0034] Where VFETMAX is the maximum rated voltage of the switching element 109, the tolerance percentage (%) provides some tolerance at the maximum rated voltage, and VINMAX is the peak DC voltage based on the general AC line range.

[0035] like Figure 2 The text further demonstrates that VIN can be determined by averaging the VSW signal. This is because an average DC voltage cannot exist across the inductor of the flyback transformer 111. (The text then repeats itself, seemingly an error.) Figure 2 The text further demonstrates that N*VOUT+VIN corresponds to the voltage in the flat region of the VSW signal, and can be determined by sampling the voltage in this flat region. Therefore, it is assumed that the voltage in the flat region (in...) Figure 2 If sampling is performed using N*VOUT+VIN, and each of VIN and the turns ratio N is determinable or otherwise known, then VOUT can also be determined:

[0036] VOUT = [PV – VIN] / N (Equation 2),

[0037] Where PV is the voltage of the sampled flat region. Once VOUT is known, it can be compared with a given OVP threshold voltage to determine whether an OVP condition has occurred. It should be noted that it is not necessary to actually calculate the absolute value of VOUT to detect an OVP condition. For example, the sampled value of N*VOUT+VIN can be compared with N*VREF+VIN, where VREF is the OVP threshold voltage, which also allows for the detection of an OVP condition. Therefore, in this example, system 100 is configured with circuitry to provide the average voltage of the VSW signal (to provide VIN), and circuitry configured to sample the flat region of the VSW signal (to provide N*VOUT=VIN). The following is related to... Figures 3 to 6 Further examples of such circuit systems are described.

[0038] like Figure 2The diagram further illustrates that a positive sag SL1 exists at the beginning of the TRESET portion. The peak shape of the TRESET portion can vary depending on the configuration, but in this example, it slopes slightly downwards from left to right. Other examples may show an upward sag and / or a more pronounced sag, or a more curved shape, or no sag or curve at all. Furthermore, the duration of the TRESET varies with the primary-side peak current IPK. The higher the value of the primary-side peak current IPK, the longer the duration of the TRESET. At the end of the TRESET window, a steep negative sag SL2 exists. In this example, the system 100 may be configured with, or in conjunction with, circuitry configured to detect and blank the TRESET portion to suppress or otherwise avoid sampling of the TRESET portion for evaluation of OVP and surge conditions. The blanking period can be fixed or variable, for example, in instances where the blanking period varies based on IPK, and for a given configuration, it can be set to be slightly longer than the TRESET.

[0039] like Figure 2 The diagram further illustrates that the leakage ringing portion contains multiple occurrences of negative rotation SL3, and the magnetized ringing portion contains multiple occurrences of negative rotation SL4. The ringing in the leakage ringing portion is caused by parasitic effects of the switching nodes (e.g., parasitic capacitance of the switching elements and transformer) and has a relatively higher frequency than the ringing in the magnetized ringing portion. The ringing in the magnetized ringing portion occurs when the secondary winding energy drops to (or reaches) zero. For a given application, the slowest leakage ringing can, for example, be twice as long as the fastest magnetized ringing. This means that any given rotation SL3 will end faster than the rotation SL4 at the first trough of V1. Therefore, in this example, the rotation detection circuitry works in conjunction with logic and a leakage ringing filter, the period of which is longer than any signal period of the leakage ringing but shorter than the time required for the rotation SL4 at the first trough to end, to generate a sampling control signal that remains active during the flat portion of the VSW signal and turns off in response to the expiration of the leakage ringing filter. In this way, gating and accurate sampling of the voltage in the flat area can be achieved.

[0040] Surge sensing OVP circuit system

[0041] Figure 3 Example shown Figure 1A block diagram of the surge sensing OVP detection circuit 103 of system 100 is shown. As illustrated, circuit 103 includes a scaling circuit 301, a VIN detection circuit 303, a slewing detection circuit 305, and an OVP and surge detection circuit 307. Other examples may be configured differently and with varying degrees of integration, but still operate to provide similar functionality. For example, in another example, each of the scaling circuit 301, the VIN detection circuit 303, and the slewing detection circuit 305 may be integrated into the OVP and surge detection circuit 307. In example operation, circuit 103 receives a switch terminal signal VSW at its input and is configured to generate an OVP signal at its output in response to an overvoltage condition (based on a given OVP threshold voltage suitable for a given application). As further shown in this example, circuit 103 may also generate a VIN surge detection signal at its output in response to a VIN surge condition. Surges can occur on the AC line voltage due to various external factors to the power converter, leading to a rapid rise in VIN (e.g., 150V / 50μs). When VOUT of system 100 exceeds a given OVP threshold, an overvoltage condition occurs, causing the OVP and surge detection circuit 307 to generate an OVP detection signal, which in turn shuts off the power converter switch to prevent damage to connected devices (loads) due to excessive voltage. Circuit 103 can distinguish between these OVP and surge conditions and suppresses the indication of a detected OVP condition when a VIN surge condition is also present. Advantageously, no auxiliary winding is required when generating the OVP and surge detection signals.

[0042] As described above, the VSW signal includes a leakage reset section, a leakage ringing section, and a magnetization ringing section, and can be used to detect VIN and VOUT, which can then be used for assessing OVP and surge conditions. Scaling circuit 301 includes an input receiving the switch terminal signal VSW (from the SW terminal of system 100) and is configured to scale the VSW signal by a scaling factor to produce a scaled version of the VSW signal. Scaling can be passive or active. For example, scaling circuit 301 can be a resistive voltage divider configured to passively scale the VSW signal from a high voltage domain (e.g., >25 volts, such as 300 volts or 700 volts) to a low voltage domain (e.g., 5 volts or less). In another example, scaling circuit 301 can be an amplifier configured with a gain less than 1 to actively attenuate (scale) the VSW signal to a target level. More generally, any type of level shifting circuit system can be used. The scaling factor provided by scaling circuit 301 can be set for the details of a given application. Other instances may not include scaling circuitry 301, such as instances where the input voltage is relatively low (e.g., 10 volts or less) or otherwise comparable to other voltages of circuitry 103 and / or where circuitry 103 is configured to handle unscaled VSW signals.

[0043] VIN detection circuit 303 includes an input for receiving a scaled VSW signal, a power supply (VDD) input, a frequency signal (FREQ) input, and a VIN(AVG) output. VIN detection circuit 303 is configured to determine the operating average input voltage VIN(AVG) of the flyback power converter based on the scaled VSW signal. For more details, see [link to previous section]. Figure 2 As described above, the average value of the VSW signal is VIN (and a scaling factor, if applicable), because an average DC voltage cannot exist across the inductor of a flyback transformer. Therefore, in this example, the VIN detection circuit 303 is configured to determine VIN(AVG) by filtering the scaled VSW signal using a low-pass filter. In one such example, the low-pass filter is a third-order filter comprising a first-order resistor-capacitor (RC) filter followed by two switched-capacitor filters. The cutoff frequency of the switched-capacitor filters can be proportional to or additionally dependent on VIN, as further described below, using the FREQ input generated by the OVP and surge detection circuit 307. This allows the low-pass filter to respond faster at higher VIN values ​​and slower at lower VIN values, thus enabling faster surge detection at higher VIN values ​​compared to lower VIN values.

[0044] The rotation detection circuit 305 includes a VSW signal input, a VDD input, a VDRV input, and an output providing a sampling control (TSAMPLE) signal. The rotation detection circuit 305 is configured to detect negative rotations SL3 and SL4 and generate a TSAMPLE control signal. The TSAMPLE control signal is used to gate the sampling of the flat-line portion of the VSW signal voltage, which in some instances may be performed by the OVP and surge detection circuit 307, but in other instances the gate may be performed elsewhere. In some instances, the rotation detection circuit 305 includes: a negative rotation detector that works in conjunction with a leakage ringing filter; and logic that allows the TSAMPLE control signal to otherwise switch high during the flat-line portion to allow sampling, and keeps the TSAMPLE control signal low after the leakage ringing filter expires to stop sampling. The VDRV signal received at the VDRV input can be used to set the logic for operation during the TOFF portion of the switching cycle (where flat-line sampling occurs) and to reset the logic during the TON portion. The sample-and-hold circuit, enabled by the TSAMPLE control signal, can be used to responsively sample the voltage in the flat region. This achieves accurate gated sampling of the flat region (which corresponds to the voltage: N*VOUT+VIN).

[0045] As described above, sampling of the TRESET portion of the VSW signal can be avoided by a circuit system configured to detect and blank the TRESET portion. For example, such a circuit system may be included in the rotation detection circuit 305, but in other instances, the circuit system may be located elsewhere. In any case, the blanking period may be fixed in some instances and variable in others, such as when the blanking period is based on IPK and set slightly longer than TRESET for a given configuration. An example of an IPK-aware blanking scheme for bypassing the TRESET portion of the VSW signal is described in U.S. Patent Application No. 19 / 016,101, filed January 10, 2025, which is incorporated herein by reference in its entirety. One such example includes: a rotation detector configured to detect forward rotation SL1 and cooperate with the blanking circuit; and logic configured to suppress rotation reporting (e.g., SL2) before a given delay period expires. Sampling of the flat portion of the VSW signal can then begin.

[0046] The OVP and surge detection circuit 307 includes inputs for receiving VDD, inputs for receiving a scaled VSW signal, inputs for receiving VIN(AVG), inputs for receiving the turns ratio (N), inputs for receiving a TSAMPLE control signal, outputs for providing a frequency signal (FREQ), outputs for providing an OVP detection signal, and outputs for providing a VIN surge detection signal. The OVP and surge detection circuit 307 is configured to use a scaled version of the VSW signal (and, if applicable, an unscaled version) and VIN(AVG) to detect the presence of an OVP condition, and if present, to suppress an indication of an OVP condition in response to the presence of an input voltage surge. In this way, the OVP and surge detection circuit 307 is configured to distinguish between a true OVP condition and a false OVP condition that is actually an input voltage surge.

[0047] In one such example, the OVP and surge detection circuit 307 are configured to sample the voltage of the flat portion of the VSW signal in response to a TSAMPLE control signal, which provides a voltage value of VIN+N*VOUT (reference). Figure 2(As described). The OVP and surge detection circuit 307 is further configured to compare VIN+N*VOUT with VIN(AVG)+N*VREF, and to indicate the OVP condition in response to VIN+N*VOUT being greater than VIN(AVG)+N*VREF. In this example, VIN corresponds to the instantaneous input voltage of the flyback power converter, VIN(AVG) corresponds to the operating average input voltage of the flyback power converter provided by the VIN detection circuit 303, N corresponds to the turns ratio of the flyback transformer (e.g., provided by the control circuit 105), VOUT corresponds to the output voltage of the flyback power converter, and VREF corresponds to the voltage limit of the flyback power converter (which may also be referred to as the OVP threshold). The OVP and surge detection circuit 307 is further configured to compare VIN(AVG) with a sample of the operating average input voltage that is voltage-adjusted to simulate or otherwise reflect the input surge condition, and to indicate the input voltage surge condition in response to VIN(AVG) being greater than the sample of the surge-adjusted operating average input voltage. The OVP and surge detection circuit 307 is further configured to suppress the indication of the OVP condition in response to an input surge condition that is also indicated at that time.

[0048] Figure 4A Example shown Figure 3 A schematic diagram of the surge sensing OVP detection circuit 103 is shown. The description of circuit 103 above also applies here, and is further extended through example arrangements of circuit systems to achieve the functionality described herein. Other examples may be configured differently, but still achieve similar functionality.

[0049] In this example, scaling circuit 301 includes a resistive voltage divider containing resistors R1 and R2, and switch S1. The divider ratio may vary from example to example, but in one example it is 1:201, where R1 = 200 kΩ and R2 = 1 kΩ. In one such example, the maximum voltage of approximately 600 volts on the VSW signal will be reduced to approximately 3 volts. Switch S1 may be used, for example, to enable / disable scaling circuit 301 (and surge sensing OVP detection circuit 103) in response to a control signal from control circuit 105. Other examples may not include switch S1, or such a switch may be provided elsewhere in the circuit (e.g., between the SW terminal and resistor R1). In some examples, switch S1 may be open during startup and low-power modes and closed during normal operation modes. Other examples may include active attenuator circuitry.

[0050] Further reference Figure 4AThe VIN detection circuit 303 is configured with a third-order low-pass filter, which includes a first-order RC filter (resistor R3 and capacitor C1), followed by two switched-capacitor filters (SCF 404 and SCF 408). SCF 404 includes switches S4 and S5, along with capacitors C2 and C3 and an inverter 405, and SCF 408 includes switches S6 and S7, along with capacitors C4 and C5 and an inverter 409. Figure 4A The example further demonstrates that the switching of switches S4 through S7 is controlled by FREQ signals from OVP and surge detection circuit 307, thus allowing the cutoff frequencies of switched capacitor filters 404 and 408 to be proportional to VIN, or otherwise dependent on VIN. A unity-gain buffer 402 is provided between the RC filter stage and SCF 404, and a unity-gain buffer 406 is provided between SCF 404 and SCF 408. Switches S2, S3, and S4, along with resistors R4, R5, and R6, can be used to precharge capacitors C1 through C5 before startup and in low-power mode. Similar to switch S1, switches S2, S3, and S4 can, for example, respond to one or more control signals from control circuit 105 and can engage during startup and low-power mode.

[0051] In the example operation, the VIN detection circuit 303 is configured to low-pass filter the VSW signal to obtain the operating average input voltage VIN(AVG) of the flyback power converter. Where applicable, both the VSW signal and VIN(AVG) can be scaled according to the scaling factor of the scaling circuit 103. As described above, since an average DC voltage cannot exist across the inductor of the flyback transformer 111, VIN(AVG) can be determined by averaging the VSW signal. Figure 4A The example further demonstrates that VIN(AVG) is used by the OVP and surge detection circuit 307 to determine the presence of OVP and input voltage surge conditions. In some such examples, VIN(AVG) may also be used for other functions, such as brown-out detection. Although the values ​​of the various components may vary from example to example, one such example has the following: R3 = 8MΩ; R4 = 50KΩ; R5 = 50KΩ; R6 = 50KΩ; C1 = 5pF; C2 = 500fF; C3 = 5pF; C4 = 500fF; and C5 = 5pF, and the cutoff frequencies of SCF404 and SCF 408 may vary between 5kHz (which corresponds to approximately 60 volts of VIN(AVG) and approximately 333kHz of FREQ signal) and 15kHz (which corresponds to approximately 400 volts of VIN(AVG) and approximately 1MHz of FREQ signal).

[0052] Further reference Figure 4AThe gyration detection circuit 305 is configured to use capacitive gyration detection to detect negative gyration of the VSW signal and generate a TSAMPLE control signal. The sensing portion of the gyration detection circuit 305 includes a current source IBIAS1, a capacitor C6, a resistor R7, and a clamp including diodes D1 and D2. Each of these components can be rated to meet the specifications of a given application (e.g., a high-voltage automotive application where VSW can vary over a wide range, such as from -2 volts to 1000 volts). Furthermore, some or all of the sensing circuitry can be integrated with other components. For example, in some instances, capacitor C6 is a high-voltage metal-insulator-metal (MIM) capacitor integrated with a semiconductor die that also includes a switching element 109 (e.g., a GaN power FET). Resistor R7 and current source IBIAS1 can be configured to provide a bias voltage level (e.g., just above ground potential, for example, in the range of 50 mV to 100 mV) at the non-inverting input of comparator 434. For example, in one instance, capacitor C6 = 150 nanofarads (e.g., rated at 700 volts), resistor R7 = 50 kΩ, and current source IBIAS1 is set to approximately 1.0 to 1.25 microamps to bias the non-inverting input of comparator 434 to approximately 50 to 62.5 millivolts. In example operation, IBIAS1, C1, and R1 effectively convert the SW node rotation into current, and the D1-D2 clamps are used to limit the voltage swing (e.g., to approximately 0.6 or 0.7 volts for a silicon diode). Other suitable rotation detector configurations can be used.

[0053] As further illustrated, comparator 434 receives the output of the sensing portion of the slewing detection circuit 305 and generates a slewing comparator signal at its output. In this example, the threshold voltage at the inverting input of comparator 434 is fixed (ground potential); however, in other examples, the threshold voltage may be variable to allow the slewing detection circuit 305 to detect both positive and negative slewing, wherein the positive slewing detection mode may be used to detect SL1 of the VSW signal for the purpose of blanking the TRESET portion of the VSW signal. Examples of circuit systems for providing such variable threshold voltages are described in previously incorporated U.S. Patent Application No. 19 / 016,101. In other examples, dedicated circuitry may be used for blanking the TRESET portion. In one such example, the forward rotation detector may be configured to also receive the output of the sensing portion of the rotation detection circuit 305 and provide a low output until forward rotation SL1 of a given switching cycle is detected and the delay period (fixed or variable) from the detection of SL1 to the start of SL2 has elapsed. At this point, a dedicated circuit provides a high output, which may then be received by, for example, a third input of an AND gate 446, to further inform the TSAMPLE control signal that the TRESET portion has passed. More generally, any circuitry can be used to detect the passage of the TRESET portion or otherwise ignore the TRESET portion so that sampling is only allowed for the flat section portion. In any of these cases, sampling of the flat section portion of the VSW signal may begin after the TRESET portion has passed and continue until the first occurrence of SL4 during a given switching cycle.

[0054] like Figure 4A As further illustrated in the example, the gyration detection circuit 305 further includes logic 438, an inverter 440, a leakage ringing filter 436, and an AND gate 446 (indicated by the & symbol). In this example, logic 438 is implemented by a D-type synchronous, active-low-reset, positive-edge-triggered flip-flop, wherein the drive signal VDRV is applied to the reset input of logic 438 via inverter 440, the data (D) input of logic 438 is held high via power supply VDD, and the clock input of logic 438 receives the gyration comparator signal from comparator 434. The TOFF control signal at the Q-bar output of logic 438, together with AND gate 446, controls the sampling performed by sample-and-hold (S&H) circuit 416, which in this example is part of OVP and surge detection circuit 307. Other configurations that implement similar functionality can be used. For example, in another instance, logic 438 is implemented by a D-type synchronous, active-high-reset, positive-edge-triggered flip-flop, where the drive signal VDRV is applied directly to the reset input of logic 438 (without inverter 440).

[0055] In practical operation, when the VDRV signal is high (during the TON portion of the VSW signal for the current switching cycle), logic 438 is reset, and the TOFF control signal at the Q-bar output of logic 438 is high. This allows the TSAMPLE control signal at the output of AND gate 446 to be high when the gyration comparator signal is also high, effectively enabling or otherwise implementing sampling of the S&H 416. When the VDRV signal goes low (during the current switching cycle, which initiates the TOFF portion of the VSW signal), logic 438 becomes set or otherwise ready to be triggered by the next positive (rising) edge received from filter 436 at the clock input of logic 438. The first positive edge from filter 436 occurs when the first negative gyration SL4 (where the VSW signal is detected) Figure 2 This is followed by a delay period (e.g., 280 nanoseconds). More specifically, when the first negative slew SL4 begins, the slew comparator signal at the output of comparator 434 transitions from high to low. This low slew comparator signal is received by filter 436, which in turn causes the filtered signal at the output of filter 436 to transition from low to high after the delay period configured in filter 436 has expired, as described below. Figure 4D The example is further described. When the positive edge of the filtered signal is received at the clock input of logic 438, this triggers the TOFF control signal at the Q-bar output of logic 438 to change from high to low, which in turn causes the TSAMPLE control signal at the output of AND gate 446 to go low, thereby preventing further sampling by S&H 416. This low state of the TSAMPLE control signal at the Q-bar output of logic 438 is maintained until VDRV goes high again (initiating the TON portion of the next switching cycle), which resets logic 438 and thus causes the TOFF control signal at the Q-bar output of logic 438 to go high. The process is repeated within the switching cycle, and so on. Furthermore, as recalled above, the TSAMPLE control signal can also be informed when the TRESET portion of the VSW signal has passed through a given switching cycle.

[0056] like Figure 4AFurther illustrating, the OVP and surge detection circuit 307 includes a VIN (AVG) processing circuit 410, a unity-gain buffer 414, a sample-and-hold circuit 416, a unity-gain buffer 418, a comparator 420, a delay unit 422, a comparator 424, a voltage-controlled oscillator (VCO) 426, a sample-and-hold circuit 428, a comparator 430, and an AND gate 432. In operation, the OVP and surge detection circuit 307 is configured to receive the VSW signal along with VIN (AVG) and the turns ratio N, and generate multiple voltage values ​​used to determine the presence of an OVP condition. If present, the OVP condition indication is suppressed in the presence of an input voltage surge condition, thereby allowing surge-sensing overvoltage protection. Table 1 lists the voltage values ​​generated in one example. Figure 4A The diagram further demonstrates that, where applicable, each of the VSW signal, VIN(AVG), and the generated voltage value can be scaled by a scaling factor caused by scaling circuit 301.

[0057] Table 1: Voltages generated by OVP and surge detection circuit 307

[0058] VIN(AVG) A buffered version of VIN(AVG) provided by VIN detection circuit 303. VIN_SURGE_REF A buffered version of VIN(AVG) adjusted to reflect surge conditions. VIN(AVG)+N*VREF A buffered version of VIN(AVG) adjusted to reflect the OVP status. VIN+N*VOUT The sampling voltage of the flat region of the VSW signal.

[0059] The VIN(AVG) processing circuit 410 receives VIN(AVG) (scaling) from the VIN detection circuit 303 and the turns ratio N from the control circuit 105, and provides a plurality of buffered outputs listed in Table 1 above. In this particular example, a first VIN(AVG) (scaling) output is provided to the non-inverting input of comparator 430, a second VIN(AVG) (scaling) output is provided to the non-inverting input of comparator 424 and the input of VCO 426, a VIN(AVG)+N*VREF (scaling) output is provided to the inverting input of comparator 420, and a VIN_SURGE_REF (scaling) output is provided to the input of sample and hold 428. In this example, the VIN(AVG)+N*VREF (scaling) output provides a first threshold voltage used by comparator 420 to determine whether an OVP condition exists, and the VIN_SURGE_REF (scaling) output provides a second threshold voltage used by comparator 430 to determine whether an input voltage surge condition exists. Figure 4B An example of the VIN(AVG) processing circuit 410 is shown and described further below.

[0060] Buffer 414 provides the scaled VSW signal from scaling circuit 301 to the input of sample-and-hold circuit 416, which is gated by the TSAMPLE control signal to allow sampling of the flat portion of the VSW signal. As described above, the voltage of the flat portion corresponds to the voltage value of VIN+N*VOUT (scaled) provided at the output of sample-and-hold circuit 416. If needed (e.g., for monitoring and / or use in other functions), buffer 418 can be used to provide the VIN+N*VOUT (scaled) value to the output terminal of circuit 307.

[0061] The VIN+N*VOUT (scaling) value from the sample-and-hold circuit 416 is also provided to the non-inverting input of comparator 420, which also receives VIN(AVG)+N*VREF (scaling) from circuit 410 at its inverting input and provides a pre-OVP signal at its output. In this way, comparator 420 is configured to compare VIN+N*VOUT (scaling) with VIN(AVG)+N*VREF (scaling) to determine whether an OVP condition is possible. Specifically, if VIN+N*VOUT (scaling) is greater than VIN(AVG)+N*VREF (scaling), the pre-OVP signal at the output of comparator 420 goes high, thus indicating a possible OVP condition; otherwise, the pre-OVP signal goes low, thus indicating that an OVP condition does not exist. This OVP condition is called a possible OVP condition because it may be a false positive caused by an input surge condition.

[0062] For this purpose, and as Figure 4AAs further illustrated, the pre-OVP signal is also used by the gated sample-and-hold circuit 428 to simultaneously sample a surge-adjusted version of the VIN(AVG) (scaled) voltage provided by circuit 303. This surge-adjusted version of VIN(AVG) (scaled) is referred to herein as VIN_SURGE_REF (scaled) and is used as a surge reference voltage for the purpose of determining the presence of an input voltage surge condition occurring simultaneously with the pre-OVP condition. More specifically, the sample-and-hold circuit 428 samples the VIN_SURGE_REF (scaled) voltage provided by circuit 410 in response to the pre-OVP signal going high, and the comparator 430 receives the sampled VIN_SURGE_REF (scaled) at its inverting input and the running VIN(AVG) (scaled) voltage at its non-inverting input, thus allowing the comparator 430 to determine whether VIN(AVG) (scaled) is greater than VIN_SURGE_REF (scaled). If so, the surge detection signal at the output of comparator 430 goes high, indicating the presence of an input surge condition; otherwise, the surge detection signal at the output of comparator 430 goes low, indicating the absence of an input surge condition. As described above, surge condition detection can be used to suppress the reporting of simultaneously reported OVP conditions.

[0063] For more details, and see reference Figure 4A AND gate 432 receives the surge detection signal from comparator 430 at one of its inputs via an inverter, and receives the pre-OVP signal from comparator 420 at the other of its inputs via delay unit 422. Delay unit 422 delays the reporting of the pre-OVP signal to allow comparator 430 to assess potential surge conditions. The delay provided by delay unit 422 varies with the FREQ signal and is proportional to VIN(AVG), confirming that surges can be detected faster at higher VIN(AVG) values ​​compared to lower VIN(AVG) values. See below for further details. Figure 4C The delay unit 422 is further described. In a typical operation, the output of AND gate 432 provides an OVP detection signal, which is only high when the pre-OVP signal is high and the surge detection signal is low. If the surge detection signal is high, the OVP condition is considered false and is therefore suppressed or not declared by AND gate 432; similarly, if the pre-OVP signal is low, then AND gate 432 does not declare the OVP condition.

[0064] like Figure 4AThe diagram further illustrates that comparator 424 receives VIN(AVG) from circuit 410 at its non-inverting input and sets its inverting input to an undervoltage lockout threshold (VIN_UVLO_REF), allowing comparator 424 to report a low voltage condition and initiate remedial action (e.g., disabling system 100 when VIN(AVG) is too low for proper operation). It should be noted that the input to comparator 424 is invertible and will still provide similar functionality (active-high output, not active-low output). VCO 426 also receives VIN(AVG) from circuit 410 at its input and generates a FREQ signal at its output. In this way, the FREQ signal is proportional to VIN(AVG), thereby allowing the cutoff frequency of each of SCF 404 and SCF 408 to be proportional to VIN(AVG), and the delay period provided by delay unit 422 to be inversely proportional to VIN(AVG). In some of these examples, for instance, the FREQ signal provided by the VCO426 is 333 kHz with a VIN(AVG) input of 60 volts and 1 MHz with a VIN(AVG) input of 420 volts. Other examples may be configured differently.

[0065] Figure 4B An example of a VIN(AVG) processing circuit 410 is shown. As shown in this example, the VIN(AVG) processing circuit 410 receives VIN(AVG) (scaling) and turns ratio N as inputs and provides multiple outputs including VIN(AVG) + N*VREF (scaling), VIN_SURGE_REF (scaling), and first and second instances of VIN(AVG) (scaling). The VIN(AVG) processing circuit 410 includes a buffer 442 that receives VIN(AVG) (scaling) at its non-inverting input and couples its output to the control terminals (e.g., gates) of transistors Q1 to Q3, which are arranged in a current mirror configuration to form multiple copies of VIN(AVG) (scaling). In this example, the transistors are p-channel field-effect transistors (PFETs), but other transistor technologies and suitable mirror circuit systems (e.g., bipolar junction transistors) can be used. Resistors R8 to R12 and current sources IBIAS2 and IBIAS3 provide bias. The source terminals of transistors Q1 through Q3 are coupled to VDD (e.g., 5 volts). The drain of transistor Q1 is coupled to ground (e.g., 0 volts) via resistor R8. The drain of transistor Q2 is coupled to ground via resistor R9. The drain of transistor Q3 is coupled to ground via resistor R11.

[0066] In operation, the output of buffer 442 is coupled to the gates of transistors Q1 through Q3, and its inverting input is coupled to the drain of Q1, which provides VIN(AVG) (scaling), thereby setting the current in transistor Q1 to VIN(AVG) / R8 (scaling). Each of transistors Q2 and Q3 replicates this current and similarly provides VIN(AVG) (scaling) at its drain. The drain of transistor Q1 is further coupled to the non-inverting input of comparator 424 and the input of VCO 426, allowing both to receive VIN(AVG) (scaling) as input. Furthermore, IBIAS2 and resistor R10 operate to adjust VIN(AVG) (scaling) at the drain of transistor Q2 by N*VREF (scaling) to provide VIN(AVG) + N*VREF (scaling), where VREF represents the scaling OVP threshold and N is the turns ratio. The resulting VIN(AVG) + N*VREF (scaling) is provided to the inverting input of comparator 420. Furthermore, IBIAS3 and resistor R12 operate to adjust VIN(AVG) at the drain of transistor Q3 by scaling the voltage to provide a scaled input surge voltage threshold known as VIN_SURGE_REF. VIN_SURGE_REF is provided to the input of sample-and-hold circuit 428, and VIN(AVG) at the drain of Q3 is provided to the non-inverting input of comparator 430.

[0067] In this example, R8 = 800 kΩ, or other appropriately high impedance, to maintain relatively low power dissipation. As shown in this example, resistor R10 can be variable to allow a range of turns ratios and / or OVP thresholds. In one such example, resistor R9 = 800 kΩ, IBIAS2 = 1 μA, VREF = 25 volts, N is in the range of a minimum turns ratio of 6 to a maximum turns ratio of 7.875, and resistor R10 can vary from 750 kΩ to 980 kΩ, for a total of 16 steps (4-bit resolution). Table 2 further illustrates such an example. The N*VREF (scaled) value corresponds to the voltage drop across resistor R10, which is added to the VIN (AVG) (scaled) value corresponding to the voltage drop across resistor R9.

[0068] Table 2: Examples with variable turns ratio (N)

[0069]

[0070] Resistor R12 is fixed in this example, but may be variable in other examples (in a similar manner to R10 described above) to allow for a range of input surges. In one example, resistor R11 = 800 kΩ, IBIAS3 is 1 microamp (μA), and resistor R12 = 40 kΩ. The VIN(AVG) (scaling) value corresponds to the voltage drop across resistor R11, and the voltage drop across resistor R12 (which is approximately 40 millivolts in this example) corresponds to the scaled voltage added to VIN(AVG) (scaling) to provide VIN_SURGE_REF (scaling). Considering the scaling factor of Example 1:201, the 40 millivolt voltage drop across resistor R11 translates to an 8-volt unscaled voltage. In such examples, within the range of 300 volts to 600 volts, an increase of 8 volts or more in VIN(AVG) is expected to indicate an input voltage surge condition. In other instances, the VIN_SURGE_REF value can be set as a percentage, for example, 101% to 110% of the expected VIN(AVG). In still other instances, the VIN_SURGE_REF value can be set empirically based on historical or theoretical data for a given system. Other instances may have different input voltage surge reference levels. More generally, the voltage added to VIN(AVG) can be set to a level to provide a VIN_SURGE_REF value that will only be exceeded during input voltage surge conditions in a given application.

[0071] Figure 4C An example of delayer 422 is shown. As described above, delayer 422 allows for faster surge detection at higher VIN(AVG) values ​​compared to lower VIN(AVG) values. In this way, the surge delay provided by delayer 422 is inversely proportional to the input voltage. More specifically, the available delay window that can be provided by delayer 422 depends on the quasi-resonant (QR) power (P) capacity of system 100, which varies with VIN(AVG), primary-side peak current (IPK), and N*VOUT (first trough QR power), as shown in Equation 3:

[0072] P = 0.5 * IPK * VIN(AVG) * N * VOUT / (VIN(AVG) + N * VOUT) (Equation 3).

[0073] The operating frequency during QR operation also varies with VIN, IPK, and N*VOUT, as well as the primary-side inductor L (the inductance of the primary coil 111p). The available delay window provided by delay unit 422 is constituted by the VIN-related clock (FREQ, generated by VCO 426), and as previously described, the VIN detection circuit 303 utilizes the VIN-related clock FREQ via SCFs 404 and 408 for modulation. The end result is that the filter response is faster at high VIN and slower at low VIN, which in turn means that surges can be detected more quickly at higher VINs compared to low VINs.

[0074] like Figure 4C As shown in the example, delay unit 422 includes an inverter 448, an OR gate 450, and a shift register containing N flip-flops 451. In one example, the shift register contains forty flip-flops (e.g., N = 40) to provide a delay of 40 cycles of a VIN(AVG) proportional clock (which is the FREQ signal in this example). In operation, delay unit 422 is enabled by the pre-OVP signal going high and will set the OVP signal at its output high after N cycles. This is prevented only by the surge detection signal going high or the pre-OVP signal going low. Continuing with the example above, for instance, the delay provided by delay unit 422 may be 40 μs when VIN(AVG) equals 400 volts and 120 μs when VIN(AVG) equals 60 volts. Other examples may be configured differently. More generally, delay unit 422 can be configured to provide one or more shorter delays at relatively high VIN(AVG) values ​​and one or more longer delays at relatively low VIN(AVG) values. Other instances may not include delay unit 422.

[0075] Figure 4DAn example of a leakage ringing filter 436 is shown. As shown, the leakage filter 436 includes a capacitor C7, a current source IBIAS4, a Schmitt trigger 454, and a transistor (switch) Q5. The capacitor C7 is coupled between the input of the Schmitt trigger 454 and ground and can be switched via the transistor Q5 based on the gyration comparator signal from the comparator 434. In this example, the transistor Q5 is implemented by an n-channel field-effect transistor (NFET), but any suitable switching technique can be used. In the example operation, when the gyration comparator signal from the comparator 434 goes low (thus indicating the start of negative gyration), the transistor Q5 turns off (opens), thereby releasing the pull-down on the input node of the Schmitt trigger 454 and allowing the capacitor C7 to charge through the constant current source IBIAS4. When the voltage across the input node of Schmitt trigger 454 (and across capacitor C7) reaches the high threshold (VTH_SCHMITT_454) of Schmitt trigger 454, the filtered signal at the output of Schmitt trigger 454 goes high and is provided to the clock input of logic 438. Subsequently, when the gyration comparator signal from comparator 434 goes high (thus indicating the start of positive gyration), transistor Q5 turns on (closes), thereby pulling the input node of Schmitt trigger 454 low, which in turn causes the filtered signal output of Schmitt trigger 454 to go low. The time from when the gyration comparator signal from comparator 434 goes low to when the output of Schmitt trigger 454 goes high corresponds to the leakage filter time. In this way, the filtered signal is a blanking signal, which effectively suppresses negative gyrations with a running time less than the leakage filter time, such as the negative gyration of the leakage ringing portion of the VSW signal. The value of the leakage filter time can be determined as: Leakage filter time = C7_CAPACITANCE * VTH_SCHMITT_454 / IBIAS4.

[0076] In one instance, the following values ​​are used: C7 is 448 femtofarads, IBIAS4 is approximately 2 microamps, and the high threshold (VTH_SCHMITT_454) of the Schmitt trigger 454 is 1.25 volts. This causes the filtered signal to transition to its high state approximately 280 ns after the gyrocomparator signal from comparator 434 goes low. More generally, the leakage filter time can be set to some time between the signal period of the leakage ringing section and the signal period of the magnetized ringing section. More specifically, according to some examples, the slowest frequency of the leakage ringing section is approximately two times or more faster than the fastest frequency of the magnetized ringing section, such that the shortest signal period of the magnetized ringing section is approximately two times or more longer than the longest signal period of the leakage ringing section. In this way, the value of the leakage filter time can be set to be greater than the signal period of the leakage ringing section but less than the signal period of the magnetized ringing section. These signal periods can vary depending on the power converter configuration and can be determined empirically or theoretically (e.g., circuit modeling and analysis). Other instances may use different logic or be configured in other ways to provide similar functionality. While in this example, leakage filter 436 provides a fixed leakage filter time, in other examples it can be configured to provide an adjustable leakage filter time. For example, leakage filter 436 can be configured to increase the leakage filter time by selectively adding more capacitors to increase the leakage filter duration as needed to blank leakage ringing.

[0077] Figure 5A The example shown is when the OVP condition exists. Figure 1 A diagram of the signals generated by the system. (Reference) Figure 4A This can further enhance understanding, and the relevant descriptions above also apply here. Figure 5AThe first (topmost) graph shows the VSW signal from the switching node SW of the power converter (e.g., system 100). In this example, the VSW signal is in the range of approximately 0 volts to approximately 300 volts. The second graph, starting from the top, shows the output voltage VOUT of the power converter. As shown, VOUT exceeds the OVP threshold (e.g., 25 volts) at approximately 5.801 milliseconds. The third and fourth graphs, starting from the top, are superimposed on each other and show the VIN+N*VOUT (scaled) voltage at the non-inverting input of comparator 420 and the VIN(AVG)+N*VREF (scaled) voltage at the inverting input of comparator 420. As shown, at approximately 5.801 milliseconds, the VIN+N*VOUT (scaled) voltage is greater than the VIN(AVG)+N*VREF (scaled) voltage. The fifth graph, starting from the top, shows the pre-OVP signal at the output of comparator 420 going high at approximately 5.801 milliseconds, thus signaling a possible OVP condition. The sixth figure from the top shows the OVP detection signal at the output of AND gate 432 going high in approximately 5.87 milliseconds, thus formally declaring the OVP state. Based on the delay provided by delayer 422, in this example, the delay from the pre-OVP signal going high to the OVP detection signal going high is approximately 69 microseconds. Although not shown, the voltage scale (y-axis) of the OVP detection signal can be the same as the pre-OVP signal (e.g., approximately 0 volts for the low state and approximately 5 volts for the high state).

[0078] Figure 5B The example shown is when an input voltage surge condition exists. Figure 1 A diagram of the signals generated by the system. (Reference) Figure 4A This can further enhance understanding, and the relevant descriptions above also apply here. Figure 5BThe first and second figures, starting from the top, are superimposed on each other and show the VSW signal from the switching node SW of the power converter (e.g., system 100) and the input voltage VIN. In this example: the VSW signal ranges from approximately 0 volts to approximately 542 volts until a surge occurs and causes the VSW signal to increase high to approximately 617 volts; and the VIN range initially starts from approximately 390 volts and then increases to approximately 504 volts during the surge condition. The third and fourth figures, starting from the top, are superimposed on each other and show the VIN+N*VOUT (scaling) voltage at the non-inverting input of comparator 420 and the VIN(AVG)+N*VREF (scaling) voltage at the inverting input of comparator 420. As shown, the VIN+N*VOUT (scaling) voltage is initially less than the VIN(AVG)+N*VREF (scaling) voltage, but then the surge condition begins at approximately 5.5 milliseconds, causing VIN+N*VOUT (scaling) to become greater than the VIN(AVG)+N*VREF (scaling) voltage. Figures 5 and 6, starting from the top, are superimposed on each other and show the VIN_SURGE_REF (scaled) voltage at the inverting input of comparator 430 (provided by sample and hold 428) and the VIN(AVG) (scaled) voltage at the non-inverting input of comparator 430. Figure 7, starting from the top, shows the pre-OVP signal at the output of comparator 420 going high at approximately 5.522 milliseconds, thereby signaling a possible OVP condition. Figure 8, starting from the top, shows the surge detection signal at the output of comparator 430 going high at approximately 5.537 milliseconds, thereby formally declaring an input voltage surge condition, which is suppressed by the operation of AND gate 432 (and the inverting input from comparator 430). In this example, the delay from the pre-OVP signal going high to the surge detection signal going high is approximately 15 microseconds, which is within the delay provided by delayer 422.

[0079] method

[0080] Figure 6 A flowchart illustrating an example of an OVP (Optical Power Verification) method for a flyback power converter is shown. For instance, the method can be implemented via... Figure 1 The method described is applicable to system 100, but other systems that can use the VSW signal at the switching node of a given system for overvoltage protection can also benefit from the method.

[0081] At 601, the method includes receiving a signal from the switch terminal (VSW). The signal includes a leakage reset time portion (T). RESET Leaking ringing parts and magnetized ringing parts, for example Figure 2As illustrated above. In some instances where the VSW signal is in a high-voltage domain, the method may further include: at 603, scaling the VSW signal to a low-voltage domain. More generally, scaling may involve converting the VSW signal from a first voltage domain or level to a second voltage domain or level, the method being configured to operate in the second voltage domain or level. For example, see the reference above. Figure 3 and 4A The described example scaling circuit 301 is used to perform this scaling. Any other suitable scaling circuit may also be used.

[0082] At 605, the method continues by low-pass filtering the VSW signal (and scaling, if applicable) to obtain the running average input voltage value VIN(AVG). For example, see the reference above. Figure 3 and 4A The described example VIN detection circuit 303 is used for this low-pass filtering. Any other circuit system configured to provide an average value for the VSW signal can also be used.

[0083] At position 607, the method continues to sample the horizontal region of the VSW signal to obtain VIN+N*VOUT. For example, see the reference above. Figure 3 and 4A This sampling is performed using the OVP and surge detection circuit 307 described in example 4C. In some such cases, the sampling can be gated by circuitry configured to detect the occurrence of the flat-line portion of the VSW signal, such as the circuitry described above. Figure 3 , 4A The example slewing detection circuit 305 described in 4D. Any other circuitry configured to sample the flat portion of the VSW signal can also be used to compare it to a reference voltage reflecting the OVP voltage limit.

[0084] At 609, the method continues to determine whether VIN + N*VOUT is greater than VIN(AVG) + N*VREF to assess whether an OVP condition may exist. For example, this determination can be made using a comparator (e.g., comparator 420). If VIN + N*VOUT is not greater than VIN(AVG) + N*VREF, then an OVP condition does not exist, and the method returns to the sampling at 607 to continue monitoring for possible OVP conditions. However, if VIN + N*VOUT is greater than VIN(AVG) + N*VREF, then an OVP condition may exist, and the method continues to assess whether a possible OVP condition could be caused by an input surge condition.

[0085] More specifically, at 611, the method continues to determine whether VIN(AVG) is greater than VIN_SURGE_REF (which is a sample of VIN(AVG) adjusted by voltage to reflect surge conditions) to assess whether an input voltage surge condition may exist. For example, this determination can be made using a comparator (e.g., comparator 430). If VIN(AVG) is not greater than VIN_SURGE_REF, then no input voltage surge condition exists, and the method continues to 613, where it indicates (or declares or confirms) that a possible OVP condition is a true OVP condition. However, if VIN(AVG) is greater than VIN_SURGE_REF, then an input voltage surge condition exists, and the method continues to 615, where the input voltage surge condition is indicated and the indication of an OVP condition is suppressed. For example, this can be achieved by referring to the above... Figure 3 and 4A The OVP and surge detection circuit 307 described in 4C is used for this indication and suppression. Any other circuitry configured to indicate a possible OVP condition when an input voltage surge condition is present, but to declare an OVP condition in other situations, may also be used.

[0086] Power System

[0087] Figure 7 A block diagram of a system 700, as shown in the example, includes a flyback power converter configured for overvoltage protection without the use of an auxiliary winding. As illustrated, system 700 includes a damper 710, a flyback transformer 711, an EMI filter 715, a rectifier 717, an AC sensing circuit 718, a synchronous rectifier transistor QSR, a synchronous rectifier (SR) controller 720, an output capacitor COUT, an output transistor QOUT, a port 722, a feedback circuit 713 including a USB-PD controller 724 and an optocoupler 726, and a controller 728 including an IC 101. In this example, system 700 converts an AC input voltage (VAC) to a DC input voltage (VIN), which is then converted by the flyback power converter to a regulated DC output voltage (VOUT). VOUT is coupled to port 722, to which a load can be coupled. In other examples, the DC input voltage VIN is obtained directly, rather than from the AC input voltage VAC.

[0088] EMI filter 715 removes unwanted noise from the line voltage, rectifier 717 rectifies the AC input, and AC sensing circuit 718 allows controller 728 to detect the presence of VAC. Any suitable EMI filter, rectifier, and sensing circuit system can be used. Other examples may directly apply VIN instead of obtaining it from the AC source shown. In these cases, system 700 may not include VAC, EMI filter 115, rectifier 117, or AC sensing circuit 718. Transformer 711 allows energy storage, energy transfer, and current isolation between input VIN and output VOUT. Any suitable flyback transformer can be used. In this example, flyback transformer 111 does not include any auxiliary winding for OVP. Other examples may include one or more auxiliary windings, for example, to provide an alternative for OVP and / or for providing trough sensing and / or bias power. Damper 710 provides clamping voltage VCLAMP and can be implemented by any suitable damping circuit. QSR and SR controller 720 jointly provide a synchronous rectifier (not...) Figure 1 The DOUT in the topology can be used to improve the efficiency of flyback topologies.

[0089] Capacitor COUT is referenced above. Figure 1 The operation is similar to that described herein. In this example, port 722 is a type-C USB port, and controller 724 is a USB-PD controller. Other general-purpose and proprietary port technologies can be used. For example, if an overvoltage condition or a high current condition is detected, QOUT can be used to disconnect the load in response to the control of controller 724. Optocoupler 726 provides the feedback voltage VFB from the secondary to the primary in an isolated manner. Controller 728 can be implemented by any suitable flyback converter control circuitry and is further configured with IC 101 so that controller 728 can provide overvoltage protection based on the VSW signal received at the SW terminal without the use of an auxiliary winding, as described differently herein. In this example, controller 728 may further include a switching element coupled between SW and ground, and may also include sensing circuitry (e.g., Figure 1 (As shown in 109 and 108). In other instances, the switching elements (and sensing circuitry, if present) may be implemented externally to the controller 728.

[0090] Other examples

[0091] Example 1 is a circuit comprising: a first comparator configured to generate a first indication of an overvoltage protection (OVP) condition of a flyback power converter using a switching terminal signal of the flyback power converter; a second comparator configured to generate a second indication of an input voltage surge condition of the flyback power converter using a switching terminal signal of the flyback power converter; and logic circuitry configured to suppress the first indication from the first comparator in response to the second indication from the second comparator.

[0092] Example 2 includes the circuit according to Example 1, wherein: a first comparator is configured to compare VIN+N*VOUT with VIN(AVG)+N*VREF, and to indicate an OVP condition in response to VIN+N*VOUT being greater than VIN(AVG)+N*VREF, wherein VIN corresponds to the input voltage of the flyback power converter, VIN(AVG) corresponds to the operating average input voltage of the flyback power converter, N corresponds to the turns ratio of the flyback power converter, VOUT corresponds to the output voltage of the flyback power converter, and VREF corresponds to the voltage limit of the flyback power converter; and a second comparator is configured to compare VIN(AVG) with a sample of the voltage-adjusted operating average input voltage, and to indicate an input voltage surge condition in response to VIN(AVG) being greater than the sample of the voltage-adjusted operating average input voltage.

[0093] Example 3 includes the circuit according to Example 2, and further includes a sampling and holding circuit configured to sample the voltage-adjusted operating average input voltage in response to an OVP state indicated by a first comparator, and to provide a sample of the voltage-adjusted operating average input voltage to the input of a second comparator.

[0094] Example 4 includes the circuit described in Example 2 or 3, wherein each of the switch terminal signals, VIN+N*VOUT, VIN(AVG), and samples of the voltage-adjusted operating average input voltage is scaled by a scaling factor.

[0095] Example 5 includes a circuit according to any one of Examples 1 to 4, wherein the logic circuit has a first input coupled to the output of a first comparator and a second input coupled to the output of a second comparator, the logic circuit being configured to indicate an OVP state in response to signals at its first and second inputs.

[0096] Example 6 includes the circuit according to Example 5, wherein a first input of the logic circuit is coupled to the output of a first comparator via a delay circuit, and the delay circuit is configured to provide a delay inversely proportional to the input voltage of the flyback power converter.

[0097] Example 7 includes a circuit according to any one of Examples 1 to 6, wherein the logic circuit includes: an inverter having an input coupled to the output of a second comparator; and an AND gate having a first input coupled to the output of a first comparator and a second input coupled to the output of the inverter.

[0098] Example 8 includes the circuit described in any one of Examples 1 to 7, and further includes: a low-pass filter circuit configured to low-pass filter the switching terminal signal of the flyback power converter to obtain the operating average input voltage of the flyback power converter, wherein the operating average input voltage is used by a first comparator to determine whether an OVP condition exists and by a second comparator to determine whether an input voltage surge condition exists.

[0099] Example 9 includes the circuit described in Example 8, wherein the low-pass filter circuit has a cutoff frequency that is proportional to the input voltage of the flyback power converter.

[0100] Example 10 includes the circuit described in any one of Examples 1 to 9, and further includes: a scaling circuit configured to scale the switching terminal signal of the flyback power converter by a scaling factor to obtain a scaled version of the switching terminal signal; wherein a first comparator uses the scaled version of the switching terminal signal to determine whether an OVP condition exists, and a second comparator uses the scaled version of the switching terminal signal to determine whether an input voltage surge condition exists.

[0101] Example 11 includes the circuit described in any one of Examples 1 to 10, and further includes: a sampling and holding circuit configured to sample the voltage of a flat-line portion of a switch terminal signal of a flyback power converter, the flat-line portion being located between a leakage ringing portion and a magnetized ringing portion of the switch terminal signal, wherein a first comparator uses the sampled voltage of the flat-line portion to determine whether an OVP condition exists.

[0102] Example 12 includes the circuit according to Example 11, and further includes: a rotation detection circuit configured to detect a negative rotation of the switch terminal signal occurring at the end of the flat region portion of the switch terminal signal, and to generate a sampling control signal in response to the detected negative rotation; wherein the sampling and holding circuit samples the voltage of the flat region portion in response to the sampling control signal.

[0103] Example 13 includes the circuit described in Example 11 or 12, wherein the sampled voltage of the flat region corresponds to VIN+N*VOUT, where VIN corresponds to the input voltage of the flyback power converter, N corresponds to the turns ratio of the flyback power converter, and VOUT corresponds to the output voltage of the flyback power converter.

[0104] Example 14 is a circuit comprising: a first circuit configured to scale a switching terminal signal of a flyback power converter by a scaling factor to generate a scaled version of the switching terminal signal; a second circuit configured to determine an operating average input voltage of the flyback power converter based on the scaled version of the switching terminal signal; and a third circuit configured to use the operating average input voltage to determine whether both an overvoltage protection (OVP) condition and an input voltage surge condition exist in the flyback power converter, and to suppress an indication of an OVP condition in response to the presence of an input voltage surge condition.

[0105] Example 15 includes the circuit described in Example 14, wherein the third circuit includes: a first comparator configured to indicate an OVP condition; a second comparator configured to indicate an input voltage surge condition; and logic circuitry configured to suppress the indication of the first comparator to the OVP condition in response to the indication of the second comparator to the input voltage surge condition.

[0106] Example 16 includes the circuit according to Example 15, wherein a first input of the logic circuit is coupled to the output of a first comparator via a delay circuit, and the delay circuit is configured to provide a delay inversely proportional to the input voltage of the flyback power converter, and a second input of the logic circuit is coupled to the output of a second comparator via an inverter.

[0107] Example 17 includes the circuit described in Example 14 or 15, wherein the third circuit includes a sampling and holding circuit configured to sample the voltage of a flat-line portion of the switching terminal signal of a flyback power converter, the flat-line portion being located between a leakage ringing portion and a magnetized ringing portion of the switching terminal signal, wherein a first comparator uses the sampled voltage of the flat-line portion to determine whether an OVP condition exists.

[0108] Example 18 includes the circuit according to Example 17, and further includes: a fourth circuit configured to detect a negative rotation of the switch terminal signal occurring at the end of the flat region portion of the switch terminal signal, and to generate a sampling control signal in response to the detected negative rotation; wherein sampling performed by the sampling and holding circuit is gated by the sampling control signal.

[0109] Example 19 is a method comprising: comparing VIN+N*VOUT with VIN(AVG)+N*VREF, wherein VIN corresponds to the input voltage of the flyback power converter, VIN(AVG) corresponds to the operating average input voltage of the flyback power converter, N corresponds to the turns ratio of the flyback power converter, VOUT corresponds to the output voltage of the flyback power converter, and VREF corresponds to the voltage limit of the flyback power converter; and in response to VIN+N*VOUT being greater than VIN(AVG)+N*VREF, comparing VIN(AVG) with a sample of the voltage-regulated operating average input voltage; indicating an input voltage surge condition in response to a sample of VIN(AVG) being greater than the voltage-regulated operating average input voltage; and indicating an overvoltage protection condition in response to a sample of VIN(AVG) not being greater than the voltage-regulated operating average input voltage.

[0110] Example 20 includes the method according to Example 19, wherein: in response to VIN+N*VOUT not being greater than VIN(AVG)+N*VREF, the method includes not indicating an overvoltage protection condition, not indicating an input voltage surge condition, and continuing to monitor overvoltage conditions and input voltage surge conditions; and in response to a sample of VIN(AVG) being greater than the voltage-adjusted operating average input voltage, the method includes indicating suppression of an overvoltage condition.

[0111] Example 21 includes the method according to Example 19 or 20, and further includes: receiving a switching terminal signal of a flyback power converter, the switching terminal signal including a leakage reset portion, a leakage ringing portion, and a magnetization ringing portion; low-pass filtering the switching terminal signal to obtain VIN(AVG); and sampling the voltage of the switching terminal signal between the leakage ringing portion and the magnetization ringing portion to obtain VIN+N*VOUT.

[0112] Example 22 includes the method according to Example 21, wherein before comparing VIN+N*VOUT with VIN(AVG)+N*VREF, the method includes scaling the switch terminal signal by a scaling factor, and wherein each of VIN+N*VOUT, VIN(AVG), and a sample of the voltage-adjusted operating average input voltage is scaled by the scaling factor.

[0113] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0114] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. This configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.

[0115] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0116] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0117] While the use of specific transistors is described herein, other transistors (or equivalent devices) can be used alternatively. For example, a p-channel field-effect transistor (PFET) can be used instead of an n-channel field-effect transistor (NFET) with little or no change to the circuit. Furthermore, other types of transistors (such as bipolar junction transistors (BJTs)) can be used. Additionally, the device can be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate, to name just a few.

[0118] In this article, "FET" being "on" means that there is a conduction channel in the FET and drain current can flow through it. "FET" being "off" means that there is no conduction channel and drain current does not flow through it. However, an off-state FET can still have current flowing through its body diode.

[0119] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. In another instance, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0120] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of said parameter.

[0121] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A circuit comprising: a first comparator configured to use a switch terminal signal of a flyback power converter to produce a first indication of an overvoltage protection (OVP) condition of the flyback power converter; a second comparator configured to use the switch terminal signal of the flyback power converter to produce a second indication of an input voltage surge condition of the flyback power converter; and a logic circuit configured to suppress the first indication from the first comparator in response to the second indication from the second comparator.

2. The circuit of claim 1, wherein: the first comparator is configured to compare VIN+N*VOUT to VIN(AVG)+N*VREF, and indicate an OVP condition in response to VIN+N*VOUT being greater than VIN(AVG)+N*VREF, where VIN corresponds to an input voltage of the flyback power converter, VIN(AVG) corresponds to a running average input voltage of the flyback power converter, N corresponds to a turns ratio of the flyback power converter, VOUT corresponds to an output voltage of the flyback power converter, and VREF corresponds to a voltage limit of the flyback power converter; and the second comparator is configured to compare VIN(AVG) to a sample of the running average input voltage adjusted by a voltage, and indicate an input voltage surge condition in response to VIN(AVG) being greater than the sample of the running average input voltage adjusted by the voltage.

3. The circuit of claim 2, comprising a sample and hold circuit configured to sample the running average input voltage adjusted by the voltage in response to the first comparator indicating the OVP condition, and provide the sample of the running average input voltage adjusted by the voltage to an input of the second comparator.

4. The circuit of claim 2, wherein each of the switch terminal signal, VIN+N*VOUT, VIN(AVG), and the sample of the running average input voltage adjusted by the voltage are scaled by a scaling factor.

5. The circuit of claim 1, wherein the logic circuit has a first input coupled to an output of the first comparator and a second input coupled to an output of the second comparator, the logic circuit configured to indicate the OVP condition in response to signals at its first and second inputs.

6. The circuit of claim 5, wherein the first input of the logic circuit is coupled to the output of the first comparator via a delay circuit, and the delay circuit is configured to provide a delay inversely proportional to an input voltage of the flyback power converter.

7. The circuit of claim 1, wherein the logic circuit includes: an inverter having an input coupled to an output of the second comparator; and an AND gate having a first input coupled to an output of the first comparator and a second input coupled to an output of the inverter.

8. The circuit of claim 1, comprising: ​ a low pass filter circuit configured to low pass filter the switch terminal signal of the flyback power converter to obtain a running average input voltage of the flyback power converter, wherein the running average input voltage is used by the first comparator to determine whether the OVP condition exists and is used by the second comparator to determine whether the input voltage surge condition exists.

9. The circuit of claim 8, wherein the low pass filter circuit has a cutoff frequency that is proportional to an input voltage of the flyback power converter.

10. The circuit of claim 1, comprising: a scaling circuit configured to scale the switch terminal signal of the flyback power converter by a scaling factor to obtain a scaled version of the switch terminal signal; wherein the first comparator uses the scaled version of the switch terminal signal to determine whether the OVP condition exists and the second comparator uses the scaled version of the switch terminal signal to determine whether the input voltage surge condition exists.

11. The circuit of claim 1, comprising: a sample and hold circuit configured to sample a voltage of a flat section of the switch terminal signal of the flyback power converter, the flat section being between a leak ring portion of the switch terminal signal and a magnetization ring portion of the switch terminal signal, wherein the first comparator uses the sampled voltage of the flat section to determine whether the OVP condition exists.

12. The circuit of claim 11, comprising: a turn detection circuit configured to detect a negative turn of the switch terminal signal that occurs at an end of the flat section of the switch terminal signal and to generate a sample control signal in response to the detected negative turn; wherein the sample and hold circuit samples the voltage of the flat section in response to the sample control signal.

13. The circuit of claim 11, wherein the sampled voltage of the flat section corresponds to VIN + N*VOUT, where VIN corresponds to an input voltage of the flyback power converter, N corresponds to a turns ratio of the flyback power converter, and VOUT corresponds to an output voltage of the flyback power converter.

14. A circuit, comprising: a first circuit configured to scale a switch terminal signal of a flyback power converter by a scaling factor to produce a scaled version of the switch terminal signal; a second circuit configured to determine a running average input voltage of the flyback power converter based on the scaled version of the switch terminal signal; and a third circuit configured to use the running average input voltage to determine whether both an overvoltage protection (OVP) condition and an input voltage surge condition exist in the flyback power converter and to suppress an indication of the OVP condition in response to the input voltage surge condition existing.

15. The circuit of claim 14, wherein the third circuit includes: a first comparator configured to indicate the OVP condition; a second comparator configured to indicate the input voltage surge condition; and a logic circuit configured to suppress the indication of the OVP condition by the first comparator in response to the indication of the input voltage surge condition by the second comparator.

16. The circuit of claim 15, wherein a first input of the logic circuit is coupled to an output of the first comparator via a delay circuit, and the delay circuit is configured to provide a delay inversely proportional to an input voltage of the flyback power converter, and a second input of the logic circuit is coupled to an output of the second comparator via an inverter.

17. The circuit of claim 15, wherein the third circuit includes: a sample-and-hold circuit configured to sample a voltage of a flat section of the switch terminal signal of the flyback power converter, the flat section being between a leaky ring portion of the switch terminal signal and a magnetization ring portion of the switch terminal signal, wherein the first comparator uses the sampled voltage of the flat section to determine whether the OVP condition exists.

18. The circuit of claim 17, comprising: a fourth circuit configured to detect a negative turn of the switch terminal signal occurring at an end of the flat section of the switch terminal signal, and generate a sample control signal in response to the detected negative turn; wherein the sampling by the sample-and-hold circuit is gated by the sample control signal.

19. A method comprising: comparing VIN+N*VOUT to VIN(AVG)+N*VREF, where VIN corresponds to an input voltage of a flyback power converter, VIN(AVG) corresponds to a running average input voltage of the flyback power converter, N corresponds to a turns ratio of the flyback power converter, VOUT corresponds to an output voltage of the flyback power converter, and VREF corresponds to a voltage limit of the flyback power converter; and in response to VIN+N*VOUT being greater than VIN(AVG)+N*VREF, comparing VIN(AVG) to a sample of the running average input voltage adjusted by a voltage; in response to VIN(AVG) being greater than the sample of the running average input voltage adjusted by the voltage, indicating an input voltage surge condition; and in response to VIN(AVG) not being greater than the sample of the running average input voltage adjusted by the voltage, indicating an over-voltage protection condition.

20. The method of claim 19, wherein: in response to VIN+N*VOUT not being greater than VIN(AVG)+N*VREF, the method includes not indicating the over-voltage protection condition, not indicating the input voltage surge condition, and continuing to monitor the over-voltage condition and the input voltage surge condition; and in response to VIN(AVG) being greater than the sample of the running average input voltage adjusted by the voltage, the method includes suppressing the indication of the over-voltage condition.

21. The method of claim 19, comprising: receiving a switch terminal signal of the flyback power converter, the switch terminal signal including a leakage reset portion, a leakage ring portion, and a magnetization ring portion; low pass filtering the switch terminal signal to obtain VIN(AVG); and sampling a voltage of the switch terminal signal between the leakage ring portion and the magnetization ring portion to obtain VIN+N*VOUT.

22. The method of claim 21, wherein prior to comparing VIN+N*VOUT to VIN(AVG)+N*VREF, the method includes scaling the switch terminal signal by a scaling factor, and wherein each of VIN+N*VOUT, VIN(AVG), and the sample of the running average input voltage adjusted by the voltage are scaled by the scaling factor.

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