FPGA routing congestion prediction method based on heterogeneous graph neural network

Abstract

The invention discloses an FPGA routing congestion prediction method based on a heterogeneous graph neural network, and the method comprises the steps: obtaining a netlist file in an FPGA design process, extracting the topological information of the file, and constructing a netlist subgraph; fPGA architecture information is obtained, and an architecture subgraph is constructed according to the architecture information; obtaining a layout file in the FPGA design process, extracting position information of each block in the file to construct a spatial mapping edge, and projecting nodes in the netlist sub-graph to the architecture sub-graph through the spatial mapping edge to obtain an integrated heterogeneous graph; constructing a heterogeneous graph neural network matched with the heterogeneous graph, wherein the heterogeneous graph neural network comprises a feature initialization module, a message passing module and a reading module; a data set is constructed according to the heterogeneous graph to train a heterogeneous graph neural network, and a neural network structure search strategy is used to optimize a message passing module; and inputting the heterogeneous graph into the heterogeneous graph neural network to obtain routing congestion information. According to the method, the accuracy of the FPGA routing congestion prediction result can be improved, the generalization ability is higher, and the time for reasoning, training and data preprocessing is shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design automation, and in particular to a FPGA routing congestion prediction method based on heterogeneous graph neural network. BACKGROUND

[0002] The goal of FPGA automated design flow is to transform a circuit behavior description into a physical layout of FPGA. First, logic synthesis transforms the circuit behavior described in hardware description language (HDL) into a gate-level netlist. Then, tech mapping and packing maps and packs the gate-level logic into the logic blocks of FPGA, such as configurable logic blocks (CLB). The placement stage determines the physical location of each logic block on the FPGA layout. The routing stage establishes the physical paths between these logic blocks. It is worth noting that not all placements can be successfully routed for FPGA with limited routing resources, which means that placement and routing is an iterative optimization process.

[0003] With the continuous shrinking of semiconductor process and the increasing complexity of circuit design, the placement and routing (PnR) stage in FPGA automated design flow faces greater and greater challenges. The number of PnR iterations and the time required for each iteration are gradually increasing, which leads to a significant increase in the time cost of FPGA design and optimization. Therefore, it is important to accurately and quickly predict the potential routing congestion of a given placement. This not only helps to avoid unnecessary routing overhead, but also effectively speeds up the PnR process, thereby improving design efficiency.

[0004] Currently, state-of-the-art FPGA routing congestion prediction methods utilize computer vision (CV) models. They transform the routing-related features of FPGA placement and routing into images, which are then input into CV models to generate routing congestion heatmaps. This image transformation relies on geometric space representation, which emphasizes the physical location of circuit elements. However, the existing methods ignore the topological information between circuit elements. In addition, the limited receptive field of the convolution kernel of CV models requires deeper networks to capture the connection relationships of circuits. On the other hand, some VLSI routing congestion prediction graphs based on heterogeneous graph neural networks represent the topology and geometry information of circuits uniformly in heterogeneous graphs. However, they cannot be applied to FPGA because these representations do not take into account the FPGA architecture, although FPGA routing must follow specific architectural paths.

[0005] In addition, existing prediction methods tend to input as many carefully designed routing-related features as possible to help the model understand the circuit, which leads to a large amount of time required for data preprocessing. SUMMARY

[0006] The application provides an FPGA routing congestion prediction method based on a heterogeneous graph neural network to overcome the problem that there is no heterogeneous graph suitable for FPGAs, resulting in ignoring the topological information of the internal connection between circuit elements, slow network prediction speed and insufficient accuracy.

[0007] To achieve the above-mentioned purpose, the technical scheme of the application is:

[0008] An FPGA routing congestion prediction method based on a heterogeneous graph neural network, comprising:

[0009] S1: obtaining a netlist file output in a packaging stage of an FPGA automated design process, extracting topological information of the netlist file to construct a netlist subgraph;

[0010] S2: obtaining FPGA architecture information, and constructing an architecture subgraph according to the FPGA architecture information;

[0011] S3: obtaining a layout file output in a layout stage of the FPGA automated design process, extracting block position information in the layout file to construct a space mapping edge, the space mapping edge projecting nodes in the netlist subgraph onto the architecture subgraph to obtain an integrated heterogeneous graph;

[0012] S4: constructing a heterogeneous graph neural network matching the heterogeneous graph, the heterogeneous graph neural network comprising a feature initialization module, a message passing module and a readout module;

[0013] S5: training the heterogeneous graph neural network according to the data set constructed according to the heterogeneous graph, and optimizing the message passing module in the heterogeneous graph neural network using a neural network structure search strategy;

[0014] S6: inputting the heterogeneous graph into the feature initialization module, processing by the message passing module optimized by the neural network structure search strategy, and obtaining routing congestion information from the readout module.

[0015] Further, obtaining a netlist file output in a packaging stage of an FPGA automated design process, extracting topological information of the netlist file to construct a netlist subgraph, comprises:

[0016] Extracting the topological information of the netlist file comprises configurable logic blocks and input / output blocks in the FPGA netlist, an abstract representation of the network and the connection relationship between blocks and networks in the netlist;

[0017] The configurable logic blocks and input / output blocks are represented as block nodes, the abstract representation of the network is represented as a net node, and the connection relationship between the blocks and the network is represented as a topological edge;

[0018] The topological edges connect all block nodes in the network to their corresponding network nodes according to the topological relationships described in the netlist, and the direction of the topological edges is consistent with the direction of the signals, thus obtaining a netlist subgraph.

[0019] Furthermore, FPGA architecture information is obtained, and an architecture sub-graph is constructed based on the FPGA architecture information, including:

[0020] The FPGA architecture information is represented using a mesh diagram;

[0021] Configurable logic blocks and input / output blocks in the FPGA architecture are represented by grid nodes. Adjacent grid nodes in the vertical and horizontal directions of the geometric space are connected by geometric edges to obtain the architecture subgraph.

[0022] Furthermore, the layout file output during the placement phase of the FPGA automated design flow is obtained, and the position information of each block in the layout file is extracted to construct spatial mapping edges. These spatial mapping edges project the nodes in the netlist subgraph onto the architecture subgraph, resulting in an integrated heterogeneous graph, including:

[0023] Based on the block location information in the layout file, two types of spatial mapping edges are designed. One type is a block mapping edge, which connects the block nodes in the netlist subgraph to the grid nodes corresponding to the positions assigned to them during the layout stage, representing the physical location of each block on the architecture subgraph. The other type is a net mapping edge, which connects the net nodes in the netlist subgraph to multiple grid nodes. All grid nodes are located within the bounding boxes of the net nodes, representing the spatial distribution of the logical network in the physical layout.

[0024] The nodes in the netlist subgraph are projected onto the architecture subgraph using the spatial mapping edges to obtain the integrated heterogeneous graph.

[0025] Furthermore, the node features of the heterogeneous graph include:

[0026] The block node is described by three features, which include: the block type represented by one-hot encoding, the number of signal inputs to the block, and the number of outputs.

[0027] The mesh node is described by four features, which include: the number of meshes covered by the mesh's bounding box in the horizontal direction, the number of meshes covered by the mesh's bounding box in the vertical direction, the number of meshes covered by the mesh's bounding box, and the ratio of the number of blocks within the mesh's bounding box to the number of meshes covered by the mesh's bounding box.

[0028] The grid node is described by a feature, which includes: the grid type represented by one-hot encoding.

[0029] Furthermore, a heterogeneous graph neural network matching the heterogeneous graph is constructed. The heterogeneous graph neural network includes a feature initialization module, a message passing module, and a readout module, comprising:

[0030] The feature initialization module initializes the features of the block nodes, mesh nodes, and grid nodes into corresponding hidden representations using a multilayer perceptron;

[0031] The heterogeneous graph with the embedded hidden representation is input into the messaging module;

[0032] A readout module consisting of a series of fully connected layers and activation functions predicts routing congestion of the circuit from a deep representation of the grid nodes.

[0033] Furthermore, the message passing module includes:

[0034] The message passing module consists of a multi-layered heterogeneous message passing mechanism. Each layer includes three types of message passing functions, heterogeneous aggregation functions, and update functions. The three types of message passing functions include netlist subgraph message passing functions, spatial mapping message passing functions, and architecture subgraph message passing functions.

[0035] The netlist subgraph message passing function is responsible for managing the topology message passing between block nodes and network nodes, as shown in formulas (1) and (2).

[0036]

[0037]

[0038] Where l represents the sequence number of the current message passing layer. This represents the message passing function for the netlist subgraph. Represents a block node, ε t Represents topological edges. This represents the hidden representation of a block node at level l. Indicates network nodes, This represents the hidden representation of a network node at layer l. This indicates that information is aggregated from block nodes of neighboring network nodes through topological edges. This indicates that the message representation of the network node is obtained through this aggregation. This indicates that information is aggregated from network nodes of neighboring block nodes through topological edges. This indicates that the message representation of the block node is obtained through this aggregation;

[0039] The spatial mapping message passing function transmits the hidden representations of block nodes and network nodes to the architecture subgraph through block mapping edges and network mapping edges, respectively, as shown in formulas (3) and (4).

[0040]

[0041]

[0042] in, Represents the space-mapped message passing function, ε mb Represents block mapping edges, ε represents the message passing function for spatial mapping from block nodes to grid nodes. mn Represents the network mapping edge, This represents the message passing function for spatial mapping from network nodes to grid nodes. This represents the message representation of the grid node obtained from the block node. This represents the message representation of the grid node obtained from the grid node;

[0043] The architecture subgraph message passing function handles message passing between mesh nodes, as shown in formula (5).

[0044]

[0045] in, This represents the message passing function of the architecture subgraph. Represents a grid node. ε represents the message passing function between grid nodes. g Represents geometric edges, This represents the message representation of the grid node obtained from the grid node. This represents the hidden representation of a mesh node at layer l.

[0046] After executing the message passing function, the message representation of each node is obtained. The message of each node is aggregated using a heterogeneous aggregation function, and the hidden representation of each node is updated to the next layer using an update function. For grid nodes, the heterogeneous aggregation function will aggregate the hidden representations from different types of nodes, as shown in formula (6).

[0047]

[0048] Where ρ represents the heterogeneous aggregation function and ψ represents the update function.

[0049] Furthermore, the heterogeneous graph neural network is trained based on the dataset constructed from the heterogeneous graph, and the message passing module in the heterogeneous graph neural network is optimized using a neural network architecture search strategy, including:

[0050] The search range for the message passing function is defined as graph convolutional networks, graph attention networks, and graph sampling and aggregation networks. The search range for the heterogeneous aggregation function is defined as linear functions that calculate the average value, linear functions that take the maximum value, linear functions that sum, and learnable linear functions.

[0051] Searching within message passing functions and heterogeneous aggregation functions reveals that the netlist subgraph message passing function is a graph attention network, the spatial mapping message passing function and the architecture subgraph message passing function are graph convolutional networks, and the heterogeneous aggregation function is a learnable linear function.

[0052] Searching for the message passing layer and hidden dimension reveals a message passing layer of 4 and a hidden dimension of 128.

[0053] This invention relates to an FPGA routing congestion prediction method based on heterogeneous graph neural networks. It involves obtaining a netlist file output during the packaging phase of the FPGA automated design process, extracting topology information from the netlist file to construct a netlist subgraph; obtaining FPGA architecture information and constructing an architecture subgraph based on this information; obtaining a layout file output during the placement phase of the FPGA automated design process, extracting the position information of each block in the layout file to construct spatial mapping edges, which project nodes from the netlist subgraph onto the architecture subgraph, resulting in an integrated heterogeneous graph; constructing a heterogeneous graph neural network to match the heterogeneous graph, the heterogeneous graph neural network including a feature initialization module, a message passing module, and a readout module; training the heterogeneous graph neural network using a dataset constructed based on the heterogeneous graph, and optimizing the message passing module using a neural network structure search strategy; and inputting the heterogeneous graph into the heterogeneous graph neural network to obtain routing congestion information. This invention improves the accuracy of FPGA routing congestion prediction results, possesses stronger generalization ability, and faster prediction speed. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a flowchart of the FPGA routing congestion prediction method based on heterogeneous graph neural networks according to the present invention.

[0056] Figure 2 This is a heterogeneous FPGA diagram of the present invention;

[0057] Figure 3 This is the FPGA heterogeneous graph neural network diagram of the present invention;

[0058] Figure 4 A flowchart for creating the dataset of this invention is provided. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] This embodiment provides an FPGA routing congestion prediction method based on heterogeneous graph neural networks, such as... Figure 1 As shown,

[0061] S1: Obtain the netlist file output during the packaging stage of the FPGA automated design process, and extract the topology information of the netlist file to construct a netlist subgraph;

[0062] S2: Obtain FPGA architecture information and construct an architecture sub-graph based on the FPGA architecture information;

[0063] S3: Obtain the layout file output in the layout stage of the FPGA automated design process, extract the position information of each block in the layout file to construct a spatial mapping edge, and project the nodes in the netlist subgraph onto the architecture subgraph to obtain the integrated heterogeneous graph.

[0064] S4: Construct a heterogeneous graph neural network that matches the heterogeneous graph, wherein the heterogeneous graph neural network includes a feature initialization module, a message passing module, and a readout module;

[0065] S5: Train the heterogeneous graph neural network based on the dataset constructed from the heterogeneous graph, and optimize the message passing module in the heterogeneous graph neural network using a neural network structure search strategy;

[0066] S6: Input the heterogeneous graph into the feature initialization module, process it through the message passing module after optimization by the neural network structure search strategy, and obtain the routing congestion information from the readout module.

[0067] Specifically, this solution first obtains the netlist file output during the packaging stage of the FPGA automated design flow, extracts the topology information of the netlist file to construct a netlist subgraph, and then obtains the FPGA architecture information, constructing an architecture subgraph based on the FPGA architecture information. Next, it obtains the layout file output during the placement stage of the FPGA automated design flow, extracts the position information of each block in the layout file to construct spatial mapping edges, and projects the nodes in the netlist subgraph onto the architecture subgraph to obtain an integrated heterogeneous graph. Second, it constructs a heterogeneous graph neural network matching the heterogeneous graph, which includes a feature initialization module, a message passing module, and a readout module. Third, it trains the heterogeneous graph neural network using a dataset constructed based on the heterogeneous graph, and optimizes the message passing module in the heterogeneous graph neural network using a neural network structure search strategy. Finally, it inputs the heterogeneous graph into the feature initialization module, processes it through the message passing module optimized by the neural network structure search strategy, obtains routing congestion information from the readout module, and determines whether to continue FPGA routing based on the routing congestion information. If there is routing congestion, the placement is redone; otherwise, routing continues.

[0068] In a specific embodiment, the scheme for obtaining the netlist file output during the packaging stage of the FPGA automated design flow and extracting the topology information of the netlist file to construct the netlist subgraph is as follows:

[0069] Extract the topology information from the netlist file, including configurable logic blocks and input / output blocks in the FPGA netlist, the abstract representation of the network, and the connection relationships between blocks and networks in the netlist, such as... Figure 2 As shown in (a), IO blocks represent input / output blocks, CLB represents configurable logic blocks, letters a, b, and c are abstract representations of networks, and arrow segments represent the connection relationships between blocks and networks in the netlist.

[0070] The configurable logic blocks and input / output blocks are represented as block nodes, the network abstraction is represented as network nodes, and the connection relationship between the blocks and the network is represented as topological edges, such as... Figure 2 As shown in (b), in the figure, parallelograms represent block nodes, circles represent network nodes, and arrow segments represent topological edges.

[0071] The topological edges connect all block nodes in the network to their corresponding network nodes according to the topological relationships described in the netlist, and the direction of the topological edges is consistent with the direction of the signal, resulting in a netlist subgraph, as shown in the netlist subgraph. Figure 2 As shown in (b).

[0072] In a specific embodiment, the scheme for obtaining FPGA architecture information and constructing an architecture sub-graph based on the FPGA architecture information is as follows:

[0073] The FPGA architecture information is represented using a mesh diagram, such as... Figure 2 As shown in (c), the white squares in the figure represent input / output blocks, the dark squares represent configurable logic blocks, and the remaining lines constitute routing channels.

[0074] Configurable logic blocks and input / output blocks in an FPGA architecture are represented by mesh nodes. Adjacent mesh nodes in the vertical, horizontal, and vertical directions of the geometric space are connected by geometric edges to obtain the architecture sub-graph, such as... Figure 2 As shown in (d), the dashed parallelograms in the figure represent grid nodes, the dashed arrow segments represent geometric edges, and the architecture sub-diagram can represent various FPGA architectures, including different sizes, shapes, and block types.

[0075] Using the two methods described above, the topology information of the circuit and the FPGA architecture can be depicted more comprehensively in the form of heterogeneous diagrams. Compared with traditional circuit representation methods based on visual models, this method can provide richer and more detailed information, thereby more effectively capturing and expressing the complexity and diversity of the circuit, and taking into account the FPGA architecture.

[0076] In a specific embodiment, the layout file output during the placement phase of the FPGA automated design flow is obtained. The position information of each block in the layout file is extracted to construct a spatial mapping edge. The spatial mapping edge projects the nodes in the netlist subgraph onto the architecture subgraph to obtain the integrated heterogeneous graph.

[0077] like Figure 2 As shown in (e), two types of spatial mapping edges are designed based on the block location information in the layout file. One type is a block mapping edge, which connects the block nodes in the netlist subgraph to the grid nodes corresponding to the positions assigned to them during the layout stage, representing the physical location of each block on the architecture subgraph. The other type is a net mapping edge, which connects the net nodes in the netlist subgraph to multiple grid nodes. All grid nodes are located within the bounding boxes of the net nodes, representing the spatial distribution of the logical network in the physical layout.

[0078] The nodes in the netlist subgraph are projected onto the architecture subgraph using the spatial mapping edges to obtain the integrated heterogeneous graph. It means that, among them, Represents a block node. Indicates network nodes, Represents a grid node, ε t Denotes a topological edge, ε g Denotes geometric edges, ε mn Denotes the network mapping edge, ε mb Representing block mapping edges, the integrated heterogeneous graph is as follows: Figure 2 As shown in (f), the overall operation process is as follows: Figure 2 As shown, the FH-Graph is a heterogeneous graph of the FPGA.

[0079] Using this solution, a message passing channel can be established between the netlist subgraph and the architecture subgraph, allowing the circuit's topology information to be projected onto the architecture subgraph, enabling the circuit's topology information to be passed and interacted in the geometric space that conforms to the FPGA architecture.

[0080] In a specific embodiment, the scheme for describing the node characteristics of the heterogeneous graph is as follows:

[0081] A series of routing-related features were extracted from the layout results and netlist topology, as shown in Table 1.

[0082] Table 1 Node Characteristics Table

[0083]

[0084] The block node is described by three features: the block type represented using one-hot encoding, the number of signal inputs to the block, and the number of outputs.

[0085] The network node is described by four characteristics: BB h The bounding box of the mesh covers the number of grid cells in the horizontal direction. v Indicates the number of grids covered by the bounding box in the vertical direction, BB area equals BB h ×BB v This indicates the number of grid cells covered by the bounding box; the block density is the ratio of the number of blocks within the bounding box to the block size. area ratio;

[0086] The grid node is described by a feature: the grid type represented using one-hot encoding.

[0087] Using this approach can reduce the time required to construct heterogeneous graph node features. The features selected in this approach have low computational cost, and when combined with heterogeneous graphs, they can eliminate features with high computational cost, such as RUDY and network density, which are present in previous methods. At the same time, it will only slightly affect the accuracy of route congestion prediction.

[0088] In a specific embodiment, the scheme for constructing a heterogeneous graph neural network that matches the heterogeneous graph, wherein the heterogeneous graph neural network includes a feature initialization module, a message passing module, and a readout module, is as follows:

[0089] The feature initialization module initializes the features of the block nodes, mesh nodes, and grid nodes into corresponding hidden representations using a multilayer perceptron;

[0090] The heterogeneous graph with the embedded hidden representation is input into the messaging module;

[0091] A readout module consisting of a series of fully connected layers and activation functions predicts routing congestion of the circuit from a deep representation of the grid nodes.

[0092] The operation process of heterogeneous graph neural networks is as follows: Figure 3 As shown, the feature initialization module uses a multilayer perceptron to... The features are initialized as the corresponding hidden representations. Subsequently, the heterogeneous graph with the corresponding hidden representation is input into the message passing module. In this module, deep representations of nodes are generated through multi-layer graph representation learning. Finally, the readout module, consisting of a series of fully connected layers and activation functions, predicts the routing congestion of the circuit from the deep representations of the grid nodes.

[0093] In the diagram, parallelograms in the feature initialization module represent the hidden representation of block nodes, circles represent the hidden representation of network nodes, and dashed parallelograms represent the hidden representation of grid nodes. The graph in the readout module is the routing congestion information.

[0094] This approach enables message transmission in both topological and geometric spaces, whereas traditional vision methods can only transmit information in geometric space. This means that the heterogeneous graph neural network in this approach can acquire and understand circuit information more comprehensively, including its topology and physical layout. This comprehensive understanding helps to predict routing congestion more accurately, thereby improving the efficiency and quality of FPGA design.

[0095] In a specific embodiment, the scheme for constructing the message passing module is as follows:

[0096] like Figure 3 As shown in the message passing module, the message passing module consists of a multi-layered heterogeneous message passing mechanism. Each layer includes three types of message passing functions, heterogeneous aggregation functions, and update functions. The three types of message passing functions include netlist subgraph message passing functions, spatial mapping message passing functions, and architecture subgraph message passing functions.

[0097] The netlist subgraph message passing function is responsible for managing topology message passing between block nodes and network nodes, as shown in formulas (7) and (8).

[0098]

[0099]

[0100] Where l represents the sequence number of the current message passing layer. This represents the message passing function for the netlist subgraph. Represents a block node, ε t Represents topological edges. This represents the hidden representation of a block node at level l. Indicates network nodes, This represents the hidden representation of a network node at layer l. This indicates that information is aggregated from block nodes of neighboring network nodes through topological edges. This indicates that the message representation of the network node is obtained through this aggregation. This indicates that information is aggregated from network nodes of neighboring block nodes through topological edges. This indicates that the message representation of the block node is obtained through this aggregation;

[0101] The spatial mapping message passing function transmits the hidden representations of block nodes and network nodes to the architecture subgraph via block mapping edges and network mapping edges, respectively, as shown in equations (9) and (10).

[0102]

[0103]

[0104] in, Represents the space-mapped message passing function, ε mb Represents block mapping edges, ε represents the message passing function for spatial mapping from block nodes to grid nodes. mn Represents the network mapping edge, This represents the message passing function for spatial mapping from network nodes to grid nodes. This represents the message representation of the grid node obtained from the block node. This represents the message representation of the grid node obtained from the grid node;

[0105] The architecture subgraph message passing function handles message passing between mesh nodes, as shown in formula (11).

[0106]

[0107] in, This represents the message passing function of the architecture subgraph. Represents a grid node. ε represents the message passing function between grid nodes. g Represents geometric edges, This represents the message representation of the grid node obtained from the grid node. This represents the hidden representation of a mesh node at layer l.

[0108] After executing the message passing function, the message representation of each node is obtained. The heterogeneous aggregation function is used to aggregate the messages of the nodes, and the update function is used to update the hidden representation of each node to the next layer. For grid nodes, the heterogeneous aggregation function will aggregate the hidden representations from different types of nodes, as shown in formula (12).

[0109]

[0110] Where ρ represents the heterogeneous aggregation function and ψ represents the update function.

[0111] Figure 3 In this context, HAGG&UPD represents heterogeneous aggregation function and update function.

[0112] This approach reduces the number of network layers, accelerating network training and inference time. Because the receptive field of convolutional kernels in visual networks is limited, deeper networks are needed to capture the topological information of circuits. This approach represents the circuit topology in a netlist subgraph when constructing the heterogeneous graph; during message passing, the circuit topology information is also passed. Therefore, this approach eliminates the need for a separate network layer to capture the circuit topology.

[0113] In a specific embodiment, the scheme for training the heterogeneous graph neural network based on the dataset constructed from the heterogeneous graph, and optimizing the message passing module in the heterogeneous graph neural network using a neural network architecture search strategy is as follows:

[0114] Step 1, Dataset Creation:

[0115] The architecture process of the dataset is as follows Figure 4 As shown, a layout subgraph is first generated from the FPGA architecture. Then, a netlist subgraph is extracted during the packaging stage, and spatial mapping edges are extracted during the layout stage. Finally, labels are generated based on the routing results. The dataset is based on open-source circuit benchmark tests. In this embodiment, 20 different circuits are tested. Before the layout stage, 200 different layouts and corresponding routing schemes are generated for each circuit by modifying random parameters, resulting in a variety of different heterogeneous graphs and routing congestion information.

[0116] A random selection strategy was adopted, allocating 80% of the data for each circuit layout to the training set and 20% of the data for the test set. All the data from the training set and the test set were eventually organized into a deep graph library dataset for further analysis and model training.

[0117] Meanwhile, to further evaluate the model's predictive ability when dealing with previously unseen circuits, this embodiment selects another 10 completely different circuits and uses the same method to generate 20 heterogeneous graphs for each circuit to form an auxiliary test set.

[0118] The second step involves optimizing the message passing module in the heterogeneous graph neural network using a neural architecture search strategy.

[0119] The search space in constructing the neural architecture search strategy: the search range of the message passing function is popular graph neural networks such as graph convolutional networks, graph attention networks, and graph sampling and aggregation networks; the search range of the heterogeneous aggregation function is linear functions that calculate the average, linear functions that take the maximum value, linear functions that sum, and learnable linear functions.

[0120] Construct a search strategy: Search within message passing functions and aggregation functions, and select the three best-performing groups; based on these three groups, perform another search to determine the optimal number of message passing layers and hidden dimensions;

[0121] Based on the search strategy, the architecture configuration of the message passing module is determined as follows: the netlist subgraph message passing function in the message passing function is a graph attention network, the spatial mapping message passing function and the architecture subgraph message passing function are graph convolutional networks, the heterogeneous aggregation function is a learnable linear function, the number of message passing layers is 4, and the hidden dimension is 128.

[0122] This approach generates more diverse layouts and corresponding routing schemes for each circuit by modifying the random parameters during the layout phase, resulting in richer and more varied data, which helps improve the model's generalization ability. Furthermore, the message passing module is optimized using an architecture search strategy. By automatically searching for the optimal network architecture, network performance can be effectively improved while reducing the workload of manually adjusting network parameters.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for predicting FPGA routing congestion based on heterogeneous graph neural networks, characterized in that, include: S1: Obtain the netlist file output during the packaging stage of the FPGA automated design process, and extract the topology information of the netlist file to construct a netlist subgraph; S2: Obtain FPGA architecture information and construct an architecture sub-graph based on the FPGA architecture information; S3: Obtain the layout file output in the layout stage of the FPGA automated design process, extract the position information of each block in the layout file to construct a spatial mapping edge, and project the nodes in the netlist subgraph onto the architecture subgraph to obtain the integrated heterogeneous graph. S4: Construct a heterogeneous graph neural network that matches the heterogeneous graph, wherein the heterogeneous graph neural network includes a feature initialization module, a message passing module, and a readout module; S5: Train the heterogeneous graph neural network based on the dataset constructed from the heterogeneous graph, and optimize the message passing module in the heterogeneous graph neural network using a neural network structure search strategy; S6: Input the heterogeneous graph into the feature initialization module, process it through the message passing module after optimization by the neural network structure search strategy, and obtain the routing congestion information from the readout module.

2. The FPGA routing congestion prediction method based on heterogeneous graph neural networks according to claim 1, characterized in that, S1 describes obtaining the netlist file output during the packaging stage of the FPGA automated design flow, and extracting the topology information from the netlist file to construct a netlist subgraph, including: Extract the topology information of the netlist file, including configurable logic blocks and input / output blocks in the FPGA netlist, the abstract representation of the network, and the connection relationship between blocks and networks in the netlist; The configurable logic blocks and input / output blocks are represented as block nodes, the network abstraction is represented as network nodes, and the connection relationship between the blocks and the network is represented as topological edges; The topological edges connect all block nodes in the network to their corresponding network nodes according to the topological relationships described in the netlist, and the direction of the topological edges is consistent with the direction of the signals, thus obtaining a netlist subgraph.

3. The FPGA routing congestion prediction method based on heterogeneous graph neural networks according to claim 1, characterized in that, S2 describes obtaining FPGA architecture information and constructing an architecture sub-graph based on the FPGA architecture information, including: The FPGA architecture information is represented using a mesh diagram; Configurable logic blocks and input / output blocks in the FPGA architecture are represented by grid nodes. Adjacent grid nodes in the vertical and horizontal directions of the geometric space are connected by geometric edges to obtain the architecture subgraph.

4. The FPGA routing congestion prediction method based on heterogeneous graph neural networks according to claim 1, characterized in that, S3 describes obtaining the layout file output during the placement phase of the FPGA automated design process, extracting the position information of each block in the layout file to construct spatial mapping edges, and projecting the nodes in the netlist subgraph onto the architecture subgraph to obtain an integrated heterogeneous graph, including: Based on the block location information in the layout file, two types of spatial mapping edges are designed. One type is a block mapping edge, which connects the block nodes in the netlist subgraph to the grid nodes corresponding to the positions assigned to them during the layout stage, representing the physical location of each block on the architecture subgraph. The other type is a net mapping edge, which connects the net nodes in the netlist subgraph to multiple grid nodes. All grid nodes are located within the bounding boxes of the net nodes, representing the spatial distribution of the logical network in the physical layout. The nodes in the netlist subgraph are projected onto the architecture subgraph using the spatial mapping edges to obtain the integrated heterogeneous graph.

5. The FPGA routing congestion prediction method based on heterogeneous graph neural networks according to claim 3, characterized in that, The node features of the heterogeneous graph include: The block node is described by three features, which include: the block type represented by one-hot encoding, the number of signal inputs to the block, and the number of outputs. The mesh node is described by four features, which include: the number of meshes covered by the mesh's bounding box in the horizontal direction, the number of meshes covered by the mesh's bounding box in the vertical direction, the number of meshes covered by the mesh's bounding box, and the ratio of the number of blocks within the mesh's bounding box to the number of meshes covered by the mesh's bounding box. The grid node is described by a feature, which includes: the grid type represented using one-hot encoding.

6. The FPGA routing congestion prediction method based on heterogeneous graph neural networks according to claim 1, characterized in that, S4 describes constructing a heterogeneous graph neural network that matches the heterogeneous graph. The heterogeneous graph neural network includes a feature initialization module, a message passing module, and a readout module, comprising: The feature initialization module initializes the features of the block nodes, mesh nodes, and grid nodes into corresponding hidden representations using a multilayer perceptron; The heterogeneous graph with the embedded hidden representation is input into the messaging module; A readout module consisting of a series of fully connected layers and activation functions predicts routing congestion of the circuit from a deep representation of the grid nodes.

7. The FPGA routing congestion prediction method based on heterogeneous graph neural networks according to claim 5, characterized in that, The message passing module includes: The message passing module consists of a multi-layered heterogeneous message passing mechanism. Each layer includes three types of message passing functions, heterogeneous aggregation functions, and update functions. The three types of message passing functions include netlist subgraph message passing functions, spatial mapping message passing functions, and architecture subgraph message passing functions. The netlist subgraph message passing function is responsible for managing the topology message passing between block nodes and network nodes, as shown in formulas (1) and (2). Where l represents the sequence number of the current message passing layer. This represents the message passing function for the netlist subgraph. Represents a block node, ε t Represents topological edges. This represents the hidden representation of a block node at level l. Indicates network nodes, This represents the hidden representation of a network node at layer l. This indicates that information is aggregated from block nodes of neighboring network nodes through topological edges. This indicates that the message representation of the network node is obtained through this aggregation. This indicates that information is aggregated from network nodes of neighboring block nodes through topological edges. This indicates that the message representation of the block node is obtained through this aggregation; The spatial mapping message passing function transmits the hidden representations of block nodes and network nodes to the architecture subgraph through block mapping edges and network mapping edges, respectively, as shown in formulas (3) and (4). in, Represents the space-mapped message passing function, ε mb Represents block mapping edges, ε represents the message passing function for spatial mapping from block nodes to grid nodes. mn Represents the network mapping edge, This represents the message passing function for spatial mapping from network nodes to grid nodes. This represents the message representation of the grid node obtained from the block node. This represents the message representation of the grid node obtained from the grid node; The architecture subgraph message passing function handles message passing between mesh nodes, as shown in formula (5). in, This represents the message passing function of the architecture subgraph. Represents a grid node. ε represents the message passing function between grid nodes. g Represents geometric edges, This represents the message representation of the grid node obtained from the grid node. This represents the hidden representation of a mesh node at layer l. The message passing function is executed to obtain the message representation of each node. The heterogeneous aggregation function is used to aggregate the messages of each node, and the update function is used to update the hidden representation of each node to the next layer. For grid nodes, the heterogeneous aggregation function will aggregate the hidden representations from different types of nodes, as shown in formula (6). Where ρ represents the heterogeneous aggregation function and ψ represents the update function.

8. The FPGA routing congestion prediction method based on heterogeneous graph neural networks according to claim 1, wherein step S5, optimizing the message passing module in the heterogeneous graph neural network using a neural network structure search strategy, includes: The search range for the message passing function is defined as graph convolutional networks, graph attention networks, and graph sampling and aggregation networks. The search range for the heterogeneous aggregation function is defined as linear functions that calculate the average value, linear functions that take the maximum value, linear functions that sum, and learnable linear functions. Searching within message passing functions and heterogeneous aggregation functions reveals that the netlist subgraph message passing function is a graph attention network, the spatial mapping message passing function and the architecture subgraph message passing function are graph convolutional networks, and the heterogeneous aggregation function is a learnable linear function. Searching for the message passing layer and hidden dimension reveals a message passing layer of 4 and a hidden dimension of 128.

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