Semiconductor element and manufacturing method thereof
By using hybrid bonding and multi-segment etching processes to form silicon through-holes on the back side of the upper wafer in a 3D integrated chip, the problem of interconnect length limitation in stacked chips is solved, achieving lower resistance connection and efficient fabrication, and improving die yield and quality.
Patent Information
- Application Number
- CN202411119714.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-01
- Filing Date
- 2024-08-15
- Publication Date
- 2026-02-06
AI Technical Summary
In existing 3D integrated chip technology, the reduced interconnect length between stacked chips limits the integration density and performance improvement, and traditional packaging methods suffer from manufacturing complexity and high cost.
A hybrid bonding process is used to dock the upper wafer with the lower wafer to form a stacked structure. Through edge trimming and multi-segment etching processes, through-silicon vias (TSVs) are formed on the back side of the upper wafer, and a pad layer is formed on its sidewall to achieve the connection of the metal interconnects.
It achieves lower resistance copper wire connections, simplifies the manufacturing process, reduces costs, and improves die yield and quality, making it suitable for in-wafer manufacturing without the need for outsourced packaging and testing.
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Figure CN121487571A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a method for fabricating semiconductor devices, and more particularly, to a method for forming a through-silicon via (TSV) on the backside of a top wafer after bonding two wafers. BACKGROUND
[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In large part, this improvement in integration density has resulted from a continual halfing of minimum feature size, which has
[0003] Three-dimensional integrated chips provide improved integration density and other advantages, such as faster speed and higher bandwidth, due to the reduced length of interconnect lines between stacked chips. However, there are still many challenges to be addressed for three-dimensional integrated chip technology. SUMMARY
[0004] One embodiment of the present invention discloses a method for fabricating semiconductor devices, which mainly provides a stacked structure including a shallow trench isolation disposed under a first substrate, a contact hole etch stop layer disposed under the shallow trench isolation, an interlayer dielectric layer disposed under the contact hole etch stop layer, and a first metal interconnect disposed under the interlayer dielectric layer. Then, a second metal interconnect is formed through the first substrate, the shallow trench isolation, the contact hole etch stop layer, and the interlayer dielectric layer and contacts the first metal interconnect and a liner layer is disposed beside the sidewall of the second metal interconnect.
[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a shallow trench isolation disposed under a first substrate, a contact hole etch stop layer disposed under the shallow trench isolation, an interlayer dielectric layer disposed under the contact hole etch stop layer, a first metal interconnect disposed under the interlayer dielectric layer, a second metal interconnect passing through the first substrate, the shallow trench isolation, the contact hole etch stop layer and the interlayer dielectric layer and contacting the first metal interconnect, and a pad layer disposed next to the sidewall of the second metal interconnect. Attached Figure Description
[0006] Figures 1 to 10 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0007] Symbol Explanation
[0008] 12: Next wafer
[0009] 14: Wafer Upgrade
[0010] 16: Base
[0011] 18: Intermetallic dielectric layer
[0012] 20: Metal interconnects
[0013] 22: Metal interconnect structure
[0014] 24: Direct-bonded internal connections
[0015] 30: Stacked structure
[0016] 32: Shallow trench isolation
[0017] 34: Contact hole etching stop layer
[0018] 36: Interlayer dielectric layer
[0019] 38: Hard Mask
[0020] 40: Hard Mask
[0021] 42: Patterned Mask
[0022] 44: Groove
[0023] 46: Groove
[0024] 48: Lining layer
[0025] 50: Groove
[0026] 52 Barrier Layers
[0027] 54: Metal layer
[0028] 56: Silicon Through-Hole Detailed Implementation
[0029] While specific configurations and arrangements are discussed herein, it should be understood that other configurations and arrangements can be utilized without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be embodied in a variety of other forms without departing from the spirit and scope of the disclosure as set forth in the appended claims.
[0030] Note that references to "one embodiment," "an embodiment," "example embodiment," "some embodiments," etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of those skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0031] In general, terminology can be understood at least in part according to an ordinary meaning process, context and the relevant art. For example, the term "one or more" as used herein, depending at least in part upon context, can be used to describe any feature, structure or characteristic in the singular or can be used to describe combinations of features, structures or characteristics. Similarly, terms such as "a," "an," or "the" again, can be understood to convey a singular usage or to convey a plural usage, at least depending upon context. Finally, the term "based on" can be understood as not necessarily requiring explicitly-stated facts as a precondition to support an assertion, and can instead allow inferred facts, or can instead be read as "based at least in part on."
[0032] It should be readily understood that the terms "on," "over," and "above" in the present disclosure should be interpreted in the broadest relative terms such that "on" means not only "directly" on something, but also includes the meaning of being on something with intervening features or layers therebetween, and "over" or "above" means not only the meaning of being over or above something, but can also include the meaning of being without intervening features or layers (i.e., directly on something).
[0033] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0034] As used herein, the term "substrate" refers to a material on which a layer of material is subsequently added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0035] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entire underlying or overlying structure, or can have an extent less than the underlying or overlying structure. Further, a layer can be a region of uniform or non-uniform thickness that is less than the thickness of a continuous structure. For example, a layer can be between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes between the top surface and the bottom surface. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon and / or thereunder. A layer can contain multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.
[0036] Reference will now be made to the drawings Figures 1 to 10 , Figures 1 to 10 A flow diagram of a method of fabricating semiconductor elements for an embodiment of the present application is shown. As shown in FIG. 1, a lower wafer 12 and an upper wafer 14 are first provided, each wafer comprising a substrate 16 of semiconductor material, each substrate 16 can have the same or different thickness depending on the fabrication process or product requirement, and each substrate 16 can be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a silicon-on-insulator (SOI) substrate, all of which are within the scope of the present application. In this embodiment, each wafer can be used to fabricate various elements such as medium voltage elements, high voltage elements, pixel circuits, low voltage elements of low voltage drive circuits, and / or graphics processing units (GPUs) in subsequent fabrication processes. Figure 1 As shown in FIG. 1, a lower wafer 12 and an upper wafer 14 are first provided, each wafer comprising a substrate 16 of semiconductor material, each substrate 16 can have the same or different thickness depending on the fabrication process or product requirement, and each substrate 16 can be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a silicon-on-insulator (SOI) substrate, all of which are within the scope of the present application. In this embodiment, each wafer can be used to fabricate various elements such as medium voltage elements, high voltage elements, pixel circuits, low voltage elements of low voltage drive circuits, and / or graphics processing units (GPUs) in subsequent fabrication processes.
[0037] The lower wafer 12 and the upper wafer 14 are then subjected to a front end of line (FEOL) process and a back end of line (BEOL) process, respectively. In the present embodiment, the FEOL process can include fabricating active and / or passive elements such as metal oxide semiconductor (MOS) transistors, oxide semiconductor field effect transistors (OS FETs), fin field effect transistors (FinFETs), or other active and / or passive elements on the wafers according to the process or product selection, and the BEOL process can include forming metal interconnect structures such as intermetal dielectric layers and metal interconnects on the active and / or passive elements. For example, in the case of fabricating MOS transistors, the FEOL process can include forming a gate structure on the substrate 16, forming a spacer on the sidewalls of the gate structure, and forming source / drain regions on both sides of the spacer, where the gate structure can include polysilicon or metal material, the spacer can include dielectric material such as silicon oxide or silicon nitride, and the source / drain regions can include different dopants such as P-type or N-type dopants according to the type of transistors to be fabricated.
[0038] An interlayer dielectric layer can then be formed on the substrate 16 and covering the MOS transistors or other active elements, and a contact plug and BEOL process can be performed to form a plurality of contact plugs connecting the source / drain regions and the gate structure in the interlayer dielectric layer, an intermetal dielectric layer 18 on the interlayer dielectric layer, and metal interconnects 20 in the intermetal dielectric layer and connecting the contact plugs, where the intermetal dielectric layer 18 and the metal interconnects 20 can form a metal interconnect structure 22, and the topmost metal interconnects on the front side of each wafer can serve as contacts for direct bond interconnects (DBIs) 24 that can be mated with DBIs 24 of another wafer in a subsequent process. In the present embodiment, the interlayer dielectric layer and the intermetal dielectric layer 18 can include oxide such as, but not limited to, tetraethyl orthosilicate (TEOS), and the contact plugs, the metal interconnects 20, and the DBIs 24 can include aluminum, chromium, copper, tantalum, molybdenum, tungsten, or combinations thereof, but are not limited thereto.
[0039] As Figure 2As shown, a hybrid bonding process is then performed to dock the lower wafer 12 and the upper wafer 14 to form a stacked structure 30. During the bonding process, the upper wafer 14 can be flipped so that the front side of the upper wafer 14 or the side exposing the direct bonding interconnect 24 faces the front side of the lower wafer 12 or the side exposing the direct bonding interconnect 24. Then, the direct bonding interconnects 24 of the two wafers are directly bonded by means of, for example, heating, so that the direct bonding interconnects 24 of the upper wafer 14 and the intermetallic dielectric layer 20 are in direct contact with the direct bonding interconnects 24 of the lower wafer 12 and the intermetallic dielectric layer 20.
[0040] Then as Figure 3 As shown, a grinding process is first performed to remove most of the substrate 16 of the upper wafer 14, leaving the metal interconnect structure 22 originally located on the substrate 16. Then, an edge trimming process is performed to remove a portion of the upper wafer 14. More specifically, the edge trimming process in this stage can utilize dicing or a back grinding tool to remove a portion of the edge of the upper wafer 14, making the overall width of the remaining upper wafer 14 smaller than the overall width of the lower wafer 12. It should be noted that after removing a portion of the edge of the upper wafer 14 using the edge trimming process, a portion of the edge of the lower wafer 12 can be removed simultaneously, making the top surface of the edge of the lower wafer 12 slightly lower than the top surface of the middle portion of the lower wafer 12, while the sidewalls of the upper wafer 14 are also aligned with a portion of the sidewalls of the lower wafer 12. In other words, after the edge trimming process, a gap G1 is preferably formed between the edge of the metal interconnect structure 22 of the upper wafer 14 and the edge of the substrate 16 of the lower wafer 12. Furthermore, in this stage, after removing most of the substrate 16 of the upper wafer 14 using a grinding process, the remaining upper wafer 14, including the metal interconnect structure 22, has a thickness preferably less than 10 micrometers, while the overall thickness of the lower wafer 12, including the substrate 16 and the metal interconnect structure 22, is preferably between 700 and 800 micrometers, or ideally about 750 micrometers. Then, grooves are formed on the back side of the upper wafer 14 by etching, and conductive material is filled to form through-silicon vias (TSVs) 56.
[0041] Please continue to refer to Figures 4 to 10 , Figures 4 to 10 This is a continuation of an embodiment of the present invention. Figure 3 This is a schematic diagram of a method for fabricating semiconductor devices. The diagram highlights the details of subsequently forming metal interconnects or through-silicon vias (TSVs) 56 on the back side of the upper wafer 14. Figures 4 to 10 Only a portion of the substrate 16 and its surrounding components on the upper wafer 14 are shown. For example... Figure 4As shown, after the lower wafer 12 and the upper wafer 14 are aligned and bonded together by the hybrid bonding method and a portion of the substrate 16 of the upper wafer 14 is removed by the grinding tool according to the aforementioned fabrication process, the remaining upper wafer 14 has a front surface facing downward and a back surface facing upward, and preferably includes a shallow trench isolation 32 disposed under the substrate 16, a contact hole etch stop layer 34 disposed under the shallow trench isolation 32, an interlayer dielectric layer 36 disposed under the contact hole etch stop layer 34, and metal interconnects 20 disposed under the interlayer dielectric layer 36, wherein the metal interconnects 20 are directly connected to the directly bonded interconnects 24. Figure 3 The metal interconnects 20 disposed between the substrate 16 of the upper wafer 14 and the directly bonded interconnects 24.
[0042] Then, a first hard mask, such as a hard mask 38, is formed on the substrate 16 of the upper wafer 14, and a second hard mask, such as a hard mask 40, is formed on the hard mask 38, wherein the hard mask 38 and the hard mask 40 preferably include different materials, for example, the hard mask 38 preferably includes TEOS and the hard mask 40 includes silicon oxynitride (SiON). In this embodiment, the thickness of the hard mask 38 is preferably between 8000-10000 angstroms or most preferably about 9000 angstroms, and the thickness of the hard mask 40 is less than half of the thickness of the hard mask 38, for example, preferably between 1800-2200 angstroms or most preferably about 2000 angstroms.
[0043] Subsequently, as shown in FIG. 4, a patterned mask 42, such as a patterned photoresist, is formed on the hard mask 40, and a first-stage etching fabrication process is performed using the patterned mask 42 as a mask to remove a portion of the hard mask 40, a portion of the hard mask 38, and a small portion of the substrate 16 to form a recess 44, wherein the bottom surface of the recess 44 is preferably slightly lower than the top surface of the substrate 16. Figure 5 As shown in FIG. 5, a second-stage etching fabrication process is then performed using the same patterned mask 42 as a mask to further remove a portion of the substrate 16 and a portion of the shallow trench isolation 32, thereby increasing the depth of the recess 44 downward and forming another recess 46, wherein the bottom surface of the recess 46 is preferably slightly lower than the top surface of the shallow trench isolation 32.
[0044] Figure 6 As shown in FIG. 6, a cleaning fabrication process is then performed to remove the remaining patterned mask 42 and impurities or contaminants remaining in the recess 46, and an atomic layer deposition (ALD) fabrication process is then performed to form a liner layer 48 in the recess 46. In this embodiment, the liner layer 48 preferably includes silicon oxide, but other dielectric materials, such as silicon nitride, can also be used according to the fabrication process requirements, and the liner layer 48 preferably fully covers the top surface of the hard mask 40, the sidewall of the hard mask 40, the sidewall of the hard mask 38, the sidewall and the top surface of the substrate 16, and the sidewall and the top surface of the shallow trench isolation 32.
[0045] As shown in FIG. 7, a first metal layer 50, such as a tungsten layer, is then formed in the recess 46 by a deposition fabrication process, and a second metal layer 52, such as a copper layer, is then formed on the first metal layer 50 by a deposition fabrication process. In this embodiment, the thickness of the first metal layer 50 is preferably between 1000-2000 angstroms or most preferably about 1500 angstroms, and the thickness of the second metal layer 52 is preferably between 5000-10000 angstroms or most preferably about 8000 angstroms. Figure 7 As shown in FIG. 8, a third metal layer 54, such as a titanium layer, is then formed on the second metal layer 52 by a deposition fabrication process, and a fourth metal layer 56, such as a titanium nitride layer, is then formed on the third metal layer 54 by a deposition fabrication process. In this embodiment, the thickness of the third metal layer 54 is preferably between 1000-2000 angstroms or most preferably about 1500 angstroms, and the thickness of the fourth metal layer 56 is preferably between 1000-2000 angstroms or most preferably about 1500 angstroms.
[0046] like Figure 8 As shown, a plasma etching process can then be performed without forming a patterned mask to remove part of the pad layer 48, all the hard mask 40, part of the shallow trench isolation 32 below the pad layer 48, part of the contact hole etch stop layer 34, part of the interlayer dielectric layer 36, and even part of the metal interconnect 20, thereby increasing the depth of the aforementioned groove 46 downward to form another groove 50, wherein the bottom surface of the groove 50 is preferably slightly lower than the top surface of the metal interconnect 20. More specifically, the etching process performed in this stage preferably first removes part of the pad layer 48 located on the top surface of the hard mask 40 and the bottom of the groove 46, and then removes all the hard masks 40 on both sides of the groove 46, part of the shallow trench isolation 32 below the groove 46, part of the contact hole etch stop layer 34, part of the interlayer dielectric layer 36, and part of the metal interconnect 20 to form the groove 50.
[0047] Then as Figure 9 As shown, a barrier layer 52 is first formed within the groove 50, covering the top surface of the hard mask 38, the sidewalls of the pad layer 48, the sidewalls of the shallow trench isolation 32, the sidewalls of the contact hole etch stop layer 34, the sidewalls of the interlayer dielectric layer 36, and the top surface of the intermetallic dielectric layer 20. Then, a metal layer 54 is formed on the barrier layer 52, filling the groove 50. In this embodiment, the barrier layer 52 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 54 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited to these.
[0048] Then as Figure 10 As shown, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove part of the metal layer 54 and part of the barrier layer 52, so that the top surfaces of the remaining barrier layer 52 and the metal layer 54 are aligned with the top surfaces of the hard mask 38 on both sides to form metal interconnects or silicon vias 56 in the groove 50 to contact the metal interconnects 20 below.
[0049] Then, according to the manufacturing process or product requirements, a multilayer metal interconnect structure (not shown) can be formed on the silicon through-hole 56 to electrically connect the silicon through-hole 56. A contact pad is then formed on the metal interconnect structure. The formation of the contact pad may include first forming a pad layer (not shown) on the metal interconnect structure, and then performing a photolithography and etching process to remove part of the pad layer, leaving the remaining pad layer as a contact pad. According to one embodiment of the present invention, the contact pad preferably contains metal, and most preferably aluminum, but may also contain copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), or alloys thereof, depending on the manufacturing process requirements, and is not limited thereto. This completes the fabrication of a semiconductor device according to the present invention.
[0050] Please refer to again Figure 3 and Figure 10 , Figure 3 and Figure 10 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 3 and Figure 10 As shown, the semiconductor device mainly includes an upper wafer 14 bonded to a lower wafer 12, wherein the upper wafer 14 and the lower wafer 12 each include a substrate 16, and the upper wafer 14 further includes a hard mask 38 disposed on the substrate 16, a shallow trench isolation 32 disposed under the substrate 16, a contact hole etch stop layer 34 disposed under the shallow trench isolation 32, an interlayer dielectric layer 36 disposed under the contact hole etch stop layer 34, a metal interconnect 20 disposed under the interlayer dielectric layer 36, and the metal interconnect or silicon via 56 passing through the hard mask 38, the substrate 16, the shallow trench isolation 32, the contact hole etch stop layer 34 and the interlayer dielectric layer 36 and contacting the metal interconnect 20, and a pad layer 48 disposed next to the sidewall of the silicon via 56.
[0051] In detail, the top surface of the hard mask 38 is flush with the top surface of the silicon through-hole 56, and the top surface of the pad layer 48 is flush with the top surfaces of the barrier layer 52 and the metal layer 54 in the silicon through-hole 56. The bottom surfaces of the barrier layer 52 and the metal layer 54 are both lower than the bottom surface of the pad layer 48, and the top surfaces of the contact hole etch stop layer 34 and the interlayer dielectric layer 36 are both lower than the bottom surface of the pad layer 48. Furthermore, although the bottom surface of the pad layer 48 in this embodiment is slightly lower than the top surface of the shallow trench isolation 32, it is not limited to this; other embodiments of the present invention may also be... Figures 6 to 7 When forming the pad layer 48, the depth of the groove 46 is adjusted so that the bottom surface of the subsequent pad layer 48 is higher than, flush with or lower than the top surface of the shallow trench isolation 32; higher than, flush with or lower than the top surface of the shallow contact hole etch stop layer 34; or even higher than, flush with or lower than the top surface of the interlayer dielectric layer 36 but still higher than the bottom surface of the silicon via 56. These variations are all within the scope of this invention.
[0052] In summary, the present application discloses a method for forming a through silicon via (TSV) on the backside of a wafer. The method includes the following steps. First, a wafer is bonded to a substrate to form a stacked structure. Then, an edge trimming process is performed to remove part of the wafer. The trimmed wafer includes a shallow trench isolation 32 formed in the substrate 16, a contact hole etch stop layer 34 formed in the shallow trench isolation 32, an interlayer dielectric layer 36 formed in the contact hole etch stop layer 34, and metal interconnects 20 formed in the interlayer dielectric layer 36. Then, a multi-step etching process is performed to remove part of the substrate and part of the shallow trench isolation. A liner layer 48 is formed in the recess. Then, an etching process is performed to remove part of the liner layer, part of the contact hole etch stop layer, and part of the interlayer dielectric layer to form a deeper recess. Finally, a conductive material is filled in the recess to form a through silicon via.
[0053] According to the preferred embodiment of the present application, the above-mentioned method for forming a through silicon via on the backside of a wafer has the following advantages. First, the copper wire formed after the face-to-face bonding of the wafer or die has a lower resistance. Second, the present application can be directly formed on a bulk silicon substrate without using a silicon-on-insulator (SOI) substrate. Third, the present application can be directly formed in a wafer factory without using an outsourced semiconductor assembly and test (OSAT) method. Fourth, the thinner silicon substrate used in the present application is easier to align during the front-end manufacturing process compared to the TSV-via-middle manufacturing process, thereby improving the die yield and quality.
[0054] The above-mentioned preferred embodiments of the present application are only examples. Any equivalent changes and modifications made according to the claims of the present application should be included in the scope of the present application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Include: Provides a stacking structure, including: Shallow trench isolation, located beneath the first basement; A contact hole etching stop layer is provided under the shallow trench isolation; An interlayer dielectric layer is disposed below the contact hole etch stop layer; The first metal interconnect is disposed under the interlayer dielectric layer; as well as A second metal interconnect is formed that passes through the first substrate, the shallow trench isolation, the contact hole etch stop layer, and the interlayer dielectric layer and contacts the first metal interconnect, and a pad layer is disposed next to the sidewall of the second metal interconnect.
2. The method of claim 1, further comprising: The first substrate is joined to the second substrate, wherein the first substrate faces upward and the second substrate faces upward; A finishing process is performed to refine the edges of the first base; A first groove is formed within the first substrate; as well as A metal layer is formed in the first groove to form the second metal interconnect.
3. The method of claim 2, further comprising: A first hard mask is formed on the first substrate; A second hard mask is formed on the first hard mask; Remove the second hard mask, the first hard mask, the first substrate, and the shallow trench isolation to form a second groove; The liner layer is formed within the second groove; Remove the pad layer, the contact hole etch stop layer, and the interlayer dielectric layer to form the first groove to expose the first metal interconnect; A barrier layer is formed within the second groove; The metal layer is formed in the second groove; and The barrier layer and the metal layer are planarized to form the second metal interconnect.
4. The method of claim 3, wherein the first hard mask and the second hard mask comprise different materials.
5. The method of claim 3, wherein the top surface of the liner layer is flush with the top surface of the barrier layer.
6. The method of claim 3, wherein the bottom surface of the barrier layer is lower than the bottom surface of the liner layer.
7. The method of claim 1, wherein the top surface of the contact hole etching stop layer is lower than the bottom surface of the pad layer.
8. A semiconductor element, characterized in that, Include: Shallow trench isolation, located beneath the first basement; A contact hole etching stop layer is provided under the shallow trench isolation; An interlayer dielectric layer is disposed below the contact hole etch stop layer; The first metal interconnect is disposed under the interlayer dielectric layer; The second metal interconnect passes through the first substrate, the shallow trench isolation, the contact hole etch stop layer and the interlayer dielectric layer and contacts the first metal interconnect. as well as A liner layer is provided next to the side wall of the second metal inner interconnect.
9. The semiconductor element of claim 8, wherein the first substrate is bonded to the second substrate.
10. The semiconductor device of claim 8, further comprising a hard mask disposed on the first substrate.
11. The semiconductor device of claim 10, wherein the top surface of the hard mask is flush with the top surface of the second metal interconnect.
12. The semiconductor element of claim 8, wherein the second metal interconnect comprises: Barrier layer; and A metal layer is disposed on the barrier layer.
13. The semiconductor device of claim 12, wherein the top surface of the pad layer is flush with the top surface of the barrier layer.
14. The semiconductor device of claim 12, wherein the bottom surface of the barrier layer is lower than the bottom surface of the pad layer.
15. The semiconductor device of claim 8, wherein the top surface of the contact hole etch stop layer is lower than the bottom surface of the pad layer.