Chip package structure and chip package method

Abstract

The application provides a chip packaging structure and a chip packaging method, and relates to the technical field of semiconductor packaging. The packaging structure comprises a substrate, a concave pad and a convex pad are formed on the surface of the substrate, the concave pad is recessed downward relative to the surface of the substrate, and the convex pad is protruded upward relative to the surface of the substrate; a first chip is electrically connected to the substrate through the convex pad; and a second chip is electrically connected to the substrate through the concave pad. Through the differential design of the concave and convex pads and the double-layer peelable structure, the reflow soldering temperature of 200-220 DEG C is supported, which is significantly improved compared with the 180-200 DEG C of the traditional PS carrier tape, the connection stability and reliability in the high-temperature process are significantly improved, the temporary carrier tape which needs to be used alone in the traditional process is saved, the manufacturing cost is reduced, and the application is suitable for complex packaging applications which need to be soldered multiple times.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a chip packaging method. Background Technology

[0002] As electronic products trend towards miniaturization and higher performance, chip packaging technology faces increasingly stringent requirements. In traditional chip packaging processes, the packaging carrier tape is a common component, but its high price increases costs. Summary of the Invention

[0003] The purpose of this invention is to provide a chip packaging structure and a chip packaging method to reduce costs and improve the reliability of chip packaging.

[0004] To achieve the above-mentioned objectives, the present invention provides a chip packaging structure, comprising:

[0005] A substrate, wherein concave pads and convex pads are formed on the upper surface of the substrate, the concave pads being recessed downward relative to the upper surface of the substrate, and the convex pads being convex upward relative to the upper surface of the substrate;

[0006] The first chip is electrically connected to the substrate via the solder pads;

[0007] The second chip is electrically connected to the substrate via the concave pad.

[0008] Optionally, the recessed pad has a depth of 50-200 micrometers, and the raised pad has a height of 30-150 micrometers.

[0009] Optionally, the concave pad is located in the outer region of the substrate, and the convex pad is located in the central region of the substrate.

[0010] Optionally, the second chip, the first chip, and the substrate are stacked in sequence.

[0011] Optionally, a third chip is also included, which is disposed on the second chip and is electrically connected to the substrate through the concave pad.

[0012] The present invention also provides a chip packaging method, comprising:

[0013] Provide substrate;

[0014] Concave pads and convex pads are formed on the upper surface of the substrate. The concave pads are recessed downward relative to the upper surface of the substrate, and the convex pads are convex upward relative to the upper surface of the substrate.

[0015] The first chip is mounted onto the substrate and electrically connected via the solder pads.

[0016] The second chip is attached to the first chip and electrically connected through the concave pad.

[0017] Package it.

[0018] Optionally, the substrate includes:

[0019] An upper metal plate, a lower metal plate, and an intermediate layer located between the upper metal plate and the lower metal plate, the intermediate layer comprising a titanium layer and a tin layer.

[0020] Optionally, the step of forming concave pads and convex pads on the surface of the substrate, wherein the concave pads are recessed downward relative to the upper surface of the substrate and the convex pads are convex upward relative to the upper surface of the substrate, includes:

[0021] The substrate is stamped from its two opposing upper and lower surfaces.

[0022] Photolithography and etching are performed on the upper surface of the stamped substrate to expose the central pad area and the surrounding pad area.

[0023] After removing the photoresist, multiple raised pads are formed in the central pad area, and multiple concave pads are formed in the surrounding pad area.

[0024] Optionally, after packaging is complete, the following steps may also be included:

[0025] During cutting, the connection of the lower metal plate is kept intact or only partially cut into the lower metal plate without completely severing it;

[0026] The intermediate layer and the lower metal plate are peeled off from the upper metal plate.

[0027] Optionally, the welding temperature during the encapsulation process is 200-220℃.

[0028] The chip packaging structure and method provided by this invention utilize differentiated pad structures—concave pads and convex pads—formed on the upper surface of a substrate. The concave pads, recessed downwards, provide physical constraint on the solder, effectively preventing lateral solder flow and collapse during high-temperature soldering, maintaining stable solder joint morphology, and improving soldering reliability. The convex pads, protruding upwards, are suitable for electrical connection to the bottom of the chip and, in conjunction with the concave pads, achieve multi-chip stacked packaging. This structure, used at soldering temperatures of 200-220°C, ensures that previously formed solder joints remain unaffected, improving solder joint stability.

[0029] The double-layer metal plate structure of this invention uses the lower metal plate as a process carrier, simplifying the packaging process and eliminating the need for a separate temporary carrier in traditional processes, thus reducing manufacturing costs. The titanium layer in the middle layer effectively prevents metallurgical bonding between the upper and lower metal plates during high-temperature processes, allowing the lower metal plate to be easily peeled off after packaging, achieving the carrier function without affecting the performance of the final package structure. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the chip packaging structure in an embodiment of the present invention;

[0031] Figure 2 This is a top view of the chip packaging structure in an embodiment of the present invention;

[0032] Figure 3 This is a side view of the chip packaging structure in an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the upper surface of the substrate of the chip packaging structure in an embodiment of the present invention;

[0034] Figure 5 This is an exploded view of the chip packaging structure in an embodiment of the present invention;

[0035] Figure 6 This is a flowchart of the chip packaging method in an embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of the stamping forming of the concave and convex structure in an embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of coating photoresist on the upper surface of a substrate in an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of the photoresist patterning in an embodiment of the present invention;

[0039] Figure 10 This is a schematic diagram illustrating photolithography and etching on the upper surface of a substrate in an embodiment of the present invention;

[0040] Figure 11 This is a schematic diagram after removing the photoresist in an embodiment of the present invention.

[0041] In the figure, 1 is the substrate; 11 is the upper metal plate; 12 is the lower metal plate; 2 is the concave pad; 3 is the convex pad; 4 is the chip; 41 is the first chip; 42 is the second chip; and 5 is the photoresist. Detailed Implementation

[0042] The present invention will now be described with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0043] The serial numbers assigned to components in this document, such as "first," "second," etc., are merely used to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention.

[0044] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0045] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0046] Example 1

[0047] This invention provides a chip packaging structure, such as... Figure 1 - Figure 3 As shown, the package includes a substrate 1, concave pads 2, convex pads 3, and at least one chip 4. The substrate 1 serves as the main support for the package structure, providing mechanical support and electrical interconnection. Concave pads 2 and convex pads 3 are formed on the surface of the substrate 1. The chip 4 includes a first chip 41 and a second chip 42. The first chip 41 is electrically connected to the substrate 1 through the convex pads 3; the second chip 42 is electrically connected to the substrate 1 through the concave pads 2.

[0048] Specifically, the concave pad 2 is recessed downward relative to the upper surface of the substrate 1, forming a recessed structure.

[0049] In this embodiment, the recessed structure provides physical constraint on the solder, effectively preventing problems such as lateral flow, collapse, or bridging of the solder during high-temperature soldering. The recessed pad 2 of this invention constrains the molten solder through the sidewalls of its groove, limiting the solder's flow range and ensuring that the solder joint maintains a stable shape and position even at high temperatures. This structure is particularly suitable for complex packaging processes requiring multiple soldering operations. In subsequent soldering processes, previously formed solder joints will not undergo morphological changes due to repeated exposure to high temperatures, ensuring the reliability of the packaging.

[0050] It should be noted that traditional packaging processes often use polystyrene (PS) plastic carrier tapes as the process carrier. Due to the heat resistance limitations of PS material, reflow soldering temperatures are typically restricted to the range of 180-200°C. Within this temperature range, the solder is in a partially molten state, which affects the soldering quality and reliability. However, the concave pad 2 structure of this invention can withstand reflow soldering temperatures of 200-220°C. At this temperature, the solder can fully melt and wet, forming a more reliable solder joint. Furthermore, the concave structure of the concave pad 2 provides even more crucial constraint on the solder at higher temperatures, effectively preventing solder collapse or bridging due to increased fluidity, thus improving the stability of the solder joint.

[0051] Furthermore, the recessed structure of the concave pad 2 increases the contact area between the solder and the substrate 1. The inner wall of the groove provides an additional metallized surface, enabling the solder to achieve metallurgical bonding at a larger interface, thereby improving the shear strength and fatigue resistance of the solder joint. The recessed structure also facilitates the venting of gas during the welding process, reduces the formation of voids inside the solder joint, and further improves the connection quality.

[0052] In one specific example, the connection between the second chip 42 and the concave pad 2 is achieved by wire bonding. Wire bonding processes include thermocompression bonding, ultrasonic bonding, or thermo-ultrasonic bonding, which are common techniques used by those skilled in the art and will not be described in detail here.

[0053] The recessed structure of the concave pad 2 provides a protective space for the bottom connection point of the bonding wire, preventing mechanical stress damage to the bonding point during subsequent packaging processes (such as molding). Simultaneously, the recessed structure increases the metallization area of ​​the pad, providing a larger bonding area, which is beneficial for reliable connection between the bonding wire and the substrate 1 and improves bonding strength. During high-temperature processes, the recessed structure provides physical protection for the bonding point, preventing the bonding interface from detaching or cracking under thermal stress.

[0054] Specifically, the bump pad 3 protrudes upward relative to the upper surface of the substrate 1, forming a raised structure. The bump pad 3 is mainly used for the connection of flip chips. Specifically, the bump pad 3 protrudes upward from the upper surface of the substrate 1 and can mate with the solder bumps or solder balls on the bottom of the flip chip to achieve electrical and mechanical connection through soldering. The protrusion height of the bump pad 3 allows it to extend into the space between the chip 4 and the substrate 1, adapting to the connection requirements of flip chips. This raised structure provides differentiated connection solutions for chips using different connection processes in multi-chip stacked packages.

[0055] In a specific example, the recessed depth of the recessed pad 2 is 50-200 micrometers. The specific recessed depth can be optimized based on the height of the chip bump, the solder volume, the connection method of the bonding wire, and the required solder joint height. Preferably, the recessed depth is 80-150 micrometers, which balances solder constraint effect, bonding point protection, and process feasibility.

[0056] In one specific example, the bump height of the convex pad 3 is 30-150 micrometers. The selection of the bump height needs to consider the spacing between chips, the solder volume, and the overall height requirements after packaging. Preferably, the bump height is 50-100 micrometers.

[0057] In a specific example, such as Figure 4 As shown, the concave pad 2 is located in the outer region of the substrate 1, and the convex pad 3 is located in the central region of the substrate 1. This layout design takes into account the functional positioning and connection requirements of different chips in a multi-chip package.

[0058] Furthermore, such as Figure 5 As shown, the second chip 42, the first chip 41, and the substrate 1 are stacked in sequence.

[0059] Specifically, the second chip 42 is connected to the substrate 1 via wire bonding. The active side of the second chip 42 faces upwards, and the pads on its edge are connected to recessed pads 2 on the outer side of the substrate 1 via bonding wires. The recessed structure of the recessed pads 2 provides protection for the bottom connection point of the bonding wires, improving bonding quality. A robust electrical connection is formed between the pads of the second chip 42 and the recessed pads 2 via the bonding wires.

[0060] The first chip 41 can be arranged in a flip-chip configuration, with its active surface facing the substrate 1. The solder bumps or solder balls on its bottom are connected to the pads 3 in the central region of the substrate 1. The pads 3 protrude upward from the upper surface of the substrate 1 and extend into the gap between the first chip 41 and the substrate 1 to achieve electrical connection with the first chip 41.

[0061] In one specific example, the chip package structure further includes a third chip disposed on the second chip 42 and connected to the recessed pad 2 via wire bonding. Preferably, the third chip has a smaller external dimension than the second chip 42. Bonding wires extend from the pads of the third chip, cross the second chip 42, and connect to the recessed pad 2 in the outer region of the substrate 1.

[0062] This layered layout enables high-density three-dimensional packaging. The first chip 41, the second chip 42, and the third chip can be chips with different functions; for example, the first chip 41 could be a logic processing chip, the second chip 42 a memory chip, and the third chip a sensor chip or a communication chip. Through the differentiated design of the concave pads 2 and convex pads 3, the three chips can achieve multi-layer stacking and reliable electrical connections within a limited package area. The recessed structure of the concave pads 2 provides a unified connection point for wire bonding from different chip layers, while protecting the connection stability of each layer during multiple reflow soldering processes. This multi-chip stacked packaging method is particularly suitable for system-in-package (SiP) applications, enabling the integration of multiple functions within a single package, significantly reducing package size, and improving system integration and performance.

[0063] Furthermore, the concave pads 2 and convex pads 3 are formed by a stamping process. Specifically, a stamping die is used to stamp the substrate 1, causing plastic deformation at the predetermined pad positions to form concave or convex structures.

[0064] The stamping process can form multiple concave pads 2 and convex pads 3 in one stamping action, which is much more efficient than the etching process that is performed area by area, and is especially suitable for mass production.

[0065] The precision of stamping dies can reach the micron level, enabling precise control of the depth of the recess and the height of the protrusion, thus ensuring the consistency of the pad size.

[0066] The sidewalls of the concave pad 2 and convex pad 3 formed by stamping are smooth and flat, without the side etching or rough surface that may be produced by the etching process. This is conducive to the wetting and bonding of the solder, and also conducive to the reliable connection between the bonding wire and the pad during wire bonding.

[0067] In summary, the chip packaging structure provided by this invention has the following beneficial effects: the recessed structure of the concave pads provides protective space for wire bonding connection points and simultaneously constrains the solder during flip-chip bonding, effectively preventing bond point detachment and solder flow during high-temperature processes at 200-220℃, thus improving soldering reliability; through the differentiated design of the concave and convex pads, wire bonding and flip-chip bonding can coexist in the same structure, supporting high-density three-dimensional packaging; the recessed structure increases the metallization area, improving bonding strength and solder joint shear strength; the concave and convex pads formed by the stamping process have high precision, good surface quality, and high processing efficiency, making them suitable for mass production. This invention simplifies the process while improving packaging reliability and is suitable for high-density, high-reliability chip packaging applications.

[0068] Example 2

[0069] This embodiment provides a chip packaging method; please refer to [reference needed]. Figure 6 This includes the following steps:

[0070] S1: Provide substrate 1;

[0071] S2: A concave pad 2 and a convex pad 3 are formed on the upper surface of the substrate 1. The concave pad 2 is recessed downward relative to the upper surface of the substrate 1, and the convex pad 3 is protruded upward relative to the upper surface of the substrate 1.

[0072] S3: The first chip 41 is mounted onto the substrate 1 and electrically connected through the solder pads 3;

[0073] S4: The second chip 42 is attached to the first chip 41 and electrically connected through the concave pad 2;

[0074] S5: Perform encapsulation.

[0075] In step S1, a substrate 1 for packaging is provided.

[0076] In one specific example, the substrate 1 includes a double-layer metal plate structure, specifically including an upper metal plate 11, a lower metal plate 12, and an intermediate layer located between the upper metal plate 11 and the lower metal plate 12. The concave pads 2 and convex pads 3 are formed on the surface of the upper metal plate 11 away from the lower metal plate 12.

[0077] The upper metal plate 11 serves as the final packaging substrate, providing pads and electrical interconnects. The thickness of the upper metal plate 11 can be selected from 0.1 to 1.0 mm, preferably 0.2 to 0.5 mm, depending on the packaging requirements. The material of the upper metal plate 11 can be copper, aluminum, or other conductive metals, preferably copper, because copper has excellent electrical conductivity, thermal conductivity, and machinability.

[0078] The lower metal plate 12 serves as a process carrier during the packaging process, providing mechanical support. The thickness of the lower metal plate 12 can be selected from 0.2 to 2.0 mm, preferably 0.5 to 1.0 mm, to provide sufficient rigidity. The material of the lower metal plate 12 is also preferably copper. Throughout the packaging process, the lower metal plate 12 remains connected to the upper metal plate 11, providing a stable carrier for chip mounting, soldering, molding, and other processes.

[0079] The intermediate layer is located between the upper metal plate 11 and the lower metal plate 12, serving as a temporary connection and preventing adhesion. The intermediate layer includes a titanium layer, which is used to prevent the upper metal plate 11 and the lower metal plate 12 from metallurgically bonding during high-temperature processes.

[0080] The mechanism of the titanium layer is as follows: Titanium has a melting point as high as 1668℃, far exceeding the temperature range used in packaging processes. During high-temperature processes such as soldering, although temperatures reach 200-220℃ or even higher, they are far below titanium's melting point. Simultaneously, titanium exhibits low reactivity with metals such as copper and tin within this temperature range, making it difficult to form intermetallic compounds. Therefore, the titanium layer forms an effective barrier between the upper metal plate 11 and the lower metal plate 12, preventing metallurgical bonding between the two copper plates at high temperatures through solid-phase diffusion or the formation of intermetallic compounds. Without the titanium layer, Cu-Cu metallurgical bonds may form at the contact interface after multiple high-temperature processes, leading to the lower metal plate 12 being unable to be peeled off after packaging or damaging the structure of the upper metal plate 11 during peeling.

[0081] In one specific example, the intermediate layer further includes a tin layer. The tin layer acts as an adhesive layer, ensuring a reliable mechanical connection between the upper metal plate 11 and the lower metal plate 12 during the process, while preventing excessive bonding force during peeling. Tin has a melting point of 232°C and is solid at room temperature, providing sufficient mechanical strength; at temperatures close to its melting point, tin's plastic deformation ability increases, which is beneficial for the peeling operation. The thickness of the tin layer can be selected from 0.5-5 micrometers, preferably 1-3 micrometers.

[0082] The intermediate layer can have a titanium layer between the upper metal plate 11 and the tin layer, and a tin layer between the titanium layer and the lower metal plate 12; or a tin layer between the upper metal plate 11 and the titanium layer, and a titanium layer between the tin layer and the lower metal plate 12; or titanium layers can be placed on both the upper and lower sides, forming a three-layer structure of titanium-tin-titanium. The specific layer sequence can be optimized according to process requirements and peel performance.

[0083] The intermediate layer can be prepared using thin film deposition techniques such as sputtering, vapor deposition, electroplating, or electroless plating, which are common practices for those skilled in the art and will not be elaborated further.

[0084] The lower metal plate 12 serves as a process carrier and can be peeled off from the upper metal plate 11 after packaging. The peeling operation can be performed after all packaging process steps are completed. The peeling method can be mechanical peeling, i.e., applying shear or tensile force to separate the lower metal plate 12 from the upper metal plate 11 at the interlayer. Due to the blocking effect of the titanium layer, the upper and lower metal plates are connected only through physical contact in the interlayer, rather than by metal bonding; therefore, the peeling process will not damage the upper metal plate 11 or its pads and chip connections.

[0085] In one specific example, the stripping operation can be performed under heating conditions. When the temperature approaches the melting point of tin, the adhesion of the tin layer decreases, which facilitates stripping. The stripped lower metal plate 12 can be cleaned and reused, achieving material recycling and further reducing costs.

[0086] In this embodiment, the lower metal plate 12 integrates the carrier tape function, eliminating the need for additional dedicated carrier tape materials, reducing the attaching and peeling steps of the carrier tape, and simplifying the process flow. The lower metal plate 12 uses conventional copper plate material, which is less expensive than dedicated carrier tapes; moreover, the lower metal plate 12 can be recycled and reused after peeling, further reducing costs. The lower metal plate 12 provides continuous rigid support throughout the packaging process, avoiding alignment errors and mechanical stress that may result from multiple carrier tape replacements, thus improving process stability and yield.

[0087] In the cutting process, conventional methods typically require applying protective tape to the front side to secure and protect the packaging unit. In this embodiment, since the lower metal plate 12 remains connected during cutting, providing bottom support for the packaging unit, the protective tape on the front side can be omitted, simplifying the process and avoiding potential contamination issues caused by tape residue.

[0088] Furthermore, step S1 specifically includes:

[0089] S11: Provides an upper metal plate 11 and a lower metal plate 12. The upper metal plate 11 and the lower metal plate 12 can be made of copper, aluminum, or other metal sheets, preferably copper. The thickness and size of the metal plates are selected according to the packaging requirements.

[0090] S12: Preparation of an intermediate layer. An intermediate layer is deposited on the lower surface of the upper metal plate 11 or the upper surface of the lower metal plate 12 by processes such as sputtering, evaporation, electroplating, or chemical plating. The intermediate layer includes a titanium layer, which is used to prevent metallurgical bonding between the upper metal plate 11 and the lower metal plate 12 during high-temperature processes.

[0091] S13: Adhere the upper metal plate 11 and the lower metal plate 12.

[0092] Furthermore, in step S2, a concave pad 2 and a convex pad 3 are formed on the upper surface of the substrate 1. The concave pad 2 is recessed downward relative to the upper surface of the substrate 1, and the convex pad 3 is convex upward relative to the upper surface of the substrate 1.

[0093] The concave pad 2 and the convex pad 3 can be formed by stamping to create concave and convex structures.

[0094] Step S2 specifically includes the following processes:

[0095] S21: The substrate 1 is stamped from its two opposing upper and lower surfaces respectively;

[0096] S22: Photolithography is performed on the upper surface of the stamped substrate 1 to etch the upper metal plate 11, exposing the central pad area and the surrounding pad area.

[0097] S23: Remove the photoresist 5, and form multiple raised pads 3 in the central pad area and multiple recessed pads 2 in the surrounding pad area.

[0098] For details, please refer to Figure 7 First, the substrate 1 is stamped from its upper and lower surfaces. Specifically, in this embodiment, the substrate 1 is a double-layer metal plate structure, stamped from the upper surface of the upper metal plate 11 and the lower surface of the lower metal plate 12. A first stamping die is used to stamp the surrounding pad area from the upper surface of the upper metal plate 11, forming a downwardly recessed structure relative to the upper surface of the upper metal plate 11 in the surrounding pad area. Simultaneously or subsequently, a second stamping die is used to stamp the central pad area from the lower surface of the lower metal plate 12, forming an upwardly convex structure relative to the upper surface of the upper metal plate 11 in the central pad area. Through stamping in both the upper and lower directions, a highly differentiated pad structure is formed on the upper surface of the upper metal plate 11: the central area convexes relative to the upper surface, while the surrounding area is recessed relative to the upper surface. During the stamping process, the stamping depth and position need to be precisely controlled so that the recess depth and convex height meet the design requirements. It should be noted that the figure only schematically illustrates the concave-convex structure on the upper surface of the upper metal plate 11 and the lower surface of the lower metal plate 12, while the structural changes inside the substrate 1 caused by stamping are not shown.

[0099] Next, photolithography and etching are performed on the upper surface of the stamped substrate 1. For details, please refer to... Figure 8 - Figure 9 Photoresist 5 is coated on the upper surface of the upper metal plate 11, and the photoresist 5 is patterned. The photoresist 5 is retained as a protective layer in the central and surrounding pad areas, while the photoresist 5 in the non-pad areas is removed to expose them. Please refer to [reference needed]. Figure 10 - Figure 11Then, the exposed non-pad areas are etched to remove the metal layer in the non-pad areas, while the metal in the pad areas is retained due to the protection of the photoresist 5. The etching method can be wet etching or dry etching, stopping at the intermediate layer. Finally, the photoresist 5 in the pad areas is removed, exposing the metal pads in the central pad area and the surrounding pad areas. The central pad area forms multiple raised pads 3, which bulge upwards relative to the upper surface of the upper metal plate 11; the surrounding pad area forms multiple recessed pads 2, which are recessed downwards relative to the upper surface of the upper metal plate 11.

[0100] Furthermore, in steps S3-S4, the first chip 41 is mounted onto the substrate 1 and electrically connected through the raised pad 3; the second chip 42 is mounted onto the first chip 41 and electrically connected through the recessed pad 2.

[0101] In another specific example, a third chip is then attached to the second chip 42 and electrically connected through the concave pad 2.

[0102] During the mounting process, the lower metal plate 12 serves as a process carrier to provide rigid support, preventing the substrate 1 from bending and deforming, and improving mounting accuracy and wire bonding quality.

[0103] Furthermore, in step S5, subsequent encapsulation processes are performed, including but not limited to: underfill, molding, marking, and cutting. During the cutting process, in the double-layer metal plate structure, the lower metal plate 12 remains connected during cutting, providing bottom support for the encapsulation unit. Cutting may only cut the upper metal plate 11 and the encapsulation body, without cutting the lower metal plate 12; or it may partially cut into the lower metal plate 12 but not completely sever it. In this way, the individual encapsulation units after cutting are still connected together by the lower metal plate 12, eliminating the need for applying protective adhesive tape (DAF tape) to the front for fixation. This simplifies the process, reduces costs, and avoids potential contamination of the encapsulation unit surface by tape residue.

[0104] Furthermore, in step S6, after the packaging process is completed, the intermediate layer and the lower metal plate 12 are peeled off from the upper metal plate 11.

[0105] The peeling operation can be performed after the cutting process. Mechanical peeling can be used, employing peeling equipment to apply shear or tensile force to separate the intermediate layer and lower metal plate 12 from the upper metal plate 11. Due to the blocking effect of the titanium layer, no metallurgical bond is formed between the upper and lower metal plates. The peeling process only needs to overcome the physical bonding force of the intermediate layer; therefore, the peeling force is relatively small and will not damage the upper metal plate 11 or its pads and circuitry.

[0106] In one specific example, stripping can be performed under heating conditions, with the temperature controlled in a range close to the melting point of the tin layer (e.g., 180-230°C), to soften the tin layer, reduce adhesion, and make it easier to strip. After stripping, some intermediate layer material may remain on the surface of the lower metal plate 12, which can be reused after cleaning.

[0107] After peeling, the chip packaging structure is separated from the intermediate layer and the lower metal plate 12, and can be used for subsequent testing, packaging and other processes.

[0108] Compared to traditional encapsulation processes using polystyrene (PS) plastic carrier tapes, whose reflow temperature is limited to 180-200°C, this embodiment raises the soldering temperature to 200-220°C. At this temperature, the solder can melt more fully, achieving better fluidity and wettability, resulting in a more uniform and reliable weld joint.

[0109] In summary, the beneficial effects of this invention are as follows: The recessed structure of the concave pads provides physical protection for the connection points of wire bonding, preventing the bonding interface from detaching or being damaged due to thermal stress during soldering or other high-temperature processes at 200-220°C. This structure is particularly suitable for hybrid packaging processes. When flip chips are soldered, the previously completed wire bonding connections can remain stable under high-temperature environments, improving the reliability and yield of the package. The differentiated design of the concave and convex pads enables multi-chip stacked packaging. High-density interconnection is achieved within a limited package area, improving integration. The use of a double-layer metal plate structure, with the lower metal plate integrating the process carrier tape function, eliminates the need for additional dedicated carrier tape, reducing carrier tape attachment and peeling steps. During the dicing process, the lower metal plate provides bottom support, eliminating the need for front protective tape and further simplifying the process. The lower metal plate uses conventional copper plate material, which is less expensive than dedicated carrier tape; and it can be recycled after peeling, achieving material recycling and significantly reducing packaging costs. The lower metal plate provides continuous rigid support throughout the packaging process, avoiding substrate deformation and alignment errors caused by multiple carrier tape changes, thus improving process stability. The titanium layer's barrier effect ensures reliable peeling of the upper and lower metal plates after multiple high-temperature processes without damaging the packaging structure. This invention simplifies the process and reduces costs, providing an excellent technical solution for high-density, high-reliability chip packaging, with broad application prospects and significant economic benefits.

[0110] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A chip packaging method, characterized in that, include: Provide substrate; Concave pads and convex pads are formed on the upper surface of the substrate. The concave pads are recessed downward relative to the upper surface of the substrate, and the convex pads are convex upward relative to the upper surface of the substrate. The substrate includes an upper metal plate, a lower metal plate, and an intermediate layer located between the upper and lower metal plates. The concave pads and the convex pads are formed by the upper metal plate. The process includes: stamping the substrate from its upper and lower surfaces respectively; performing photolithography and etching on the upper surface of the stamped substrate to expose a central pad area and a surrounding pad area; removing the photoresist, thereby forming a plurality of convex pads in the central pad area and a plurality of concave pads in the surrounding pad area. The first chip is mounted onto the substrate and electrically connected via the solder pads. The second chip is attached to the first chip and electrically connected through the concave pad. Perform encapsulation; During cutting, the connection of the lower metal plate is kept intact or only partially cut into the lower metal plate without completely severing it; The intermediate layer and the lower metal plate are peeled off from the upper metal plate.

2. The chip packaging method according to claim 1, characterized in that, The intermediate layer includes a titanium layer and a tin layer.

3. The chip packaging method according to claim 1, characterized in that, The welding temperature during the encapsulation process is 200-220℃.

4. A chip packaging structure, characterized in that, Manufactured by the chip packaging method according to any one of claims 1 to 3, comprising: A substrate, wherein concave pads and convex pads are formed on the upper surface of the substrate, the concave pads and convex pads are formed by stamping the same metal layer of the substrate, the concave pads are recessed downward relative to the upper surface of the substrate, and the convex pads are convex upward relative to the upper surface of the substrate. The first chip is electrically connected to the substrate via the solder pads; The second chip is electrically connected to the substrate via the concave pad.

5. The chip packaging structure according to claim 4, characterized in that, The recessed pad has a depth of 50-200 micrometers, and the raised pad has a height of 30-150 micrometers.

6. The chip packaging structure according to claim 4, characterized in that, The concave pads are located in the outer region of the substrate, and the convex pads are located in the central region of the substrate.

7. The chip packaging structure according to claim 4 or 6, characterized in that, The second chip, the first chip, and the substrate are stacked in sequence.

8. The chip packaging structure according to claim 7, characterized in that, It also includes a third chip, which is disposed on the second chip and is electrically connected to the substrate through the concave pad.

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