Precise synthesis-based graph mapping method

Abstract

The invention discloses a graph mapping method based on precise synthesis, and the method comprises the steps: constructing a precise synthesis structure library based on NPN equivalence classes, and inputting the precise synthesis structure library into a Boolean network; k-Cut cutting enumeration is carried out on the input Boolean network, a truth table is calculated, cutting is matched with a structure in a precise comprehensive structure library through Boolean matching, and rapid search is realized in combination with NPN classification; the overlay network is generated through multi-round mapping optimization, logic sharing nodes are mined in combination with structural hash, and the multi-round mapping optimization comprises delay-oriented mapping, global area topological optimization and local accurate area optimization; and a new target network is generated based on the optimized overlay network, redundant nodes are removed, and final network construction is completed. According to the method, manual intervention is not needed through full-process automatic mapping and a redundancy removal mechanism, the labor cost of a technical mapping link in chip design is remarkably reduced, and the method is particularly suitable for efficient design of complex circuits and emerging majority of logic base technologies.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and in particular to a graph mapping method based on exact synthesis. BACKGROUND

[0002] In the design of digital integrated circuits, technology mapping is a key step to convert technology-independent Boolean networks (such as NAND graphs, majority voting graphs) into technology-dependent structures (such as standard cells, lookup tables), which directly affects the area, delay and power consumption performance of the chip. The traditional technology mapping method has significant limitations:

[0003] On the one hand, the logic sharing capability is insufficient. Existing methods mostly rely on a single graph representation (such as only based on AIG) or a fixed cutting strategy, making it difficult to tap the sharing potential between different logic structures, resulting in too many redundant nodes and limited area optimization effect. For example, LUT-based mapping is prone to lose the shared logic of the original network when covering the circuit, and introduces additional nodes after decomposition.

[0004] On the other hand, the global optimization capability is limited. Traditional methods mostly use local greedy strategies (such as optimizing single-node cutting), lack of consideration of the global area and delay of the circuit, and are prone to local optimization. At the same time, the manually designed mapping process needs to adjust parameters for different technology nodes, which is inefficient and difficult to adapt to the design needs of complex circuits and emerging technologies (such as adiabatic quantum flux parameterizer superconducting circuits, quantum dot cellular automata).

[0005] Therefore, there is an urgent need for an efficient mapping method that can dynamically integrate the advantages of multiple graph representations, achieve global optimization and logic sharing, to break through the performance bottleneck of traditional methods. SUMMARY

[0006] The purpose of the present application is to provide a graph mapping method based on exact synthesis to solve one or more technical problems existing in the prior art, at least to provide a beneficial choice or create conditions.

[0007] The present application adopts the following technical solutions to achieve the above-mentioned application purposes:

[0008] The present application provides a graph mapping method based on exact synthesis, comprising:

[0009] Construct an exact synthesis structure library based on NPN equivalence classes and input a Boolean network;

[0010] Perform k-Cut cutting enumeration on the input Boolean network and calculate the truth table, match the cutting with the structures in the exact synthesis structure library through Boolean matching, and realize fast lookup combined with NPN classification;

[0011] The covering network is generated through multi-round mapping optimization, and the logic sharing node is mined in combination with structure hash, wherein the multi-round mapping optimization comprises delay-oriented mapping, global area topology optimization and local accurate area optimization;

[0012] A new target network is generated based on the optimized covering network, redundant nodes are removed, and final network construction is completed.

[0013] Further, the input Boolean network is cut and enumerated by k-Cut, and a truth table is calculated, the cut is matched with the structure in the accurate synthesis structure library through Boolean matching, and fast searching is realized in combination with NPN classification, including:

[0014] The cut enumeration of the input Boolean network is performed in topological order, the k-Cut cut is reserved, and the truth table is minimized, and the Boolean matching considers the positive and negative polarities to optimize the logic sharing;

[0015] The NPN equivalence class function corresponding to each K-Cut cut is calculated, the minimum structure of each NPN class with 5 inputs or less is generated through the accurate synthesis tool, and the parameters of the structure are recorded;

[0016] For each NPN class, multiple alternative structures are stored to cope with different optimization objectives.

[0017] Further, the cut enumeration of the input Boolean network is performed in topological order, the k-Cut cut is reserved, and the truth table is minimized, and the Boolean matching considers the positive and negative polarities to optimize the logic sharing, including:

[0018] When the cut enumeration reserves the k-Cut cut, the topological order is guaranteed by traversing the network through a topological view;

[0019] The cut reservation strategy reserves at most cut_limit cuts for each node, sorts the cuts in the order of "size first, delay second", minimizes the truth table of the cut, and removes variables without functional support;

[0020] The positive and negative polarity matching calculates the inverse form ~f of the truth table f of each cut, respectively searches for matching structures in the library, and realizes logic sharing.

[0021] Further, the delay-oriented mapping selects the cut according to the arrival time, and selects the cut that meets the delay, including:

[0022] In the delay-oriented mapping, the arrival time of the primary input node is initialized to 0;

[0023] The arrival time of the combination node is the maximum value of the sum of the arrival times of all inputs and the corresponding input pin delay;

[0024] For each node, the arrival time of the best matching structure is calculated for the positive and negative phases, respectively.

[0025] Further, the global area topology optimization is a global area optimization based on area topology iterative adjustment cut selection coverage, comprising:

[0026] In the global area topology optimization, the area topology is defined as the weighted sum of the node's own area and the area topology of all predecessor nodes according to the fan-out ratio;

[0027] By iteratively updating the area topology in reverse topological order, the area topology of the node accurately reflects its contribution to the global area, thereby tending to select a cut with smaller area topology and reducing global area redundancy.

[0028] Further, the local accurate area optimization reduces the area by using an accurate area algorithm to select the optimal cut coverage, comprising:

[0029] The local area optimization traverses the nodes in topological order;

[0030] The accurate area of the candidate cut is recursively calculated, comprising:

[0031] The area of the logic gate itself is first calculated;

[0032] Then, the area contribution of the leaf node is recursively accumulated according to its reference count to accurately evaluate the new area and select a more optimal cut to reduce the area.

[0033] Further, a new target network is generated based on the optimized coverage network, redundant nodes are removed, and the final network construction is completed, comprising:

[0034] The primary inputs of the input Boolean network are traversed, and corresponding input nodes are created in the target network;

[0035] According to the optimized coverage network, a matching target structure is created for each node in topological order, and the connection relationship between nodes is established;

[0036] The redundant node removal operation is performed to delete the dangling nodes in the target network that are not referenced by the primary output, and the final network construction is completed.

[0037] Further, the primary inputs of the input Boolean network are traversed, and corresponding input nodes are created in the target network, comprising:

[0038] For a combinational circuit, nodes consistent with the number of primary inputs of the input network are directly created, and the fan-out list is initialized to empty;

[0039] For a sequential circuit, a D flip-flop node is additionally created, with its data input connected to the combinational logic output, its clock input connected to the global clock signal, and its reset input connected to the global reset signal, so that the timing characteristics are consistent with the original network.

[0040] Further, according to the optimized overlay network, a matching target structure is created for each node in topological order, and a connection relationship between nodes is established, including:

[0041] The node is strictly created in topological order, ensuring that all predecessor nodes of the current node have been completed.

[0042] For each node, the matching super gate is called according to the best cut leaf set {c1, c2,..., ck}, and the output of the leaf node is connected to the input of the super gate.

[0043] If the cut truth table requires a leaf c2 to be inverted, an inverter is inserted between c2 and the super gate.

[0044] For the substructure of the super gate, the sub-gate is recursively created and connected according to the library-defined topology, so that the internal structure is complete.

[0045] Further, a redundant node removal operation is performed to delete the dangling nodes in the target network that are not referenced by the primary output, and the final network construction is completed, including:

[0046] Starting from the primary output node, all directly or indirectly referenced nodes are traversed through depth-first search and marked as "valid";

[0047] Traverse the target network and delete all nodes marked as "invalid" and all their input and output edges;

[0048] Check if the source node and the target node of all edges exist, remove the dangling edges whose source node or target node has been deleted, so that there is no invalid connection in the network topology, and the final network construction is completed.

[0049] The beneficial effects of the present application are as follows:

[0050] The present application can be applied to the heterogeneous characteristics of multi-graph representation of digital logic circuits, and according to the topological structure and functional requirements of the input Boolean network, the k-Cut cut enumeration and truth table optimization are performed on the nodes, and the adaptive target structure is obtained by combining the NPN equivalence class matching. In multiple rounds of optimization, the global area flow and local accurate area adjustment are coordinated, and the logic sharing node is dynamically mined, rather than relying only on the logic graph or local cut selection. Compared with the traditional technology mapping method, the optimization space can be more fully explored, and the area and delay of the given circuit can be optimized. At the same time, the automatic mapping and redundant removal mechanism throughout the process does not require human intervention, which significantly reduces the labor cost in the technology mapping link of chip design, and is especially suitable for efficient design of complex circuits and emerging majority logic technology. BRIEF DESCRIPTION OF DRAWINGS

[0051] Fig. 1A flowchart of an overall process of a method for efficiently simplifying a digital logic circuit based on deep learning is provided according to an embodiment of the present application.

[0052] Fig. 2 A mapping optimization schematic diagram of cutting and accurate area coverage of a circuit in a method for efficiently simplifying a digital logic circuit based on deep learning is provided according to an embodiment of the present application.

[0053] Fig. 3 A super gate coverage schematic diagram of generating a new network in a method for efficiently simplifying a digital logic circuit based on deep learning is provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0054] The graph mapping method based on accurate synthesis provided by the present application, on the one hand, breaks through the logic sharing limitation of traditional logic graphs by constructing a unified NPN equivalence class structure library, fusing the adaptation ability of multiple graph representations (NAND graph, majority voting graph, XOR-AND-inverter graph, etc.), precomputing the minimum structure by using accurate synthesis, and combining forward and reverse polarity matching, and effectively excavates the sharing potential between different logic structures; on the other hand, by means of multi-round global-local optimization (delay-oriented mapping, area topology optimization, accurate area optimization) and structure hash technology, the collaborative optimization of area and delay is realized, and the performance bottleneck of local greedy strategy is avoided. The method reduces manual intervention through automatic cutting enumeration and matching process, significantly improves the mapping efficiency (17% higher than traditional methods), supports flexible conversion between multiple graph representations, can directly adapt to emerging technologies of majority logic base (such as AQFP superconducting circuit), and is more easily to realize global optimization compared with fixed process method, thereby providing a high-performance mapping solution with area and delay advantages for complex circuit design.

[0055] As shown in Figs. 1-3 The graph mapping method based on accurate synthesis provided by the present application specifically includes the following steps:

[0056] S100: Construct an accurate synthesis structure library based on NPN equivalence class, and input a Boolean network.

[0057] S200: Perform k-Cut cutting enumeration on the input Boolean network and calculate a truth table, match the cutting with the structures in the accurate synthesis structure library through Boolean matching, and realize fast lookup in combination with NPN classification.

[0058] In the above S100 and S200, specifically includes:

[0059] The cutting enumeration is performed in topological order, the k-Cut cutting is retained and the truth table is minimized, and the Boolean matching simultaneously considers forward and reverse polarity to optimize logic sharing;

[0060] Cut enumeration guarantees the topological order by traversing the network in topological view, ensuring that the cut enumeration of the parent node is completed after the child node to avoid dependency conflicts. The cut reservation strategy reserves at most cut_limit cuts (default 49) for each node, sorted by "size first, delay second", prioritizing small size and low delay cuts. Meanwhile, the truth table of the cut is minimized by removing non-functional supported variables to compress the size and improve matching efficiency. Forward and reverse polarity matching calculates the inverse form ~f for each cut truth table f, and searches for matching structures in the library. If f matches a 2-input AND gate (AND2) and ~f matches a 2-input NAND gate (NAND2), the optimal option is selected based on area and delay. For example, when multiple fanout nodes require inverted output, a 2-input NAND gate is preferred to reduce the number of inverters and achieve logic sharing.

[0061] The NPN equivalence class function corresponding to each k-Cut cut is calculated, and the minimum structure of each NPN class with 5 inputs or less is generated by an accurate synthesis tool (such as a SAT-based synthesis tool), such as an AIG NAND gate structure, a MIG majority gate structure, and an XAG XOR-AND structure. The node count, depth, and other parameters of the structure are recorded. For each NPN class, multiple alternative networks of the same NPN function are stored to address different optimization objectives (area priority or delay priority).

[0062] S300: Generate a cover network through multiple rounds of mapping optimization, combined with structure hash mining to find logic sharing nodes, wherein the multiple rounds of mapping optimization include delay-oriented mapping, global area topology optimization, and local accurate area optimization.

[0063] In the above S300, specifically comprising:

[0064] Delay-oriented mapping selects cuts based on arrival time:

[0065] The arrival time calculation rule is: the arrival time of the primary input (PI) node is initialized to 0; the arrival time of the combination node is the maximum of the sum of the arrival times of all inputs and the corresponding input pin delay, i.e. the arrival time of node n = max (arrival time of input leaf + leaf pin delay to n). For each node, the arrival time of the best matching structure is calculated for the positive and negative phases respectively;

[0066] Global area optimization adjusts Cut selection coverage based on area topology iteration:

[0067] In global area topology optimization, the area topology of a node is defined as the weighted sum of the node's own area and the area topologies of all its predecessor nodes according to the fan-out ratio, i.e., the area topology of node n = the area of node n + Σ (the area topology of an input leaf node * the fan-out number of the leaf node to n / the total fan-out number of the leaf node), where the weight reflects the proportion of the current node in the total fan-out of the leaf node. By iteratively updating the area topology in reverse topological order from the primary output to the primary input, the area topology of a node is more accurately reflected in its contribution to the global area, and thus the selection of a cut with a smaller area topology (e.g., a cut with a high sharing degree) is favored, reducing the global area redundancy.

[0068] Local area optimization reduces the area by selecting the optimal Cut cut to cover:

[0069] Local precise area optimization traverses the nodes in topological order throughout the entire network: for each candidate cut of a node, the precise area is calculated recursively. During the calculation, in combination with the reference count of the leaf node, when the leaf node is shared by multiple cuts, according to the number of times it is referenced by the current cut, its area contribution to the current cut is recursively accumulated. Specifically, the area of the logical gate corresponding to the cut is first calculated, and then the area contributed by the leaf node is recursively accumulated according to the reference of the leaf node in the current cut, so as to accurately evaluate the actual incremental area of the cut, and to reduce the area by selecting a better cut.

[0070] To solve the problem of insufficient logic sharing capability and excessive redundant nodes in traditional mapping methods, the structure hashing technology is introduced to mine logical shared nodes during the generation of the overlay network.

[0071] The specific implementation is as follows: the logical structure (such as a super gate, a combination of sub-gates) corresponding to the candidate cut selected after multiple rounds of optimization is hashed — taking the truth table features, input and output polarities, and internal topological connection relationships of the structure as the hash keys, a global structure hash table is constructed. When the structure hash value of a new candidate cut already exists in the table, it indicates that the logical structure has been reused by other nodes in the network, and there is no need to repeatedly construct a new node, and the existing shared node can be directly referenced; if the hash value does not exist, the hash keys of the structure and the node reference information are stored in the table to complete the registration of the new structure. The core purpose of this operation is to actively reduce the generation of redundancy during the generation of the overlay network: by reusing shared nodes, the construction of repeated logical structures is avoided, which directly reduces the global area and makes the 'contribution of a node to the global area' calculation more accurate in subsequent global area topology optimization (reducing the interference of repeated structures on the area weight). At the same time, the shared nodes mined by the structure hashing need to meet the delay constraint matching with the current node to ensure that the area optimization does not sacrifice the timing performance.

[0072] S400: Based on the optimized overlay network, a new target network is generated, redundant nodes are removed, and the final network construction is completed.

[0073] In the above S400, specifically includes:

[0074] Traverse the primary input of the input Boolean network, create corresponding input nodes in the target network:

[0075] For combinational circuits, directly create nodes consistent with the number of primary inputs of the input network, the node type is marked as "input", and the fanout list is initialized as empty; for sequential circuits, additional D flip-flop nodes (type "ff") are created, whose data input is connected to the output of the combinational logic, the clock input is connected to the global clock signal (defined as rising edge / falling edge in the original network), and the reset input is connected to the global reset signal (active high / low), ensuring that the timing characteristics are consistent with the original network;

[0076] According to the optimized cover network, create matching target structures (such as standard cells, majority gates, etc.) for each node in topological order, and establish the connection relationship between nodes:

[0077] Strictly create nodes in topological order (from input to output), ensuring that all predecessor nodes of the current node have been created. For each node, call the matching supergate (such as 3-input majority gate MAJ3) according to the best cut leaf set {c1, c2,..., ck}, and connect the output of the leaf node to the input of the supergate; if the Cut truth table requires a leaf (such as c2) to be inverted, an inverter is inserted between c2 and the supergate. For the substructure of the supergate (such as MAJ3 consisting of 2 AND gates and 1 OR gate), recursively create subgates and connect them according to the library-defined topology, ensuring the integrity of the internal structure;

[0078] Perform redundant node removal operation to delete dangling nodes in the target network that are not referenced by the primary output, ensuring network integrity:

[0079] Mark all reachable nodes: starting from the primary output node, traverse all directly or indirectly referenced nodes through depth-first search (DFS), and mark them as "valid"; traverse the target network, delete all nodes marked as "invalid" and all their input / output edges to avoid redundant logic; check if the source node and target node of all edges exist, remove dangling edges whose source node or target node has been deleted, ensure that there are no invalid connections in the network topology, and complete the final network construction.

[0080] Structural hashing is to actively reuse logical structures in the cover network generation phase, reducing duplicate nodes from the source; while redundant node removal is to traverse the reachable nodes of the primary output through depth-first search after the target network is built, cleaning up dangling nodes that are not referenced (including isolated nodes that are not shared and have no actual function).

[0081] As shown in the following table, in the MIG test cases of the EPFL combinational logic circuit, the embodiment adopts the graph mapping algorithm based on exact synthesis to realize the mapping of MIG and AIG circuits. Due to the inherent differences between the two types of circuit structures, performance loss is easy to occur in the mapping process. In the experiment, the number of nodes (Node) is used as the measurement index of the area of the AIG circuit, and the results show that: when mapping the MIG circuit into the AIG circuit, compared with the current latest Versatile Mapping algorithm, the number of nodes of the AIG circuit obtained by the algorithm is reduced by an average of 17.7%, effectively verifying the improvement of the quality of the mapped circuit.

[0082]

[0083] In summary, through the above graph mapping method based on exact synthesis, the present application can be aimed at the multi-graph representation heterogeneous characteristics of digital logic circuits, according to the topological structure and functional requirements of the input Boolean network, perform k-Cut cutting enumeration and truth table optimization on the nodes, and obtain the adaptive target structure combined with NPN equivalence class matching; and in multiple rounds of optimization, coordinate global area flow and local accurate area adjustment, dynamically mine logical shared nodes, rather than relying only on logical graphs or local cutting selection, compared with the traditional technology mapping method, it can realize more comprehensive exploration of the optimization space, and realize the cooperative optimization of area and delay for the given circuit. At the same time, the whole-process automatic mapping and redundancy removal mechanism does not require manual intervention, significantly reducing the labor cost in the technical mapping link of chip design, and is especially suitable for efficient design of complex circuits and emerging majority logic technology.

[0084] The above only describes the preferred embodiments of the present application, and it should be pointed out that for ordinary skilled persons in the technical field, several improvements and modifications can be made without departing from the technical principles of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A graph mapping method based on exact synthesis, characterized in that, include: Construct a precise synthesis structure library based on NPN equivalence classes and input a Boolean network; The input Boolean network is k-cut enumerated and the truth table is calculated. The cuts are matched with the structures in the accurate synthesis structure library through Boolean matching. Combined with NPN classification, fast search is achieved. The overlay network is generated through multi-round mapping optimization, and shared nodes are obtained by combining structural hash mining logic. The multi-round mapping optimization includes delay-guided mapping, global area topology optimization, and local precise area optimization. A new target network is generated based on the optimized overlay network, redundant nodes are removed, and the final network construction is completed.

2. The graph mapping method based on exact synthesis according to claim 1, characterized in that, The input Boolean network is k-cut and the truth table is computed. Boolean matching is used to match the cuts with structures in a precise synthetic structure library. Combined with NPN classification, fast lookup is achieved, including: The input Boolean network cut enumeration is performed in topological order, preserving the k-Cut cut and minimizing the truth table. Boolean matching considers both positive and negative polarity to optimize logical sharing. Calculate the NPN equivalence class function corresponding to each K-Cut cut, generate the minimum structure of each NPN class with no more than 5 inputs using the exact synthesis tool, and record the parameters of the structure; For each NPN class, multiple alternative structures are stored to address different optimization objectives.

3. The graph mapping method based on exact synthesis according to claim 2, characterized in that, The input Boolean network cut enumeration is performed in topological order, preserving the k-Cut cut and minimizing the truth table. Boolean matching considers both positive and negative polarities to optimize logical sharing, including: When preserving the k-Cut cut during cut enumeration, the topological order is ensured by traversing the network through a topological view. The cut retention strategy retains at most cut_limit cuts for each node, sorted by "size first, delay second", minimizes the truth table of cuts, and removes variables that do not support functionality. For each cut truth table f, the forward and reverse polarity matching synchronously calculates its inverse form ~f, and searches for matching structures in the library to achieve logical sharing.

4. The graph mapping method based on exact synthesis according to claim 1, characterized in that, The delay-guided mapping selects segments based on arrival time, choosing segments that meet the delay requirements, including: In delayed guided mapping, the arrival time of the primary input node is initialized to 0; The arrival time of a composite node is the maximum of the sum of the arrival times of all its inputs and the delays of the corresponding input pins; For the positive and negative phases of each node, calculate the arrival time of the optimal matching structure.

5. A graph mapping method based on exact synthesis according to claim 1, characterized in that, The global area topology optimization is a global area optimization based on area topology iteration to adjust the cut selection coverage, including: In global area topology optimization, area topology is defined as the weighted sum of the area of ​​a node itself and the area topology of all its predecessor nodes in proportion to their fan-out ratio. By iteratively updating the area topology in reverse topological order, the area topology of a node accurately reflects its contribution to the global area, thus tending to select cuts with smaller area topologies and reducing global area redundancy.

6. The graph mapping method based on exact synthesis according to claim 1, characterized in that, The local precise area optimization reduces the area through a precise area algorithm and selects the optimal cut coverage, including: Local area optimization involves traversing nodes in topological order. Recursively calculate the precise area of ​​candidate cuts, including: First, calculate the area of ​​the logic gate itself; Then, based on the reference count of the leaf nodes, their area contribution is recursively accumulated to accurately evaluate the newly added area and select a better cut to reduce the area.

7. The graph mapping method based on exact synthesis according to claim 1, characterized in that, A new target network is generated based on the optimized overlay network, redundant nodes are removed, and the final network construction is completed, including: Traverse the primary inputs of the input Boolean network and create the corresponding input nodes in the target network; Based on the optimized coverage network, a matching target structure is created for each node in topological order, and the connection relationship between the nodes is established. Perform redundant node removal operation to delete dangling nodes in the target network that are not referenced by the primary output, and complete the final network construction.

8. A graph mapping method based on exact synthesis according to claim 7, characterized in that, Iterate through the primary inputs of the input Boolean network and create corresponding input nodes in the target network, including: For combinational circuits, directly create nodes with the same number of primary inputs as the input network, and initialize the fanout list to empty; For sequential circuits, an additional D flip-flop node is created, with its data input connected to the combinational logic output, clock input connected to the global clock signal, and reset input connected to the global reset signal, so that the timing characteristics are consistent with the original network.

9. A graph mapping method based on exact synthesis according to claim 7, characterized in that, Based on the optimized coverage network, a matching target structure is created for each node in topological order, and the connection relationships between nodes are established, including: Create nodes strictly according to the topological order, ensuring that all predecessor nodes of the current node have been created; For each node, the matching super gate is invoked based on the optimal leaf set {c1,c2,...,ck}, and the output of the leaf node is connected to the input of the super gate; If the truth table of cutting requires that a certain leaf c2 be inverted, then an inverter is inserted between c2 and the supergate; For the substructures of the supergate, subgates are recursively created and connected according to the topology defined in the library to make the internal structure complete.

10. A graph mapping method based on exact synthesis according to claim 7, characterized in that, Perform redundant node removal operations to delete dangling nodes in the target network that are not referenced by the primary output, completing the final network construction, including: Starting from the primary output node, traverse all nodes that are directly or indirectly referenced by the node using a depth-first search and mark them as "valid". Traverse the target network and delete all nodes marked as "invalid" and all their input and output edges; Check if the source and target nodes of all edges exist, remove any dangling edges whose source or target nodes have been deleted, so that there are no invalid connections in the network topology, and complete the final network construction.

Images