Memory model configuration method and device, computer equipment and storage medium

Abstract

The invention relates to a memory model configuration method and device, computer equipment and a storage medium, the method is applied to core grain verification, a core grain comprises a plurality of chip sets, and each chip set has a corresponding verification environment; the method comprises the following steps: acquiring the total access times of each chip set for accessing a memory model in a chip grain verification process; and determining the verification environment corresponding to the chipset with the maximum total access frequency as a target environment for configuring the memory model. The memory model is configured into the verification environment corresponding to the chipset with the maximum total access frequency, so that the cross-thread request of each chipset in the core grain verification process can be reduced, and the simulation efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular to a method, apparatus, computer device, and storage medium for configuring a memory model. Background Technology

[0002] In chip verification, typically only the functional module under test (DUT) uses real hardware, while other functional modules often use functional module models. Additionally, processors use processor models, and storage systems are simulated using memory models.

[0003] With the advent of chiplet technology, chiplets are increasingly being used in chip design. A chiplet can contain multiple chips, and its verification environment typically includes verification environments for multiple chips. Therefore, configuring the memory models for each chip verification environment has become a critical technical problem to be solved in chiplet verification. Summary of the Invention

[0004] Based on this, this application provides a method, apparatus, computer device, computer-readable storage medium, and computer program product for configuring a memory model that can effectively determine the memory model configuration environment.

[0005] Firstly, this application provides a method for configuring a memory model, the method being applied to chip verification, wherein the chip comprises multiple chips, each chip having a corresponding verification environment; the method includes:

[0006] Obtain the number of times each chip accesses the memory model during the chip verification process;

[0007] The verification environment corresponding to the chip with the highest number of accesses is determined as the target environment for configuring the memory model.

[0008] In one embodiment, obtaining the number of times each chip accesses the memory model during the chip verification process includes: obtaining the number of times each chip writes memory and reads memory during the chip verification process; and determining the number of times each chip accesses the memory model based on the number of times each chip writes memory and reads memory.

[0009] In one embodiment, obtaining the number of memory writes and the number of memory reads for each chip during the chip verification process includes: determining the function type of each chip; and obtaining the number of memory writes and the number of memory reads for each chip during the chip verification process using a matching estimation method based on the function type of the chip.

[0010] In one embodiment, the memory model includes on-chip storage, off-chip storage, and system storage; obtaining the number of memory writes and reads for each chip during the chip verification process includes: for each chip, calculating the first number of writes to the on-chip storage, the second number of writes to the off-chip storage, and the third number of writes to the system storage during the chip verification process based on a preset estimation method; determining the sum of the first, second, and third writes; and determining the sum as the number of memory writes for the chip during the chip verification process; and calculating the first number of reads to the on-chip storage, the second number of reads to the off-chip storage, and the third number of reads to the system storage during the chip verification process based on the estimation method; determining the sum of the first, second, and third reads; and determining the sum as the number of memory reads for the chip during the chip verification process.

[0011] In one embodiment, the estimation method includes at least one of waveform statistics based on a single-chip verification environment, analogy with similar chips, electronic design automation analysis, and empirical estimation.

[0012] In one embodiment, the method further includes configuring the memory model in the target environment for chip verification.

[0013] Secondly, this application provides a method for configuring a memory model, the method being applied to chip verification, wherein the chip includes multiple chipsets, each chipset having a corresponding verification environment; the method includes:

[0014] Obtain the total number of times the memory model is accessed for each of the chipsets during the chip verification process;

[0015] The verification environment corresponding to the chipset with the highest total number of accesses is determined as the target environment for configuring the memory model.

[0016] In one embodiment, each chipset includes one or more chips; obtaining the total number of times the memory model is accessed during the chip verification process for each chipset includes: for each chipset, obtaining the number of times the memory model is accessed by each chip in the chipset during the chip verification process; obtaining the sum of the number of times the memory model is accessed by each chip in the chipset, and determining the sum as the total number of times the memory model is accessed by the chipset.

[0017] In one embodiment, the above-mentioned method of obtaining the number of times each chip in the chipset accesses the memory model during the chip verification process includes: obtaining the number of times each chip in the chipset performs memory writes and the number of times each chip performs memory reads during the chip verification process; and determining the number of times each chip accesses the memory model based on the number of times each chip performs writes and the number of times each chip performs reads.

[0018] In one embodiment, obtaining the number of memory writes and the number of memory reads for each chip in the chipset during the chip verification process includes: determining the function type of each chip in the chipset; and obtaining the number of memory writes and the number of memory reads for each chip during the chip verification process using a matching estimation method based on the function type of the chip.

[0019] In one embodiment, the memory model includes on-chip storage, off-chip storage, and system storage; obtaining the number of memory writes and reads for each chip in the chipset during chip verification includes: for each chip, calculating the first number of writes to the on-chip storage, the second number of writes to the off-chip storage, and the third number of writes to the system storage during chip verification based on a preset estimation method; determining the sum of the first, second, and third writes; and determining the sum as the number of memory writes for the chip during chip verification; and calculating the first number of reads to the on-chip storage, the second number of reads to the off-chip storage, and the third number of reads to the system storage during chip verification based on the estimation method; determining the sum of the first, second, and third reads; and determining the sum as the number of memory reads for the chip during chip verification.

[0020] In one embodiment, the estimation method includes at least one of waveform statistics based on a single-chip verification environment, analogy with similar chips, electronic design automation analysis, and empirical estimation.

[0021] In one embodiment, the method further includes configuring the memory model in the target environment for chip verification.

[0022] In one embodiment, the plurality of chipsets includes a first chipset and a second chipset. The verification environment of the first chipset uses a first thread, and the verification environment of the second chipset uses a second thread. The chip verification includes: if the verification environment of the first chipset is a target environment, upon receiving a read / write memory operation on any chip in the first chipset, accessing the memory model based on the first thread to process the read / write memory operation; establishing cross-thread communication between the second thread of the second chipset and the first thread of the first chipset, and upon receiving a read / write memory operation on any chip in the second chipset, accessing the memory model through the second thread based on the cross-thread communication to process the read / write memory operation.

[0023] Thirdly, this application provides a memory model configuration apparatus, which is applied to chip verification, wherein the chip includes multiple chips, each chip having a corresponding verification environment; the apparatus includes:

[0024] The access count acquisition module is configured to acquire the number of times each chip accesses the memory model during the chip verification process;

[0025] The configuration environment determination module is configured to determine the verification environment corresponding to the chip with the highest number of accesses as the target environment for configuring the memory model.

[0026] Fourthly, this application provides a memory model configuration apparatus, which is applied to chip verification, wherein the chip includes multiple chipsets, and each chipset has a corresponding verification environment; the apparatus includes:

[0027] The access count acquisition module is configured to acquire the total number of accesses to the memory model for each chipset during the chip verification process;

[0028] The configuration environment determination module is configured to determine the verification environment corresponding to the chipset with the largest total number of accesses as the target environment for configuring the memory model.

[0029] Fifthly, this application provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described method.

[0030] Sixthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0031] In a seventh aspect, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0032] The aforementioned memory model configuration method, apparatus, computer device, computer-readable storage medium, and computer program product are applied to chip verification, where the chip includes multiple chipsets, each with a corresponding verification environment. The method involves obtaining the total number of accesses to the memory model for each chipset during chip verification; and determining the verification environment corresponding to the chipset with the highest total access count as the target environment for configuring the memory model. By configuring the memory model to the verification environment corresponding to the chipset with the highest total access count, it reduces cross-thread requests between chipsets during chip verification, thereby improving simulation efficiency. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a GPU-based computer system in one embodiment;

[0035] Figure 2 This is a schematic diagram of the chip verification environment and memory model in one embodiment;

[0036] Figure 3 This is a schematic diagram of a chip-based computer system in one embodiment;

[0037] Figure 4 This is a schematic diagram of a multi-threaded verification simulation in one embodiment;

[0038] Figure 5 This is a flowchart illustrating a method for configuring a memory model in one embodiment;

[0039] Figure 6 This is a flowchart illustrating the steps for obtaining the number of chip accesses in one embodiment;

[0040] Figure 7 This is a schematic diagram illustrating the configuration of a memory model in one embodiment;

[0041] Figure 8 This is a flowchart illustrating the configuration method of the memory model in another embodiment;

[0042] Figure 9This is a flowchart illustrating the steps for obtaining the total number of chipset accesses in one embodiment;

[0043] Figure 10 A schematic diagram illustrating the configuration of the memory model in another embodiment;

[0044] Figure 11 This is a structural block diagram of a memory model configuration device in one embodiment;

[0045] Figure 12 A structural block diagram of a memory model configuration device in another embodiment;

[0046] Figure 13 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] It should be noted that the terms "first," "second," etc., used in this application may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more.

[0049] like Figure 1 The diagram illustrates a computer system based on a GPU (Graphics Processing Unit) chip. The system includes a graphics card and a motherboard connected via communication. The motherboard comprises a processor and system memory. The processor, such as the CPU, is the central processing unit of the computer system, responsible for executing instructions and processing data. System memory refers to the motherboard's memory, such as RAM (Random Access Memory), used to store the operating system, applications, and currently processed data.

[0050] A graphics card is a crucial component of a computer system, responsible for displaying graphics. A graphics card typically consists of a GPU chip and video memory (VRAM, also known as external memory in a diagram). VRAM is a separate memory located outside the GPU chip and is used to store graphics and computational data.

[0051] The GPU chip is essentially the heart and brain of a graphics card, primarily used for graphics rendering and processing in graphics applications. It generally includes functional modules (as shown in Functional Module 1 and Functional Module 2 in the diagram) and on-chip memory. Functional Module 1 and Functional Module 2 are different functional modules within the GPU chip, used to perform specific tasks. On-chip memory refers to the memory integrated on the GPU chip, used for fast data access. Typically, the storage system of a GPU chip can include on-chip memory, off-chip memory, and system memory.

[0052] In chip functional module verification, typically only the module under test (DUT) uses actual hardware, i.e., RTL (Register Transfer Level, an abstract model of synchronous digital circuitry that describes how data flows between registers and combinational logic circuits and how it operates synchronously via clock signals, based on a hardware description language). Other functional modules often use functional module models, such as... Figure 2 As shown. In addition, the processor uses a processor model, while the storage system uses a memory model to simulate it.

[0053] A memory model is an abstract representation used to simulate and describe memory behavior in a computer system or chip verification environment. It defines how the processor, memory, and other hardware components interact, particularly the order, consistency, and visibility of memory accesses. Memory models are commonly used in simulation and verification environments to simulate the behavior of memory systems in actual hardware. Different address regions are used in a memory model to store the contents of different memory types (such as on-chip memory, off-chip memory, and system memory); therefore, a memory model can include on-chip memory regions, off-chip memory regions, and system memory regions.

[0054] With the advent of chip technology, chips are being increasingly used in chip design. For example... Figure 3 The diagram shown is a schematic of a chip-based computer system. Figure 1 As can be seen from the comparison, the GPU chip in a graphics card is replaced by a chip containing multiple sub-chips (sub-chip one and sub-chip two in the figure). Each sub-chip has a corresponding functional module (such as functional module one and functional module two) and on-chip memory. Moreover, multiple sub-chips share the graphics card's video memory (i.e., off-chip memory in the figure) and the motherboard (including the processor and system memory).

[0055] Therefore, the verification environment for a chip typically includes verification environments for multiple sub-chips, such as... Figure 4 As shown, chip verification simulation typically uses multi-threading technology for inter-chip interaction. Each chip's verification environment within the chip uses its own thread (e.g., chip one uses the first thread, chip two uses the second thread) for cross-thread communication.

[0056] Typically, for the functional modules under test (DUTs) of each chip within a chip, it's necessary to ensure the consistency of the data stored in the memory model within the verification environment. For example, suppose the data stored at address Addr_w in external memory is 0. When a second chip writes data to address Addr_w in external memory and updates it to 1, if the second chip then reads data from that address, the read data should be 1, not 0. The same principle applies to system memory.

[0057] Therefore, in order to ensure the consistency of memory model storage data in the chip verification environment, it is common practice to share a memory model among the verification environments of multiple sub-chips in the chip, where the memory model is placed in the verification environment of any chip in the chip.

[0058] Since multiple chips within a single core share a single memory model, the requirement for data consistency is not violated. However, because there is only one memory model for a core, and it is set within the verification environment of any chip within that core, if a chip with a memory model performs a memory read / write operation, it can do so directly within its own thread. However, if other chips (i.e., chips without a memory model in the core) need to perform memory read / write operations, they must initiate cross-thread read / write requests to the chip with the memory model. In verification simulations, an excessive number of cross-thread requests increases thread switching overhead, synchronization mechanism overhead, and communication overhead, leading to memory access latency and significantly impacting simulation efficiency.

[0059] Based on this, in order to improve simulation efficiency, embodiments of this application provide a memory model configuration method. This method is applied to chip verification, wherein the chip includes multiple chips, and each chip has a corresponding verification environment. Figure 5 As shown, the method includes:

[0060] Step 502: Obtain the number of times each chip accesses the memory model during the chip verification process.

[0061] Among them, chip verification refers to the simulation testing and verification of the actual operation of the chip through various means after the chip design is completed, so as to ensure that the chip can work normally under various conditions and meet the design specifications.

[0062] A memory model is an abstract representation used to simulate and describe memory behavior. Specifically, it is used in simulation and verification environments to simulate the behavior of memory systems in actual hardware. In this embodiment, the memory model may include on-chip storage areas, off-chip storage areas, and system storage areas, and different storage areas can be represented by different address ranges.

[0063] In chip verification, to ensure the consistency of memory model storage data within the chip verification environment, a shared memory model can be used across the verification environments of multiple sub-chips within the chip. Therefore, in this embodiment, to reduce cross-thread requests and improve simulation efficiency, the number of times each chip accesses the memory model during the chip verification process can be obtained before chip verification, and the memory model can be configured based on subsequent steps. The number of times each chip accesses the memory model can be obtained based on chip verification scenario prediction or testing.

[0064] Step 504: Determine the verification environment corresponding to the chip with the highest number of accesses as the target environment for configuring the memory model.

[0065] Specifically, after obtaining the number of times each chip in the core process accesses the memory model during the core verification process based on the above steps, the magnitude of the access counts for each chip can be compared to determine the chip with the highest access count. The verification environment corresponding to the chip with the highest access count is then identified as the target environment for configuring the memory model, thereby reducing cross-thread requests between chips during the core verification process.

[0066] In the above memory model configuration method, the number of times each chip in the core accesses the memory model during the core verification process is obtained, and the verification environment corresponding to the chip with the highest number of accesses is determined as the target environment for configuring the memory model. By configuring the memory model to the verification environment corresponding to the chip with the highest number of accesses, cross-thread requests between chips during core verification can be reduced, thereby improving simulation efficiency.

[0067] In one exemplary embodiment, such as Figure 6 As shown, in step 502, the number of times each chip accesses the memory model during the chip verification process is obtained, which may specifically include:

[0068] Step 602: Obtain the number of memory writes and the number of memory reads for each chip during the chip verification process.

[0069] The write count refers to the number of times the chip accesses the memory model to perform write data operations during the chip verification process. Similarly, the read count refers to the number of times the chip accesses the memory model to perform read data operations during the chip verification process.

[0070] In this embodiment, for each chip in the chip, the number of times the chip accesses the memory model to perform write data operations (i.e., the write count) and the number of times the chip performs read data operations (i.e., the read count) during the chip verification process can be obtained.

[0071] Step 604: Determine the number of memory accesses for each chip based on the number of writes and reads for each chip.

[0072] For example, if the number of writes to a chip is WX and the number of reads is RX, then the number of memory accesses of that chip is (WX+RX).

[0073] In the above embodiments, by obtaining the number of memory writes and the number of memory reads for each chip during the chip verification process, and determining the number of memory accesses for each chip based on the number of writes and reads, the accuracy of determining the number of accesses for each chip is improved.

[0074] In one exemplary embodiment, such as Figure 7 As shown, the example uses a chip assembly consisting of three chips (e.g., chip A, chip B, and chip C). Chips A, B, and C each have their own verification environment, and they share a common memory model.

[0075] Assuming chip A needs to write to memory WA times and read from memory RA times during the chip verification process, the total number of memory accesses for chip A is MA = (WA + RA). Assuming chip B needs to write to memory WB times and read from memory RB times, the total number of memory accesses for chip B is MB = (WB + RB). Assuming chip C needs to write to memory WC times and read from memory RC times, the total number of memory accesses for chip C is MC = (WC + RC).

[0076] If MA = 100,000 times, MB = 1,000,000 times, and MC = 10,000 times, then in traditional technology, the memory model is placed arbitrarily without considering the number of times each chip accesses the memory model. If the memory model is placed on chip A, the complete simulation process will generate (MB + MC) times, or 1,010,000 cross-thread requests; if the memory model is placed on chip B, the complete simulation process will generate (MA + MC) times, or 110,000 cross-thread requests; and if the memory model is placed on chip C, the complete simulation process will generate (MA + MB) times, or 1,100,000 cross-thread requests. It is evident that placing the memory model on chip A or chip C will result in a higher number of cross-thread requests.

[0077] If the method described in this application is applied, by obtaining the number of memory model accesses (such as MA, MB, and MC) of each chip (chip A, chip B, and chip C) during the chip verification process, and comparing the values ​​of MA, MB, and MC, if MA = 100,000 times, MB = 1,000,000 times, and MC = 10,000 times, then MB > MA > MC. Therefore, chip B can be identified as having the largest number of accesses. As shown by the data above, configuring the memory model in the verification environment corresponding to chip B for chip verification results in the fewest cross-thread requests compared to configuring the memory model in chip A or chip C. Therefore, based on the method described in this application, by configuring the memory model in the verification environment corresponding to the chip with the highest number of accesses in the chip for chip verification, the cross-thread requests between chips during the chip verification process can be minimized, thereby improving the simulation efficiency of chip verification.

[0078] It is understood that the above-described chip scenario involving three chips is only used to illustrate the solution of this application and is not intended to limit the scope of protection of this application. In practice, it can also be applied to chip scenarios involving more chips. In this application, reducing the number of cross-thread requests is used as an optimization indicator to improve simulation efficiency. Cross-thread requests are reduced by optimizing the memory model configuration location. Specifically, the memory model is configured in the verification environment corresponding to the chip with the highest access frequency in the chip for chip verification, thereby minimizing cross-thread requests between chips during chip verification and improving the simulation efficiency of chip verification.

[0079] In an exemplary embodiment, step 602 involves obtaining the number of memory writes and memory reads for each chip during the chip verification process. Specifically, this may include: determining the functional type of each chip; and using a matching estimation method based on the functional type of the chip to obtain the number of memory writes and memory reads for that chip during the chip verification process.

[0080] The functional type of a chip can include its functional role and behavior pattern. For example, what the chip does (e.g., central processing unit, graphics processing unit, network processing unit, I / O (input / output) controller, etc.), or the main responsibility of the chip in the chip (e.g., responsible for general computing, graphics rendering, algorithm acceleration, data handling, connecting to external devices, etc.).

[0081] The estimation method may include at least one of the following: waveform statistics based on a single-chip verification environment, analogy with similar chips, electronic design automation (EDA) analysis, and empirical estimation.

[0082] The waveform statistics method for single-chip verification environments involves building or reusing a simulation environment for a single chip, simulating it with a simulator, and collecting and counting the number of memory writes and reads during the simulation using waveform tools (such as automated debugging systems like Verdi and GTKWave). The analogy method involves finding development documents or simulation reports of existing chips with similar functions to the chip being analyzed, thereby obtaining the number of memory writes and reads during the simulation of those similar chips. The differences between the current chip and the similar chip are then analyzed, and the write and read counts of the similar chip are adjusted accordingly to obtain the write and read counts for the current chip. Electronic Design Automation (EDA) involves writing a simple test platform and stimulus, and inserting a transaction monitor between the chip and the memory model. By starting the chip simulation, the transaction monitor can automatically count the number of memory writes and reads during the simulation. The empirical estimation method estimates the number of memory writes and reads for the current chip based on past experience.

[0083] For example, for a mature CPU IP chip, there may be readily available performance models or simulation tools (such as ISS (Instruction Set Simulator)) that can provide relatively accurate statistics on memory write and read counts. In such cases, these readily available performance models or simulation tools can be used to directly obtain the memory access counts for that chip. For a new dedicated accelerator chip, it may be necessary to estimate bandwidth requirements through its architecture documentation or build a simple functional model (or reference model) to initially estimate its memory write and read counts. However, for a PHY (Physical) chip, its memory accesses (mainly configuration register accesses) may be very few, and its memory write and read counts can be obtained through empirical estimation or simple analysis.

[0084] Therefore, in this embodiment, the accuracy of evaluating the number of memory accesses of each chip in the chip can be improved by analyzing the functional type of each chip and using a matching estimation method based on the functional type of each chip.

[0085] In an exemplary embodiment, the memory model includes on-chip storage, off-chip storage, and system storage. In step 602, obtaining the number of memory writes and reads for each chip during the chip verification process may further include: for each chip, based on a preset estimation method, obtaining the first number of writes to on-chip storage, the second number of writes to off-chip storage, and the third number of writes to system storage during the chip verification process; determining the sum of the first, second, and third write counts; and determining this sum as the number of memory writes during the chip verification process. Furthermore, based on the same estimation method, obtaining the first number of reads to on-chip storage, the second number of reads to off-chip storage, and the third number of reads to system storage during the chip verification process; determining the sum of the first, second, and third read counts; and determining this sum as the number of memory reads during the chip verification process.

[0086] Since the memory model includes on-chip memory, off-chip memory, and system memory, to further improve the accuracy of estimating the number of memory accesses for each chip within a die, a deeper understanding and analysis of the chip's functions and behavioral patterns can be conducted. The number of writes and reads to on-chip memory, off-chip memory, and system memory can be statistically analyzed or estimated separately. Finally, the total number of writes and reads to on-chip memory, off-chip memory, and system memory can be summarized to obtain the total number of memory accesses for the chip's memory model.

[0087] Based on the same inventive concept, this application also provides a memory model configuration method applied to chip verification. The chip includes multiple chipsets, each chipset has a corresponding verification environment, and each chipset may include one or more chips. For example... Figure 8 As shown, the method includes:

[0088] Step 802: Obtain the total number of times the memory model is accessed during the chip verification process for each chipset.

[0089] In the memory model configuration described above, the chip environment places multiple chips with identical or different functions within a single chipset verification environment, using a single memory model. For more complex chip products, it may be necessary to use multi-threaded technology to jointly simulate multiple similar verification environments. To ensure the consistency of memory model stored data during simulation, a shared memory model can be used across multiple chipset verification environments within the chip. Furthermore, to reduce cross-thread requests and improve simulation efficiency, the total number of memory model accesses for each chipset during chip verification can be obtained before proceeding with chip verification, and the memory model configuration can be based on this information in subsequent steps. The total number of memory model accesses for each chipset can be obtained by statistically analyzing the access counts of each chip within that chipset.

[0090] Step 804: The verification environment corresponding to the chipset with the highest total number of accesses is determined as the target environment for configuring the memory model.

[0091] Specifically, after obtaining the total number of memory model accesses for each chipset during the chip verification process based on the above steps, the total number of accesses for each chipset can be compared to determine the chipset with the highest total number of accesses. The verification environment corresponding to the chipset with the highest total number of accesses is then designated as the target environment for configuring the memory model, thereby reducing cross-thread requests between chipsets during chip verification.

[0092] In the memory model configuration method described above, the total number of times each chipset accesses the memory model during chip verification is obtained. The verification environment corresponding to the chipset with the highest total access count is then determined as the target environment for configuring the memory model. By configuring the memory model to the verification environment corresponding to the chipset with the highest total access count, cross-thread requests between chipsets during chip verification can be reduced, thereby improving simulation efficiency.

[0093] In one exemplary embodiment, such as Figure 9 As shown, in step 802, the total number of memory model accesses for each chipset during the chip verification process is obtained, which may specifically include:

[0094] Step 902: For each chipset, obtain the number of times each chip in the chipset accesses the memory model during the chip verification process.

[0095] Each chipset includes one or more chips, and during chip verification, each chip in the chipset may access the memory model. Therefore, in this embodiment, for each chipset, the number of times each chip in the chipset accesses the memory model during chip verification can be obtained. The number of times each chip accesses the memory model can be obtained based on chip verification scenario prediction or testing.

[0096] Step 904: Obtain the sum of the number of times each chip in the chipset accesses the memory model, and determine the sum as the total number of times the chipset accesses the memory model.

[0097] Locally, after obtaining the number of times each chip in the chipset accesses the memory model during the chip verification process, the sum of the access counts of each chip in the chipset can be calculated, and the sum is determined as the total number of times the chipset accesses the memory model.

[0098] For example, if a chipset A includes two chips, A1 and A2, and the memory access count of chip A1 is AX1 and the memory access count of chip A2 is AX2 based on the above steps, then the total number of memory accesses for chipset A is (AX1 + AX2).

[0099] In this embodiment, for each chipset, the number of times each chip in the chipset accesses the memory model during the chip verification process, and the sum of these access counts, are determined as the total number of memory model accesses for the chipset. By statistically analyzing the number of memory model accesses by each chip in the chipset during chip verification, the total number of accesses for the corresponding chipset can be calculated, thereby improving the accuracy of the total chipset access count.

[0100] In an exemplary embodiment, step 902, obtaining the number of times each chip in the chipset accesses the memory model during the chip verification process, may include: obtaining the number of memory writes and the number of memory reads for each chip during the chip verification process; and determining the number of times each chip accesses the memory model based on the write and read counts. The specific implementation can be found above. Figure 6 The embodiments shown are not described in detail here.

[0101] In one exemplary embodiment, obtaining the number of memory writes and memory reads for each chip in the chipset during the chip verification process may include: determining the function type of each chip in the chipset; and obtaining the number of memory writes and memory reads for each chip during the chip verification process using a matching estimation method based on the function type of the chip.

[0102] In an exemplary embodiment, the memory model includes on-chip storage, off-chip storage, and system storage. Obtaining the number of memory writes and reads for each chip in the chipset during chip verification includes: for each chip, calculating the first write count to on-chip storage, the second write count to off-chip storage, and the third write count to system storage during chip verification based on a preset estimation method; determining the sum of the first, second, and third write counts; and determining the sum as the number of memory writes during chip verification. Also, calculating the first read count to on-chip storage, the second read count to off-chip storage, and the third read count to system storage during chip verification based on an estimation method; determining the sum of the first, second, and third read counts; and determining the sum as the number of memory reads during chip verification.

[0103] In one exemplary embodiment, the estimation method includes at least one of the following: waveform statistics based on a single-chip verification environment, analogy with similar chips, electronic design automation analysis, and empirical estimation.

[0104] In one exemplary embodiment, the method may further include configuring the memory model in the target environment for chip verification.

[0105] In an exemplary embodiment, multiple chipsets include a first chipset and a second chipset. The verification environment of the first chipset uses a first thread, and the verification environment of the second chipset uses a second thread. Chip verification includes: if the verification environment of the first chipset is the target environment, upon receiving a read / write memory operation on any chip in the first chipset, accessing the memory model based on the first thread to process the read / write memory operation; establishing cross-thread communication between the second thread of the second chipset and the first thread of the first chipset, and upon receiving a read / write memory operation on any chip in the second chipset, accessing the memory model through the second thread based on the cross-thread communication to process the read / write memory operation.

[0106] It is understood that the specific implementation methods of the exemplary embodiments in this section can be referred to the embodiments in the corresponding sections above, and will not be repeated here.

[0107] In one exemplary embodiment, such as Figure 10 As shown, the example illustrates a chip consisting of three chipsets (e.g., chipset A, chipset B, and chipset C). Chipset A, chipset B, and chipset C each have their own verification environment, and each verification environment uses a corresponding thread (e.g., thread A for chipset A, thread B for chipset B, and thread C for chipset C). Chipset A, chipset B, and chipset C share a single memory model. Chipset A may include two chips, such as chip A1 and chip A2; chipset B may include four chips, such as chip B1, chip B2, chip B3, and chip B4; and chipset C may include three chips, such as chip C1, chip C2, and chip C3.

[0108] Assuming that during the chip verification process, chip A1 in chipset A needs to write to memory WA1 times and read from memory RA1 times, then the total number of memory accesses by chip A1 is KA1 = (WA1 + RA1); chip A2 needs to write to memory WA2 times and read from memory RA2 times, then the total number of memory accesses by chip A2 is KA2 = (WA2 + RA2). Therefore, the total number of memory accesses in chipset A is KA = (KA1 + KA2).

[0109] If chip B1 in chipset B needs to write to memory WB1 times and read from memory RB1 times, then the number of memory accesses by chip B1 is KB1 = (WB1 + RB1). Similarly, the number of memory accesses by chip B2 is KB2, by chip B3 is KB3, and by chip B4 is KB4. Therefore, the total number of memory accesses in chipset B is KB = (KB1 + KB2 + KB3 + KB4). If the total number of memory accesses in chipset C is KC = (KC1 + KC2 + KC3).

[0110] If KA = 50,000 times, KB = 100,000 times, and KC = 10,000 times. Because traditional technology places memory models arbitrarily without considering the number of accesses from each chipset to the memory model, if the memory model is placed in chipset A, then any read / write operation on any chip in chipset B requires thread B to call thread A through cross-thread communication to access the memory model in chipset A to process the corresponding read / write operation. Similarly, any read / write operation on any chip in chipset C requires thread C to call thread A through cross-thread communication to access the memory model in chipset A to process the corresponding read / write operation. The complete simulation process will generate (KB + KC) times, or 110,000 cross-thread requests. If the memory... If the model is placed in chipset B, then any read / write operation on the memory of any chip in chipset A requires thread A to call thread B via cross-thread communication to access the memory model in chipset B to process the corresponding read / write operation. Similarly, any read / write operation on the memory of any chip in chipset C requires thread C to call thread B via cross-thread communication to access the memory model in chipset B to process the corresponding read / write operation. The complete simulation process will generate (KA+KC) times, or 60,000 cross-thread requests. Similarly, if the memory model is placed in chipset C, the complete simulation process will generate (KA+KB) times, or 150,000 cross-thread requests. It is evident that placing the memory model in chipset A or chipset C will result in a higher number of cross-thread requests.

[0111] If the method described in this application is applied, by obtaining the total number of memory model accesses (e.g., KA, KB, and KC) for each chipset (chipset A, chipset B, and chipset C) during the chip verification process, and comparing the values ​​of KA, KB, and KC, if KA = 50,000 times, KB = 100,000 times, and KC = 10,000 times, then KB > KA > KC. Therefore, chipset B can be identified as having the largest number of accesses. As shown by the data above, configuring the memory model in the verification environment corresponding to chipset B for chip verification results in the fewest cross-thread requests compared to configuring the memory model in chipset A or chipset C. Therefore, based on the method described in this application, by configuring the memory model in the verification environment corresponding to the chipset with the largest total number of accesses in the chip for chip verification, the cross-thread requests between chips during the chip verification process can be minimized, thereby improving the simulation efficiency of chip verification.

[0112] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0113] Based on the same inventive concept, this application also provides a memory model configuration apparatus for implementing the memory model configuration method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more memory model configuration apparatus embodiments provided below can be found in the limitations of the memory model configuration method described above, and will not be repeated here.

[0114] In one exemplary embodiment, such as Figure 11 As shown, a memory model configuration device is provided. This device is used for chip verification, whereby the chip comprises multiple chips, each chip having a corresponding verification environment. The device includes:

[0115] The access count acquisition module 1102 is configured to acquire the number of times each chip accesses the memory model during the chip verification process;

[0116] The configuration environment determination module 1104 is configured to determine the verification environment corresponding to the chip with the highest number of accesses as the target environment for configuring the memory model.

[0117] In an exemplary embodiment, the access count acquisition module is further configured to perform: acquiring the number of memory writes and the number of memory reads for each chip during the chip verification process; and determining the number of accesses to the memory model for each chip based on the number of writes and the number of reads for each chip.

[0118] In an exemplary embodiment, the access count acquisition module is further configured to perform: for each chip, determine the function type of the chip; based on the function type of the chip, use a matching estimation method to obtain the number of memory writes and the number of memory reads that occurred during the chip verification process.

[0119] In an exemplary embodiment, the memory model includes on-chip storage, off-chip storage, and system storage; the access count acquisition module is further configured to perform: for each chip, calculating, based on a preset estimation method, the first write count of the chip's operations on the on-chip storage, the second write count of the chip's operations on the off-chip storage, and the third write count of the chip's operations on the system storage during the chip verification process; determining the sum of the first write count, the second write count, and the third write count; and determining the sum as the number of memory writes performed by the chip during the chip verification process; and calculating, based on the estimation method, the first read count of the chip's operations on the on-chip storage, the second read count of the chip's operations on the off-chip storage, and the third read count of the chip's operations on the system storage during the chip verification process; determining the sum of the first read count, the second read count, and the third read count; and determining the sum as the number of memory reads performed by the chip during the chip verification process.

[0120] In one embodiment, the estimation method includes at least one of waveform statistics based on a single-chip verification environment, analogy with similar chips, electronic design automation analysis, and empirical estimation.

[0121] In one exemplary embodiment, the apparatus further includes a configuration module configured to perform chip verification by configuring the memory model in the target environment.

[0122] In one exemplary embodiment, such as Figure 12 As shown, a memory model configuration device is provided. This device is used for chip verification, whereby the chip includes multiple chipsets, each chipset having a corresponding verification environment. The device includes:

[0123] The access count acquisition module 1202 is configured to acquire the total number of accesses to the memory model for each chipset during the chip verification process;

[0124] The configuration environment determination module 1204 is configured to determine the verification environment corresponding to the chipset with the largest total number of accesses as the target environment for configuring the memory model.

[0125] In an exemplary embodiment, each chipset includes one or more chips; the access count acquisition module is further configured to perform: for each chipset, acquire the number of times each chip in the chipset accesses the memory model during the chiplet verification process; acquire the sum of the number of times each chip in the chipset accesses the memory model, and determine the sum as the total number of times the chipset accesses the memory model.

[0126] In an exemplary embodiment, the access count acquisition module is further configured to perform: acquiring the number of memory writes and the number of memory reads for each chip in the chipset during the chip verification process; and determining the number of accesses to the memory model for each chip based on the number of writes and the number of reads for each chip.

[0127] In an exemplary embodiment, the access count acquisition module is further configured to perform: for each chip in the chipset, determine the function type of the chip; based on the function type of the chip, use a matching estimation method to obtain the number of memory writes and the number of memory reads that occurred during the chip verification process.

[0128] In an exemplary embodiment, the memory model includes on-chip storage, off-chip storage, and system storage; the access count acquisition module is further configured to perform: for each chip, calculating, based on a preset estimation method, the first write count of the chip's operations on the on-chip storage, the second write count of the chip's operations on the off-chip storage, and the third write count of the chip's operations on the system storage during the chip verification process; determining the sum of the first write count, the second write count, and the third write count; and determining the sum as the number of memory writes performed by the chip during the chip verification process; and calculating, based on the estimation method, the first read count of the chip's operations on the on-chip storage, the second read count of the chip's operations on the off-chip storage, and the third read count of the chip's operations on the system storage during the chip verification process; determining the sum of the first read count, the second read count, and the third read count; and determining the sum as the number of memory reads performed by the chip during the chip verification process.

[0129] In one exemplary embodiment, the estimation method includes at least one of waveform statistics based on a single-chip verification environment, analogy with similar chips, electronic design automation analysis, and empirical estimation.

[0130] In one exemplary embodiment, the apparatus further includes a configuration module configured to perform chip verification by configuring the memory model in the target environment.

[0131] In an exemplary embodiment, the plurality of chipsets includes a first chipset and a second chipset. The verification environment of the first chipset uses a first thread, and the verification environment of the second chipset uses a second thread. The device further includes a verification module configured to perform: if the verification environment of the first chipset is a target environment, upon receiving a read / write memory operation on any chip in the first chipset, accessing the memory model based on the first thread to process the read / write memory operation; establishing cross-thread communication between the second thread of the second chipset and the first thread of the first chipset, and upon receiving a read / write memory operation on any chip in the second chipset, accessing the memory model through the second thread based on the cross-thread communication to process the read / write memory operation.

[0132] Each module in the configuration device of the above memory model can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0133] In one exemplary embodiment, a computer device is provided, the internal structure of which can be as shown in the figure. Figure 13 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores chip verification data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When executed by the processor, the computer program implements a memory model configuration method.

[0134] Those skilled in the art will understand that Figure 13 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0135] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0136] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0137] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0138] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0140] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for configuring a memory model, characterized in that, The method is applied to chip verification, wherein the chip comprises multiple chipsets, and each chipset has a corresponding verification environment; the method includes: Obtain the total number of times the memory model is accessed for each of the chipsets during the chip verification process; The verification environment corresponding to the chipset with the highest total number of accesses is determined as the target environment for configuring the memory model.

2. The method according to claim 1, characterized in that, Each chipset includes one or more chips; obtaining the total number of memory model accesses for each chipset during chip verification includes: For each chipset, the number of times each chip in the chipset accesses the memory model during the chip verification process is obtained; The sum of the number of times each chip in the chipset accesses the memory model is obtained, and the sum is determined as the total number of times the chipset accesses the memory model.

3. The method according to claim 2, characterized in that, The step of obtaining the number of times each chip in the chipset accesses the memory model during the chip verification process includes: The number of memory writes and the number of memory reads for each chip in the chipset during the chip verification process are obtained. The number of memory accesses for each chip is determined based on the number of writes and reads for each chip.

4. The method according to claim 3, characterized in that, The step of obtaining the number of memory writes and the number of memory reads for each chip in the chipset during the chip verification process includes: For each chip in the chipset, determine the functional type of the chip; Based on the functional type of the chip, a matching estimation method is used to obtain the number of memory writes and the number of memory reads during the chip verification process.

5. The method according to claim 3, characterized in that, The memory model includes on-chip storage, off-chip storage, and system storage; obtaining the number of memory writes and reads for each chip in the chipset during chip verification includes: For each chip, the first number of write operations to the on-chip storage, the second number of write operations to the off-chip storage, and the third number of write operations to the system storage are calculated based on a preset estimation method during the chip verification process. The sum of the first number of write operations, the second number of write operations, and the third number of write operations is determined, and the sum is determined as the number of memory write operations that occur during the chip verification process. Based on the estimation method, the first number of reads of the chip's on-chip storage, the second number of reads of the chip's off-chip storage, and the third number of reads of the chip's system storage during the chip verification process are calculated. The sum of the first number of reads, the second number of reads, and the third number of reads is determined, and the sum is determined as the number of memory reads that occurred during the chip verification process.

6. The method according to claim 4 or 5, characterized in that, The estimation methods include at least one of the following: waveform statistics based on a single-chip verification environment, analogy with similar chips, electronic design automation analysis, and empirical estimation.

7. The method according to any one of claims 1 to 5, characterized in that, The method further includes: The memory model is configured in the target environment for chip verification.

8. The method according to claim 7, characterized in that, The plurality of chipsets includes a first chipset and a second chipset, wherein the verification environment of the first chipset uses a first thread, and the verification environment of the second chipset uses a second thread; the chip verification includes: If the verification environment of the first chipset is the target environment, upon receiving a read / write memory operation on any chip in the first chipset, the memory model is accessed based on the first thread to process the read / write memory operation. Establish cross-thread communication between the second thread of the second chipset and the first thread of the first chipset. When a read / write memory operation is received for any chip in the second chipset, the second thread accesses the memory model based on the cross-thread communication to process the read / write memory operation.

9. A memory model configuration device, characterized in that, The apparatus is used for chip verification, wherein the chip comprises multiple chipsets, and each chipset has a corresponding verification environment; the apparatus includes: The access count acquisition module is configured to acquire the total number of accesses to the memory model for each chipset during the chip verification process; The configuration environment determination module is configured to determine the verification environment corresponding to the chipset with the largest total number of accesses as the target environment for configuring the memory model.

10. The apparatus according to claim 9, characterized in that, Each of the chipsets includes one or more chips; the access count acquisition module is also configured to perform: For each chipset, the number of times each chip in the chipset accesses the memory model during the chip verification process is obtained; The sum of the number of times each chip in the chipset accesses the memory model is obtained, and the sum is determined as the total number of times the chipset accesses the memory model.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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