Multi-target quantum circuit mapping method and device of quantum computer, equipment and medium

Abstract

The invention discloses a multi-target quantum circuit mapping method and device of a quantum computer, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps: decomposing a quantum circuit based on the architecture of a target quantum computer, and determining a current initial mapping relation in combination with a preset collaborative evaluation function; inputting the current initial mapping relation into the line, and selecting and executing a swap gate operation sequence in combination with a preset two-stage multi-target collaborative optimization strategy to complete a middle bit routing operation to obtain a first mapping relation at the tail end of the current line; reversing the unmapped line, performing middle bit routing in combination with the optimization strategy and the first mapping relationship, and triggering line reversing and middle bit routing again to obtain a second mapping relationship at the tail end of the current line; skipping to the step of inputting the current initial mapping relation into the line again until the condition is met; and analyzing the line depth of the middle bit routing operation, determining a mapping strategy and completing mapping. And efficient heuristic line mapping of multi-objective optimization can be better realized.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and medium for multi-objective quantum circuit mapping in quantum computers. Background Technology

[0002] Currently, heuristic algorithms have achieved significant results in quantum circuit mapping. However, existing solutions are mostly limited to single-objective optimization, that is, improving the mapping quality by optimizing only one metric (such as the number of quantum gates, quantum circuit depth, or the fidelity of quantum gates in the quantum circuit). However, considering the characteristics of NISQ devices (Noisy Intermediate-Scale Quantum devices), these metrics are not completely isolated; they are coupled and mutually influential. An advantage in one metric cannot fully reflect the quality of the entire mapping result.

[0003] To balance these indicators, some studies have attempted multi-objective optimization. However, these studies have not incorporated the idea of ​​multi-objective optimization into the evaluation function. Instead, they indirectly affect other indicators by optimizing one indicator. The strategies are simple and suffer from problems such as high computational resource consumption and poor collaborative optimization effect.

[0004] Therefore, how to comprehensively consider indicators such as quantum circuit depth and design evaluation functions in a reasonable and comprehensive manner to better achieve efficient heuristic circuit mapping for multi-objective optimization remains a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a method, apparatus, device, and medium for multi-objective quantum circuit mapping in quantum computers. This invention solves the problems of insufficient consideration of evaluation functions, simplistic strategies, high computational resource overhead, and poor collaborative optimization effects in existing related schemes. It comprehensively considers indicators such as quantum circuit depth and rationally and comprehensively designs evaluation functions, thereby better realizing efficient heuristic circuit mapping for multi-objective optimization. The specific scheme is as follows:

[0006] In a first aspect, this application provides a method for multi-objective quantum circuit mapping in a quantum computer, comprising:

[0007] Based on the architecture of the target quantum computer, the quantum circuit is decomposed, and based on the corresponding decomposition results and the hierarchical structure information of the quantum circuit, the weights of the gate operations are assigned to determine the weighting results; the decomposition results include single-qubit gates and two-qubit gates.

[0008] Based on the weighting result, the logical bit priority information of the quantum circuit is determined, and the logical bit priority information and the preset cooperative evaluation function are used to determine the target quantum bit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture, so as to obtain the current initial mapping relationship.

[0009] The current initial mapping relationship is input into the quantum circuit, and combined with the preset two-stage multi-objective collaborative optimization strategy, the selection and execution of the switching gate operation sequence are carried out to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit.

[0010] The unmapped quantum circuit is reversed using the corresponding first reversed circuit and the preset two-stage multi-objective collaborative optimization strategy. The first mapping relationship is used as the current initial mapping relationship for intermediate bit routing. The circuit reversal operation and the intermediate bit routing operation are triggered again to obtain the second mapping relationship at the end of the current circuit. The multi-objectives include circuit depth, quantum gate distance and swap gate decomposition characteristics.

[0011] The second mapping relationship is used as the current initial mapping relationship, and the process jumps back to the step of inputting the current initial mapping relationship into the quantum circuit until the preset loop termination condition is met.

[0012] By analyzing the line depth value corresponding to each intermediate bit routing operation in the loop process, a target mapping strategy is determined, and a line mapping operation corresponding to the quantum line is executed based on the target mapping strategy; the target mapping strategy includes the corresponding current initial mapping relationship, the first mapping relationship, or the second mapping relationship.

[0013] Optionally, based on the architecture of the target quantum computer, the quantum circuit is decomposed, and based on the corresponding decomposition results and the hierarchical structure information of the quantum circuit, weights for gate operations are assigned, including:

[0014] Based on the preset decomposition algorithm and the architecture of the target quantum computer, the quantum circuit is decomposed to determine the decomposition result.

[0015] The quantum circuit is hierarchically divided to obtain its hierarchical structure information.

[0016] Based on the hierarchical structure information, the circuit levels corresponding to the single-qubit gate and the double-qubit gate in the circuit decomposition results are determined;

[0017] Weights are assigned to the corresponding gate operations based on the circuit hierarchy to determine the weighting result; the gate operations include single-qubit gate operations and two-qubit gate operations.

[0018] Optionally, determining the logical bit priority information of the quantum circuit based on the weighting result includes:

[0019] For any logical bit in the quantum circuit, the weight value of the current logical bit is determined based on the weighting result and the gate operation information corresponding to the current logical bit.

[0020] The weight values ​​corresponding to each logical bit in the quantum circuit are sorted to determine the logical bit priority information;

[0021] For any two logical bits in the quantum circuit, the corresponding bit weights are determined based on the corresponding two-qubit gate operation and the weighting result.

[0022] Optionally, the step of using the logical bit priority information and a preset cooperative evaluation function to determine the target qubit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture, so as to obtain the current initial mapping relationship, includes:

[0023] In the initial mapping phase, for any logical bit to be mapped in the quantum circuit, based on the first evaluation function in the preset cooperative evaluation function and combined with the logical bit priority information, the influence of the current logical bit to be mapped on the quantum bit placement in the architecture on the mapped neighboring logical bits is analyzed to obtain the first evaluation result.

[0024] Based on the second evaluation function in the preset collaborative evaluation function, and combined with the logical bit priority information, the influence of the current logical bit to be mapped in the architecture on the placement of the quantum bits on the unmapped neighbor logical bits is analyzed to obtain the second evaluation result;

[0025] The first evaluation result and the second evaluation result are standardized to determine the first post-processed result and the second post-processed result.

[0026] A size comparison is performed based on the first processed result and the second processed result, and the target quantum bit mapping bit of the current logical bit to be mapped in the architecture is determined according to the corresponding comparison result;

[0027] Based on the target quantum bit mapping bits of each of the logical bits to be mapped, a mapping is performed to obtain the current initial mapping relationship.

[0028] Optionally, the step of inputting the current initial mapping relationship into the quantum circuit, and combining it with a preset two-stage multi-objective collaborative optimization strategy to select and execute the sequence of swap gate operations to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit, includes:

[0029] Input the current initial mapping relationship into the quantum circuit and run the quantum circuit;

[0030] Configure the current candidate set of switch gate operations; wherein the current candidate set of switch gate operations is not greater than the edge set corresponding to the architecture;

[0031] Based on a preset two-stage multi-objective collaborative optimization strategy and a preset operation evaluation function, it is determined whether each candidate switch gate operation in the current candidate switch gate operation set meets the preset screening conditions, so as to determine the screening condition judgment result.

[0032] If the result of the filtering condition judgment indicates that there are multiple candidate switching gate operations that meet the criteria in the current candidate set of switching gate operations, then the operation filtering result is determined.

[0033] Based on a preset multi-objective optimization function and a preset switching gate operation decomposition strategy, the frequency of action, position of action, and maximum line depth of each switching gate operation in the operation screening results are analyzed on the bit to determine the operation analysis results.

[0034] Based on the operation analysis results and operation screening results, the switching gate operation sequence corresponding to the quantum circuit is determined;

[0035] Based on the aforementioned exchange gate operation sequence, the preset single-qubit gate fan-in and fan-out mechanism, and each single-qubit gate and each double-qubit gate in the quantum circuit, the intermediate bit routing operation corresponding to the quantum circuit is completed, and the first mapping relationship at the end of the current circuit is obtained.

[0036] Optionally, after determining the result of the filtering criteria, the method further includes:

[0037] If the result of the screening condition judgment indicates that none of the candidate switching gate operations in the current candidate set of switching gate operations are satisfied, then the circuit depth is optimized based on the preset single-qubit gate fan-in fan-out mechanism, and according to the corresponding optimized quantum circuit, the process jumps back to the step of configuring the current candidate set of switching gate operations.

[0038] Optionally, the step of reversing the unmapped quantum circuit, utilizing the corresponding first reversed circuit and the preset two-stage multi-objective collaborative optimization strategy, and using the first mapping relationship as the current initial mapping relationship for intermediate bit routing, and triggering the circuit reversal operation and the intermediate bit routing operation again, includes:

[0039] The unmapped quantum circuit is reversed to obtain a first reversed circuit.

[0040] The first mapping relationship is used as the current initial mapping relationship and input into the first reversed line, and the first reversed line is run;

[0041] Based on the preset two-stage multi-objective collaborative optimization strategy, the selection and execution of the switching gate operation sequence are performed to complete the intermediate bit routing operation corresponding to the first reversed line, so as to obtain the third mapping relationship at the end of the current line.

[0042] The unmapped first reversed line is reversed to obtain the second reversed line;

[0043] The third mapping relationship is used as the current initial mapping relationship and input into the second reversed line, and the second reversed line is run;

[0044] Based on the preset two-stage multi-objective collaborative optimization strategy, the selection and execution of the switching gate operation sequence are performed to complete the intermediate bit routing operation corresponding to the second reversed line, so as to obtain the second mapping relationship at the end of the current line.

[0045] Secondly, this application provides a multi-objective quantum circuit mapping device for a quantum computer, comprising:

[0046] The gate operation weighting module is used to decompose the quantum circuit based on the architecture of the target quantum computer, and assign weights to the gate operations based on the corresponding circuit decomposition results and the hierarchical structure information of the quantum circuit to determine the weighting results; the circuit decomposition results include single-qubit gates and two-qubit gates;

[0047] The collaborative evaluation module is used to determine the logical bit priority information of the quantum circuit based on the weighting result, and to use the logical bit priority information and the preset collaborative evaluation function to determine the target quantum bit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture, so as to obtain the current initial mapping relationship.

[0048] The first routing module is used to input the current initial mapping relationship into the quantum circuit, and combine it with a preset two-stage multi-objective collaborative optimization strategy to select and execute the sequence of switching gate operations in order to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit.

[0049] The second routing module is used to reverse the unmapped quantum circuit, utilize the corresponding first reversed circuit and the preset two-stage multi-objective collaborative optimization strategy, and use the first mapping relationship as the current initial mapping relationship for intermediate bit routing, and trigger the circuit reversal operation and the intermediate bit routing operation again to obtain the second mapping relationship at the end of the current circuit; the multi-objective includes circuit depth, quantum gate distance and swap gate decomposition characteristics;

[0050] The step jump module is used to take the second mapping relationship as the current initial mapping relationship and jump back to the step of inputting the current initial mapping relationship into the quantum circuit until the preset loop termination condition is met.

[0051] The mapping strategy determination module is used to determine the target mapping strategy by analyzing the line depth value corresponding to each intermediate bit routing operation in the loop process, and to perform the line mapping operation corresponding to the quantum line based on the target mapping strategy; the target mapping strategy includes the corresponding current initial mapping relationship, the first mapping relationship, or the second mapping relationship.

[0052] Thirdly, this application provides an electronic device, comprising:

[0053] Memory, used to store computer programs;

[0054] A processor for executing the computer program to implement the steps of the aforementioned multi-objective quantum circuit mapping method for quantum computers.

[0055] Fourthly, this application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the steps of the aforementioned multi-objective quantum circuit mapping method for quantum computers.

[0056] As can be seen, in this application, based on the architecture of the target quantum computer, the quantum circuit is decomposed, and based on the corresponding decomposition results and the hierarchical structure information of the quantum circuit, weights are assigned to gate operations to determine the weighting results; the decomposition results include single-qubit gates and two-qubit gates; based on the weighting results, the logical bit priority information of the quantum circuit is determined, and using the logical bit priority information and a preset cooperative evaluation function, the target qubit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture is determined to obtain the current initial mapping relationship; the current initial mapping relationship is input to the quantum circuit, and combined with a preset two-stage multi-objective cooperative optimization strategy, the selection and execution of the gate operation sequence are performed to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit; the unmapped quantum circuit is then processed. The process involves reversing the current path, utilizing the corresponding first reversed path and the preset two-stage multi-objective collaborative optimization strategy, and using the first mapping relationship as the current initial mapping relationship for intermediate bit routing. The path reversal operation and the intermediate bit routing operation are then triggered again to obtain the second mapping relationship at the end of the current path. The multi-objectives include path depth, quantum gate distance, and swap gate decomposition characteristics. The second mapping relationship is used as the current initial mapping relationship, and the process jumps back to the step of inputting the current initial mapping relationship into the quantum path until a preset loop termination condition is met. By analyzing the path depth values ​​corresponding to each intermediate bit routing operation during the loop process, a target mapping strategy is determined, and a path mapping operation corresponding to the quantum path is executed based on the target mapping strategy. The target mapping strategy includes the corresponding current initial mapping relationship, the first mapping relationship, or the second mapping relationship. In other words, in this application, the quantum circuit is first decomposed according to its architecture, and the weighting result of the gate operation is determined by combining the hierarchical structure information of the circuit. Then, the logical bit priority information of the circuit is determined based on the weighting result, and the current initial mapping relationship of the circuit is determined by combining the preset cooperative evaluation function. Then, the current initial mapping relationship is input into the quantum circuit, and the selection and execution of the gate operation sequence is performed by combining the preset two-stage multi-objective cooperative optimization strategy to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit. Then, the unmapped quantum circuit is reversed, and the intermediate bit routing operation is executed again by combining the first mapping relationship and the preset two-stage multi-objective cooperative optimization strategy. After the operation is completed, the circuit reversal operation and intermediate bit routing operation are triggered again to obtain the second mapping relationship at the end of the current circuit. Then, the second mapping relationship is used as the current initial mapping relationship, and the process jumps back to the step of inputting the current initial mapping relationship into the quantum circuit until the preset loop termination condition is met. The circuit depth value corresponding to each intermediate bit routing operation in the loop process is analyzed to determine the target mapping strategy, and the circuit mapping corresponding to the quantum circuit is completed according to the target mapping strategy.This approach addresses issues such as insufficient consideration of evaluation functions, simplistic strategies, high computational resource overhead, and poor collaborative optimization in existing related schemes. It enables a comprehensive and rational design of evaluation functions, taking into account indicators such as quantum circuit depth, thereby achieving more efficient heuristic circuit mapping for multi-objective optimization. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0058] Figure 1 A flowchart of a multi-objective quantum circuit mapping method for quantum computers provided in this application;

[0059] Figure 2 A flowchart of a specific method for multi-objective quantum circuit mapping in a quantum computer is provided in this application;

[0060] Figure 3 A schematic diagram of a specific two-stage multi-objective collaborative optimization routing process provided for this application;

[0061] Figure 4 A schematic diagram of a multi-objective quantum circuit mapping device for a quantum computer is provided in this application;

[0062] Figure 5 This application provides a structural diagram of an electronic device. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] Currently, heuristic algorithms have achieved significant results in quantum circuit mapping. However, existing solutions are mostly limited to single-objective optimization, that is, improving the mapping quality by optimizing only one metric (such as the number of quantum gates, quantum circuit depth, or the fidelity of quantum gates in the quantum circuit). However, considering the characteristics of NISQ devices, these metrics are not completely isolated; they are coupled and influence each other. An advantage in one metric cannot fully reflect the quality of the entire mapping result.

[0065] To balance these indicators, some studies have attempted multi-objective optimization. However, these studies have not incorporated the idea of ​​multi-objective optimization into the evaluation function. Instead, they indirectly affect other indicators by optimizing one indicator. The strategies are simple and suffer from problems such as high computational resource consumption and poor collaborative optimization effect.

[0066] To address this, this application provides a multi-objective quantum circuit mapping scheme for quantum computers, which solves the problems of insufficient evaluation function consideration, simple strategy, large computational resource overhead, and poor cooperative optimization effect in existing related schemes. It can comprehensively consider indicators such as quantum circuit depth and design evaluation functions in a reasonable and comprehensive manner, thereby better realizing efficient heuristic circuit mapping for multi-objective optimization.

[0067] See Figure 1 As shown, this embodiment of the invention discloses a multi-objective quantum circuit mapping method for quantum computers, comprising:

[0068] Step S11: Based on the architecture of the target quantum computer, decompose the quantum circuit, and assign weights to the gate operations based on the corresponding decomposition results and the hierarchical structure information of the quantum circuit to determine the weighting results; the decomposition results include single-qubit gates and two-qubit gates.

[0069] In this embodiment, combined with Figure 2 As shown, the given quantum circuit needs to be processed into a form containing only single-qubit gates and two-qubit gates, and weights are assigned to all gate operations according to the hierarchical structure of the quantum circuit. Specifically: based on a preset decomposition algorithm and the architecture of the target quantum computer, the quantum circuit is decomposed to determine the decomposition result; the quantum circuit is hierarchically divided to obtain the hierarchical structure information of the quantum circuit; based on the hierarchical structure information, the circuit levels corresponding to the single-qubit gates and two-qubit gates in the circuit decomposition result are determined; weights are assigned to the corresponding gate operations based on the circuit levels to determine the weighting result; the gate operations include single-qubit gate operations and two-qubit gate operations. It can be understood that in this embodiment, the gate operations in the quantum circuit are decomposed into basic gate operations that can be supported by the architecture of the target quantum computer, including single-qubit gate operations and two-qubit gate operations, so that the quantum circuit can be mapped to this quantum hardware architecture later.

[0070] It is important to understand that the hierarchical division of quantum circuits can be weighted according to the following formula, assigning weights to each qubit gate operation (including single-qubit and two-qubit gate operations) in the circuit:

[0071] ;

[0072] In the formula, Represents the first in the original quantum circuit Individual door operation, This refers to the qubit gate operation (also known as the quantum gate operation). The weight value, Representing qubit gate operations The level of the line it belongs to.

[0073] Step S12: Based on the weighting result, determine the logical bit priority information of the quantum circuit, and use the logical bit priority information and the preset cooperative evaluation function to determine the target quantum bit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture, so as to obtain the current initial mapping relationship.

[0074] In this embodiment, after the weighting of the gate operation is completed, the weighting result is used to determine the weight of each logical bit in the quantum circuit and the weight between qubits with two-qubit gates. Specifically: for any logical bit in the quantum circuit, the weight value of the current logical bit is determined based on the weighting result and the gate operation information corresponding to the current logical bit; the weight values ​​corresponding to each logical bit in the quantum circuit are sorted to determine the logical bit priority information; for any two logical bits in the quantum circuit, the corresponding bit weights are determined based on the corresponding two-qubit gate operation and the weighting result.

[0075] It is important to understand that in this embodiment, after defining the weight of each quantum gate, the priority of each logical bit is determined based on the sum of the gate operation weights associated with the current logical bit. Specifically, the priority of the first logical bit in the circuit... 1 logical bit weight It is defined as the sum of the weights of all gate operations associated with that logical bit. In the formula, This represents the total number of gate operations associated with this logical bit.

[0076] After calculating the weight values ​​of all logical bits, logical bits with higher weight values ​​are processed with higher priority because their associated gate operations are more concentrated at the beginning of the line, potentially reducing the use of subsequent SWAP gates (also known as switching gates). This is achieved by assigning weight values ​​to each logical bit. Prioritize the logical bits, mapping the highest-priority bits first and then processing the lower-priority bits sequentially. Furthermore, the weights between any two bits... Defined as the sum of the weights of all qubit gate operations involving both qubits, specifically expressed as: In this context, qubit q or w is used in qubit gate operations. middle.

[0077] Subsequently, based on the obtained logical bit priority information, and using an initial mapping algorithm that considers dual factors, an initial mapping is obtained. Specifically: In the initial mapping stage, for any logical bit to be mapped in the quantum circuit, based on the first evaluation function in the preset collaborative evaluation function and combined with the logical bit priority information, the influence of the current logical bit to be mapped in the architecture on the mapped neighboring logical bits is analyzed to obtain a first evaluation result; based on the second evaluation function in the preset collaborative evaluation function and combined with the logical bit priority information, the influence of the current logical bit to be mapped in the architecture on the unmapped neighboring logical bits is analyzed to obtain a second evaluation result; the first evaluation result and the second evaluation result are standardized to determine the first processed result and the second processed result; a size comparison is performed based on the first processed result and the second processed result, and the target quantum bit mapping bit of the current logical bit to be mapped in the architecture is determined according to the corresponding comparison result; based on the target quantum bit mapping bit of each logical bit to be mapped, mapping is performed to obtain the current initial mapping relationship.

[0078] It's important to understand that the initial mapping is crucial because, in a quantum architecture, the core position is typically located in the center, so the logical bit with the highest weight should be mapped to that position first. For the remaining logical bits to be mapped in the circuit, this initial mapping algorithm primarily considers two factors: first, the impact of logical bit placement on already mapped (i.e., the mapping from logical bits to physical quantum bits) logical neighbor nodes; and second, the impact on unmapped logical neighbor nodes. By considering both factors, the effectiveness of bit placement can be comprehensively evaluated.

[0079] To evaluate the impact of mapped nodes, this embodiment designs a function in the initial mapping section. This function considers the distance between the logical bit q and its mapped logical neighbor node w, as well as the associated gate weights. The specific function form is:

[0080] ;

[0081] Where q is the logical bit to be mapped. Let be the physical location in the quantum device (i.e., the quantum computer in this embodiment), that is, the physical qubit corresponding to logical qubit q in the quantum device, and w be the mapped logical neighbor node of q. The diameter of the architecture graph (AG) corresponding to the architecture (a graph structure used to describe the connections between physical qubits in a quantum device, where nodes represent physical qubits and edges represent specific connections between them). This represents the shortest distance between the two nodes. The function is designed to map logical bit q to its logical neighbor w and ensure that the weight between the two nodes is greater, thereby maximizing the objective function. This potentially increases the likelihood of subsequent door operations being performed.

[0082] Next, the impact on unmapped neighbor nodes is evaluated. To this end, this embodiment defines another heuristic function. Its form is as follows:

[0083] ;

[0084] In the formula, u represents the unmapped logical neighbor node of q. The number of unmapped nodes connected to q. For nodes The number of free neighbor nodes. Let be the weight between bits q and u. The goal of this function is to ensure that the neighbors of unmapped logical bits are mapped to the nearest free position by maximizing the function value. If there are not enough free positions to accommodate the unmapped logical neighbor nodes of q, the function applies a penalty term; if there are extra free positions, it provides a positive reward.

[0085] During this process, the following may occur and Since the values ​​differ significantly, this section performs Z-score standardization on these two functions, transforming them into... and Subsequently, by introducing adjustment parameters... and To adjust the weights of the two, the final comprehensive judgment function is shown below:

[0086] .

[0087] Within this framework, for each logical bit q to be mapped at different positions in the quantum architecture Next, the comprehensive judgment function is calculated, and the physical location corresponding to the maximum value is selected for mapping. By repeatedly executing this process, all logical bits are traversed until all logical bits are mapped to their corresponding physical qubits, thus obtaining an effective initial mapping relationship. It defines the one-to-one correspondence between logical bits and physical qubits in a circuit.

[0088] Through the heuristic function and weight allocation strategy described above, the proposed initial mapping algorithm can effectively evaluate the placement of qubits, ensuring that the communication distance between logical bits is minimized, thereby reducing the need for SWAP gates. This algorithm not only considers the influence of mapped logical bits but also comprehensively evaluates the influence of unmapped neighbor nodes to ensure that the mapping decision for each logical bit is optimal.

[0089] Step S13: Input the current initial mapping relationship into the quantum circuit, and combine it with the preset two-stage multi-objective collaborative optimization strategy to select and execute the sequence of swap gate operations (which are the basic operations used to swap the states of two bits in quantum computing) to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit.

[0090] In this embodiment, combined with Figure 3 As shown, after determining the current initial mapping relationship, it is input into the quantum circuit. The intermediate bit routing algorithm with two-stage multi-objective cooperative optimization is used to select the SWAP gate operation sequence until all gate operations are executed, and the mapping relationship at the end of the circuit is obtained. Specifically: The current initial mapping relationship is input into the quantum circuit, and the quantum circuit is run; a current candidate set of switching gate operations is configured; wherein, the current candidate set of switching gate operations is not greater than the edge set corresponding to the architecture; based on a preset two-stage multi-objective collaborative optimization strategy and a preset operation evaluation function, it is determined whether each candidate switching gate operation in the current candidate set of switching gate operations meets the preset screening conditions, so as to determine the screening condition judgment result; if the screening condition judgment result shows that there are multiple candidate switching gate operations in the current candidate set that meet the conditions, then the operation screening result is determined; based on the preset multi-objective optimization function and the preset switching gate operation decomposition strategy, the frequency of action, position of action, and maximum depth of the circuit after action of each switching gate operation in the operation screening result are analyzed to determine the operation analysis result; based on the operation analysis result and the operation screening result, the sequence of switching gate operations corresponding to the quantum circuit is determined; based on the sequence of switching gate operations, the preset single-qubit gate fan-in and fan-out mechanism, and each single-qubit gate and each double-qubit gate in the quantum circuit, the intermediate bit routing operation corresponding to the quantum circuit is completed, and the first mapping relationship at the end of the current circuit is obtained. If the result of the screening condition judgment indicates that none of the candidate switching gate operations in the current candidate set of switching gate operations are satisfied, then the circuit depth is optimized based on the preset single-qubit gate fan-in fan-out mechanism, and according to the corresponding optimized quantum circuit, the process jumps back to the step of configuring the current candidate set of switching gate operations.

[0091] It is important to understand that during the forward traversal of the route to route intermediate bits:

[0092] (1) Define the current candidate set of switching gate operations. In the worst case, the candidate set contains the set of all edges in the quantum architecture. However, many SWAP gate operations can be excluded. Specifically, if a SWAP gate operation cannot reduce the bit distance between gate operations in the front-end layer, it is considered invalid. Such SWAP gate operations not only fail to effectively promote the execution of subsequent CNOT gate operations, but may also introduce additional computational resource overhead, reducing the overall efficiency of the algorithm. Based on this principle, a candidate set of SWAP gates is defined. Each element This involves all logical bits Q associated with the first k two-bit gate operations in the quantum circuit. This strategy ensures... The size of the set is always less than or equal to This effectively reduces the demand for computing resources.

[0093] (2) The first stage of the two-stage collaborative optimization algorithm is preset.

[0094] A heuristic function ES is proposed to evaluate the effectiveness of a single SWAP gate operation. The ES function focuses primarily on the maximum number of qubit gates that a single SWAP gate operation can execute, ensuring that the current SWAP gate operation is optimal within a given local search space. The ES function is defined as follows:

[0095] .

[0096] In the formula, This indicates the insertion of a single SWAP gate operation. Then, the number of executable two-qubit gates in the quantum circuit. The heuristic function ES calculates all possible SWAP gate operations. The larger the ES value, the higher the local benefit of the current SWAP gate operation, because more two-qubit gates can be executed.

[0097] (3) Define a variable DP to track the depth of a bit. Whenever a single-qubit gate operation is performed on a logical bit, the corresponding DP value is incremented by 1, reflecting the current depth of the bit. In addition, a set SG is defined to store the single-qubit gates for the corresponding bit. If there are executable CNOT gate operations in the current circuit, these qubit gates will be applied to specific bits to realize the fan-in and fan-out of single-qubit gates.

[0098] Regarding fan-in of single-qubit gates: To effectively track the depth of each logical bit in a quantum circuit and reduce the circuit depth of a specific logical bit, a DP variable is first defined to store the current circuit depth state of each qubit. Specifically, DP(Q) represents the current depth of bit Q, initially set to 0. During qubit gate execution, the DP variable is updated according to different gate types to reflect changes in qubit depth. For single-qubit gate operations, the DP value of the relevant qubit increases by 1 each time the operation is executed; while for two-qubit gate operations (such as CNOT gates), assuming it acts on logical bits p and q, the corresponding two physical qubits... and The DP value is updated to: When a SWAP gate operation is inserted, this operation is actually implemented by decomposing it into three CNOT gates. Therefore, during DP updates, the impact of the SWAP gate operation is reflected by increasing by 3, specifically: Using the DP update method described above, the circuit depth of each qubit can be accurately tracked, ensuring that changes in the depth of each node during the execution of the quantum circuit are reflected in a timely and accurate manner.

[0099] Regarding fan-out of single-qubit gates: Single-qubit gate operations are stored in a memory area called SG. Specifically, during the execution of a quantum circuit, when a two-qubit gate operation that satisfies the current device connectivity constraints is encountered... When a two-qubit gate operation is executable under the current quantum architecture, the corresponding single-qubit gate is retrieved from the SG and applied to the quantum circuit. The core of this strategy is that once a two-qubit gate operation is executable under the current quantum architecture, the stored single-qubit gate is retrieved from the SG and applied to ensure that the difference in circuit depth between qubits remains within a small range. During quantum circuit execution, if a CNOT gate operation that does not satisfy the architecture constraints is encountered, the algorithm needs to insert a SWAP gate operation (assuming it is a bit). and Related door operations Additional adjustments were made beforehand.

[0100] First, the qubit with the minimum circuit depth among the two target physical qubits is calculated using the following expression:

[0101] .

[0102] Next, a certain number of single-qubit gate operations are popped from the corresponding storage region SG(s) to ensure the target physical qubit. and The depth difference between them should be kept as small as possible to avoid a sharp increase in circuit depth after inserting a SWAP gate operation. In this process, the number k of single-qubit gate pops is determined by the following formula:

[0103] ;

[0104] In the formula, This represents the number of single-qubit gate operations in the storage region SG(s). This constraint formula guarantees that the storage region's capacity limit will not be exceeded even when there are significant differences in qubit depth.

[0105] (4) The second stage of the pre-set two-stage collaborative optimization algorithm.

[0106] From the candidate set Select a SWAP gate operation And use the ES function to calculate the corresponding function value. and take the maximum value. When FQ=0, it means there is no SWAP gate operation that allows subsequent two-qubit gate operations to be executed directly; if FQ=0, it means there is no SWAP gate operation that allows subsequent two-qubit gate operations to be executed directly. If the FQ value is 0 and multiple identical FQ values ​​exist, then the set of SWAP gate operations needs further filtering. In this case, through fine-tuning, the algorithm can select the optimal SWAP gate operation.

[0107] When FQ When the FQ value is 0, the corresponding SWAP gate operation is first identified. Then, in the case of multiple identical FQ values, the bit distance between gate operations and the line depth are further considered. To this end, the algorithm defines the following refined heuristic function. And with the goal of minimizing its value:

[0108] ;

[0109] In the formula, This indicates the maximum depth of the line after inserting a SWAP gate at the current position, i.e.: ,in, This refers to the line depth corresponding to each qubit. This design can effectively avoid inserting SWAP gates on qubits with higher depths.

[0110] parameter Aiming to reduce the number of swap gates and increase the gate cancellation probability, the core idea is to optimize the overall structure of the quantum circuit by rationally selecting the insertion position of the swap gate so that it cancels out the existing qubit gate operations on the left. To this end, a RECENT set is introduced to record the most recently executed gate operation for each qubit. Initially, The value is 0. If, before the insertion of the SWAP gate operation, the number of qubits involved in the SWAP gate is... and The following relationship must be satisfied: This indicates that the quantum bit and The same door operation is involved. At this point, A positive value indicates that, through appropriate decomposition, this gate can cancel out the previous two-qubit gate, thereby further simplifying the circuit structure.

[0111] exist In the definition, this embodiment introduces the decay value function decay, considering the decay value function decay in qubits. and When performing a SWAP operation, the decay of the two bits will increase by a constant. This design aims to guide the algorithm to prioritize qubits that have not recently participated in SWAP gate operations, thereby effectively reducing the depth of the circuit. The specific form is:

[0112] .

[0113] Where F represents the set of gates in the front-end layer, E represents the set of gates in the extension layer, and Dis( Dis(F) represents the sum of the distances between all quantum gates in F. (,E) represents the sum of the distances between all qubit gates in F and E. Indicates the size of the set. The size of the set is represented by E, and the range of E can be determined by a preset lookahead window size. In the computation, a discount factor w needs to be set for the gate operations in the extended layer E, because these gates are located at the end of the circuit and have a smaller impact on the overall result. Finally, by minimizing the entire function... It can select the optimal SWAP gate operation from all candidate SWAP gate operations and insert it into the quantum circuit to perform subsequent gate operations.

[0114] When ES is 0, the processing is relatively simple. This means that after inserting any SWAP gate operation from the current candidate set, no two-qubit gate can be executed. In this case, the algorithm selects the CNOT gate with the smallest distance in the front-end layer that does not satisfy the device connectivity constraint, inserts a SWAP gate operation, aims to reduce the bit distance of the CNOT gate, and ensures that the SWAP gate operation satisfies the minimum requirement among this series of operations. Conditions. This routing process is repeated until all qubit gates in the circuit have been executed.

[0115] Step S14: Perform circuit reversal on the unmapped quantum circuit, utilize the corresponding first reversed circuit and the preset two-stage multi-objective collaborative optimization strategy, and use the first mapping relationship as the current initial mapping relationship for intermediate bit routing, and trigger the circuit reversal operation and the intermediate bit routing operation again to obtain the second mapping relationship at the end of the current circuit; the multi-objective includes circuit depth, quantum gate distance and swap gate decomposition characteristics.

[0116] In this embodiment, after completing the intermediate bit routing operation of a forward traversal of the line and obtaining the first mapping relationship at the end of the current line, the quantum line is reversed, the mapping relationship obtained in the previous step is applied to the line, and the routing algorithm is executed again until all gate operations are completed and the mapping relationship at the end of the line is obtained. Specifically: the unmapped quantum line is reversed to obtain a first reversed line, the first mapping relationship is used as the current initial mapping relationship and input into the first reversed line, and the first reversed line is run; based on the preset two-stage multi-objective collaborative optimization strategy, the selection and execution of the switch gate operation sequence are performed to complete the intermediate bit routing operation corresponding to the first reversed line, so as to obtain the third mapping relationship at the end of the current line; the unmapped first reversed line is reversed to obtain a second reversed line; the third mapping relationship is used as the current initial mapping relationship and input into the second reversed line, and the second reversed line is run; based on the preset two-stage multi-objective collaborative optimization strategy, the selection and execution of the switch gate operation sequence are performed to complete the intermediate bit routing operation corresponding to the second reversed line, so as to obtain the second mapping relationship at the end of the current line. In other words, the entire unmapped quantum circuit (Original Circuit, OC) is reversed to obtain the reversed circuit (OCRS), and the mapping relationship generated at the end of the previous stage is input into the current circuit. After all quantum gates are executed in the routing stage, the current circuit OCRS is reversed again to obtain OC, and the same routing process is repeated.

[0117] It is understandable that this stage will involve two route reversals, and after each reversal, a pre-defined two-stage multi-objective collaborative optimization strategy will be used to perform an intermediate bit routing operation on the reversed route. The execution logic of each intermediate bit routing operation is the same, and it will reset... DP, SG.

[0118] Step S15: Use the second mapping relationship as the current initial mapping relationship, and jump back to the step of inputting the current initial mapping relationship into the quantum circuit until the preset loop termination condition is met.

[0119] Combination Figure 2As shown, the preset loop termination condition in this embodiment can be the number of iterations. Specifically, the intermediate routing bit operation in steps S13 and S14 will be repeated until the current iteration count reaches the iteration count threshold, at which point the loop will terminate.

[0120] Step S16: By analyzing the line depth value corresponding to each intermediate bit routing operation in the loop process, determine the target mapping strategy, and execute the line mapping operation corresponding to the quantum line based on the target mapping strategy; the target mapping strategy includes the corresponding current initial mapping relationship, the first mapping relationship, or the second mapping relationship.

[0121] It is important to understand the iterative process in this embodiment: For a given quantum circuit, an initial mapping is first applied and a routing algorithm is executed to generate a feasible implementation that conforms to the architectural constraints and has a specific circuit depth. Then, the mapping relationship output at the end of this process is used as the initial mapping for its inverse circuit, and the routing operation is executed again, resulting in a circuit depth for the inverse circuit as well. This process is repeated until a preset termination condition is met. Afterward, the circuit depths generated by all intermediate bit routing stages (including forward and reverse) are statistically analyzed and compared. The initial mapping and routing scheme with the smallest depth are selected as the optimal solution, thus obtaining the target mapping strategy. Finally, the circuit mapping operation corresponding to the quantum circuit is executed based on the target mapping strategy.

[0122] In this way, multi-objective collaborative optimization of gate number and circuit depth can be achieved on datasets of different sizes and on quantum devices, and the final mapping results can show significant performance advantages in both gate number and circuit depth.

[0123] In summary, this embodiment first proposes a scheme for representing line depth and a storage scheme for single-bit quantum gates, which are used for subsequent design of heuristic functions. Next, it proposes a gate weight definition method based on line layering, thereby further defining the weight of each logical bit in the line and the weights between CNOT gate bits in the line. In the initial mapping stage, this embodiment proposes an initial mapping scheme that considers the influence of dual factors. Specifically, it designs a collaborative evaluation function to evaluate the influence of mapped and unmapped bits on the current bit to be mapped. This evaluation function guides the current bit to the optimal position on the physical coupling graph, ultimately finding an optimal initial mapping relationship. In the intermediate bit routing stage, this embodiment proposes a two-stage SWAP collaborative optimization scheme. Specifically, in the first stage, unlike most other heuristic circuit mapping schemes that select the SWAP gate operation that minimizes the distance between subsequent gates, this embodiment selects the SWAP gate operation that maximizes the number of subsequent executable gates, based on the number of subsequent executable gates. In the second stage, addressing the possibility that multiple SWAP gate operations may exist in the first stage that maximize the number of subsequent executable gates, this embodiment proposes a more refined heuristic function. The optimal SWAP gate operation is selected from the candidate optimal SWAP gate set based on three aspects: the frequency of SWAP gate operation on bits, the maximum circuit depth after the SWAP gate operation, and the gate cancellation characteristics present in the circuit. To more fully utilize the gate cancellation characteristics in quantum circuits, this embodiment uses an adaptive SWAP decomposition strategy during intermediate bit routing to further reduce the circuit depth. Unlike other algorithms that use only a fixed SWAP decomposition method, the adaptive SWAP decomposition strategy decomposes the SWAP based on the quantum gate characteristics before the SWAP operation. The gate cancellation property refers to the fact that quantum circuits consist of qubits and quantum gates. A quantum gate is mathematically represented as a unitary matrix, meaning that when two identical quantum gates are applied sequentially to the same qubit, their effects will cancel each other out. Similarly, two-qubit gates also possess this property; when one CNOT gate is immediately followed by another CNOT gate, the effects of the two CNOT gates will cancel each other out.

[0124] Therefore, in this application, the quantum circuit is first decomposed according to its architecture, and the weighting result of the gate operation is determined by combining the hierarchical structure information of the circuit. Then, the logical bit priority information of the circuit is determined based on the weighting result, and the current initial mapping relationship of the circuit is determined by combining the preset cooperative evaluation function. Then, the current initial mapping relationship is input into the quantum circuit, and the selection and execution of the gate operation sequence are performed by combining the preset two-stage multi-objective cooperative optimization strategy to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit. Then, the unmapped quantum circuit is reversed, and the intermediate bit routing operation is executed again by combining the first mapping relationship and the preset two-stage multi-objective cooperative optimization strategy. After the operation is completed, the circuit reversal operation and intermediate bit routing operation are triggered again to obtain the second mapping relationship at the end of the current circuit. Then, the second mapping relationship is used as the current initial mapping relationship, and the process jumps back to the step of inputting the current initial mapping relationship into the quantum circuit until the preset loop termination condition is met. The circuit depth value corresponding to each intermediate bit routing operation in the loop process is analyzed to determine the target mapping strategy, and the circuit mapping corresponding to the quantum circuit is completed according to the target mapping strategy. This approach addresses issues such as insufficient consideration of evaluation functions, simplistic strategies, high computational resource overhead, and poor collaborative optimization in existing related schemes. It enables a comprehensive and rational design of evaluation functions, taking into account indicators such as quantum circuit depth, thereby achieving more efficient heuristic circuit mapping for multi-objective optimization.

[0125] See Figure 4 As shown in the embodiments, this application also discloses a multi-objective quantum circuit mapping device for a quantum computer, comprising:

[0126] The gate operation weighting module 11 is used to decompose the quantum circuit based on the architecture of the target quantum computer, and to assign weights to the gate operations based on the corresponding circuit decomposition results and the hierarchical structure information of the quantum circuit, so as to determine the weighting results; the circuit decomposition results include single-qubit gates and two-qubit gates.

[0127] The collaborative evaluation module 12 is used to determine the logical bit priority information of the quantum circuit based on the weighting result, and to use the logical bit priority information and the preset collaborative evaluation function to determine the target quantum bit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture, so as to obtain the current initial mapping relationship.

[0128] The first routing module 13 is used to input the current initial mapping relationship into the quantum circuit, and combine it with a preset two-stage multi-objective collaborative optimization strategy to select and execute the switching gate operation sequence in order to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit.

[0129] The second routing module 14 is used to reverse the unmapped quantum circuit, utilize the corresponding first reversed circuit and the preset two-stage multi-objective collaborative optimization strategy, and use the first mapping relationship as the current initial mapping relationship for intermediate bit routing, and trigger the circuit reversal operation and the intermediate bit routing operation again to obtain the second mapping relationship at the end of the current circuit; the multi-objective includes circuit depth, quantum gate distance and swap gate decomposition characteristics;

[0130] Step jump module 15 is used to take the second mapping relationship as the current initial mapping relationship and jump back to the step of inputting the current initial mapping relationship into the quantum circuit until the preset loop termination condition is met;

[0131] The mapping strategy determination module 16 is used to determine the target mapping strategy by analyzing the line depth value corresponding to each intermediate bit routing operation in the loop process, and to perform the line mapping operation corresponding to the quantum line based on the target mapping strategy; the target mapping strategy includes the corresponding current initial mapping relationship, the first mapping relationship or the second mapping relationship.

[0132] In some specific embodiments, the gate operation authorization module 11 may specifically include:

[0133] The circuit decomposition unit is used to decompose quantum circuits based on a preset decomposition algorithm and the architecture of the target quantum computer in order to determine the circuit decomposition results.

[0134] A hierarchical partitioning unit is used to partition the quantum circuit hierarchically to obtain the hierarchical structure information of the quantum circuit.

[0135] The hierarchy determination unit is used to determine the circuit hierarchy corresponding to the single-qubit gate and the double-qubit gate in the circuit decomposition result based on the hierarchy structure information.

[0136] The weighting unit is used to assign weights to corresponding gate operations based on the circuit hierarchy to determine the weighting result; the gate operations include single-qubit gate operations and two-qubit gate operations.

[0137] In some specific embodiments, the collaborative evaluation module 12 may specifically include:

[0138] The weight value determination unit is used to determine the weight value of any logical bit in the quantum circuit based on the weighting result and the gate operation information corresponding to the current logical bit.

[0139] The priority determination unit is used to sort the weight values ​​corresponding to each logical bit in the quantum circuit to determine the logical bit priority information.

[0140] The bit weight determination unit is used to determine the corresponding bit weight for any two logical bits in the quantum circuit based on the corresponding two-qubit gate operation and the weighting result.

[0141] In some specific embodiments, the collaborative evaluation module 12 may specifically include:

[0142] The first evaluation unit is used, during the initial mapping stage, to analyze the impact of the placement of the current logical bit to be mapped in the architecture on the mapped neighboring logical bits, based on the first evaluation function in the preset cooperative evaluation function and combined with the logical bit priority information, for any logical bit to be mapped in the quantum circuit, so as to obtain the first evaluation result.

[0143] The second evaluation unit is used to analyze the impact of the placement of the current unmapped logical bit in the architecture on the unmapped neighbor logical bits based on the second evaluation function in the preset collaborative evaluation function and in combination with the logical bit priority information, so as to obtain the second evaluation result.

[0144] A standardization unit is used to standardize the first evaluation result and the second evaluation result to determine the first processed result and the second processed result.

[0145] The mapping bit determination unit is used to perform a size comparison based on the first processed result and the second processed result, and determine the target quantum bit mapping bit of the current logical bit to be mapped in the architecture according to the corresponding comparison result;

[0146] The initial mapping determination unit is used to perform mapping based on the target quantum bit mapping bits of each of the logical bits to be mapped, so as to obtain the current initial mapping relationship.

[0147] In some specific embodiments, the first routing module 13 may specifically include:

[0148] The first mapping input unit is used to input the current initial mapping relationship into the quantum circuit and run the quantum circuit;

[0149] An operation candidate set configuration unit is used to configure the current switch gate operation candidate set; wherein, the current switch gate operation candidate set is not greater than the edge set corresponding to the architecture;

[0150] The screening condition judgment unit is used to determine whether each candidate switch gate operation in the current candidate set of switch gate operations meets the preset screening conditions based on the preset two-stage multi-objective collaborative optimization strategy and the preset operation evaluation function, so as to determine the screening condition judgment result.

[0151] The first screening result determination unit is used to determine the operation screening result if the screening condition judgment result indicates that there are multiple candidate switching gate operations that satisfy the current candidate switching gate operation.

[0152] The operation analysis unit is used to analyze the frequency of action, position of action and maximum line depth of each of the switching gate operations in the operation screening results based on a preset multi-objective optimization function and a preset switching gate operation decomposition strategy, so as to determine the operation analysis results.

[0153] An operation sequence determination unit is used to determine the switching gate operation sequence corresponding to the quantum circuit based on the operation analysis results and operation screening results.

[0154] The first mapping relationship determination unit is used to complete the intermediate bit routing operation corresponding to the quantum circuit based on the exchange gate operation sequence, the preset single-qubit gate fan-in and fan-out mechanism, and each single-qubit gate and each double-qubit gate in the quantum circuit, and to obtain the first mapping relationship at the end of the current circuit.

[0155] In some specific embodiments, the multi-objective quantum circuit mapping device of the quantum computer may further include:

[0156] The line depth optimization unit is used to perform line depth optimization based on the preset single-qubit gate fan-in fan-out mechanism if the result of the screening condition judgment indicates that none of the candidate switching gate operations in the current candidate set of switching gate operations are satisfied, and then jump back to the step of configuring the current candidate set of switching gate operations according to the corresponding optimized quantum line.

[0157] In some specific embodiments, the second routing module 14 may specifically include:

[0158] The first circuit reversal unit is used to reverse the unmapped quantum circuit to obtain a first reversed circuit.

[0159] The second mapping input unit is used to input the first mapping relationship as the current initial mapping relationship into the first reversed line and run the first reversed line;

[0160] The third mapping relationship determination unit is used to select and execute the switching gate operation sequence based on the preset two-stage multi-objective collaborative optimization strategy, so as to complete the intermediate bit routing operation corresponding to the first reversed line, so as to obtain the third mapping relationship at the end of the current line.

[0161] The second line reversal unit is used to reverse the unmapped first reversed line to obtain the second reversed line.

[0162] The third mapping input unit is used to input the third mapping relationship as the current initial mapping relationship into the second reversed line and run the second reversed line;

[0163] The second mapping relationship determination unit is used to select and execute the switching gate operation sequence based on the preset two-stage multi-objective collaborative optimization strategy, so as to complete the intermediate bit routing operation corresponding to the second reversed line, so as to obtain the second mapping relationship at the end of the current line.

[0164] Furthermore, embodiments of this application also disclose an electronic device, Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0165] Figure 5 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the multi-objective quantum circuit mapping method for quantum computers disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0166] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0167] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0168] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the multi-objective quantum circuit mapping method of the quantum computer executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks.

[0169] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned multi-objective quantum circuit mapping method for quantum computers. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0170] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0171] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0172] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0173] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0174] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for mapping multi-objective quantum circuits in a quantum computer, characterized in that, include: Based on the architecture of the target quantum computer, the quantum circuit is decomposed, and based on the corresponding decomposition results and the hierarchical structure information of the quantum circuit, the weights of the gate operations are assigned to determine the weighting results; the decomposition results include single-qubit gates and two-qubit gates. Based on the weighting result, the logical bit priority information of the quantum circuit is determined, and the logical bit priority information and the preset cooperative evaluation function are used to determine the target quantum bit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture, so as to obtain the current initial mapping relationship. The current initial mapping relationship is input into the quantum circuit, and combined with the preset two-stage multi-objective collaborative optimization strategy, the selection and execution of the switching gate operation sequence are carried out to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit. The unmapped quantum circuit is reversed using the corresponding first reversed circuit and the preset two-stage multi-objective collaborative optimization strategy. The first mapping relationship is used as the current initial mapping relationship for intermediate bit routing. The circuit reversal operation and the intermediate bit routing operation are triggered again to obtain the second mapping relationship at the end of the current circuit. The multi-objectives include circuit depth, quantum gate distance and swap gate decomposition characteristics. The second mapping relationship is used as the current initial mapping relationship, and the process jumps back to the step of inputting the current initial mapping relationship into the quantum circuit until the preset loop termination condition is met. By analyzing the line depth value corresponding to each intermediate bit routing operation in the loop process, a target mapping strategy is determined, and a line mapping operation corresponding to the quantum line is executed based on the target mapping strategy; the target mapping strategy includes the corresponding current initial mapping relationship, the first mapping relationship, or the second mapping relationship.

2. The multi-objective quantum circuit mapping method for quantum computers according to claim 1, characterized in that, The architecture based on the target quantum computer decomposes the quantum circuits and assigns weights to gate operations based on the decomposition results and the hierarchical structure information of the quantum circuits, including: Based on the preset decomposition algorithm and the architecture of the target quantum computer, the quantum circuit is decomposed to determine the decomposition result. The quantum circuit is hierarchically divided to obtain its hierarchical structure information. Based on the hierarchical structure information, the circuit levels corresponding to the single-qubit gate and the double-qubit gate in the circuit decomposition results are determined; Weights are assigned to the corresponding gate operations based on the circuit hierarchy to determine the weighting result; the gate operations include single-qubit gate operations and two-qubit gate operations.

3. The multi-objective quantum circuit mapping method for quantum computers according to claim 1, characterized in that, The determination of the logical bit priority information of the quantum circuit based on the weighting result includes: For any logical bit in the quantum circuit, the weight value of the current logical bit is determined based on the weighting result and the gate operation information corresponding to the current logical bit. The weight values ​​corresponding to each logical bit in the quantum circuit are sorted to determine the logical bit priority information; For any two logical bits in the quantum circuit, the corresponding bit weights are determined based on the corresponding two-qubit gate operation and the weighting result.

4. The multi-objective quantum circuit mapping method for quantum computers according to claim 1, characterized in that, The step of using the logical bit priority information and a preset cooperative evaluation function to determine the target quantum bit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture, so as to obtain the current initial mapping relationship, includes: In the initial mapping phase, for any logical bit to be mapped in the quantum circuit, based on the first evaluation function in the preset cooperative evaluation function and combined with the logical bit priority information, the influence of the current logical bit to be mapped on the quantum bit placement in the architecture on the mapped neighboring logical bits is analyzed to obtain the first evaluation result. Based on the second evaluation function in the preset collaborative evaluation function, and combined with the logical bit priority information, the influence of the current logical bit to be mapped in the architecture on the placement of the quantum bits on the unmapped neighbor logical bits is analyzed to obtain the second evaluation result; The first evaluation result and the second evaluation result are standardized to determine the first post-processed result and the second post-processed result. A size comparison is performed based on the first processed result and the second processed result, and the target quantum bit mapping bit of the current logical bit to be mapped in the architecture is determined according to the corresponding comparison result; Based on the target quantum bit mapping bits of each of the logical bits to be mapped, a mapping is performed to obtain the current initial mapping relationship.

5. The multi-objective quantum circuit mapping method for quantum computers according to claim 1, characterized in that, The process of inputting the current initial mapping relationship into the quantum circuit, and combining it with a preset two-stage multi-objective collaborative optimization strategy to select and execute the sequence of swap gate operations to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit, includes: Input the current initial mapping relationship into the quantum circuit and run the quantum circuit; Configure the current candidate set of switch gate operations; wherein the current candidate set of switch gate operations is not greater than the edge set corresponding to the architecture; Based on a preset two-stage multi-objective collaborative optimization strategy and a preset operation evaluation function, it is determined whether each candidate switch gate operation in the current candidate switch gate operation set meets the preset screening conditions, so as to determine the screening condition judgment result. If the result of the filtering condition judgment indicates that there are multiple candidate switching gate operations that meet the criteria in the current candidate set of switching gate operations, then the operation filtering result is determined. Based on a preset multi-objective optimization function and a preset switching gate operation decomposition strategy, the frequency of action, position of action, and maximum line depth of each switching gate operation in the operation screening results are analyzed on the bit to determine the operation analysis results. Based on the operation analysis results and operation screening results, the switching gate operation sequence corresponding to the quantum circuit is determined; Based on the aforementioned exchange gate operation sequence, the preset single-qubit gate fan-in and fan-out mechanism, and each single-qubit gate and each double-qubit gate in the quantum circuit, the intermediate bit routing operation corresponding to the quantum circuit is completed, and the first mapping relationship at the end of the current circuit is obtained.

6. The multi-objective quantum circuit mapping method for quantum computers according to claim 5, characterized in that, After determining the result of the screening criteria, the process also includes: If the result of the screening condition judgment indicates that none of the candidate switching gate operations in the current candidate set of switching gate operations are satisfied, then the circuit depth is optimized based on the preset single-qubit gate fan-in fan-out mechanism, and according to the corresponding optimized quantum circuit, the process jumps back to the step of configuring the current candidate set of switching gate operations.

7. The multi-objective quantum circuit mapping method for a quantum computer according to any one of claims 1 to 6, characterized in that, The process of reversing the unmapped quantum circuit, utilizing the corresponding first reversed circuit and the preset two-stage multi-objective collaborative optimization strategy, and using the first mapping relationship as the current initial mapping relationship for intermediate bit routing, and then triggering the circuit reversal operation and the intermediate bit routing operation again, includes: The unmapped quantum circuit is reversed to obtain a first reversed circuit. The first mapping relationship is used as the current initial mapping relationship and input into the first reversed line, and the first reversed line is run; Based on the preset two-stage multi-objective collaborative optimization strategy, the selection and execution of the switching gate operation sequence are performed to complete the intermediate bit routing operation corresponding to the first reversed line, so as to obtain the third mapping relationship at the end of the current line. The unmapped first reversed line is reversed to obtain the second reversed line; The third mapping relationship is used as the current initial mapping relationship and input into the second reversed line, and the second reversed line is run; Based on the preset two-stage multi-objective collaborative optimization strategy, the selection and execution of the switching gate operation sequence are performed to complete the intermediate bit routing operation corresponding to the second reversed line, so as to obtain the second mapping relationship at the end of the current line.

8. A multi-objective quantum circuit mapping device for a quantum computer, characterized in that, include: The gate operation weighting module is used to decompose the quantum circuit based on the architecture of the target quantum computer, and assign weights to the gate operations based on the corresponding circuit decomposition results and the hierarchical structure information of the quantum circuit to determine the weighting results; the circuit decomposition results include single-qubit gates and two-qubit gates; The collaborative evaluation module is used to determine the logical bit priority information of the quantum circuit based on the weighting result, and to use the logical bit priority information and the preset collaborative evaluation function to determine the target quantum bit mapping bit of each logical bit to be mapped in the quantum circuit in the architecture, so as to obtain the current initial mapping relationship. The first routing module is used to input the current initial mapping relationship into the quantum circuit, and combine it with a preset two-stage multi-objective collaborative optimization strategy to select and execute the sequence of switching gate operations in order to complete the intermediate bit routing operation and obtain the first mapping relationship at the end of the current circuit. The second routing module is used to reverse the unmapped quantum circuit, utilize the corresponding first reversed circuit and the preset two-stage multi-objective collaborative optimization strategy, and use the first mapping relationship as the current initial mapping relationship for intermediate bit routing, and trigger the circuit reversal operation and the intermediate bit routing operation again to obtain the second mapping relationship at the end of the current circuit; the multi-objective includes circuit depth, quantum gate distance and swap gate decomposition characteristics; The step jump module is used to take the second mapping relationship as the current initial mapping relationship and jump back to the step of inputting the current initial mapping relationship into the quantum circuit until the preset loop termination condition is met. The mapping strategy determination module is used to determine the target mapping strategy by analyzing the line depth value corresponding to each intermediate bit routing operation in the loop process, and to perform the line mapping operation corresponding to the quantum line based on the target mapping strategy; the target mapping strategy includes the corresponding current initial mapping relationship, the first mapping relationship, or the second mapping relationship.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the multi-objective quantum circuit mapping method for a quantum computer as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program, which, when executed by a processor, implements the multi-objective quantum circuit mapping method for a quantum computer as described in any one of claims 1 to 7.

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