Intelligent PCB patch detection method and system

Abstract

The invention discloses an intelligent PCB patch detection method and system, and the method comprises the steps: carrying out the static elimination processing of a detection environment of a PCB patch, carrying out the static detection, obtaining an initial image of the PCB patch when a detection condition is satisfied, obtaining the position of the PCB patch, and judging whether the number of patches is abnormal or not; when the number of the patches is smaller than a preset number, marking that the patches are lost; when the number of the patches is equal to a preset number, determining a sampling area of a PCB patch position, adaptively calculating a first distance according to a patch shielding rate and a preset distance correction value, calculating a second distance according to the environmental parameters, and carrying out weighted summation on the first distance and the second distance to calculate a target distance so as to determine a sampling point; and calculating a patch offset rate according to the coordinates of the sampling points, and when the offset rate exceeds a preset offset rate, marking that the patch position is abnormal. According to the invention, the detection automation degree is improved, and meanwhile, the coverage capability and the judgment accuracy of various patch defects are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of PCB technology, and in particular to an intelligent PCB patch inspection method and system. Background Technology

[0002] Currently, with the rapid development of the electronics manufacturing industry towards high density and high precision, the quality inspection of PCB surface mount technology (SMT) has become a crucial link in ensuring the reliability of electronic products. Traditional PCB SMT inspection relies heavily on manual visual inspection or image recognition methods based on fixed rules, which have the following technical shortcomings: First, electrostatic interference in the inspection environment can easily lead to high noise in image acquisition, affecting the accuracy of subsequent analysis; second, most methods rely solely on morphological features to determine the presence of SMTs, making it difficult to effectively distinguish complex situations such as partial occlusion and tilted placement, resulting in missed or false detections; third, existing offset detection methods typically use fixed sampling points or thresholds, lacking the ability to adapt to environmental parameters and SMT states, and exhibiting poor stability under interference such as occlusion and reflection. Summary of the Invention

[0003] To address at least one of the aforementioned technical problems, this invention provides an intelligent PCB patch inspection method and system.

[0004] In a first aspect, the present invention provides an intelligent PCB surface mount inspection method, the method comprising: After electrostatic discharge (ESD) elimination treatment is performed on the PCB patch inspection environment, ESD detection is conducted to obtain the ESD detection value of the inspection environment. When the ESD detection value meets the inspection conditions, the PCB patch is transported to the inspection platform and the initial image of the PCB patch is obtained. Semantic segmentation is performed on the initial image to obtain the detection region and PCB patch positions. It is then determined whether there are any abnormalities in the number of PCB patches at each detection region position. If the number of patches is less than a preset number, it is marked as a missing patch. When the number of patches equals the preset number, extract the texture features of the PCB patch positions and calculate the image sharpness. Calculate the patch occlusion rate based on the texture features and image sharpness. Determine the sampling area for the PCB chip placement location, adaptively calculate the first distance based on the chip occlusion rate and preset distance correction value, calculate the second distance based on environmental parameters, and calculate the target distance by weighted summation of the first and second distances. Determine sampling points on the circumference of the circle with the center point of the sampling area as the center and the target distance as the radius. The patch offset rate is calculated based on the coordinates of the sampling points. When the offset rate exceeds the preset offset rate, it is marked as an abnormal patch position.

[0005] Preferably, the step of extracting texture features of the PCB patch location and calculating image sharpness, and calculating patch occlusion rate based on texture features and image sharpness, includes: Extract the ROI image of the PCB patch location, and perform grayscale conversion and Gaussian filtering on the ROI image; Local binary pattern features are calculated from the processed ROI image, and the texture disorder is determined based on the histogram entropy value of the local binary pattern features. The processed ROI image is convolved with the Laplacian operator. The variance of the second derivative image after convolution is calculated, and the image sharpness is determined based on the variance value. The texture disorder and image sharpness are normalized and aligned, and the patch occlusion rate is calculated by weighted summation.

[0006] Preferably, determining the sampling point on a circle with the center point of the sampling area as the center and the target distance as the radius includes: Divide the circumference into 16 equal parts to obtain 16 basic sampling points; The 16 basic sampling points were clustered, and the center point of each cluster was used as the final sampling point.

[0007] Preferably, the electrostatic discharge (ESD) elimination treatment is performed on the PCB surface mount testing environment before ESD detection is performed to obtain the ESD detection value of the testing environment, including: The detection environment is divided into several detection points. The electrostatic detection value of each monitoring point and the measurement change value of each adjacent monitoring point are calculated. The electrostatic detection value of the detection environment is calculated based on the electrostatic detection value of each monitoring point and the measurement change value of the adjacent monitoring points.

[0008] Secondly, the present invention also provides an intelligent PCB surface mount inspection system, the system comprising: The electrostatic discharge (ESD) detection unit is used to perform ESD elimination treatment on the PCB surface mount device (PCB) inspection environment before performing ESD detection to obtain the ESD detection value of the inspection environment. When the ESD detection value meets the inspection conditions, the PCB surface mount device is transported to the inspection platform and the initial image of the PCB surface mount device is acquired. The chip quantity detection unit is used to perform semantic segmentation on the initial image to obtain the detection area and PCB chip position, and to determine whether there is an abnormality in the number of chips at the PCB chip position in each detection area; when the number of chips is less than the preset number, it is marked as chip loss; The occlusion rate calculation unit is used to extract the texture features of the PCB patch positions and calculate the image sharpness when the number of patches equals the preset number, and calculate the patch occlusion rate based on the texture features and image sharpness. The sampling point analysis unit is used to determine the sampling area of ​​the PCB chip position. It adaptively calculates the first distance based on the chip occlusion rate and the preset distance correction value, calculates the second distance based on environmental parameters, and calculates the target distance by weighted summation of the first distance and the second distance. The sampling points are determined on the circumference of the circle with the center point of the sampling area as the center and the target distance as the radius. The patch position detection unit is used to calculate the patch offset rate based on the coordinates of the sampling point. When the offset rate exceeds the preset offset rate, it is marked as an abnormal patch position.

[0009] Preferably, the occlusion rate calculation unit is further used for: Extract the ROI image of the PCB patch location, and perform grayscale conversion and Gaussian filtering on the ROI image; Local binary pattern features are calculated from the processed ROI image, and the texture disorder is determined based on the histogram entropy value of the local binary pattern features. The processed ROI image is convolved with the Laplacian operator. The variance of the second derivative image after convolution is calculated, and the image sharpness is determined based on the variance value. The texture disorder and image sharpness are normalized and aligned, and the patch occlusion rate is calculated by weighted summation.

[0010] Preferably, the sampling point analysis unit is further configured to divide the circumference into 16 equal parts to obtain 16 basic sampling points; The 16 basic sampling points were clustered, and the center point of each cluster was used as the final sampling point.

[0011] Preferably, the electrostatic detection unit is further used for: The detection environment is divided into several detection points. The electrostatic detection value of each monitoring point and the measurement change value of each adjacent monitoring point are calculated. The electrostatic detection value of the detection environment is calculated based on the electrostatic detection value of each monitoring point and the measurement change value of the adjacent monitoring points.

[0012] Thirdly, the present invention also provides an electronic device including a processor and a memory, the memory being used to store computer program code, the computer program code including computer instructions, wherein when the processor executes the computer instructions, the electronic device performs the method as described in the first aspect above and any possible implementation thereof.

[0013] Fourthly, the present invention also provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor of an electronic device, cause the processor to perform a method as described in the first aspect above and any possible implementation thereof.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides an intelligent PCB surface mount inspection method. The method includes: performing electrostatic discharge (ESD) elimination treatment on the PCB surface mount inspection environment and then performing ESD detection to obtain the ESD detection value of the inspection environment; when the ESD detection value meets the detection conditions, transporting the PCB surface mount to the inspection platform and acquiring an initial image of the PCB surface mount; performing semantic segmentation on the initial image to obtain the inspection area and PCB surface mount position, and determining whether there is an abnormality in the number of PCB surface mounts at each inspection area position; when the number of surface mounts is less than a preset number, marking it as a missing surface mount; when the number of surface mounts is equal to the preset number, extracting the texture features of the PCB surface mount position and calculating the image sharpness, and calculating the surface mount occlusion rate based on the texture features and image sharpness; determining the sampling area of ​​the PCB surface mount position, adaptively calculating a first distance based on the surface mount occlusion rate and a preset distance correction value, calculating a second distance based on environmental parameters, and weighted summing the first distance and the second distance to calculate the target distance; determining sampling points on the circumference of a circle with the center point of the sampling area as the center and the target distance as the radius; calculating the surface mount offset rate based on the coordinates of the sampling points, and marking it as an abnormal surface mount position when the offset rate exceeds a preset offset rate.

[0015] The intelligent PCB patch inspection method proposed in this invention significantly reduces the interference of environmental static electricity on image quality by introducing electrostatic elimination and detection steps, providing a reliable data foundation for subsequent processing. Furthermore, semantic segmentation accurately locates the detection area and patch position, and the occlusion rate is calculated by combining texture features and sharpness, effectively solving the problem of misjudgment caused by partial occlusion. More importantly, an adaptive distance calculation mechanism based on occlusion rate and environmental parameters dynamically adjusts the sampling point position, enabling offset detection to possess both environmental adaptability and state awareness capabilities, significantly improving the accuracy of judging complex patch states.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the accompanying drawings used in the embodiments of the present invention or the background art will be described below.

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0019] Figure 1 This is a flowchart illustrating an intelligent PCB chip inspection method provided in an embodiment of the present invention. Figure 2 for Figure 1 A flowchart illustrating the sub-steps of step S30; Figure 3 This is a schematic diagram of an intelligent PCB surface mount inspection system provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] Please see Figure 1 , Figure 1 This is a flowchart illustrating an intelligent PCB surface mount inspection method provided in an embodiment of the present invention. Figure 1 As shown, the method includes: S10. After performing electrostatic discharge elimination treatment on the PCB patch inspection environment, perform electrostatic discharge detection to obtain the electrostatic discharge detection value of the inspection environment; when the electrostatic discharge detection value meets the inspection conditions, transport the PCB patch to the inspection platform and obtain the initial image of the PCB patch.

[0024] A dual-channel ion fan is used to perform 360° electrostatic removal in the testing environment, with the fan speed and duration set. Simultaneously, the anti-static floor grounding system of the testing platform is activated to ensure the grounding resistance remains stable within safe limits. A high-precision electrostatic meter is used to measure at five points in the testing area: upper left, upper right, center, lower left, and lower right. Several sets of data are collected at each point, and the arithmetic mean is taken as the electrostatic detection value. The measured electrostatic detection value is compared with a preset testing condition, such as ≤±50V. Only when this condition is met will the control system trigger the conveyor to safely and smoothly transport the PCB board under test to the designated position on the image acquisition platform. A high-resolution initial image of the PCB is acquired using a pre-calibrated industrial camera under uniform and stable lighting.

[0025] Static electricity can attract dust and interfere with the normal operation of sensors. This step fundamentally eliminates the problems of image blurring, increased noise, and loss of detail that may be caused by electrostatic interference, providing a high-quality and reliable data foundation for all subsequent image analysis. Static electricity can also damage delicate imaging equipment or sensitive components on PCBs; this step also provides effective protection against this potential damage.

[0026] In one embodiment, the step of performing electrostatic discharge (ESD) elimination treatment on the PCB surface mount testing environment and then performing ESD testing to obtain the ESD detection value of the testing environment may further include: The detection environment is divided into several detection points. The electrostatic detection value of each monitoring point and the measurement change value of each adjacent monitoring point are calculated. The electrostatic detection value of the detection environment is calculated based on the electrostatic detection value of each monitoring point and the measurement change value of the adjacent monitoring points.

[0027] ; In the formula, The final electrostatic discharge (ESD) value for the testing environment. For the first Electrostatic discharge values ​​at each monitoring point location. This is the amplification factor, used to amplify the effect of changes in electrostatic value. Indicates shared ownership One monitoring point.

[0028] in, The range of values ​​is usually 100. Magnification factor The size can be adjusted according to the characteristics of the testing environment, such as equipment layout and ventilation conditions. In electrostatic sensitive areas, such as the chip testing area, the size can be increased. The value is used to improve sensitivity, for example. When the environmental static electricity distribution is relatively stable, such as during the testing of ordinary components and PCBs, the static electricity level can be appropriately reduced. The value, such as the range of values ​​is This is to avoid minor fluctuations from causing excessive interference with the results.

[0029] This embodiment replaces single-point detection with sampling at multiple monitoring points, comprehensively reflecting the electrostatic distribution of the detection environment and avoiding misjudgments caused by localized electrostatic anomalies. Introducing the electrostatic change values ​​from adjacent monitoring points considers the spatial continuity and gradient of electrostatics, better reflecting the distribution characteristics of the electrostatic field in the actual environment. (The amplification factor is then used.) Highlighting the impact of sudden changes in electrostatic values, localized areas of electrostatic anomaly can be quickly identified, and a weighted average formula is used to calculate... This method retains the contribution of the absolute value of static electricity at each point while incorporating spatial variation characteristics, making the final result more reflective of the overall static safety of the environment.

[0030] S20. Perform semantic segmentation on the initial image to obtain the detection area and PCB patch position, and determine whether there is an abnormality in the number of PCB patch positions in each detection area; when the number of patches is less than the preset number, mark it as a patch loss.

[0031] This embodiment aims to detect surface mount anomalies, which typically include quantity anomalies and positional anomalies. In PCB surface mount production, "quantity anomalies," such as missing components, are completely different in nature and impact from "positional misalignment." Quantity anomalies can directly lead to PCB malfunction and are beyond repair, because each component, such as resistors, capacitors, and chips, is a core component for achieving a specific function. If there are missing components (quantity < preset value), even if the remaining components are perfectly positioned, the PCB will still malfunction due to the lack of critical components; for example, a missing resistor in a power circuit will cause a short circuit, and a missing chip in a signal circuit will cause communication interruption. Such PCBs are considered "fundamentally defective" and do not require further inspection for positional misalignment or appearance. They can be directly marked as "scrap" or "reworked," avoiding ineffective testing and resource waste. Positional misalignment, on the other hand, is a "precision issue" and can be partially repaired or reconstructed. Whether positional misalignment, such as a component deviating from a preset coordinate, constitutes a defect needs to be determined based on the amount of misalignment. Generally, if the misalignment is within the industry standard's allowable range, the PCB can still be soldered and function normally; if the misalignment exceeds the standard, it can be repaired by reworking and adjusting the component positions, such as using a robotic arm for repositioning. Therefore, the severity of abnormal component quantity is usually far greater than that of abnormal component quantity, and thus must be detected and addressed first. Furthermore, the detection of abnormal component placement is only meaningful if it is based on the premise of "normal quantity." Therefore, this step first determines whether there are any abnormalities in the number of components at different positions on the PCB.

[0032] Specifically, the initial image is processed using pre-trained deep learning semantic segmentation models such as U-Net and DeepLab. This model can identify and distinguish different parts of the image at the pixel level, and the output includes "detection regions," such as various pads or predetermined patch areas on a PCB board, and "PCB patch positions," which are precise masks of areas where actual components exist. For each "detection region" identified by the model, the existence of a corresponding "patch position" mask within it is checked. If a detection region contains no patch pixels, or its area is much smaller than normal, the number of patches at that location is determined to be less than a preset number (usually 1), and the system automatically marks that location as "patch missing."

[0033] Semantic segmentation models can effectively overcome interference from uneven lighting and complex backgrounds, locating components and pads more accurately than traditional image processing methods, significantly reducing the probability of missed and false detections. Therefore, this method can process the entire board image in parallel, quickly locating the positions of all missing components, with efficiency far exceeding manual visual inspection or traditional point-by-point scanning algorithms.

[0034] S30. When the number of patches equals the preset number, extract the texture features of the PCB patch positions and calculate the image clarity. Calculate the patch occlusion rate based on the texture features and image clarity.

[0035] When the number of patches equals the preset number, it is further determined whether the PCB patch position is abnormal. Abnormal PCB patch position (such as offset or tilt) is not determined by a single pixel or a single position. Furthermore, patches may have partial occlusion, blurred edges such as solder paste coverage, or interference from adjacent components. Therefore, different sampling points have different functions. The essence of selecting different sampling points is to perform "targeted sampling" based on patch features such as occlusion, shape, and key positioning areas, rather than indiscriminate traversal, thereby taking into account both "accuracy improvement" and "efficiency optimization".

[0036] For example, for a rectangular chip patch, its four corner points are the positioning references, meaning that offset calculation relies on the corner coordinates. If only the middle area of ​​the edge is sampled, coordinate calculation errors may occur due to edge wear / occlusion. Therefore, selecting a combination of corner points and edge midpoints as sampling points allows for cross-verification of multiple coordinates, reducing errors from a single sampling point. If the patch has partial occlusion, the occluded area must be avoided, such as the chip edge obscured by adjacent capacitors. Unoccluded "effective positioning areas," such as the chip pin area or silkscreen marking area, should be selected as sampling points. Therefore, if sampling points are not differentiated, incorrect sampling of occluded areas will lead to distorted offset rate calculations, resulting in the "visual offset" caused by occlusion being misjudged as actual patch offset. To accurately analyze patch offset, this embodiment first calculates the patch occlusion rate and then combines it with the movement distance to determine the optimal sampling point.

[0037] See Figure 2 In one embodiment, the step of extracting texture features of the PCB patch location and calculating image sharpness, and calculating patch occlusion rate based on texture features and image sharpness, includes: S301. Extract the ROI image of the PCB patch location, and perform grayscale conversion and Gaussian filtering on the ROI image. S302. Calculate local binary pattern features from the processed ROI image, and determine the texture disorder based on the histogram entropy value of the local binary pattern features; S303. Perform Laplacian convolution on the processed ROI image, calculate the variance of the second derivative image after convolution, and determine the image sharpness based on the variance value. S304. Normalize and homogenize the texture disorder and image clarity, and calculate the patch occlusion rate by weighted summation.

[0038] In this embodiment, based on the precise coordinate mask of the "PCB patch location" obtained in the S20 semantic segmentation step, the corresponding sub-image region is cropped from the initial image acquired in S10. This ROI image confines all subsequent calculations within the component body, eliminating background interference. The color ROI image is converted to a grayscale image, and weighted by the RGB three-color channels to conform to the human eye's sensitivity to different colors, simplifying the amount of data for subsequent processing. Then, a Gaussian convolution kernel is used to perform a convolution operation on the grayscale ROI image. This step aims to suppress any random noise that may exist in the image, while also preserving the image's edge information well, providing a "smooth" but feature-preserving data foundation for subsequent texture and sharpness calculations.

[0039] To calculate texture disorder, for each pixel in the preprocessed ROI image, its own grayscale value is used as a threshold. Eight pixels within its circular neighborhood (e.g., with a radius of one pixel) are sampled and compared using binary comparison. If the neighboring pixel value is greater than or equal to the center pixel value, it is marked as 1; otherwise, it is marked as 0. This binary sequence is treated as a binary number and converted to decimal, which is the LBP value of the center pixel. An LBP feature map is generated by traversing the entire image. Then, the distribution of all LBP values ​​(0-255) in the entire LBP feature map is statistically analyzed to form a histogram, and the information entropy of this histogram is calculated. The entropy value of the LBP histogram directly reflects the complexity and randomness of the image texture. The higher the entropy value, the more disordered and irregular the texture. A patch with a clean surface and uniform texture has a low LBP histogram entropy value; while when the patch is occluded by foreign objects, damaged, or contaminated, its surface texture pattern is disrupted, resulting in a higher entropy value. Therefore, this calculated entropy value is used as a quantitative indicator of texture disorder.

[0040] Furthermore, the Laplacian operator is used to perform convolution operations on the preprocessed grayscale ROI image. The Laplacian operator is highly sensitive to details such as edges and sharp corners in the image, and the convolution result will enhance these areas. The variance of all pixel values ​​is calculated for the second derivative image obtained after convolution. The magnitude of the variance directly reflects the amount of high-frequency information in the image. The larger the variance value, the clearer and sharper the image edges, the higher the contrast, and thus the better the image sharpness. Conversely, if the patch is obscured by a semi-transparent object, has a blurred surface, or is out of focus, its Laplacian convolution response will be weaker, and the variance value will also decrease significantly. Therefore, this variance value is used as a quantitative indicator of image sharpness.

[0041] Finally, to calculate the patch occlusion rate, texture disorder (entropy value) and image sharpness (variance value) are mapped to the interval [0,1], respectively. Normalization can be achieved using max-min normalization: ;in, The theoretical range can be obtained by statistically analyzing a large number of known good and known occlusion samples, or by using the relative maximum and minimum values ​​of the current batch of images. After normalization, the two indicators have opposite meanings: higher texture disorder (larger value) indicates a greater likelihood of occlusion, while higher image sharpness (larger value) indicates less occlusion. Therefore, one of the indicators needs to be "flipped" so that the two indicators are in the same direction in terms of numerical meaning, that is, larger values ​​indicate a more severe problem. Usually, the sharpness indicator is flipped, and the difference between 1 and this value is used to obtain the sharpness after unification. At this time, both texture disorder and sharpness become larger values, representing a greater likelihood of occlusion. Finally, the two indicators are linearly fused according to their importance to calculate the final patch occlusion rate. The specific values ​​of the weights of texture disorder and sharpness can be determined through experiments or machine learning optimization based on the importance of texture and sharpness features in the actual detection scenario. For example, if the occlusions are mostly foreign objects that alter the texture, a value with a larger weight for texture disorder, such as 0.7, can be assigned; if the occlusions are mostly oil stains that blur the image, a value with a larger weight for clarity, such as 0.6, can be assigned.

[0042] Therefore, by combining two complementary feature metrics—texture disorder (LBP entropy) and image sharpness (Laplacian variance)—different types of occlusion defects can be effectively distinguished. For example, solid foreign objects (such as solder balls) can cause drastic texture changes, while liquid contaminants (such as flux residue) or oil stains mainly cause image blurring. A single feature may miss detections, but dual-feature fusion ensures that all types of occlusion can be effectively captured, significantly reducing both the false negative and false positive rates.

[0043] S40. Determine the sampling area of ​​the PCB chip location, adaptively calculate the first distance based on the chip occlusion rate and the preset distance correction value, calculate the second distance based on the environmental parameters, and calculate the target distance by weighted summation of the first distance and the second distance. Determine the sampling point on the circumference with the center point of the sampling area as the center and the target distance as the radius.

[0044] In one embodiment, the first distance, the second distance, and the target distance are calculated as follows: ; In the formula, The first distance, Image acquisition height, The preset distance correction value, The decay rate coefficient satisfies ; For patch occlusion rate; ; In the formula, The second distance, For the preset threshold, For environmental sensitivity coefficient, satisfying ， This represents the average occlusion rate of the area surrounding the current patch location. ; ; In the formula, For the target distance, These are dynamic weighting coefficients.

[0045] In the above formula, The patch occlusion rate is the core input. The higher the occlusion rate, the worse the image quality of the component itself, and the less reliable the features. This can be understood as "visibility" or "credibility". The clearer the element, the higher this value. This is an exponentially decaying term. The decay rate coefficient controls the rate of decay. This is related to "reliability". As the occlusion worsens, this term increases rapidly. The entire formula indicates that the worse the image quality of the component itself, the higher the uncertainty, and the more conservative the system adopts a strategy, i.e., using a larger sampling radius. This allows for the search of potentially valid feature points across a wider area, avoiding the inability to locate points due to blurry local images. Image acquisition height, The preset distance correction value is a scaling factor used to adapt the calculation results to the actual physical dimensions and system accuracy requirements. Dividing by 2 is to constrain the range of the calculation results. This represents the average occlusion rate of the area surrounding the current component placement location, reflecting the overall quality of the local environment in which the component is located. If the surrounding components are dirty or occluded, it indicates a potential problem across the entire area (e.g., splash contamination). The preset threshold is a benchmark value that represents the ideal level of environmental quality. It measures the gap between the environmental threshold and the perfect state. It is an amplifying factor for the degree of environmental degradation. The higher the average shading rate of the surrounding area, the worse the environment, and the larger this denominator becomes. The environmental sensitivity coefficient is used to control the degree of amplification. Therefore... This becomes an "environmental compensation quantity." When the environment is favorable, the compensation quantity is larger. The compensation amount will be appropriately increased to achieve higher accuracy; however, it will decrease when the environment deteriorates. It will shrink to avoid using an excessively large radius in an environment with overall ambiguity, which would amplify the error. The dynamic weighting coefficient is not a fixed value, but changes dynamically, and its magnitude depends on the uncertainty of the current component itself. Environmental benchmarks The comparison. When the component itself is severely obscured ( (very large) It approaches 1. At this point, the target distance is... Almost entirely by (Based on its own state) determines; when the element itself is very clear ( (very small) It approaches 0. At this point, the target distance is... Almost entirely by Decision based on environmental conditions.

[0046] In this way, the rigid mode of traditional fixed-radius sampling is broken. The sampling strategy can be dynamically adjusted according to the real-time status of each element and its local environment. When faced with complex conditions such as occlusion, contamination, and changes in lighting, the system does not blindly raise or lower the detection standards, but intelligently adjusts its detection strategy. In areas with poor quality, it expands the sampling range to "try to see clearly"; in areas with good quality, it performs precise measurements. This greatly improves the stability and accuracy of detection under various harsh conditions. Computational resources are concentrated where they are most needed. For clear elements, fast and accurate measurements are performed; for blurred elements, more computational resources and a larger sampling range are used for judgment, thereby optimizing the overall detection efficiency while ensuring accuracy. By increasing the sampling radius of blurred elements, misjudgments caused by the loss or distortion of local feature points, such as misjudging occlusion as offset, are avoided, significantly improving the reliability of the detection results.

[0047] Preferably, determining the sampling point on a circle with the center point of the sampling area as the center and the target distance as the radius includes: Divide the circumference into 16 equal parts to obtain 16 basic sampling points; The 16 basic sampling points were clustered, and the center point of each cluster was used as the final sampling point.

[0048] In this embodiment, uniform and dense sampling (e.g., 16 points) on a circle with a radius equal to the target distance generates a large number of spatially nearest and feature-similar points. For example, for a rectangular patch capacitor with a regular shape and uniform surface, the edge features of its opposite sides may be very similar in the image. Dense sampling near these similar points yields redundant information, and repeated calculations waste valuable processing time. Subsequent step S50 requires offset calculation based on the coordinates of these sampling points. The number of sampling points directly determines the computational load. On high-speed, high-precision production lines, the detection of each component must be completed in milliseconds, so reducing unnecessary computation is crucial. This embodiment adopts a strategy of "uniformly distributing points first, then clustering for simplification," aiming to capture the contour features of components with the fewest and most representative sampling points, thereby intelligently eliminating redundancy. By reducing the number of sampling points from 16 to single digits, such as 4-6, through clustering, the computational load of all subsequent calculations based on sampling points (such as edge localization, coordinate comparison, and offset calculation) is significantly reduced. This sharp reduction in computational load allows the system to output results faster, greatly improving the throughput of the entire detection process.

[0049] S50. Calculate the patch offset rate based on the sampling point coordinates. When the offset rate exceeds the preset offset rate, mark it as an abnormal patch position.

[0050] In this embodiment, the actual pixel coordinates of a preset number of sampling points can be extracted, converted into physical coordinates, and the deviation between each sampling point and the design coordinates can be calculated. The average offset is calculated using the root mean square formula. Finally, when calculating the offset rate, the magnitude of the offset rate is equal to the ratio of the average offset to the maximum allowable offset, which is specifically set according to the patch type. During anomaly marking, typically, when the offset rate > 5% (precision components) or > 10% (ordinary components), it is determined to be a positional anomaly. The abnormal area is marked with a yellow dashed box in the image, indicating the offset direction and offset rate, and simultaneously stored in the detection database. In this way, the offset rate index can be quantified, achieving an objective evaluation of the patch position accuracy and avoiding the subjectivity of manual judgment. Differentiated thresholds are set for components with different accuracy requirements, balancing detection rigor with production feasibility and reducing the false positive rate.

[0051] In summary, the intelligent PCB patch inspection method proposed in this embodiment significantly reduces the interference of environmental static electricity on image quality by introducing electrostatic elimination and inspection steps, providing a reliable data foundation for subsequent processing. Furthermore, semantic segmentation accurately locates the detection area and patch position, and the occlusion rate is calculated by combining texture features and sharpness, effectively solving the misjudgment problem caused by partial occlusion. More importantly, by using an adaptive distance calculation mechanism based on occlusion rate and environmental parameters, the sampling point position is dynamically adjusted, enabling offset detection to possess both environmental adaptability and state awareness capabilities, significantly improving the accuracy of judging complex patch states.

[0052] See Figure 3 In one embodiment, the present invention also provides an intelligent PCB surface mount inspection system, the system comprising: The electrostatic discharge (ESD) detection unit 100 is used to perform ESD elimination treatment on the PCB patch detection environment and then perform ESD detection to obtain the ESD detection value of the detection environment. When the ESD detection value meets the detection conditions, the PCB patch is transported to the detection platform and the initial image of the PCB patch is obtained. The chip quantity detection unit 200 is used to perform semantic segmentation on the initial image to obtain the detection area and PCB chip position, and to determine whether there is an abnormality in the number of chips at the PCB chip position in each detection area; when the number of chips is less than the preset number, it is marked as chip loss. The occlusion rate calculation unit 300 is used to extract the texture features of the PCB patch position and calculate the image clarity when the number of patches is equal to the preset number, and calculate the patch occlusion rate based on the texture features and image clarity. The sampling point analysis unit 400 is used to determine the sampling area of ​​the PCB chip position. It adaptively calculates the first distance based on the chip occlusion rate and the preset distance correction value, calculates the second distance based on environmental parameters, and calculates the target distance by weighted summation of the first distance and the second distance. The sampling points are determined on the circumference with the center point of the sampling area as the center and the target distance as the radius. The patch position detection unit 500 is used to calculate the patch offset rate based on the coordinates of the sampling point. When the offset rate exceeds the preset offset rate, it is marked as an abnormal patch position.

[0053] In one embodiment, the occlusion rate calculation unit 300 is further used for: Extract the ROI image of the PCB patch location, and perform grayscale conversion and Gaussian filtering on the ROI image; Local binary pattern features are calculated from the processed ROI image, and the texture disorder is determined based on the histogram entropy value of the local binary pattern features. The processed ROI image is convolved with the Laplacian operator. The variance of the second derivative image after convolution is calculated, and the image sharpness is determined based on the variance value. The texture disorder and image sharpness are normalized and aligned, and the patch occlusion rate is calculated by weighted summation.

[0054] In one embodiment, the sampling point analysis unit 400 is also used to divide the circumference into 16 equal parts to obtain 16 basic sampling points; The 16 basic sampling points were clustered, and the center point of each cluster was used as the final sampling point.

[0055] In one embodiment, the electrostatic detection unit 100 is further configured to: The detection environment is divided into several detection points. The electrostatic detection value of each monitoring point and the measurement change value of each adjacent monitoring point are calculated. The electrostatic detection value of the detection environment is calculated based on the electrostatic detection value of each monitoring point and the measurement change value of the adjacent monitoring points.

[0056] It is understood that the system provided in this embodiment has functions or includes modules that can be used to execute the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0057] The present invention also provides an electronic device including a processor and a memory, the memory being used to store computer program code, the computer program code including computer instructions, wherein when the processor executes the computer instructions, the electronic device performs a method as described in any of the above possible implementations.

[0058] The present invention also provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor of an electronic device, cause the processor to perform a method as described in any of the above possible implementations.

[0059] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0060] Those skilled in the art will readily understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. Those skilled in the art will also readily understand that the various embodiments of the present invention have different focuses, and for the sake of convenience and brevity, the same or similar parts may not be repeated in different embodiments. Therefore, parts not described or not described in detail in one embodiment can be referred to in other embodiments.

Claims

1. An intelligent PCB surface mount inspection method, characterized in that, The method includes: After electrostatic discharge (ESD) elimination treatment is performed on the PCB patch inspection environment, ESD detection is conducted to obtain the ESD detection value of the inspection environment. When the ESD detection value meets the inspection conditions, the PCB patch is transported to the inspection platform and the initial image of the PCB patch is obtained. Semantic segmentation is performed on the initial image to obtain the detection region and PCB patch positions. It is then determined whether there are any abnormalities in the number of PCB patches at each detection region position. If the number of patches is less than a preset number, it is marked as a missing patch. When the number of patches equals the preset number, extract the texture features of the PCB patch positions and calculate the image sharpness. Calculate the patch occlusion rate based on the texture features and image sharpness. Determine the sampling area for the PCB chip placement location, adaptively calculate the first distance based on the chip occlusion rate and preset distance correction value, calculate the second distance based on environmental parameters, and calculate the target distance by weighted summation of the first and second distances. Determine sampling points on the circumference of the circle with the center point of the sampling area as the center and the target distance as the radius. The patch offset rate is calculated based on the coordinates of the sampling points. When the offset rate exceeds the preset offset rate, it is marked as an abnormal patch position.

2. The intelligent PCB surface mount inspection method according to claim 1, characterized in that, The process of extracting texture features from the PCB patch locations and calculating image sharpness, and then calculating the patch occlusion rate based on the texture features and image sharpness, includes: Extract the ROI image of the PCB patch location, and perform grayscale conversion and Gaussian filtering on the ROI image; Local binary pattern features are calculated from the processed ROI image, and the texture disorder is determined based on the histogram entropy value of the local binary pattern features. The processed ROI image is convolved with the Laplacian operator. The variance of the second derivative image after convolution is calculated, and the image sharpness is determined based on the variance value. The texture disorder and image sharpness are normalized and aligned, and the patch occlusion rate is calculated by weighted summation.

3. The intelligent PCB surface mount inspection method according to claim 1, characterized in that, The determination of sampling points on a circle with the center point of the sampling area as the center and the target distance as the radius includes: Divide the circumference into 16 equal parts to obtain 16 basic sampling points; The 16 basic sampling points were clustered, and the center point of each cluster was used as the final sampling point.

4. The intelligent PCB surface mount inspection method according to claim 1, characterized in that, The electrostatic discharge (ESD) elimination process is performed on the PCB surface mount device (PCB) inspection environment before ESD detection is conducted to obtain the ESD detection value of the inspection environment, including: The detection environment is divided into several detection points. The electrostatic detection value of each monitoring point and the measurement change value of each adjacent monitoring point are calculated. The electrostatic detection value of the detection environment is calculated based on the electrostatic detection value of each monitoring point and the measurement change value of the adjacent monitoring points.

5. An intelligent PCB surface mount inspection system, characterized in that, The system includes: The electrostatic discharge (ESD) detection unit is used to perform ESD elimination treatment on the PCB surface mount device (PCB) inspection environment before performing ESD detection to obtain the ESD detection value of the inspection environment. When the ESD detection value meets the inspection conditions, the PCB surface mount device is transported to the inspection platform and the initial image of the PCB surface mount device is acquired. The chip quantity detection unit is used to perform semantic segmentation on the initial image to obtain the detection area and PCB chip position, and to determine whether there is an abnormality in the number of chips at the PCB chip position in each detection area; when the number of chips is less than the preset number, it is marked as chip loss; The occlusion rate calculation unit is used to extract the texture features of the PCB patch positions and calculate the image sharpness when the number of patches equals the preset number, and calculate the patch occlusion rate based on the texture features and image sharpness. The sampling point analysis unit is used to determine the sampling area of ​​the PCB chip position. It adaptively calculates the first distance based on the chip occlusion rate and the preset distance correction value, calculates the second distance based on environmental parameters, and calculates the target distance by weighted summation of the first distance and the second distance. The sampling points are determined on the circumference of the circle with the center point of the sampling area as the center and the target distance as the radius. The patch position detection unit is used to calculate the patch offset rate based on the coordinates of the sampling point. When the offset rate exceeds the preset offset rate, it is marked as an abnormal patch position.

6. The intelligent PCB surface mount inspection system according to claim 5, characterized in that, The occlusion rate calculation unit is also used for: Extract the ROI image of the PCB patch location, and perform grayscale conversion and Gaussian filtering on the ROI image; Local binary pattern features are calculated from the processed ROI image, and the texture disorder is determined based on the histogram entropy value of the local binary pattern features. The processed ROI image is convolved with the Laplacian operator. The variance of the second derivative image after convolution is calculated, and the image sharpness is determined based on the variance value. The texture disorder and image sharpness are normalized and aligned, and the patch occlusion rate is calculated by weighted summation.

7. The intelligent PCB surface mount inspection system according to claim 5, characterized in that, The sampling point analysis unit is also used to divide the circumference into 16 equal parts to obtain 16 basic sampling points; The 16 basic sampling points were clustered, and the center point of each cluster was used as the final sampling point.

8. The intelligent PCB surface mount inspection system according to claim 5, characterized in that, The electrostatic detection unit is also used for: The detection environment is divided into several detection points. The electrostatic detection value of each monitoring point and the measurement change value of each adjacent monitoring point are calculated. The electrostatic detection value of the detection environment is calculated based on the electrostatic detection value of each monitoring point and the measurement change value of the adjacent monitoring points.

9. An electronic device, characterized in that, include: A processor and a memory, the memory being used to store computer program code, the computer program code including computer instructions, wherein when the processor executes the computer instructions, the electronic device performs the intelligent PCB placement inspection method as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which includes program instructions that, when executed by a processor of an electronic device, cause the processor to perform the intelligent PCB surface mount inspection method according to any one of claims 1 to 4.

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