Method and device for testing bit error rate of digital isolator
By using pseudo-random binary sequences and FPGAs for signal delay and logic operations in digital isolator testing, the problems of small and inaccurate bit error rate testing in existing technologies are solved, achieving efficient and accurate bit error detection and quality assessment.
Patent Information
- Application Number
- CN202511663198.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-02-10
AI Technical Summary
Existing methods for testing the bit error rate of digital isolators have a small test volume, making it difficult to capture probabilistic bit errors and simulate random waveforms in real-world application scenarios, resulting in inaccurate test results.
Using a pseudo-random binary sequence as the input signal, the input signal is generated and delayed by a field-programmable gate array (FPGA), and logical operations are performed with the output signal. The error is counted using XOR or XNOR gate logic circuits, and the logical operations are periodically triggered to avoid glitches. A clock signal is generated to control synchronization and support long-term data transmission testing.
It achieves accurate identification and location of errors in digital isolators, reduces the risk of misjudgment, provides quantitative quality assessment indicators, and the test results are closer to actual use scenarios.
Smart Images
Figure CN121508752A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit testing, specifically to a method and apparatus for testing the bit error rate of a digital isolator. Background Technology
[0002] Digital isolators are widely used in high-voltage / low-voltage conversion circuits. Their function is to transmit the digital signal input from the high-voltage / low-voltage end to the low-voltage / high-voltage end, achieving signal isolation between the high-voltage and low-voltage modules while enabling signal exchange. In the development of digital isolator chips, the modulation / demodulation function is the core of the chip design.
[0003] Figure 1 The circuit system structure diagram of a typical digital isolator in the prior art is shown, such as... Figure 1 As shown, the input signal Vin enters the digital isolator chip at the TX terminal (transmitter). It first undergoes shaping and level conversion, followed by modulation to convert the input square wave signal into a signal that can be transmitted through the isolation medium. Various modulation methods can be used, such as OOK (on / off keying) modulation, edge-triggered modulation, pulse counting modulation, and pulse polarity modulation. The modulated signal is then sent to the isolation medium, which can be a capacitor, inductor, or optocoupler. After passing through the isolation medium, the modulated signal is demodulated at the RX terminal (receiver) of the circuit system. The demodulated signal is then output from the output port via the output driver. Figure 1 The output signal Vout in the circuit. Depending on the modulation method, there are different demodulation circuit schemes. For example, a signal modulated by OOK can be demodulated using envelope detection.
[0004] In the design of signal modulation / demodulation circuits for digital isolators, special consideration must be given to details such as the selection, size, and layout of capacitors, resistors, and switches. These components require strict specifications; even minor, unpredictable process deviations can easily lead to signal transmission errors, i.e., bit errors. Practice shows that these bit errors are not deterministic; their trigger probability varies with the application scenario, requiring extensive data testing to detect. However, existing testing methods often have limited testing and detection capabilities, making it difficult to address this type of testing challenge. Summary of the Invention
[0005] To address the problem of difficulty in testing bit error rates when using digital isolators for isolated transmissions, a first aspect of this application provides a method for testing the bit error rate of a digital isolator. This testing method specifically includes:
[0006] Obtain the delay time of the digital isolator under test;
[0007] Generate an input signal, which includes a pseudo-random binary sequence;
[0008] The input signal is delayed based on the delay time to obtain the delayed input signal;
[0009] Input the input signal to the transmitter of the digital isolator under test, and obtain the output signal from the receiver of the digital isolator under test.
[0010] Logical operations are performed on the delayed input and output signals to obtain the result signal, wherein the logical operations are triggered periodically;
[0011] The high or low levels in the result signal are counted, and the bit error rate of the digital isolator under test is obtained based on the counting results.
[0012] Optionally, an XOR gate logic circuit can be used to perform logical operations and count the high levels in the result signal; or, an XNOR gate logic circuit can be used to perform logical operations and count the low levels in the result signal.
[0013] Optionally, the test method may also include pausing the test method when the comparison results of the delayed input signal and the output signal are inconsistent, so as to carry out timely debugging and subsequent analysis.
[0014] Optionally, an oscilloscope can be used to test the digital isolator under test to obtain the delay time.
[0015] Optionally, the input and / or output signals can be shaped using a digital buffer or a Schmitt trigger.
[0016] Optionally, the test method may also include: generating a clock signal; and using the clock signal to control the periodic triggering of logical operations.
[0017] In the aforementioned alternative scheme, the continuous comparison behavior is discretized by generating a clock signal for periodic triggering. The clock signal can be set in the stable period of the compared signal (the delayed input and output signals) (such as the middle of the period), thereby avoiding the unstable edges of signal changes and filtering out glitches.
[0018] Optionally, the same field-programmable gate array can be used to perform tasks such as generating input signals, delaying processing, generating clock signals, and counting the result signals.
[0019] The calculation result signal, counting result and bit error rate are sent to the storage module through a field-programmable gate array;
[0020] The counting results and / or bit error rate are transmitted to the display module via a field-programmable gate array (FPGA).
[0021] Logical operations are performed using a field-programmable gate array (FPGA).
[0022] Optionally, the test method may also include applying interference to the digital isolator under test;
[0023] The interference can be selected from one or more of the following: electromagnetic interference, preset temperature, preset humidity, and mechanical vibration.
[0024] A second aspect of this application provides a testing apparatus for the bit error rate of a digital isolator, the testing apparatus including a field-programmable gate array and a logic operation module;
[0025] The field-programmable gate array is configured to: generate input signals, delay the input signals, and count the operation result signals from the logic operation module, and obtain the bit error rate of the digital isolator under test based on the counting result. The input signals are used to input to the transmitting end of the digital isolator under test, and the input signals include pseudo-random binary sequences.
[0026] The logic operation module is configured to perform logic operations on the delayed input signal and the output signal from the receiver of the digital isolator under test, and output the operation result signal. The logic operation module is periodically triggered.
[0027] Optionally, the logic operation module is equipped with an XOR gate logic circuit, and the field-programmable gate array is configured to count the high level in the operation result signal; or, the logic operation module is equipped with an XNOR gate logic circuit, and the field-programmable gate array is configured to count the low level in the operation result signal.
[0028] Optionally, the field-programmable gate array is configured to pause the test if the comparison results of the delayed input signal and the output signal are inconsistent.
[0029] Optionally, a buffer module may also be included, which is equipped with a digital buffer or a Schmitt trigger for shaping the input signal and / or the output signal.
[0030] Optionally, an oscilloscope is also included, which is used to test the digital isolator under test to obtain the delay time;
[0031] The field-programmable gate array is configured to delay the input signal according to the delay time.
[0032] Optionally, the field-programmable gate array can be configured as follows:
[0033] A clock signal is generated, which is used to control the periodic triggering of the logic operation module.
[0034] Optionally, it may also include at least one of a display module, an input module, and a storage module;
[0035] The input module is used to input the delay time for delay processing;
[0036] The display module is used to display the counting results and / or bit error rate;
[0037] The storage module is used to store the operation result signal, the counting result, and the bit error rate.
[0038] Optionally, the operating rate of the field-programmable gate array (FPGA) is at least twice the transmission rate of the digital isolator under test.
[0039] Optionally, the logic operation module is integrated inside the field-programmable gate array.
[0040] In summary, the testing method and corresponding testing device for the bit error rate of digital isolators provided in this application embodiment generate a pseudo-random binary sequence (PRBS) as the input signal and automatically count the comparison results, supporting data transmission tests over a relatively long period. This solves the problems of traditional methods (such as oscilloscope testing) having small test quantities and only being able to detect short waveforms, thus more effectively capturing errors of digital isolators in probabilistic bit error scenarios.
[0041] Based on this, by delaying the input signal according to the delay time, the delayed input signal is aligned with the output signal. Then, by periodically triggering logical operations (such as XOR operations), the location of the bit error can be accurately identified. This overcomes the drawback of traditional methods that make it difficult to locate the bit error point due to signal misalignment.
[0042] By periodically triggering logical operations (avoiding glitches) and signal alignment, the risk of misjudgment is reduced, ensuring the accuracy of test results. Furthermore, the bit error rate, obtained based on counting results, provides a quantitative quality assessment metric, facilitating product reliability analysis. Attached Figure Description
[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.
[0044] Figure 1 This is a circuit system structure diagram of a typical application of digital isolators in the prior art, for reference only.
[0045] Figure 2 This is a flowchart illustrating the method for testing the bit error rate of a digital isolator provided in an embodiment of this application;
[0046] Figure 3 This is a schematic diagram of a pseudo-random binary sequence involved in an embodiment of this application;
[0047] Figure 4 This is an architectural diagram of a digital isolator bit error rate testing device provided in an embodiment of this application;
[0048] Figure 5 This is a test example of a test method for testing the bit error rate of a digital isolator provided in the embodiments of this application. Detailed Implementation
[0049] This application will now be described more fully below with reference to the accompanying drawings. However, this application can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided herein to make this application more detailed and complete, and to fully convey the scope of this application to those skilled in the art. The same reference numerals denote the same objects throughout the drawings.
[0050] In this specification, it will also be understood that when a component is referred to as being "connected to" other components relative to them, such as "connected to" other components, the component may be directly connected to or directly coupled to the component, or there may be an intermediary third component; in addition, in the embodiments of this application, "connection" may specifically be a connection in terms of signal transmission.
[0051] To address the bit error rate testing issues of existing digital isolators, the applicant has attempted various testing methods, including:
[0052] (1) Use a signal generator to input a square wave into the digital isolator, and then use an oscilloscope to simultaneously detect the correspondence between the input and output signals;
[0053] (2) Use a signal generator to generate an input signal, and use an oscilloscope or data acquisition card to collect the input waveform and output waveform values at the same time. Then perform data analysis based on the input waveform and output waveform.
[0054] Regarding the aforementioned method (1), due to its small detection volume, for digital isolators, the occurrence of bit errors is a probabilistic event rather than a certainty. Such bit error problems require a large amount of data testing to detect, but oscilloscope testing can often only detect a segment of waveform or a few trigger points. In addition, the input and output are generally not aligned, requiring manual judgment to determine whether the input and output correspond. All of these factors limit the amount of detection data. Therefore, due to the limitations of the combination system of oscilloscope and signal generator and the manual judgment method, method (1) is not suitable for large-scale data testing.
[0055] Furthermore, when using an oscilloscope to determine bit errors, manual judgment is often required. Testers might choose to directly count the total number of high and low levels. This method of counting can lead to inaccurate information such as signal alignment or misalignment. Even if the tester discovers a mismatch between the number of high and low levels, it's difficult to pinpoint the location of the bit error.
[0056] Furthermore, method (1) is difficult to simulate random waveforms in actual application scenarios. In the actual use of digital isolators, the input signal of the digital isolator may be various waveforms. For example, a continuous high level for a long time, a sudden low level, or frequent switching between high and low levels. However, ordinary function signal generators cannot customize waveforms. Arbitrary wave signal generators are expensive, programming for such random signals is complicated, and the signal output rate and maximum level cannot be satisfied at the same time, making it difficult to achieve the random waveform required for testing.
[0057] As for the aforementioned method (2), it can lead to difficulties in data analysis when the data volume is too large. For example, a digital isolator with a data transmission rate of 100Mbps requires a sampling frequency of at least 200Mbps. During the test, the input and output waveforms generate at least 400M bits of data per second. If the test lasts for 1 hour, 1.44T bits of data will be generated. Such a large amount of data makes subsequent analysis extremely difficult and hard to complete. At the same time, method (2) has excessively high requirements for equipment. The data acquisition card with a speed of around 100Mbps and the computer used for subsequent data analysis both place extremely high performance demands on the equipment, which will increase the cost of the test.
[0058] In addition, similar to method (1), method (2) is difficult to simulate random waveforms in real-world application scenarios.
[0059] Considering the drawbacks of the aforementioned methods (1) and (2), this application aims to provide a solution that can adapt to data transmission tests over extremely long periods of time. Compared with traditional error testing methods, it has a larger testing volume and longer testing time, and can more accurately locate error points, making the testing of digital isolators closer to their actual use scenarios, thereby obtaining accurate test results.
[0060] In a specific embodiment of this application, a method for testing the bit error rate of a digital isolator is provided, such as... Figure 2 As shown, this testing method includes the following steps:
[0061] Obtain the delay time of the digital isolator under test;
[0062] Generate an input signal, which includes a pseudo-random binary sequence;
[0063] The input signal is delayed based on the delay time to obtain the delayed input signal;
[0064] Input the input signal to the transmitter of the digital isolator under test, and obtain the output signal from the receiver of the digital isolator under test.
[0065] Logical operations are performed on the delayed input and output signals to obtain the result signal, wherein the logical operations are triggered periodically;
[0066] The high or low levels in the result signal are counted, and the bit error rate of the digital isolator under test is obtained based on the counting results.
[0067] In a typical embodiment, for the digital isolator under test, the delay time of the digital isolator is first measured using an external device such as an oscilloscope. After obtaining the delay time, the oscilloscope is connected to a Field Programmable Gate Array (FPGA), and the delay time is input into the FPGA chip. Each digital signal emitted from the FPGA must pass through this delay time before being output to the logic operation module for logical operations, such as an XOR operation, to keep the input / output signals as synchronized as possible.
[0068] The pseudo-random binary sequence (PRBS) used in the embodiments is generally implemented using a linear feedback shift register (LSFR). Assuming a 16-bit PRBS, the final signal state is as follows: Figure 3 As shown, the sequence starts with a 1-bit pulse, gradually shifting from bit 0 to bit 15. This is followed by a 2-bit pulse, gradually shifting from bits 0 and 1 to bits 14 and 15. This process continues until all pulse patterns are achieved.
[0069] In a typical embodiment, a Field-Programmable Gate Array (FPGA) is primarily used as the execution entity for the test method, performing most of the steps in the test method, such as... Figure 4As shown, a pseudo-random binary sequence is generated using an FPGA as the input signal. After the input signal enters the digital isolator under test (DUT), it is isolated by the DUT, and the output signal is obtained and output from the Dout1 terminal. By simultaneously feeding the input and output signals into a logic operation module for a logic operation such as XOR, bit error detection can be achieved. The detection result (i.e., the logic judgment result) is output to the FPGA. The FPGA accumulates a count based on the obtained bit error detection results and can also output the count result to a display module or store it simultaneously.
[0070] Regarding the delay processing step of the input signal in the aforementioned embodiments, it can be explained that, ideally, a correct signal transmission performed by the digital isolator under test should consist of identical logical sequences of the input and output signals. When the input signal (i.e., the pseudo-random binary sequence) and the output signal are XORed, the output should remain low. However, in actual digital isolators, the input signal arrives at the output after a delay following input to the input port. The input and output signals are not synchronized, making it impossible to directly use both signals simultaneously for error detection.
[0071] To address the aforementioned issues, this application embodiment delays the input signal before performing a logical operation (e.g., the aforementioned "XOR" logical operation) with the output signal. The delay time should be the same as the delay time of the digital isolator under test. The input signal delay can be directly implemented by the FPGA, specifically through an internal FPGA counter. The signal delay data can be obtained by testing the digital isolator under test using an oscilloscope.
[0072] In a typical embodiment, the delay time may need to be tested and experimented on repeatedly to obtain the most suitable result. Once the delay time is set, long-term testing can be performed. The bit error rate results of the long-term test will be displayed on the display module. In actual settings, it is also possible to choose to stop the system as soon as a bit error occurs; in other words, the test is paused when the comparison results of the delayed input signal and output signal are inconsistent. The state is preserved for subsequent analysis. After the test, the relevant quality issues of the product can be assessed by judging the number of bit errors. Of course, testing can continue even when bit errors occur, continuously recording and calculating information such as the bit error rate.
[0073] In the foregoing embodiments, logical operations (such as the aforementioned "XOR" logical operation) are performed periodically, rather than continuously. This avoids glitches in the logical operations caused by misalignment between the input and output signal clocks.
[0074] In an optional embodiment, an XOR gate logic circuit is used to perform a logical operation, that is, to perform an "XOR" logical operation, and correspondingly, the high level in the result signal is counted.
[0075] Alternatively, a NAND gate logic circuit can be used to perform a logical operation, i.e., to perform an "XOR" logical operation, and correspondingly, the low-level signals in the result signal are counted. In the following description of this application, the "XOR" logical operation will be used as an example to illustrate the logical operation.
[0076] In this embodiment, pseudo-random binary sequences are generated using internal FPGA code to simulate various digital signal scenarios.
[0077] When the FPGA and the digital isolator under test (DUT) interact, signal transmission losses during actual testing, such as those on the PCB, can affect the waveform of the transmitted signals. To address this issue, at least one of a digital buffer and a Schmitt trigger can be added in the embodiment to smooth the waveforms of the input and output signals. This digital buffer or Schmitt trigger also serves as a level shifter.
[0078] In an optional embodiment, the testing method further includes generating a clock signal. The clock signal controls the periodic triggering of logic operations. It should be understood that in digital circuits, when two signals with micro-level timing discrepancies (not fully synchronized) undergo continuous logic operations, very narrow, unaccounted pulses (glitch) are generated at the signal transition edges due to brief, non-stationary differences. The optional embodiment discretizes the continuous comparison behavior by introducing a clock signal for periodic triggering. In a preferred embodiment, the clock signal is set to appear synchronously during the stable periods (e.g., the middle of the cycle) of the operated signals (delayed input and output signals), thereby avoiding unstable edges of signal changes. This ensures that only genuine, stable signal logic differences are identified as errors, while glitches are effectively filtered out. This is one of the core guarantees for achieving high-precision, high-reliability error detection in this application.
[0079] Furthermore, by generating a clock signal, the testing method becomes insensitive to minute timing fluctuations caused by signal transmission loss and delay. Even if the input and output signals are not perfectly synchronized, as long as the clock is stable at the sampling point, a correct judgment can be made. This reduces the requirements of the testing method on hardware layout and routing.
[0080] During testing, the error rate status of the digital isolator can also be tested by introducing external interference conditions. Therefore, in optional embodiments, the test also includes applying interference to the digital isolator under test; the interference can be one or more of electromagnetic interference, preset temperature, preset humidity, and mechanical vibration. Depending on the interference conditions, the entire test can be performed simultaneously with the application of external interference, such as high temperature and humidity, mechanical vibration, electromagnetic interference, etc. Alternatively, the test can be performed after the external interference conditions are applied, such as high temperature aging, accelerated fatigue testing, etc. The resulting error rate status is also an important reference for evaluating the quality of digital isolator products.
[0081] In an optional embodiment, the same FPGA chip is used to perform the generation of input signals, delay processing, generation of clock signals, and counting of the operation result signals; the operation result signals, counting results, and bit error rate are transmitted to the storage module through the FPGA; and the counting results and / or bit error rate are transmitted to the display module through the FPGA.
[0082] In a typical embodiment, the test method is performed using an FPGA, which utilizes a total of seven signal functions of the FPGA:
[0083] (1) Generate a pseudo-random binary sequence as the input signal for the digital isolator;
[0084] (2) Perform signal delay processing on the pseudo-random binary input signal to make it as aligned as possible with the output signal of the digital isolator;
[0085] (3) Generate a clock synchronized with the input signal to control the triggering of the XOR gate;
[0086] (4) Receive the output signal of the XOR gate logic judgment (logic operation);
[0087] (5) Receive the signal delay time data of the digital isolator tested by an external oscilloscope;
[0088] (6) Store some information in the storage medium;
[0089] (7) Send the error information to the display module.
[0090] Optionally, logic operations can be performed using an FPGA, meaning the logic steps are implemented internally within the FPGA. This avoids the use of external devices, thus simplifying the circuit structure used in testing. However, this alternative approach also results in opaque logic judgments. For example, in a certain state, signal glitches / jitter may lead to misjudgments, and the tester cannot manually verify whether it is indeed a bit error, ultimately leading to inaccurate test results.
[0091] This application also provides a testing device for the bit error rate of a digital isolator, such as... Figure 4As shown, this test setup includes a field-programmable gate array (FPGA) and a logic operation module.
[0092] The FPGA is configured to generate an input signal, perform delay processing on the input signal, and count the operation result signal from the logic operation module. The bit error rate of the digital isolator under test is obtained based on the counting result. The input signal is used to input to the transmitting end of the digital isolator under test, and the input signal includes a pseudo-random binary sequence.
[0093] The logic operation module is configured to perform logic operations on the delayed input signal and the output signal from the receiver of the digital isolator under test, and output the operation result signal. The logic operation module is periodically triggered.
[0094] In an optional embodiment, the logic operation module is provided with an XOR gate logic circuit, and the FPGA is configured to count the high level in the operation result signal; or, the logic operation module is provided with an XNOR gate logic circuit, and the FPGA is configured to count the low level in the operation result signal.
[0095] In an optional embodiment, the FPGA is configured to pause the test if the computational results of the delayed input and output signals are abnormal, such as if a bit error occurs.
[0096] In an optional embodiment, the test apparatus further includes a buffer module, which is provided with at least one of a digital buffer and a Schmitt trigger for shaping the input signal and / or the output signal.
[0097] In an optional embodiment, the testing apparatus further includes an oscilloscope for testing the digital isolator under test to obtain the delay time; the FPGA is configured to delay the input signal based on the delay time.
[0098] In an optional embodiment, the FPGA is configured to generate a clock signal to control the periodic triggering of the logic operation module.
[0099] In an optional embodiment, the testing device further includes at least one of a display module, an input module, and a storage module, wherein the input module is used to input the delay time of the delay processing; the display module is used to display the counting result and / or the bit error rate; and the storage module is used to store the calculation result signal, the counting result, and the bit error rate.
[0100] In an alternative embodiment, the logic operation module is integrated inside the FPGA.
[0101] In an optional embodiment, the FPGA's operating speed is at least twice the transmission speed of the digital isolator under test. This is because the maximum operating speed of the FPGA depends on the transmission speed of the digital isolator under test. For example, given that the transmission speed of existing digital isolators generally reaches 150 Mbps, the maximum operating speed of the FPGA used in this embodiment should be greater than 300 Mbps (150 MHz). In addition, some digital isolators have transmission speeds of 200 Mbps or even 600 Mbps, which requires FPGA chips with higher operating speeds.
[0102] Figure 5 This paper illustrates a test example of a method for testing the bit error rate of a digital isolator provided in an embodiment of this application. In the figure, the input signal generated by the FPGA, i.e., the pseudo-random signal, is first delayed by the FPGA to align as closely as possible with the output signal, and then an XOR operation is performed with the output signal. Figure 5 In this design, the output signal is not strictly aligned with the delayed input signal; instead, a small clock offset is retained to represent a realistic signal scenario. The trigger point for each XOR logic operation should be in the middle of the input signal cycle after the FPGA delay. Regardless of whether the input signal is high or low, it will undergo XOR logic processing.
[0103] Specifically, in Figure 5 In the XOR gate, at clock node ①, both input signals are high, so the output is low; at clock nodes ② and ③, both input signals are low, so the output is low; at clock node ④, one input signal is high and the other is low, so the output is high; at clock node ⑤, the output signal returns to low. The high level generated between clock nodes ④ and ⑤ is recognized by the FPGA and used for error counting. This pulse can also be used to pause all test setups, preserving the fault scene for testing personnel to troubleshoot.
[0104] In summary, the testing method and corresponding testing device for the bit error rate of digital isolators provided in this application embodiment generate pseudo-random binary sequences (PRBS) as input signals and automatically count the comparison results, supporting data transmission tests over a relatively long period. This solves the problems of traditional methods (such as oscilloscope testing) having small test quantities and only being able to detect short waveforms, thus more effectively capturing errors of digital isolators in probabilistic bit error scenarios.
[0105] By delaying the input signal according to the delay time, aligning the delayed input signal with the output signal, and then periodically triggering logical operations (such as XOR logic operations), the location of the bit error can be accurately identified. This overcomes the drawback of traditional methods that make it difficult to locate the bit error point due to signal misalignment.
[0106] By periodically triggering logical operations (avoiding glitches) and signal alignment, the risk of misjudgment is reduced, ensuring the accuracy of test results. Furthermore, the bit error rate, obtained based on counting results, provides a quantitative quality assessment metric, facilitating product reliability analysis.
[0107] The above description is only a partial embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for testing the bit error rate of a digital isolator, characterized in that, include: Obtain the delay time of the digital isolator under test; Generate an input signal, the input signal comprising a pseudo-random binary sequence; The input signal is delayed based on the delay time to obtain the delayed input signal; The input signal is input to the transmitting end of the digital isolator under test, and the output signal from the receiving end of the digital isolator under test is obtained. Logical operations are performed on the delayed input signal and the output signal to obtain the operation result signal, wherein the logical operations are triggered periodically; The high or low levels in the result signal of the operation are counted, and the bit error rate of the digital isolator under test is obtained based on the counting results.
2. The test method according to claim 1, characterized in that, The logic operation is performed using an XOR gate logic circuit, and the high level in the operation result signal is counted. or, The logic operation is performed using an NAND gate logic circuit, and the low levels in the result signal of the operation are counted.
3. The test method according to claim 1, characterized in that, The delay time is obtained by testing the digital isolator under test using an oscilloscope.
4. The test method according to claim 1, characterized in that, Also includes: The input signal and / or the output signal are shaped using a digital buffer or a Schmitt trigger.
5. The test method according to any one of claims 1 to 4, characterized in that, Also includes: Generate clock signal; The clock signal controls the periodic triggering of the logical operations.
6. The test method according to claim 5, characterized in that, Using the same field-programmable gate array, the generation of the input signal, the delay processing, the generation of the clock signal, and the counting of the operation result signal are executed. The calculation result signal, the counting result, and the bit error rate are transmitted to the storage module through the field-programmable gate array; The counting result and / or the bit error rate are transmitted to the display module through the field-programmable gate array; The logical operation is performed by the field-programmable gate array.
7. The test method according to any one of claims 1 to 4, characterized in that, It also includes applying interference to the digital isolator under test; The interference is one or more of the following: electromagnetic interference, preset temperature, preset humidity, and mechanical vibration.
8. A testing device for the bit error rate of a digital isolator, characterized in that, Including field-programmable gate arrays and logic operation modules; The field-programmable gate array is configured to: generate an input signal, delay the input signal, and count the operation result signal from the logic operation module, and obtain the bit error rate of the digital isolator under test based on the counting result. The input signal is used to input to the transmitting end of the digital isolator under test, and the input signal includes a pseudo-random binary sequence. The logic operation module is configured to perform logic operations on the delayed input signal and the output signal from the receiver of the digital isolator under test, and output the operation result signal, wherein the logic operation module is periodically triggered.
9. The testing apparatus according to claim 8, characterized in that, The logic operation module is equipped with an XOR gate logic circuit, and the field-programmable gate array is configured to count the high level in the operation result signal. or, The logic operation module is equipped with an XNOR gate logic circuit, and the field-programmable gate array is configured to count the low levels in the operation result signal.
10. The testing apparatus according to claim 8, characterized in that, It also includes at least one of a buffer module and an oscilloscope, wherein: The buffer module is equipped with a digital buffer or a Schmitt trigger for shaping the input signal and / or the output signal. The oscilloscope is used to test the digital isolator under test to obtain the delay time; the field-programmable gate array is configured to delay the input signal according to the delay time.
11. The testing apparatus according to any one of claims 8 to 10, characterized in that, The field-programmable gate array is configured as follows: A clock signal is generated, which is used to control the logic operation module to be triggered periodically.
12. The testing apparatus according to any one of claims 8 to 10, characterized in that, It also includes at least one of a display module, an input module, and a storage module, wherein: The input module is used to input the delay time for the delay processing; The display module is used to display the counting results and / or bit error rate; The storage module is used to store the calculation result signal, the counting result, and the bit error rate.
13. The testing apparatus according to any one of claims 8 to 10, characterized in that, The logic operation module is integrated inside the field-programmable gate array.
14. The testing apparatus according to any one of claims 8 to 10, characterized in that, The operating speed of the field-programmable gate array is at least twice the transmission speed of the digital isolator under test.