Isolator

Abstract

Embodiments provide an isolator capable of achieving miniaturization. According to one embodiment, the isolator includes a substrate portion, a first chip, and a second chip. The substrate portion has an insulating layer and a pair of coils. The pair of coils face each other in the thickness direction with an insulating layer therebetween. The first chip is disposed so as to face one surface of the substrate portion. The first chip is connected to one of the pair of coils. The second chip is disposed so as to face the other surface of the substrate portion. The second chip is connected to the other of the pair of coils.

Description

[0001] Reference to relevant applications

[0002] This application claims priority to Japanese Patent Application No. 2024-160192 (filed on September 17, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to isolators. Background Technology

[0004] An isolator is known to transmit a signal from a transmitting circuit to a receiving circuit while isolating the transmitting circuit from the receiving circuit. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide an isolator that can be miniaturized.

[0006] The isolator in this embodiment includes a substrate, a first chip, and a second chip. The substrate has an insulating layer and a pair of coils. The pair of coils are positioned opposite each other in the thickness direction, separated by the insulating layer. The first chip is disposed opposite to one side of the substrate. The first chip is connected to one of the pair of coils. The second chip is disposed opposite to the other side of the substrate. The second chip is connected to the other of the pair of coils. Attached Figure Description

[0007] Figure 1 This is a top view of the isolator in the implementation method.

[0008] Figure 2 This is a cross-sectional view of the isolator package of the isolator in the implementation method.

[0009] Figure 3 This is a perspective view of the substrate portion of the isolator according to the embodiment.

[0010] Figure 4 This is a perspective view of the substrate portion of the isolator according to the embodiment.

[0011] Figure 5 This is a cross-sectional view of the substrate portion of the isolator according to the embodiment.

[0012] Figure 6 This is a cross-sectional view of the base plate portion of a modified isolator.

[0013] Explanation of reference numerals in the attached figures

[0014] 10… isolator; 11… first terminal portion; 11… terminal portion; 12… second terminal portion; 21… first semiconductor chip (first chip); 22… second semiconductor chip (second chip); 40, 140… substrate portion; 41, 141… substrate; 41a, 41c, 41d, 141a, 141c, 141d, 142a, 142c… insulating layer; 43… coil; 45… first wiring portion; 46… second wiring portion; 141… first substrate; 142… second substrate; 149… adhesive layer (insulating layer); D… thickness. DETAILED DESCRIPTION

[0015] Hereinafter, the isolator of the embodiment will be described with reference to the drawings.

[0016] (First Embodiment)

[0017] Hereinafter, the structure of the isolator 10 of the first embodiment will be described. Figure 1 is a plan view showing an example of the plan layout of the isolator 10 of the embodiment. Figure 2 is a sectional view of the isolator package 1 of the embodiment.

[0018] As shown in Figure 2 , the isolator package 1 has the isolator 10 and a package member 50. The package member 50 is composed of, for example, an insulating resin material. The package member 50 encloses the isolator 10 to protect it from the outside.

[0019] The isolator 10 is a so-called digital isolator. The isolator 10 has a plurality of first terminal portions 11, a plurality of second terminal portions 12, a first semiconductor chip (first chip) 21, a second semiconductor chip (second chip) 22, and a substrate portion 40.

[0020] The substrate portion 40 is plate-shaped. The substrate portion 40 is a module that functions as a digital isolator. A transformer is mounted on the substrate portion 40. The substrate portion 40 is configured to transmit a signal using the transformer in a state in which a transmitting-side circuit (primary circuit) and a receiving-side circuit (secondary circuit) are insulated. Details of the structure of the substrate portion 40 will be described later.

[0021] Hereinafter, a plane parallel to the surface of the substrate portion 40 will be referred to as an XY plane. Directions that intersect each other perpendicularly in the XY plane will be referred to as an X-axis direction and a Y-axis direction. In particular, in the isolator 10, a direction in which the terminal portions 11, 12 protrude will be referred to as the X-axis direction. Furthermore, a direction that intersects the XY plane will be referred to as a Z-axis direction. The Z-axis direction coincides with the thickness direction of the substrate portion 40. In addition, the Z-axis direction also coincides with the thickness directions of the first semiconductor chip 21, the second semiconductor chip 22, and the substrate portion 40.

[0022] In the following description, the side on which the second semiconductor chip 22 is disposed relative to the substrate 40 is referred to as the upper side (+Z), and the opposite side, i.e., the side on which the first semiconductor chip 21 is disposed relative to the substrate 40, is referred to as the lower side (-Z). Furthermore, the orientation of the isolator package 1 during use is not limited to the above-described vertical direction.

[0023] The substrate portion 40 has an upper surface 40b facing upward (+Z) and a lower surface 40a facing downward (-Z). The second semiconductor chip 22 is fixed to the upper surface 40b of the substrate portion 40 via an insulating adhesive 32. The first semiconductor chip 21 is fixed to the lower surface 40a of the substrate portion 40 via an insulating adhesive 31. During the manufacturing process, before the isolator 10 is fixed by encapsulating it with the packaging component 50, the insulating adhesives 31 and 32 temporarily fix the first semiconductor chip 21 and the second semiconductor chip 22 to the substrate portion 40.

[0024] The substrate portion 40 is electrically connected to the first semiconductor chip 21 and the second semiconductor chip 22 via a bump portion BP. The substrate portion 40 is connected to the first semiconductor chip 21 and the second semiconductor chip 22, for example, by flip-chip bonding. The bump portion BP is formed, for example, by soldering.

[0025] like Figure 1 As shown, when viewed from the thickness direction (Z-axis direction) of the substrate portion 40, the first semiconductor chip 21 and the second semiconductor chip 22 overlap each other. The substrate portion 40 is sandwiched between the first semiconductor chip 21 and the second semiconductor chip 22.

[0026] like Figure 2 As shown, a plurality of first terminal portions 11 and a plurality of second terminal portions 12 are connected to the lower surface 40a of the substrate portion 40 via a solder portion SD. Thus, the substrate portion 40 is electrically connected to the plurality of first terminal portions 11 and the plurality of second terminal portions 12.

[0027] A circuit 21a is formed on the first semiconductor chip 21. The circuit 21a includes a signal transceiver circuit and a modulation and demodulation circuit. The circuit 21a is electrically connected to the substrate 40 via a bump portion BP connected to the upper surface of the first semiconductor chip 21.

[0028] A circuit 22a is formed on the second semiconductor chip 22. The circuit 22a includes a signal transceiver circuit and a modulation and demodulation circuit. The circuit 22a is electrically connected to the substrate 40 via a bump portion BP connected to the lower surface of the second semiconductor chip 22.

[0029] The plurality of first terminal portions 11 and the plurality of second terminal portions 12 are each a plate-shaped metal member extending along the XY plane. The plurality of first terminal portions 11 and the plurality of second terminal portions 12 are each connected to the substrate portion 40 at the upper surface. The plurality of first terminal portions 11 and the plurality of second terminal portions 12 are each formed of a single plate material. The plurality of first terminal portions 11 and the plurality of second terminal portions 12 are each divided from each other by cutting off a portion that is connected to the substrate portion 40 at the middle.

[0030] As shown in Figure 1 , the solder portions SD for connecting the first terminal portions 11 to the substrate portion 40 and the solder portions SD for connecting the second terminal portions 12 to the substrate portion 40 are arranged at end portions on opposite sides in the X-axis direction of the substrate portion 40. From the thickness direction (Z-axis direction) of the substrate portion 40, the solder portions SD for connecting the first terminal portions 11 to the substrate portion 40 and the solder portions SD for connecting the second terminal portions 12 to the substrate portion 40 are arranged at different positions from the first semiconductor chip 21 and the second semiconductor chip 22.

[0031] Figure 3 is a perspective view of the substrate portion 40 of the present embodiment as viewed obliquely from above. Figure 4 is a perspective view of the substrate portion 40 of the present embodiment as viewed obliquely from below. Figure 5 is a cross-sectional view of the substrate portion 40. Further, in Figure 3 and Figure 4 , the insulating layers covering the first coil 43 and the second coil 44 are illustrated in order to easily understand the structure of the first coil 43 and the second coil 44. In addition, in Figure 5 , the illustration of the insulating adhesives 31, 32 that fix the substrate portion 40 to the first semiconductor chip 21 and the second semiconductor chip 22 is omitted.

[0032] As shown in Figure 3 and Figure 4 , the substrate portion 40 of the present embodiment is formed of a single substrate 41. The substrate 41 of the present embodiment is a flexible substrate. However, the substrate 41 can also be a rigid substrate. In addition, the substrate 41 can also be a rigid-flexible combined substrate. As the shape of the substrate 41, for example, a rectangular shape can be applied, but is not limited to a rectangular shape, and any shape can be applied.

[0033] As shown in Figure 5 , the first coil 43, the second coil 44, the first wiring portion 45, the second wiring portion 46, and the plurality of pads P1, P2, P3, P4, P5, P6, P7, P8 are provided inside the substrate 41. The first coil 43, the second coil 44, the first wiring portion 45, the second wiring portion 46, the pads P1, P2, P3, P4, P5, P6, P7, P8 are formed of, for example, a copper foil or a copper plating, and have electrical conductivity.

[0034] The substrate 41 is formed by stacking multiple insulating layers 41a, 41b, 41c, 41d, 41e, 41f, and 41g. The multiple insulating layers 41a, 41b, 41c, 41d, 41e, 41f, and 41g are arranged from bottom to top in the order of first insulating layer 41a, second insulating layer 41b, third insulating layer 41c, fourth insulating layer 41d, fifth insulating layer 41e, sixth insulating layer 41f, and seventh insulating layer 41g.

[0035] Of the multiple pads P1, P2, P3, P4, P5, P6, P7, and P8, the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, and the fifth pad P5 (hereinafter referred to as the first to fifth pads) are disposed inside the second insulating layer 41b, and the sixth pad P6, the seventh pad P7, and the eighth pad P8 (hereinafter referred to as the sixth to eighth pads P6, P7, and P8) are disposed inside the sixth insulating layer 41f.

[0036] In the first insulating layer 41a, which is lower than the second insulating layer 41b, the portions overlapping with the first to fifth pads P1, P2, P3, P4, and P5 when viewed along the thickness direction (Z-axis direction) are removed. Thus, the first to fifth pads P1, P2, P3, P4, and P5 are exposed on the underside of the substrate portion 40. The first pad P1 is electrically connected to the first terminal portion 11 via the solder portion SD. Similarly, the fifth pad P5 is electrically connected to the second terminal portion 12 via the solder portion SD. The second pad P2, the third pad P3, and the fourth pad P4 are electrically connected to the first semiconductor chip 21 via the bump portion BP, respectively.

[0037] like Figure 4 As shown, the third pad P3 is electrically connected to the central end of the first coil 43. The fourth pad P4 is electrically connected to the outer peripheral end of the first coil 43. Viewed from the thickness direction (Z-axis direction), the third pad P3 and the fourth pad P4 have, for example, a rounded rectangular shape. However, the shapes of the third pad P3 and the fourth pad P4 are not limited to this.

[0038] like Figure 5 As shown, in the seventh insulating layer 41g, which is above the sixth insulating layer 41f, the portions overlapping with the sixth to eighth pads P6, P7, and P8 when viewed along the thickness direction (Z-axis direction) are removed. Therefore, the sixth to eighth pads P6, P7, and P8 are exposed on the upper side of the substrate portion 40. The sixth to eighth pads P6, P7, and P8 are electrically connected to the second semiconductor chip 22 via bump portions BP.

[0039] like Figure 3As shown, the sixth pad P6 is electrically connected to the central end of the second coil 44. The seventh pad P7 is electrically connected to the outer peripheral end of the second coil 44. The sixth pad P6 and the seventh pad P7 can have, for example, different shapes and sizes from the third pad P3 and the fourth pad P4, as viewed in the thickness direction (Z-axis direction). More specifically, in the case where the third pad P3 and the fourth pad P4 each have a rectangular shape, the sixth pad P6 and the seventh pad P7 can each have, for example, a circular shape, and can each be larger than the third pad P3 and the fourth pad P4, respectively.

[0040] The third pad P3 and the sixth pad P6 are disposed at positions overlapping each other, as viewed in the thickness direction (Z-axis direction). The fourth pad P4 and the seventh pad P7 are disposed at positions overlapping each other, as viewed in the thickness direction (Z-axis direction).

[0041] Further, as shown in FIG. 6, a dummy pad Pdm can also be provided in the substrate portion 40. The dummy pad Pdm is provided, for example, inside the sixth insulating layer 41f, like the sixth to eighth pads P6, P7, P8. Alternatively, the dummy pad Pdm can be provided in the same layer as the first to fifth pads P1, P2, P3, P4, P5. Figure 3 The dummy pad Pdm is disposed, for example, at a position symmetrical to the seventh pad P7 with the sixth pad P6 as a center, as viewed in the thickness direction (Z-axis direction) of the substrate portion 40. The position and size of the dummy pad Pdm can be determined, for example, based on the center of gravity of the substrate portion 40, or the like, in a manner that makes it easy to horizontally hold the substrate portion 40 with respect to the XY plane when the substrate portion 40 is mounted. Alternatively, the substrate 41 can include a plurality of dummy pads Pdm.

[0042] As shown in FIG. 6, the first coil 43 is provided inside the third insulating layer 41c. In the present embodiment, the upper surface of the first coil 43 is located, for example, at a position lower than the upper surface of the third insulating layer 41c. However, the upper surface of the first coil 43 can be flush with the upper surface of the third insulating layer 41c. The lower portion of the first coil 43 can be subjected to plating treatment. Alternatively, the first coil 43 can be composed of, for example, two or more copper foils.

[0043] Figure 5 As shown in FIG. 6, the first coil 43 is provided inside the third insulating layer 41c. In the present embodiment, the upper surface of the first coil 43 is located, for example, at a position lower than the upper surface of the third insulating layer 41c. However, the upper surface of the first coil 43 can be flush with the upper surface of the third insulating layer 41c. The lower portion of the first coil 43 can be subjected to plating treatment. Alternatively, the first coil 43 can be composed of, for example, two or more copper foils.

[0044] As shown in FIG. 6, the first coil 43 is provided inside the third insulating layer 41c. In the present embodiment, the upper surface of the first coil 43 is located, for example, at a position lower than the upper surface of the third insulating layer 41c. However, the upper surface of the first coil 43 can be flush with the upper surface of the third insulating layer 41c. The lower portion of the first coil 43 can be subjected to plating treatment. Alternatively, the first coil 43 can be composed of, for example, two or more copper foils. Figure 4 As shown in FIG. 6, the first coil 43 has a shape wound in a spiral shape, and has a prescribed inductance, as viewed in the thickness direction (Z-axis direction) of the substrate portion 40. The first coil 43 is also referred to as a primary coil. The first coil 43 becomes a path of an electric signal between the bump portion BP connected to the third pad P3 and the bump portion BP connected to the fourth pad P4.

[0045] As shown in FIG. 6, the first coil 43 has a shape wound in a spiral shape, and has a prescribed inductance, as viewed in the thickness direction (Z-axis direction) of the substrate portion 40. The first coil 43 is also referred to as a primary coil. The first coil 43 becomes a path of an electric signal between the bump portion BP connected to the third pad P3 and the bump portion BP connected to the fourth pad P4. Figure 5 ​As shown, the second coil 44 is provided in the fifth insulating layer 41e. In the present embodiment, the lower surface of the second coil 44 is located, for example, at a position higher than the lower surface of the fifth insulating layer 41e. However, the lower surface of the second coil 44 can be flush with the lower surface of the fifth insulating layer 41e. The upper portion of the second coil 44 can also be subjected to plating treatment. In addition, the second coil 44 can also be composed of two or more copper foils, for example.

[0046] As shown, when the substrate portion 40 is viewed in the thickness direction (Z-axis direction), the second coil 44 has a shape wound in a spiral shape, and has a prescribed inductance. The second coil 44 is also referred to as a secondary coil. The second coil 44 becomes a path of an electric signal between the bump portion BP connected to the sixth pad P6 and the bump portion BP connected to the seventh pad P7. Figure 3

[0047] By the above structure, in the substrate portion 40 of the present embodiment, the insulating layer 41d and the pair of coils 43, 44 opposed in the thickness direction (Z-axis direction) with the insulating layer 41d interposed therebetween are provided. That is, the first coil 43 and the second coil 44 are arranged so as to be opposed to each other in the thickness direction (Z-axis direction) with separation therebetween.

[0048] In the present embodiment, a portion of the third insulating layer 41c, the fourth insulating layer 41d, and a portion of the fifth insulating layer 41e are interposed between the first coil 43 and the second coil 44.

[0049] The thickness D of the insulating layers 41c, 41d, 41e arranged between the first coil 43 and the second coil 44 is preferably 25 μm or more. As a material constituting the insulating layers 41c, 41d, 41e arranged between the first coil 43 and the second coil 44, a material having a withstand voltage of 100 kV / mm or more, such as polyimide, is generally used. In this case, therefore, by setting the thickness D to 25 μm or more, the withstand voltage between the first coil 43 and the second coil 44 can be made 2.5 kV or more. In addition, the thickness D of the insulating layers 41c, 41d, 41e arranged between the first coil 43 and the second coil 44 is preferably 100 μm or less. By setting the thickness D to 100 μm or less, the first coil 43 and the second coil 44 can be arranged in close proximity, and the transmission efficiency of an electric signal between the first coil 43 and the second coil 44 can be improved. For the same reason, the thickness D is more preferably 50 μm or less.

[0050] ​Further, in the present embodiment, the insulating layer disposed between the pair of coils 43, 44 is composed of a plurality of layers (insulating layers 41c, 41d, 41e), but the insulating layer disposed between the pair of coils 43, 44 can also be a single layer. For example, in a case where the upper surface of the first coil 43 is flush with the upper surface of the third insulating layer 41c and the lower surface of the second coil 44 is flush with the lower surface of the fifth insulating layer 41e, the insulating layer disposed between the pair of coils 43, 44 is a single layer (fourth insulating layer 41d). In this case, the thickness D of the insulating layer disposed between the pair of coils 43, 44 coincides with the thickness of the fourth insulating layer 41d.

[0051] As shown in FIG. 6, the first wiring portion 45 is disposed in the third insulating layer 41c. In the present embodiment, the first wiring portion 45 is disposed in the same layer as the first coil 43. However, the first wiring portion 45 can also be disposed in a different layer from the first coil 43. Figure 5

[0052] One end portion of the first wiring portion 45 is connected to the first pad P1, and the other end portion of the first wiring portion 45 is connected to the second pad P2. As described above, the first pad P1 is connected to the first terminal portion 11 via the solder portion SD. In addition, the second pad P2 is connected to the first semiconductor chip 21 via the bump portion BP. Thus, the first wiring portion 45 electrically connects the first terminal portion 11 and the first semiconductor chip 21 in a bridging manner.

[0053] The second wiring portion 46 has a first portion 46a, a second portion 46b, and a third portion 46c. The first portion 46a is disposed in the fifth insulating layer 41e. In the present embodiment, the first portion 46a is disposed in the same layer as the second coil 44. However, the first portion 46a can also be disposed in a different layer from the second coil 44. One end portion of the first portion 46a is connected to the eighth pad P8. In addition, the other end portion of the first portion 46a is connected to the second portion 46b. The second portion 46b penetrates the third insulating layer 41c, the fourth insulating layer 41d, and the fifth insulating layer 41e.

[0054] The second portion 46b is formed, for example, by plating the inner side surface of the through hole with copper. The upper end portion of the second portion 46b is connected to the first portion 46a. The lower end portion of the second portion 46b is connected to the third portion 46c.

[0055] The third portion 46c is disposed in the third insulating layer 41c. In the present embodiment, the third portion 46c is disposed in the same layer as the first coil 43 and the first wiring portion 45. However, the third portion 46c can also be disposed in a different layer from the first coil 43 and the first wiring portion 45. One end portion of the third portion 46c is connected to the second portion 46b. In addition, the other end portion of the third portion 46c is connected to the fifth pad P5. ​

[0056] Therefore, one end of the second wiring portion 46 is connected to the eighth pad P8, and the other end of the second wiring portion 46 is connected to the fifth pad P5. As described above, the eighth pad P8 is connected to the second semiconductor chip 22 via the bump portion BP. In addition, the fifth pad P5 is connected to the second terminal portion 12 via the solder portion SD. Therefore, the second wiring portion 46 electrically connects the second semiconductor chip 22 and the second terminal portion 12 in a bridging manner.

[0057] In the substrate portion 40, the first coil 43, the first wiring portion 45, and the third portion 46c of the second wiring portion 46 are formed on the same layer. Also, in the substrate portion 40, the second coil 44 and the first portion 46a of the second wiring portion 46 are disposed on the same layer. According to the present embodiment, the conductive metal patterns having mutually different functions are disposed on the same layer. Thereby, compared to a case where the conductive metal patterns having different functions are disposed on mutually different layers, it is possible to realize miniaturization of the thickness dimension of the substrate portion 40. In addition, according to the present embodiment, it is possible to reduce the number of layers of the substrate 41 constituting the substrate portion 40 and to manufacture the substrate portion 40 inexpensively.

[0058] Further, in the substrate 41, it is also possible to dispose the conductive metal patterns having different functions on mutually different layers. In this case, when the substrate portion 40 is observed from the thickness direction (Z-axis direction), it is easy to miniaturize the size of the isolator 10 observed from the thickness direction by partially overlapping the wiring portion with the coil, or the like.

[0059] Next, the path of the electric signal to the isolator 10 will be described. The electric signal input from the first terminal portion 11 is input to the first semiconductor chip 21 via the solder portion SD, the first pad P1, the first wiring portion 45 of the substrate portion 40, the second pad P2, and the bump portion BP. This electric signal is input to the first coil 43 of the substrate portion 40 from the circuit portion of the first semiconductor chip 21 via the bump portion BP, the pads P3, P4.

[0060] The first coil 43 converts the input electric signal into magnetic energy. The second coil 44 receives the magnetic energy converted by the first coil 43 and converts it again into electric energy. The isolator 10 insulates the first semiconductor chip 21 connected to the first coil 43 and the second semiconductor chip 22 connected to the second coil 44 by passing through conversion into magnetic energy between the first coil 43 and the second coil 44.

[0061] The electric signal flowing through the second coil 44 is input to the second semiconductor chip 22 via the pads P6, P7, and the bump portion BP. This electric signal flows to the second terminal portion 12 from the circuit portion of the second semiconductor chip 22 via the solder portion SD, the second wiring portion 46 of the substrate portion 40, the fifth pad P5, and the solder portion SD.

[0062] Thus, in the isolator 10 of the present embodiment, an electric signal input from the first terminal portion 11 reaches the first semiconductor chip 21 via the substrate portion 40. In addition, an electric signal of the circuit portion of the first semiconductor chip 21 flows to the circuit portion of the second semiconductor chip 22 via the pair of coils 43, 44 of the substrate portion 40. Further, an electric signal flowing through the circuit portion of the second semiconductor chip 22 is output from the second terminal portion 12 via the substrate portion 40.

[0063] The isolator 10 of the present embodiment has the substrate portion 40, the first semiconductor chip 21, and the second semiconductor chip 22. The substrate portion 40 has the insulating layers 41c, 41d, 41e and the pair of coils 43, 44 which oppose each other in the thickness direction across the insulating layers 41c, 41d, 41e. The first semiconductor chip 21 is disposed in opposition to one face (lower face 40a) of the substrate portion 40. The first semiconductor chip 21 is connected to one of the pair of coils 43, 44 (first coil 43). The second semiconductor chip 22 is disposed in opposition to the other face (upper face 40b) of the substrate portion 40. The second semiconductor chip 22 is connected to the other of the pair of coils 43, 44 (second coil 44).

[0064] According to the present embodiment, the first semiconductor chip 21 and the second semiconductor chip 22 are stacked in the up-down direction on the substrate portion 40 having the pair of coils 43, 44 and functioning as an isolation module. Thus, when the isolator 10 is viewed from the thickness direction (Z-axis direction), the substrate portion 40, the first semiconductor chip 21, and the second semiconductor chip 22 can be disposed overlapping each other. As a result, the size of the isolator 10 viewed from the thickness direction (Z-axis direction) can be downsized. In other words, the size of the isolator 10 in the X-axis direction or the Y-axis direction can be downsized.

[0065] In addition, according to the present embodiment, the isolation module composed of the pair of coils 43, 44 and the insulating layers 41c, 41d, 41e located therebetween is formed inside the substrate portion 40. Thus, compared to the case where the isolation module is formed inside the semiconductor chip, the thickness D of the insulating layers 41c, 41d, 41e can be easily adjusted, and the insulation performance of the isolation module can be easily improved. Moreover, by forming the isolation module inside the substrate portion 40, the isolator 10 can be manufactured inexpensively.

[0066] Further, according to the present embodiment, the first semiconductor chip 21 and the second semiconductor chip 22 are stacked on the substrate portion 40 in the thickness direction (Z-axis direction). Therefore, the first semiconductor chip 21 and the second semiconductor chip 22 can be electrically connected to the substrate portion 40 by flip-chip bonding. According to the present embodiment, the connection process using wire bonding can be omitted from the manufacturing process of the isolator 10, and the isolator 10 can be manufactured inexpensively. In addition to this, the connection by flip-chip bonding has higher reliability than the connection by wire bonding. According to the present embodiment, the isolator 10 having high reliability can be provided.

[0067] The isolator 10 of the present embodiment has the first terminal portion 11. The first terminal portion 11 is connected to the substrate portion 40. The substrate portion 40 has a first wiring portion 45. The first wiring portion 45 electrically connects the first terminal portion 11 and the first semiconductor chip 21.

[0068] According to this structure, the first terminal portion 11 and the first semiconductor chip 21 can be connected via the first wiring portion 45 of the substrate portion 40, rather than being directly connected. Therefore, the connection between the first semiconductor chip 21 and the first terminal portion 11 by wire bonding is not required, and the isolator 10 having high reliability and being inexpensive can be provided.

[0069] The isolator 10 of the present embodiment has the second terminal portion 12. The second terminal portion 12 is connected to the substrate portion 40. The substrate portion 40 has a second wiring portion 46. The second wiring portion 46 electrically connects the second terminal portion 12 and the second semiconductor chip 22. The first terminal portion 11 and the second terminal portion 12 are each disposed opposite to one face (lower face 40a) of the substrate portion 40.

[0070] According to this structure, the second terminal portion 12 and the second semiconductor chip 22 can be connected via the second wiring portion 46 of the substrate portion 40, rather than being directly connected. Therefore, the connection between the second semiconductor chip 22 and the second terminal portion 12 by wire bonding is not required, and the isolator 10 having high reliability and being inexpensive can be provided. Further, according to the present embodiment, the first terminal portion 11 and the second terminal portion 12 are disposed on the same face side of the substrate portion 40. Therefore, the first terminal portion 11 and the second terminal portion 12 can be connected to the substrate portion 40 at the same time from the same direction, and the manufacturing process of the isolator 10 can be easily simplified.

[0071] In the isolator 10 of the present embodiment, the thickness D of the insulating layers 41c, 41d, 41e disposed between the pair of coils 43, 44 is 25 μm or more. According to this structure, the isolator 10 having high reliability in which the withstand voltage between the coils 43, 44 is sufficiently ensured can be provided.

[0072] In the isolator 10 of the present embodiment, at least a portion of the substrate portion 40 is preferably a flexible substrate. In the flexible substrate, it is easy to make the thickness D of the insulating layers 41c, 41d, 41e between the coils 43, 44 thin. More specifically, it is easy to make the thickness D of the insulating layers 41c, 41d, 41e a thickness of 25 μm or more and 50 μm or less. Therefore, by making the region in which the pair of coils 43, 44 is provided in the substrate portion 40 of a flexible substrate, it is possible to make the insulating layers 41c, 41d, 41e between the pair of coils 43, 44 thin. As a result, it is possible to arrange the pair of coils 43, 44 close to each other, and it is possible to improve the transmission efficiency of the isolator 10.

[0073] In the isolator 10 of the present embodiment, at least a portion of the substrate portion 40 is preferably a rigid substrate. The rigid substrate can be manufactured at a low cost compared to the flexible substrate. Therefore, by making at least a portion of the substrate portion 40 a rigid substrate, it is possible to manufacture at a low cost compared to the case where the entire substrate portion is manufactured by a flexible substrate.

[0074] In the isolator 10 of the present embodiment, the substrate portion is composed of a single substrate 41 in which one of the pair of coils 43, 44 and the other are formed in mutually different layers.

[0075] According to this structure, compared to the case where the substrate portion is formed by bonding a substrate including the first coil and a substrate including the second coil (a modification described later), it is possible to suppress the complication of the manufacturing process. More specifically, in the case where the substrate portion is formed by bonding a substrate including the first coil and a substrate including the second coil, sometimes the characteristics of the isolator module can be deteriorated due to misalignment of the first coil and the second coil in the bonding process. Therefore, in order to suppress misalignment of the first coil and the second coil, the manufacturing process can be complicated. According to the present embodiment, the first coil 43 and the second coil 44 are both provided in the same substrate 41, so the coils 43, 44 are difficult to misalign with each other in a plane orthogonal to the thickness direction, it is possible to suppress the deterioration of the characteristics, and it is possible to suppress the complication of the manufacturing process.

[0076] (Modification)

[0077] Next, based on the above description, the substrate portion 140 of the modification that can be employed in the present embodiment will be described. Figure 6 The substrate portion 140 of the modification that can be employed in the present embodiment will be described. The substrate portion 140 of the present modification is mainly different from the above-described embodiment in that a plurality of substrates 141, 142 are bonded in the thickness direction to form. In addition, for the constituent elements of the same form as the above-described embodiment, the same reference numerals are attached, and the description thereof is omitted.

[0078] As with the substrate portion 40 of the above-described embodiment, the substrate portion 140 of the present modification functions as an isolation module arranged between the first semiconductor chip 21 and the second semiconductor chip 22 in the isolator 10. Further, in the present modification, the illustration of the plurality of pads provided to the substrate portion 140 is omitted. Figure 6

[0079] The substrate portion 40 of the present modification has an adhesive layer (insulating layer) 149, a first substrate 141, and a second substrate 142. In the present modification, both the first substrate 141 and the second substrate 142 are flexible substrates. However, either one or both of the first substrate 141 and the second substrate 142 can be rigid substrates, and can also be a rigid-flexible combined substrate.

[0080] The first coil 43 is provided inside the first substrate 141. The outer shape of the first substrate 141 is formed by laminating a plurality of insulating layers 141a, 141b, 141c, 141d. The first coil 43 is buried inside the insulating layer 141c. Further, although the illustration of a part is omitted, inside the first substrate 141, as with the above-described embodiment, a part of the first wiring portion 45 and the second wiring portion 46, the plurality of pads P1, P2, P3, P4, P5 are provided.

[0081] The second coil 44 is provided inside the second substrate 142. The outer shape of the second substrate 142 is formed by laminating a plurality of insulating layers 142a, 142b, 142c, 142d. The second coil 44 is buried inside the insulating layer 142c. Further, although the illustration of a part is omitted, inside the second substrate 142, as with the above-described embodiment, a part of the first wiring portion 45 and the second wiring portion 46, the plurality of pads P5, P6, P7, P8 are provided.

[0082] The adhesive layer 149 is composed of an insulating adhesive. The adhesive layer 149 is arranged between the first substrate 141 and the second substrate 142. The adhesive layer 149 adheres the uppermost insulating layer 141d of the first substrate 141 and the lowermost insulating layer 142d of the second substrate 142. Thus, the adhesive layer 149 integrates the first substrate 141 and the second substrate 142.

[0083] The substrate portion 140 of the present modification has the first substrate 141 and the second substrate 142. The first substrate 141 and the second substrate 142 are laminated in the thickness direction (Z-axis direction) with the adhesive layer (insulating layer) 149 interposed therebetween. One of the pair of coils 43, 44 (the first coil 43) is formed in the first substrate 141. The other of the pair of coils 43, 44 (the second coil 44) is formed in the second substrate 142.

[0084] ​According to the present modification example, the substrate portion 140 is formed by bonding the first substrate 141 including the first coil 43 to the second substrate 142 including the second coil 44. Thus, the thickness of the adhesive layer 149 at the time of bonding can be easily controlled. Thereby, the withstand voltage and the transmission efficiency of the isolator 10 can be adjusted.

[0085] Further, according to the present modification example, a process of bonding the first substrate 141 to the second substrate 142 after connecting the first substrate 141 to the first semiconductor chip 21 and connecting the second substrate 142 to the second semiconductor chip 22 can be employed. Thus, simplification of the processes of flip chip bonding of the first substrate 141 to the first semiconductor chip 21 and flip chip bonding of the second substrate 142 to the second semiconductor chip 22 can be achieved.

[0086] According to at least one embodiment of the above description, by providing the substrate portion 40 having a pair of coils facing each other across the insulating layer and the first semiconductor chip 21 and the second semiconductor chip 22 sandwiching the substrate portion 40 from both sides in the thickness direction (Z-axis direction), an isolator 10 capable of miniaturizing the planar size can be provided.

[0087] Several embodiments of the present application have been described above, but these embodiments are presented by way of example and are not intended to limit the scope of the application. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and modifications thereof are included in the scope and spirit of the application, and are also included in the scope of the application and equivalents thereof as recited in the claims.

Claims

1. An isolator, characterized in that, have: The substrate portion has an insulating layer and a pair of coils facing each other in the thickness direction separated by the insulating layer; The first chip is disposed facing one side of the substrate and is connected to one of the pair of coils; as well as The second chip is disposed opposite to the other side of the substrate and is connected to the other of the pair of coils.

2. The isolator according to claim 1, characterized in that, The isolator has a first terminal portion that is connected to the substrate portion. The substrate portion has a first wiring portion that electrically connects the first terminal portion to the first chip.

3. The isolator according to claim 2, characterized in that, The isolator includes a second terminal portion that is connected to the substrate portion. The substrate portion has a second wiring portion that electrically connects the second terminal portion to the second chip. Both the first terminal portion and the second terminal portion are disposed opposite to one side of the substrate portion.

4. The isolator according to claim 1, characterized in that, The thickness of the insulating layer is 25 μm or more.

5. The isolator according to claim 1, characterized in that, At least a portion of the substrate is a flexible substrate.

6. The isolator according to claim 1, characterized in that, At least a portion of the substrate is a rigid substrate.

7. The isolator according to claim 1, characterized in that, The substrate portion is composed of a single substrate on which one of the pair of coils is formed on different layers.

8. The isolator according to claim 1, characterized in that, The substrate portion has a first substrate and a second substrate stacked in the thickness direction with the insulating layer as a barrier. One of the pair of coils is formed on the first substrate. The other of the pair of coils is formed on the second substrate.

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