Control system supporting multi-host concurrent access, storage device and storage medium

Abstract

The invention discloses a control system supporting concurrent access of multiple hosts, a storage device and a medium, and relates to the technical field of data storage, the system runs on a control module externally connected with the storage device, and the system comprises a communication connection management unit used for establishing connection with multiple hosts through at least two host interfaces; the access request receiving unit is used for receiving access requests sent by different hosts through an uplink port of the multi-host switching chip, and the access arbitration and scheduling unit is used for carrying out real-time arbitration and unified scheduling on the requests according to a preset strategy; and the instruction forwarding and execution unit forwards an arbitrated instruction to the storage unit for execution through a downlink port, and the system further integrates a cache consistency management unit, a configurable arbitration strategy unit, a multi-mode storage space management unit and the like, so that the data consistency, the access efficiency and the system reliability during multi-host concurrent access are ensured. According to the scheme, efficient and safe parallel access of a plurality of hosts to a single storage device is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, in particular to a control system supporting concurrent access of multiple hosts, a storage device and a storage medium. BACKGROUND

[0002] With the rapid development of information technology and the deepening of digital transformation, the application demand of multiple computer hosts to collaboratively process the same complex task or share the same data source in real time is increasingly prominent and has been widely penetrated into multiple key fields. For example, in the process of professional video production and nonlinear editing, the production team often needs multiple editing workstations to access high-rate raw video materials at the same time; in the field of high-performance scientific computing and large-scale numerical simulation, multiple computing nodes need to read or write massive intermediate data or result files in parallel; in the distributed database cluster and cloud computing infrastructure, ensuring low-latency and high-throughput access of each node to the central data storage is the core of service performance; in addition, in modern collaborative office, remote collaboration and cross-department project management, team members also need to efficiently and seamlessly operate the same set of documents or data sets. However, the current commonly used traditional external storage devices (including portable mobile hard drives, solid state drives and large-capacity desktop storage arrays, etc.) still follow the "one machine exclusive" design concept in terms of hardware interface and access protocol, which seriously limits the sharing capability of the device in a multi-host environment. This inherent design mode seriously limits the sharing capability of the device in a multi-host environment, resulting in many limitations of the existing technical solutions when multiple hosts need to access the same storage resource at the same time.

[0003] In addition to the above limitations of the access mode, in the complex scenario where multiple hosts attempt to write to the same storage device concurrently, how to effectively coordinate the write order, avoid data overwrite or damage, maintain the consistency of file system metadata, and design an effective locking mechanism or distributed file system to prevent conflicts are all core technical problems that the existing simple sharing solutions have failed to properly solve. At the same time, in the scenario of long-time access by multiple hosts, how to intelligently manage the power supply state of the storage device itself to ensure its continuous and stable operation is also an important link to ensure data security and business continuity. SUMMARY

[0004] The present application aims to overcome the above-mentioned defects of the prior art and provide a control system running on an external storage device control module supporting concurrent access of multiple hosts, a corresponding external storage device and a computer readable storage medium. The control system realizes efficient, orderly and safe concurrent access of multiple host devices to a single external storage device through software and hardware collaborative design.

[0005] To achieve the above objectives, the present invention provides a control system that operates on the control module of the external storage device, characterized in that it includes the following core units: The communication connection management unit is used to establish and maintain physical and data communication connections with at least two host devices through at least two host interfaces. This unit is responsible for interface protocol handshakes, link establishment, and monitoring, ensuring that each host interface can communicate independently and stably with its corresponding host. The types of host interfaces may include, but are not limited to, high-speed interfaces such as USB-C, Thunderbolt, and PCIe, or combinations thereof.

[0006] The access request receiving unit is used to receive access requests and data forwarded from different host devices via at least two uplink ports of the multi-host switching chip, on a one-to-one basis. This unit serves as the entry point for data inflow, ensuring that I / O requests from different hosts can be clearly distinguished and sent to subsequent processing flows. The introduction of the multi-host switching chip is a key hardware foundation for achieving physical channel isolation and logical convergence.

[0007] The access arbitration and scheduling unit is used to perform real-time arbitration and unified scheduling of access requests received from different host devices through different uplink ports. Based on a preset arbitration strategy, this unit coordinates the access timing and permissions of each host to shared storage resources, avoiding access conflicts and optimizing overall I / O performance. Its core function is to determine which host's access request can be executed at any given time.

[0008] The instruction forwarding and execution unit is used to forward the arbitrated and scheduled access instructions to the storage unit (such as NVMe SSD, SATA SSD, or mechanical hard drive) through at least one downlink port of the multi-host switching chip to perform the corresponding read and write operations. This unit ensures that the instructions authorized by the arbitrator can be accurately and efficiently delivered to the storage medium and complete the data access.

[0009] Furthermore, to enhance the robustness and data reliability of the system, the control system also includes a cache consistency management unit and an arbitration strategy execution unit.

[0010] The cache consistency management unit is used to execute the MESI (Modify, Exclusive, Shared, Invalidate) or its variants (such as MOESI) cache consistency protocol. This unit ensures data consistency when multiple hosts concurrently access the same data block in the storage unit by finely managing the state of cache lines (e.g., tracking which hosts cache which data blocks, and whether these cache copies are dirty or clean data). When a host wants to modify a data block, the unit invalidates the corresponding cache copies on other hosts via protocol messages, thereby preventing problems such as dirty reads or write loss.

[0011] The arbitration policy execution unit is the core of the access arbitration and scheduling unit's policy implementation, used to schedule host access requests based on configurable policies. Preferably, the policies include, but are not limited to, round-robin, fixed priority, or dynamic priority policies. Dynamic priority policies can intelligently adjust according to the characteristics of I / O requests and system status to optimize overall performance.

[0012] Preferably, the arbitration strategy execution unit is configured to execute one or more optimization strategies, including the following, when a dynamic priority strategy is enabled: Read requests to storage units have higher priority than write requests. This helps reduce read wait times on the host and improves system response speed, as read operations typically have a more direct impact on user experience or task flow.

[0013] Small-sized random access requests within storage units are given higher priority than large-sized sequential access requests. This is because small-sized random I / O (such as database transaction log writing and metadata operations) is more sensitive to latency, while large-sized sequential I / O (such as large file copying) has high throughput requirements but is relatively insensitive to short-term latency. Prioritizing random I / O can prevent it from being blocked by high-volume sequential I / O, thereby improving performance under mixed workloads.

[0014] Preferably, to meet diverse application requirements, the control system further includes a storage space management mode unit. This unit supports multiple storage space management configuration modes: In partitioned mode, the unit divides the physical storage space of the storage unit into at least two logical partitions, and can be configured such that each logical partition can only be accessed by a specified host interface. This is equivalent to a single physical device, but logically providing a dedicated, isolated storage area for each host, suitable for scenarios such as data isolation and multi-tenancy.

[0015] In shared mode, the unit treats the storage unit as a complete logical volume for concurrent access by all connected host devices. In this mode, concurrent read and write operations are securely managed through the collaborative work of the aforementioned access arbitration and scheduling unit and cache consistency management unit, ensuring data consistency. This is suitable for applications requiring multiple hosts to jointly process the same dataset, such as collaborative editing and shared databases.

[0016] In mirrored synchronization mode, this unit simultaneously writes write data from any host interface to two or more designated logical partitions of the storage unit to achieve real-time data backup or mirroring. For example, data written by host A will be backed up to partition 1 and partition 2 simultaneously, providing a hot backup data source for host B and enhancing data reliability.

[0017] Preferably, to improve the reliability of data transmission, the control system further includes a data verification unit. This unit uses mature verification methods, such as Cyclic Redundancy Check (CRC) or MD5 checksum, to detect and correct errors in the data transmitted between the host interface and the storage unit. This can effectively detect and correct data errors caused by signal interference, transmission errors, etc., ensuring data integrity.

[0018] Preferably, considering the potential differences in power supply capabilities provided by multiple host connections, the control system further includes a power management unit. This unit is used to: identify the power supply capabilities (such as the power negotiated by the USB PD protocol) of the at least two host interfaces, and prioritize obtaining operating power from the interface with the stronger power supply capability to power the entire external storage device. This intelligent power selection helps ensure that the device, especially high-performance SSDs, receives a stable and sufficient power supply, avoiding performance degradation or instability due to insufficient power supply.

[0019] Furthermore, the power management unit is configured to automatically switch to power supply from another normally connected host through its corresponding host interface when the currently prioritized host interface is disconnected (e.g., the host is unexpectedly shut down or the cable is unplugged) during the mirror synchronization mode (or other critical operating modes). This seamless power switching mechanism maintains the continuity of the mirror synchronization process or other background tasks, preventing data backup failures or unexpected power outages due to main power interruptions.

[0020] Based on the same inventive concept, the present invention also provides an external storage device. The device includes: case; At least two host interfaces, the interface type of which is USB-C, Thunderbolt, PCIe or a combination thereof; The storage device, which can be an NVMe SSD, SATA SSD, or hard disk drive, is the carrier of storage units. The control module, whose main body is a multi-host switching chip, is located inside the housing and connected to the at least two host interfaces and the memory, providing physical multiplexing capability. The control module runs the control system described above.

[0021] Preferably, the multi-host switching chip includes at least two uplink ports and two downlink ports for enabling concurrent connections between dual hosts and dual storage.

[0022] Finally, the present invention provides a computer-readable storage medium having a computer program (or firmware) stored thereon, which, when executed by a processor (i.e., the control module), implements all the functions of the control system as described above.

[0023] In summary, compared with the prior art, the technical solution provided by this invention brings significant and multi-layered beneficial effects: This invention achieves revolutionary direct concurrent access capabilities, completely breaking the traditional "one-machine exclusive" model of external storage devices. Through a built-in multi-host switching chip, it enables multiple hosts to directly and concurrently access a single storage device, eliminating all intermediate steps, resulting in the shortest data transmission path, extremely low latency, and extremely high efficiency. It constructs a robust data security and consistency fortress. By integrating a cache management unit based on advanced protocols such as MESI and multiple data verification mechanisms, it provides strong hardware-level protection for data integrity and consistency in complex multi-host access environments, from concurrency control to the transmission process, effectively avoiding data errors and conflicts. It offers a highly flexible and configurable user experience, supporting multiple working modes such as partitioning, sharing, and mirroring, enabling a single device to adapt to various diverse application scenarios such as data isolation, collaborative work, and real-time backup, greatly enhancing the device's practical value and user satisfaction. It possesses excellent compatibility, scalability, and practicality, supporting multiple mainstream high-speed interfaces and storage media, and can be flexibly designed into different product forms, making this technology easy to industrialize and meeting the diverse needs of both ordinary consumers and professional users, with a broad market prospect. Attached Figure Description

[0024] Figure 1 This is a flowchart of the control system described in Embodiment 1 of the present invention.

[0025] Figure 2 This is a schematic diagram of the external storage device described in Embodiment 2 of the present invention.

[0026] The components are as follows: 100-Control system, 101-Communication connection management unit, 102-Access request receiving unit, 103-Access arbitration and scheduling unit, 104-Arbitration strategy execution unit, 105-Instruction forwarding and execution unit, 106-Cache consistency management unit, 107-Power supply management unit, 108-Data verification unit, 109-Storage space management mode unit; 200-External storage device, 201-Housing, 202-Host interface, 203-Motherboard, 204-Multi-host switching chip, 205-Memory, 206-Control module, 207-Power management circuit. Detailed Implementation

[0027] The present invention will now be described in further detail with reference to the accompanying drawings. It should be noted that this embodiment is an exemplary description of the technical solution of the present invention and does not constitute any limitation on the scope of protection of the present invention. Those skilled in the art should understand that any reasonable modifications and variations without departing from the design concept and core architecture of the present invention should be considered to fall within the scope of protection of the present invention.

[0028] Example 1: Implementation of the Control System This embodiment details the specific implementation and technical advantages of the control system running on the external storage device control module. This control module can be a dedicated microprocessor highly integrated within a multi-master switching chip, featuring low power consumption and high real-time performance. The control system is stored as firmware in the memory associated with the control module, and is automatically loaded and executed by the control module after the device is powered on, achieving intelligent and efficient management and control of the entire storage device.

[0029] like Figure 1 As shown, the control system 100, as a fully functional software architecture, includes the following core units that work together, each playing a key role in ensuring the stable, efficient, and safe operation of the equipment in a multi-host environment: Communication Connection Management Unit 101: This unit is the cornerstone of the physical and logical connection between the device and the external host, responsible for the intelligent establishment, status monitoring, and dynamic maintenance of the underlying communication link. Taking the two mainstream full-featured USB-C host interfaces as examples, the Communication Connection Management Unit 101 can quickly and reliably detect host connection and disconnection events by monitoring the CC (Configuration Channel) pin signal level changes of each interface in real time and accurately. When a host successfully connects, the Communication Connection Management Unit 101 will actively initiate and execute a complex USB Power Delivery protocol negotiation process to obtain optimal power supply capacity and data transmission bandwidth, and simultaneously complete various initialization tasks of the USB data link layer, thereby establishing a stable and high-speed data communication channel. To ensure the reliability of the link, the Communication Connection Management Unit 101 will periodically send heartbeat packets to the connected host or continuously monitor the electrical status and protocol state machine of the link. Once an abnormal host disconnection is detected, the unit can sense it within milliseconds and immediately send a notification to other relevant units, triggering the corresponding emergency handling process to maximize data consistency and device availability. For higher-speed and more complex interfaces such as Thunderbolt or PCIe, the communication connection management unit 101 is responsible for executing the corresponding link training, status polling and parameter negotiation processes to ensure that the link operates stably in the best state.

[0030] Access Request Receiving Unit 102: This unit acts as the "frontline outpost" for data access, interacting closely and efficiently with the uplink port controller of the multi-host switching chip. Its workflow is as follows: When host A sends an NVMe command (such as a read or write request) to the storage device through its connected first interface, the command packet is first received by the hardware of the first uplink port of the multi-host switching chip. Access Request Receiving Unit 102 then obtains the original command packet promptly and accurately by reading the status register or dedicated data buffer corresponding to the first uplink port within the chip. To distinguish the source of the request throughout the processing flow, Access Request Receiving Unit 102 immediately labels the command clearly as "from host A," and then places this tagged access request into a globally shared, first-in-first-out or priority-based queue of pending requests, awaiting scheduling by the arbitration unit. This design effectively isolates and identifies the I / O flows of different hosts, laying the foundation for subsequent fair arbitration and accurate routing.

[0031] Access Arbitration and Scheduling Unit 103: This unit serves as the "traffic control center" of the entire control system. Its core is a highly efficient and configurable scheduler that continuously monitors the status of the queue of pending requests. Access Arbitration and Scheduling Unit 103 itself does not directly formulate strategies; instead, it invokes a dedicated arbitration strategy execution unit 104 to prioritize or select requests in the queue. This design separates strategy from mechanism, making the arbitration logic highly flexible and easily expandable and updated.

[0032] Flexibility in policy configuration: The device supports multiple arbitration policies, which can be preset via dedicated device management software running on the host or via physical DIP switches on the device casing. Common policy modes include, but are not limited to: "polling" mode, ensuring absolute fairness; "fixed priority" mode, ensuring faster response for critical hosts; and "adaptive priority" mode, which can dynamically adjust based on factors such as I / O type (read / write), request size, and wait time.

[0033] Intelligent Arbitration Process: Assume the current queue of pending requests contains both a large sequential write request from host A and a small random read request from host B. If the device is configured in a simple "round-robin" mode, the access arbitration and scheduling unit 103 will strictly follow an alternating order: the request from host A will be processed in the first scheduling cycle, the request from host B in the next cycle, and so on, achieving basic fairness. If a more intelligent combination of "read operations prioritize write operations" and "small-size random I / O prioritizes" strategy is enabled, the decision logic of the access arbitration and scheduling unit 103 will conduct a comprehensive evaluation. It will determine that the small-size random read request from host B has a higher overall priority. Therefore, the access arbitration and scheduling unit 103 will prioritize removing the request from host B's queue and submit it to the subsequent instruction forwarding and execution unit 105 for processing, thereby effectively reducing overall system latency and improving response speed.

[0034] Instruction forwarding and execution unit 105: Once the access arbitration and scheduling unit 103 selects a pending access request, the forwarding and execution unit 105 immediately takes over and is responsible for the specific execution of the request. It sends the request and its related parameters completely and accurately to the SSD controller through the downlink port of the multi-host switching chip. After performing the actual read operation on the internal flash memory, the SSD controller returns the requested data block through the downlink port. Upon receiving the data, the forwarding and execution unit 105, based on the source tag initially carried in the request, controls the internal crossbar switch of the multi-host switching chip to accurately route the data to the correct uplink port, ultimately delivering it successfully to host B, completing a full I / O service. For write requests, the process is similar but in the reverse direction: data travels from the host through the uplink port to the forwarding and execution unit 105, and then the forwarding and execution unit 105 writes it to the SSD through the downlink port. This unit ensures that data is transmitted correctly and without error in any complex multi-host path.

[0035] Cache Coherence Management Unit 106: This unit is crucial when multiple hosts concurrently access the same storage space. It maintains a fine-grained cache directory by using software simulation or auxiliary hardware with the classic MESI or its variants to record which data blocks in the storage device are currently cached by which hosts, and the status of these cache copies.

[0036] Data verification unit 108: This unit acts as a "quality supervisor" along the data transmission path, providing robust assurance for end-to-end data integrity. For example, when receiving write data from a host, data verification unit 108 calculates the CRC32 checksum of the received data in real time. Before finally submitting the data to the SSD controller for writing to flash memory, the checksum may be calculated again and compared with the one calculated during reception. Similarly, when reading data from the SSD and preparing to send it to a host, data verification unit 108 also calculates the data's checksum and appends it to the data packet for transmission. The host can verify the received data. This complete verification mechanism effectively detects and corrects data errors that may occur due to interference during transmission, greatly improving system reliability.

[0037] Power Management Unit 107: This unit is responsible for monitoring and intelligently managing the power supply status of each host interface. It obtains the voltage and current values ​​of each interface in real time by sampling the interface voltage through its internal ADC module or by reading the registers of the power management IC through the I2C / SPI interface.

[0038] Intelligent power supply selection strategy: Assuming the first interface supports 100W PD 3.0 power supply, while the second interface supports 60W PD power supply, the power management unit 107 will prioritize obtaining main power from the first interface based on a preset strategy during power-on initialization or connection changes, providing ample power to all components within the device, including the SSD, multi-host switching chip, and control module.

[0039] Seamless power switching ensures high availability: Consider a critical scenario: the device is operating in a highly available mirror synchronization mode and is currently powered by the host on the first interface. If the host on the first interface suddenly fails or is manually shut down, the power management unit 107 will quickly detect the voltage drop on the first interface within milliseconds or even microseconds through the voltage monitoring circuit. It immediately generates an interrupt signal and controls the OR-ing power switching circuit composed of MOSFETs to seamlessly and smoothly switch the main power supply path to the second interface, where the host connected to the second interface continues to power the device. This process is extremely rapid, ensuring that the ongoing mirror synchronization operation will not fail due to power interruption, guaranteeing business continuity and data integrity.

[0040] Storage space management mode unit 109: This unit provides flexible storage resource allocation and management capabilities. During device initialization or through dynamic configuration via user commands, it sets the logical manner in which the physical storage space is presented to the host computer.

[0041] Partitioning Mode: The storage space management mode unit 109 divides a physically contiguous 1TB SSD capacity into two independent 500GB logical units (LUN0 and LUN1) by sending standard NVMe management commands or SCSI commands to the SSD controller. Then, by configuring the access control list (ACL) of the multi-host switching chip or setting software filtering rules in this control system, it strictly stipulates that the first uplink port is only authorized to access LUN0, and the second uplink port is only authorized to access LUN1. This mode achieves hard isolation of storage space at the physical level, providing the best security and performance isolation.

[0042] Shared Mode: Storage space management unit 109 presents the entire 1TB SSD as a unified, large logical unit (LUN0) to all uplink ports. In this mode, multiple hosts can concurrently access the same storage space. Data consistency and concurrency control in this mode rely entirely on the aforementioned access arbitration and scheduling unit 103 and cache consistency management unit 106 for efficient and reliable management.

[0043] Mirror Synchronization Mode: The storage space management mode unit 109 divides the physical capacity of the SSD into two identical LUNs and establishes a mirror relationship. When a write request is received from either uplink port, the storage space management mode unit 109 intercepts the request and replicates it into two identical write operations, pointing to LUN0 and LUN1 respectively. These two write operations are submitted to the access arbitration and scheduling unit 103 for scheduling. The system strives to ensure that these two write operations are written to the two LUNs atomically, i.e., either both succeed or both fail, thereby maintaining real-time data synchronization on the two LUNs and achieving high-reliability redundancy. Read requests can then be read from either LUN according to the load balancing strategy.

[0044] Example 2: Implementation of External Storage Devices like Figure 2 As shown, a high-performance, high-reliability external storage device 200 specifically includes the following hardware components: Housing 201: Made of high-quality aluminum alloy or other metal materials (with good electromagnetic shielding and heat dissipation effects) or high-strength engineering plastics.

[0045] At least two host interfaces 202: The host interfaces 202 are of type USB-C, Thunderbolt, PCIe, or a combination thereof. The illustration shows two interfaces conforming to the USB-C physical form factor standard, soldered onto a carefully designed motherboard 203 inside the device.

[0046] Memory 205: This is an NVMe SSD, SATA SSD, or mechanical hard drive, and is the carrier of the storage unit. The illustration shows a high-performance M.2 interface NVMe SSD.

[0047] Control module 206: The main body of the control module is a multi-host switching chip 204, which is disposed within the housing and connected to the at least two host interfaces 202 and the memory. The control module 206 runs the control system described in Embodiment 1 above. The multi-host switching chip 204 is a core switching chip, which includes at least two uplink ports and two downlink ports for enabling concurrent connections between dual hosts and dual storage. Its uplink ports are connected to at least two host interfaces 202 respectively through motherboard traces, and its downlink ports are connected to the memory 205.

[0048] Power management circuit 207: A complex power subsystem containing a high-efficiency DC-DC voltage converter, an OR-ing MOSFET for power path management, overvoltage / overcurrent protection circuitry, etc. Its main function is to draw power from at least two host interfaces 202, intelligently select and switch between them, and ultimately provide stable voltage to various components.

[0049] After the device is powered on, the control module 206 first performs hardware initialization, then loads the firmware from the non-volatile memory into memory and starts running, thereby instantiating and activating all the functional units as described in Embodiment 1, making the device 200 an intelligent, high-performance external storage solution that supports secure concurrent access from multiple hosts.

[0050] Example 3: Implementation of a computer-readable storage medium A computer-readable storage medium, in its physical form, may be an SPI Flash memory chip with a capacity of 8MB (or greater). This chip stores machine code that can be directly executed by a microcontroller, generated by compiling and linking source code carefully written in a high-level language. This source code fully implements all the functional logic and algorithms of the communication connection management unit 101, access request receiving unit 102, access arbitration and scheduling unit 103, arbitration policy execution unit 104, instruction forwarding and execution unit 105, cache consistency management unit 106, power supply management unit 107, data verification unit 108, and storage space management mode unit 109, as described in detail in Embodiment 1.

[0051] Once the pre-programmed SPI Flash chip is accurately soldered onto the reserved pads on the motherboard 203 of the device described in Embodiment 2, and reliably connected to the SPI interface pins of the control module 206 via PCB traces, the control module 206, during power-on initialization, reads the firmware code from a specific starting address of the SPI Flash through its built-in Bootloader program, loads it into its internal SRAM or external SDRAM, and then executes it. This process gives the device a soul on a hardware basis, thereby enabling advanced capabilities such as intelligent support for concurrent access from multiple hosts, cache consistency maintenance, intelligent power management, and data verification.

[0052] The above description is merely a preferred embodiment of the present invention, illustrating its technical details and advantages through detailed unit descriptions and scenario examples. However, the scope of protection of the present invention is not limited thereto. Any variations, substitutions, or improvements that can be easily conceived by those skilled in the art within the scope of the technical principles and core architecture disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the claims.

Claims

1. A control system supporting concurrent access from multiple hosts, characterized in that, include: The communication connection management unit is used to establish and maintain physical and data communication connections with at least two host devices through at least two host interfaces respectively; The access request receiving unit is used to receive host connection status information from the communication connection management unit, and to receive access requests and data forwarded by the communication connection management unit through the multi-host switching chip; The access arbitration and scheduling unit is used to receive access requests from the access request receiving unit, perform real-time arbitration and unified scheduling of access requests from different host devices, and coordinate the access sequence and permissions of each host to the shared storage resources according to the preset arbitration strategy. The instruction forwarding and execution unit is used to receive the arbitration result and scheduling instruction from the access arbitration and scheduling unit, and forward the access instruction after arbitration and scheduling to the storage unit through the multi-host switching chip.

2. The control system according to claim 1, characterized in that, Also includes: The cache consistency management unit is used to receive access request information from the access request receiving unit, provide cache consistency status information to the access arbitration and scheduling unit, and send cache consistency control instructions to the instruction forwarding and execution unit. It is used to execute MESI or its variant cache consistency protocol and ensure data consistency when multiple hosts concurrently access the same data block in the storage unit by managing the cache line status. The arbitration strategy execution unit is used to provide arbitration strategy configuration information to the access arbitration and scheduling unit, and to schedule host access requests based on polling, fixed priority or dynamic priority strategies.

3. The control system according to claim 2, characterized in that: The arbitration strategy execution unit is configured to execute the following strategies when the dynamic priority strategy is enabled: read requests for storage units have higher priority than write requests, and / or, small-sized random access requests for storage units have higher priority than large-sized sequential access requests.

4. The control system according to claim 1, characterized in that, Also includes: The storage space management mode unit is used to provide storage space configuration information to the access arbitration and scheduling unit and send space management instructions to the instruction forwarding and execution unit, which supports partition mode, shared mode and mirror synchronization mode. In the partitioning mode, the storage space of the storage unit is divided into at least two logical partitions, and each logical partition is configured to be accessible only by a specified host interface. In the shared mode, the storage unit is provided as a complete logical volume for all connected host devices to access; In the mirror synchronization mode, write data from any host interface is simultaneously written to two or more designated logical partitions of the storage unit.

5. The control system according to claim 1, characterized in that, Also includes: The data verification unit is used to receive and verify the write data from the access request receiving unit, and to provide the verified read data to the instruction forwarding and execution unit. It uses CRC or MD5 verification methods to perform error detection and correction on the data transmitted between the host interface and the storage unit.

6. The control system according to claim 1, characterized in that, Also includes: The power supply management unit is used to receive host interface connection status information from the communication connection management unit, identify the power supply capabilities of the at least two host interfaces, and preferentially obtain working power from the interface with stronger power supply capabilities.

7. The control system according to claim 6, characterized in that: The power supply management unit is also configured to: in mirror synchronization mode, if the host interface currently given priority for power supply is detected to be disconnected, automatically switch to another normally connected host to supply power to the device through its corresponding host interface.

8. An external storage device, characterized in that, include: case; At least two host interfaces, wherein the interface type of the host interfaces is USB-C, Thunderbolt, PCIe or a combination thereof; The storage device is an NVMe SSD, a SATA SSD, or a hard disk drive; The control module, the main body of which is a multi-host switching chip, is disposed within the housing. The control module is connected to the at least two host interfaces and the memory. The control module is configured to perform the functions of the control system as described in any one of claims 1 to 7.

9. The external storage device according to claim 8, characterized in that: The multi-host switching chip includes at least two uplink ports and two downlink ports to enable concurrent connections between dual hosts and dual storage.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the functions of the control system as described in any one of claims 1 to 7.

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