GPU (Graphics Processing Unit) inter-card interconnection method for reducing communication delay

Abstract

The invention relates to the technical field of GPUs, and particularly discloses a GPU inter-card interconnection method for reducing communication delay, which comprises the following steps: S1, preparing a bearing substrate and designing a three-layer interconnection substrate; s2, dividing a plurality of independent virtual channels, and configuring a special buffer area; s3, presetting an acquisition period, acquiring a time node when the special buffer area is occupied, acquiring a time node when the special buffer area becomes empty, and calculating traffic delay; s4, presetting an ideal delay corresponding to each layer, dividing a crowded channel and an idle channel according to the flow delay, and respectively calculating a crowded delay and a residual delay; and S5, respectively adjusting the crowded channel and the idle channel based on the crowded delay and the residual delay. Through the structural design of the three layers of interconnected substrates and a dynamic bandwidth regulation and control mechanism, a closed loop is formed from transmission path optimization, delay accurate sensing to resource dynamic allocation, and delay depth reduction and stable control are realized.

Description

Technical Field

[0001] This invention relates to the field of GPU technology, and more specifically to a method for inter-GPU interconnection that reduces communication latency. Background Technology

[0002] Current dedicated interconnect technologies like NVLink offer high bandwidth through direct point-to-point connections, but the rigidity of their physical topology limits further latency reduction. Within a single node, as the number of GPUs increases, the wiring complexity required to achieve full interconnection grows exponentially, resulting in long and irregular signal transmission paths. When a GPU needs to communicate with a non-directly connected peer, data must be relayed through an intermediate GPU, introducing multiple "handshakes" and forwarding delays. This significantly increases actual communication latency and generates unpredictable jitter, which is fatal for AI training or scientific computing tasks requiring tight synchronization. Summary of the Invention

[0003] The purpose of this invention is to provide a method for interconnecting GPU cards to reduce communication latency and solve the above-mentioned technical problems.

[0004] The objective of this invention can be achieved through the following technical solutions: A method for reducing communication latency between GPU cards includes the following steps: S1: Prepare a carrier substrate for TSV according to a preset specification, and design a three-layer interconnect substrate, wherein the three-layer interconnect substrate includes a data channel layer, a control signal layer and a power layer in sequence. S2: Divide the physical links in the data channel layer into n independent physical links and denot them as independent virtual channels, where n represents the preset number of physical links, and configure a dedicated buffer of a preset size for each independent virtual channel. S3: Preset the collection period T, and periodically acquire the traffic delay t of each independent virtual channel at the collection period T, including the following steps: Obtain the size B of the data packet to be transmitted in the independent virtual channel, and obtain the corresponding time node t when the space occupied by the dedicated buffer is B. start And obtain the time node t when the dedicated buffer becomes empty again. end Calculate the traffic delay t=t end -t start ; S4: Preset the ideal delays t1, t2 and t3 for each layer of the three-layer interconnect substrate. If the flow delay t is greater than the ideal delay of the three-layer interconnect substrate to which the independent virtual channel belongs, it is recorded as a congested channel. Otherwise, it is recorded as an idle channel. Calculate the congestion delay YT=t in the congested channel over -t over_s , where t overt represents the flow delay corresponding to the congested channel. over_s The ideal delay corresponding to the three interconnect substrates to which the congested channel belongs; Calculate the remaining delay XT=t of the idle channel. free -t free_s , where t free t represents the traffic latency corresponding to the idle channel. free_s This represents the ideal delay corresponding to the three interconnect substrates to which the idle channel belongs; S5: Methods for adjusting independent virtual channels based on congestion delay YT and remaining delay XT include: Calculate the magnification factor FY = (t) over_s +YT) / t over This increases the physical bandwidth of congested channels by FY times; Calculate the reduction factor FX = (t) free_s -XT) / t free This reduces the physical bandwidth of the idle channel by a factor of FX.

[0005] As a further aspect of the present invention: in step S1, a chip spacing interval [L1, L2] is preset to ensure that the spacing L between each layer of the three interconnect substrate is within the chip spacing interval [L1, L2].

[0006] As a further aspect of the present invention: in step S1, each layer of the three-layer interconnect substrate is connected by microbumps, and the spacing between the microbumps is less than L1.

[0007] As a further aspect of the present invention: in step S2, the physical link in the data channel layer is divided into n independent virtual channels, and the physical link bandwidth of each independent virtual channel is equal.

[0008] As a further aspect of the present invention: in step S2, the maximum value B of a single transmission data packet in an independent virtual channel is obtained. max Make the space of the dedicated buffer greater than or equal to B. max .

[0009] As a further aspect of the present invention: in step S3, the independent virtual channel is periodically adjusted with a collection period T.

[0010] As a further aspect of the present invention: in step S3, the transmission time of the data packet on the physical link is ignored and the traffic delay t is not included.

[0011] As a further aspect of the present invention: in step S4, the priority of each layer of the three-layer interconnect substrate is obtained to ensure that the ideal delay corresponding to the three-layer interconnect substrate with a higher priority value is smaller.

[0012] The beneficial effects of this invention are as follows: First, this invention isolates the data channel layer, control signal layer and power layer in layers through a three-layer interconnect substrate, avoiding the lengthy paths and interference caused by the interweaving of different signals in traditional wiring, making the data transmission path more regular and the signal loss less, thus laying a hardware foundation for reducing latency.

[0013] The data channel layer is then divided into n independent virtual channels and configured with dedicated buffers, so that data transmission in each channel does not have to wait for other channels to release resources, completely avoiding the "queueing delay" in the shared link, ensuring smoother direct transmission from the source GPU to the target GPU, and significantly reducing the basic latency.

[0014] Based on a preset acquisition period T, the scheme periodically acquires the traffic delay t of each independent virtual channel, and records the t when the dedicated buffer occupies the size B of the data packet to be transmitted. start t when the buffer is empty end It calculates the actual time it takes for data to be transmitted from entering a dedicated buffer to being fully transmitted. This latency collection method based on the entire lifecycle of data packets makes latency perception extremely accurate.

[0015] Then, by combining the ideal delays t1, t2, and t3 corresponding to each layer of the three-layer interconnect substrate, the scheme further distinguishes between congested and idle channels, and calculates the congestion delay YT=t over -t over_s and remaining delay XT=t free -t free_s This quantifies the degree of delay deviation in different channels, providing a basis for subsequent delay optimization.

[0016] Next, for congested passageways, the solution uses an amplification factor FY = (t) over_s +YT) / t over By increasing the physical bandwidth by FY times, the channel congestion problem is directly alleviated. This avoids data queuing and multiple "handshake" waiting caused by channel congestion in traditional technologies. Furthermore, it eliminates the need to rely on intermediate GPUs to relay non-directly connected data, completely eliminating forwarding and accumulated latency caused by relays. This allows the actual transmission latency of congested channels to quickly approach the ideal latency. over_s To move closer; and for the idle channel, by reducing the coefficient FX = (t free_s -XT) / t free By reducing the physical bandwidth by a factor of FX, idle bandwidth resources are efficiently allocated to congested channels, avoiding bandwidth waste and ensuring that core data transmission channels always have sufficient bandwidth support. Even if the number of GPUs increases, latency will not deteriorate with expansion.

[0017] This dynamic bandwidth adjustment based on real-time latency data not only ensures that the actual latency of each channel fluctuates around the ideal latency, significantly suppressing latency jitter, but also reduces the probability of additional operations such as signal error correction and retransmission, lowering the system's additional latency. Simultaneously, it allows GPU resources to be more concentrated on core computing rather than communication coordination, indirectly optimizing end-to-end latency. This perfectly suits tightly synchronized tasks such as AI training and scientific computing, which have extremely high requirements for latency stability and low latency. In summary, this invention, through the structured design of a three-layer interconnect substrate and a dynamic bandwidth control mechanism, forms a closed loop from transmission path optimization and precise latency perception to dynamic resource allocation, achieving deep latency reduction and stable control. Attached Figure Description

[0018] The invention will now be further described with reference to the accompanying drawings.

[0019] Figure 1 This is a flowchart illustrating a GPU card interconnection method for reducing communication latency according to the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Please see Figure 1 As shown, this invention provides a method for inter-GPU card interconnection to reduce communication latency, comprising the following steps: S1: Prepare a carrier substrate for TSV according to a preset specification, and design a three-layer interconnect substrate, wherein the three-layer interconnect substrate includes a data channel layer, a control signal layer and a power layer in sequence. S2: Divide the physical links in the data channel layer into n independent physical links and denot them as independent virtual channels, where n represents the preset number of physical links, and configure a dedicated buffer of a preset size for each independent virtual channel. S3: Preset the collection period T, and periodically acquire the traffic delay t of each independent virtual channel at the collection period T, including the following steps: Obtain the size B of the data packet to be transmitted in the independent virtual channel, and obtain the corresponding time node t when the space occupied by the dedicated buffer is B. start And obtain the time node t when the dedicated buffer becomes empty again. end Calculate the traffic delay t=t end -t start ; S4: Preset the ideal delays t1, t2 and t3 for each layer of the three-layer interconnect substrate. If the flow delay t is greater than the ideal delay of the three-layer interconnect substrate to which the independent virtual channel belongs, it is recorded as a congested channel. Otherwise, it is recorded as an idle channel. Calculate the congestion delay YT=t in the congested channel over -t over_s , where t over t represents the flow delay corresponding to the congested channel. over_s The ideal delay corresponding to the three interconnect substrates to which the congested channel belongs; Calculate the remaining delay XT=t of the idle channel. free -t free_s , where t free t represents the traffic latency corresponding to the idle channel. free_s This represents the ideal delay corresponding to the three interconnect substrates to which the idle channel belongs; S5: Methods for adjusting independent virtual channels based on congestion delay YT and remaining delay XT include: Calculate the magnification factor FY = (t) over_s +YT) / t over This increases the physical bandwidth of congested channels by FY times; Calculate the reduction factor FX = (t) free_s -XT) / t free This reduces the physical bandwidth of the idle channel by a factor of FX.

[0022] It should be noted that, firstly, this invention precisely fabricates the carrier substrate integrating TSVs according to preset specifications, and designs a three-layer structured interconnect substrate, clearly divided from top to bottom into a data channel layer, a control signal layer, and a power layer. This layered isolation architecture achieves complete separation of the physical domains of different signal types. Compared to the signal interleaving conflicts caused by the shared wiring space for data, control, and power signals in traditional NVLink technology, this solution confines core data transmission, device collaborative control commands, and stable power supply to independent layers, completely avoiding mutual interference and path contention issues during different signal transmissions. The data channel layer does not need to detour to avoid control signals or power lines; the transmission path is strictly limited to its dedicated layer, achieving the shortest and most regular physical path, significantly reducing the additional transmission losses caused by signal interleaving in traditional wiring, such as lengthy and bent paths. Simultaneously, the vertical interconnect characteristics of TSVs further shorten the signal transmission distance between layers, avoiding the planar detour delays of traditional wiring. The layered design also makes the signal transmission characteristics of each layer more targeted. The data channel layer can focus on optimizing bandwidth and transmission rate, the control signal layer can enhance the accuracy of instruction transmission, and the power layer can ensure power supply stability. The three do not interfere with each other, which reduces the increase in transmission latency caused by signal crosstalk and reduces the probability of retransmission due to interference. It lays a solid foundation for latency reduction at the hardware architecture level, making the physical transmission path of data from the source GPU to the target GPU shorter and more efficient, fundamentally breaking through the path length and latency bottleneck caused by the rigidity of traditional physical topology.

[0023] Subsequently, based on the hardware architecture of the three-layer interconnect substrate, the physical links of the data channel layer are divided into n independent physical links and defined as independent virtual channels. Simultaneously, a pre-defined dedicated buffer is configured for each independent virtual channel. Data packets from different channels can be transmitted in parallel on their dedicated links without waiting for other channels to release bandwidth or buffer resources, completely avoiding the "queueing" latency common in shared links. The dedicated buffer configuration further ensures the continuity of data packet transmission. When the size of the data packet to be transmitted is B, the buffer can directly accept the complete data packet, avoiding transmission interruptions or waiting due to insufficient buffering. Combined with the independence of the physical links, data packets are transmitted "as soon as they arrive." This design allows direct transmission between the source GPU and the target GPU to bypass resource contention, resulting in a smoother data transmission process and significantly reducing basic latency from the transmission scheduling perspective.

[0024] Next, to achieve dynamic latency control, a pre-set acquisition period T is used to continuously acquire the real-time traffic latency t of each independent virtual channel. The acquisition process focuses on the entire lifecycle of data packet transmission, and latency quantification is achieved by capturing two key time points: when the data packet to be transmitted is completely written into the dedicated buffer and the buffer occupancy reaches B, the system automatically records the initial time point t. startOnce all data packets have been transmitted and the dedicated buffer is empty again, the termination time node t is recorded synchronously. end By calculating t=t end -t start This gives the complete transmission time of the data packet in the corresponding virtual channel, i.e., the traffic delay t.

[0025] After collecting the real-time traffic delay t of each independent virtual channel, a delay deviation quantization system is constructed by combining the pre-calibrated ideal delays t1, t2, and t3 of each layer of the three-layer interconnect substrate to distinguish between congested and idle channels. The system compares the real-time traffic delay t of each independent virtual channel with the ideal delay corresponding to its layer. If the traffic delay t... over Higher than the ideal delay t of its layer over_s If the current load is too high, it is considered a congested channel, indicating that the transmission delay exceeds the limit; if the traffic delay t free Lower than the ideal delay t of its layer free_s If the channel is empty, it indicates that its bandwidth resources are not being fully utilized. Based on this, the solution uses the formula YT=t over -t over_s Calculate the congestion delay YT in the congested lane to intuitively quantify the specific value by which the delay exceeds the ideal baseline; using the formula XT=t free -t free_s The remaining latency XT of idle channels is calculated to determine the redundancy space where the latency is below the ideal baseline. This quantification method abandons the traditional fuzzy channel status judgment mode and presents the degree of latency deviation and resource utilization status of different channels. It provides a data-driven and implementable decision-making basis for subsequent targeted adjustment of channel bandwidth, precise mitigation of congestion latency, and efficient utilization of idle resources, ensuring that latency optimization measures are more targeted.

[0026] Finally, a bandwidth adjustment mechanism is constructed based on its congestion delay YT, using the amplification factor formula FY=(t) over_s +YT) / t over The appropriate bandwidth amplification ratio is calculated, dynamically expanding the physical bandwidth of the congested channel by a factor of FY. This improves the data transmission throughput of the congested channel, fundamentally alleviating the packet congestion problem. It completely avoids the time-consuming steps of packet queuing and multiple "handshake" confirmations caused by insufficient channel bandwidth in traditional technologies. Furthermore, it eliminates the need for intermediate GPUs for non-direct data relay, completely eliminating forwarding latency and accumulated latency loss from multiple forwardings. This allows the actual transmission latency of the congested channel to quickly approach the preset ideal latency t. over_s convergence.

[0027] Meanwhile, for idle channels, based on the remaining delay XT, the reduction factor formula FX = (t free_s -XT) / tfree The bandwidth contraction ratio is calculated, and the physical bandwidth of idle channels is compressed by a factor of FX. Idle bandwidth resources are efficiently released and redistributed to congested channels, achieving dynamic and balanced allocation of bandwidth resources across the entire link. This avoids resource waste in traditional fixed bandwidth allocation models while ensuring that core data transmission channels always have sufficient bandwidth support. Through dynamic, on-demand bandwidth allocation, the low-latency transmission characteristics of each channel are maintained, effectively avoiding the problem of latency deterioration due to increased wiring complexity after expanding the number of GPUs in traditional technologies, thus ensuring communication efficiency in large-scale collaborative scenarios.

[0028] This dynamic bandwidth adjustment based on real-time latency data not only ensures that the actual latency of each channel always fluctuates around the ideal latency, significantly suppressing latency jitter, but also reduces the probability of additional operations such as signal error correction and retransmission, thereby reducing additional system latency. In summary, this invention, through the structured design of a three-layer interconnect substrate and a dynamic bandwidth control mechanism, forms a closed loop from transmission path optimization and precise latency perception to dynamic resource allocation, achieving deep latency reduction and stable control.

[0029] In another preferred embodiment of the present invention, a chip spacing interval [L1, L2] is preset to ensure that the spacing L between each layer of the three interconnect substrate is within the chip spacing interval [L1, L2].

[0030] It is worth noting that, to further optimize the latency control effect of the hardware architecture, a chip spacing range [L1, L2] is pre-set, ensuring that the actual spacing L between each layer of the three-layer interconnect substrate falls within this range. This serves two purposes: too small a spacing can easily lead to increased crosstalk between layers, increasing transmission delay and retransmission risk; too large a spacing will lengthen the signal transmission path, directly increasing the basic latency and violating the principle of shortest path optimization in a layered architecture. By limiting the spacing L to [L1, L2], crosstalk interference caused by excessive proximity of signals between layers is avoided, ensuring the independence and stability of signal transmission in each layer, while also preventing the path length problem caused by excessive spacing, maintaining the advantage of short path signal transmission. Furthermore, this allows for more efficient inter-layer signal transmission, further reducing vertical transmission delay.

[0031] In another preferred embodiment of the present invention, each layer of the three-layer interconnect substrate is connected by microbumps, and the spacing between the microbumps is less than L1.

[0032] Understandably, microbumps are used to interconnect layers, with the spacing between microbumps limited to a minimum value L1 within a preset chip spacing range. As a high-density, low-impedance connection carrier, the compact spacing of microbumps synergistically optimizes with the interlayer spacing [L1, L2]. A spacing smaller than L1 ensures that microbumps can be densely arranged within a reasonable interlayer space, increasing interlayer interconnect density, while avoiding excessively large bump spacing that would lengthen the signal transmission path, further compressing vertical transmission delay. The low contact resistance of microbumps reduces energy loss and delay accumulation during signal transmission. Simultaneously, the densely arranged microbumps provide multiple parallel connections, enhancing the redundancy and stability of interlayer data transmission and reducing delay fluctuations caused by single-point failures.

[0033] In another preferred embodiment of the present invention, the physical links in the data channel layer are divided into n independent virtual channels, and the physical link bandwidth of each independent virtual channel is equal.

[0034] It is important to note that when dividing the data channel layer into independent virtual channels, it is crucial to ensure that the physical link bandwidth of each independent virtual channel remains equal. This design lays the initial foundation for subsequent dynamic bandwidth adjustments. Equal initial bandwidth ensures that all virtual channels have consistent transmission capabilities in the early stages of operation, avoiding imbalances caused by inherent congestion in some channels and inherent idleness in others due to differences in initial bandwidth, thus reducing meaningless latency deviations at the source. Simultaneously, equal bandwidth allocation makes the latency data collected from each channel more comparable, resulting in more accurate determinations of congested and idle channels based on traffic latency, and providing benchmark data for calculating the amplification factor FY and the reduction factor FX.

[0035] Furthermore, this initial equalization design complements the subsequent dynamic bandwidth adjustment, ensuring stable low latency in the early stages of system operation while making the dynamic allocation of bandwidth resources more reasonable and efficient. This ensures that channel resource allocation is always optimized around the goal of low latency, thereby maintaining communication latency at the optimal level in multi-GPU collaborative scenarios.

[0036] In another preferred embodiment of the present invention, the maximum value B of a single transmission of data packets in an independent virtual channel is obtained. max Make the space of the dedicated buffer greater than or equal to B. max .

[0037] It should be noted that the maximum value B of a single data packet transmitted in each independent virtual channel is first obtained. max The space of the dedicated buffer is explicitly limited to be greater than or equal to B. max The purpose of this design is to avoid transmission interruptions and waiting delays. If the buffer space is less than B... maxThe largest data packet in a single transmission cannot be stored completely, requiring split transmission or waiting for buffer release, incurring additional splitting and queuing delays, which violates the original design principle of independent virtual channels for instant transmission. Buffer space adaptation B max Subsequently, it can directly accept any single data packet transmission, ensuring that transmission starts immediately after the data packet is completely stored, without splitting or waiting, thus maintaining the continuity of the transmission process. At the same time, ample buffer space avoids data packet loss and retransmission due to buffer overflow, reduces the latency accumulation caused by retransmission, and makes the collection of traffic latency t more accurate. This provides reliable data support for subsequent channel status determination and bandwidth adjustment, further solidifying the foundation of low-latency communication from the buffer configuration level.

[0038] In another preferred embodiment of the present invention, the independent virtual channel is periodically adjusted with a collection period T.

[0039] Understandably, periodic adjustments are made to the independent virtual channels using a collection period T to ensure that bandwidth adjustments precisely match the real-time status of the channels. Periodic adjustments can dynamically track changes in traffic latency for each channel, promptly capturing dynamic transitions between congested and idle states, and avoiding latency accumulation or resource waste. Through continuous optimization over the T-period, the bandwidth of each channel is always adapted to actual transmission needs, maintaining latency stable within the ideal range, and ensuring low latency and high reliability of communication in multi-GPU collaborative scenarios.

[0040] In another preferred embodiment of the present invention, the transmission time of data packets on the physical link is ignored and the traffic delay t is not included.

[0041] It is worth noting that the transmission time of data packets on the physical link is ignored. Only the t value of the data packets stored in the dedicated buffer is considered. start and t with an empty buffer end Based on the calculation, the inherent time-consuming interference of physical link transmission is eliminated, allowing the traffic delay t to reflect optimizable delay items such as channel congestion and buffer waiting. This provides purer reference data for subsequent channel status determination and dynamic bandwidth adjustment, making delay optimization more targeted.

[0042] In another preferred embodiment of the present invention, the priority of each layer of the three-layer interconnect substrate is obtained to ensure that the ideal delay corresponding to the three-layer interconnect substrate with the higher priority value is smaller.

[0043] It is worth noting that the priority of each layer of the three-layer interconnect substrate is first obtained, and the priority order of the data channel layer, control signal layer, and power layer is clearly defined, ensuring that the higher priority layer corresponds to a lower ideal latency. This design allows the core transmission link to be optimized with lower ideal latency as the goal, focusing on latency control of the critical path, tilting resources towards high priority layers, strengthening the low latency orientation from the baseline setting level, ensuring the efficiency of core signal transmission, and meeting the low latency requirements of multi-GPU collaboration.

[0044] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A method for inter-GPU card interconnection to reduce communication latency, characterized in that, Includes the following steps: S1: Prepare a carrier substrate for TSV according to a preset specification, and design a three-layer interconnect substrate, wherein the three-layer interconnect substrate includes a data channel layer, a control signal layer and a power layer in sequence. S2: Divide the physical links in the data channel layer into n independent physical links and denot them as independent virtual channels, where n represents the preset number of physical links, and configure a dedicated buffer of a preset size for each independent virtual channel. S3: Preset the collection period T, and periodically acquire the traffic delay t of each independent virtual channel at the collection period T, including the following steps: Obtain the size B of the data packet to be transmitted in the independent virtual channel, and obtain the corresponding time node t when the space occupied by the dedicated buffer is B. start And obtain the time node t when the dedicated buffer becomes empty again. end Calculate the traffic delay t=t end -t start ; S4: Preset the ideal delays t1, t2 and t3 for each layer of the three-layer interconnect substrate. If the flow delay t is greater than the ideal delay of the three-layer interconnect substrate to which the independent virtual channel belongs, it is recorded as a congested channel. Otherwise, it is recorded as an idle channel. Calculate the congestion delay YT=t in the congested channel over -t over_s , where t over t represents the flow delay corresponding to the congested channel. over_s The ideal delay corresponding to the three interconnect substrates to which the congested channel belongs; Calculate the remaining delay XT=t of the idle channel. free -t free_s , where t free t represents the traffic latency corresponding to the idle channel. free_s This represents the ideal delay corresponding to the three interconnect substrates to which the idle channel belongs; S5: Methods for adjusting independent virtual channels based on congestion delay YT and remaining delay XT include: Calculate the magnification factor FY = (t) over_s +YT) / t over This increases the physical bandwidth of congested channels by FY times; Calculate the reduction factor FX = (t) free_s -XT) / t free This reduces the physical bandwidth of the idle channel by a factor of FX.

2. The GPU card interconnection method for reducing communication latency according to claim 1, characterized in that, In step S1, a chip spacing interval [L1, L2] is preset to ensure that the spacing L between each layer of the three interconnect substrate is within the chip spacing interval [L1, L2].

3. The GPU card interconnection method for reducing communication latency according to claim 1, characterized in that, In step S1, each layer of the three interconnect substrate is connected by microbumps, and the spacing between the microbumps is less than L1.

4. The GPU card interconnection method for reducing communication latency according to claim 1, characterized in that, In step S2, the physical links in the data channel layer are divided into n independent virtual channels, and the physical link bandwidth of each independent virtual channel is made equal.

5. The GPU card interconnection method for reducing communication latency according to claim 1, characterized in that, In step S2, the maximum value B of a single transmission of data packets in an independent virtual channel is obtained. max Make the space of the dedicated buffer greater than or equal to B. max .

6. The GPU card interconnection method for reducing communication latency according to claim 1, characterized in that, In step S3, the independent virtual channel is periodically adjusted with a collection period T.

7. The GPU card interconnection method for reducing communication latency according to claim 1, characterized in that, In step S3, the transmission time of data packets on the physical link is ignored and the traffic delay t is not included.

8. The GPU card interconnection method for reducing communication latency according to claim 1, characterized in that, In step S4, the priority of each layer of the three-layer interconnect substrate is obtained to ensure that the ideal delay of the three-layer interconnect substrate with a higher priority value is smaller.

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