An image sensor with a dynamic low power counter architecture

Abstract

The application discloses an image sensor with a dynamic low-power consumption counter architecture and relates to the field of image sensors, which comprises a phase-locked loop module, a row selection module, a pixel array and a column ADC, wherein the column ADC comprises an ADC clock generation module, a slope signal generation module, a comparator array module and a state judgment module; the ADC clock generation module processes an input first clock signal and outputs a second clock signal and a third clock signal that act in the Rs interval and the Ss interval; the slope signal generation module outputs a slope reference signal according to the third clock signal; the comparator array module compares a pixel signal with the slope reference signal to obtain a comparator output signal; and the state judgment module outputs a first state switching signal and a second state switching signal according to the comparator output signal, wherein the first state switching signal controls a counter and a latch operation array module. The image sensor can dynamically reduce the redundant power consumption generated by the column ADC in the interval outside the effective reading action in the pixel reading process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image sensors, in particular to an image sensor with a dynamic low-power consumption counter architecture. BACKGROUND

[0002] With the advent of the Internet of Things era, the application range of image sensors (referred to as CIS: CMOS Image Sensor) is becoming more and more extensive, and many new application scenarios have also emerged, among which the monitoring of moving objects and low power consumption are two important research directions. Unlike traditional application scenarios, the Internet of Things and intelligent security fields that have emerged in recent years more often use a battery-powered mode, so the power consumption of the sensors used largely determines the standby time and use experience of the device. In recent years, the number of pixels of image sensors has risen to tens of millions or even hundreds of millions, and the power consumption has also doubled with the increase in pixels. How to reduce the dynamic power consumption of image sensors is still a major technical problem of image sensors. SUMMARY

[0003] The purpose of the present application is to provide an image sensor with a dynamic low-power consumption counter architecture, which effectively reduces the redundant power consumption of the image sensor outside the effective action interval.

[0004] The present application is implemented by the following technical solutions:

[0005] The image sensor with a dynamic low-power consumption counter architecture provided by the present application embodiment comprises a phase-locked loop module, a row selection module, a pixel array, a column ADC and a timing control module,

[0006] The phase-locked loop module is used to multiply the clock signal provided by an external crystal oscillator and then provide corresponding clock signals for each module;

[0007] The row selection module is used to gate a certain row of pixels and output a pixel control signal to the pixel array;

[0008] The pixel array is used to collect the light signals of the shooting object according to the pixel control signal and output the pixel signals converted from the light signals to the column ADC;

[0009] The column ADC comprises an ADC clock generation module, a slope signal generation module, a comparator array module and a state judgment module. The ADC clock generation module is used to output a second clock signal and a third clock signal in the Rs interval and the Ss interval after processing the input first clock signal. The second clock signal is a count reference clock signal provided by a counter and a latch operation module, and the third clock signal is a slope reference clock signal provided by a slope signal generation module;

[0010] The slope signal generation module is configured to output a slope reference signal according to a third clock signal and input the slope reference signal to the comparator array module.

[0011] The comparator array module is configured to compare the pixel signal and the slope reference signal to obtain a comparator output signal.

[0012] The state judgment module is configured to output a first state switching signal and a second state switching signal according to the comparator output signal, the first state switching signal being configured to control the counter and the latch operation array module, and the second state switching signal being configured to control the ADC clock generation module, the slope signal generation module and the comparator array module.

[0013] The timing control module provides timing control signals for normal operation of the image sensor.

[0014] Further, the column ADC further comprises a counter and latch operation array module, the counter and latch operation array module adopting a structure of multiple columns sharing a counter unit, comprising a counter unit and a latch operation unit, and a count output of one counter unit being simultaneously supplied to multiple latch operation units.

[0015] The counter unit counts along with the second clock signal when the pixel signal and the slope reference signal are compared, and when the size relationship between the pixel signal and the slope reference signal is reversed, the comparator output signal is flipped, triggering the latch operation unit to latch the count value of the comparator output signal flipping time, and the counter obtains a real-time count value by counting the time length.

[0016] The latch operation unit is connected with the comparator array module, and when a column comparator output signal is flipped in the Rs interval and the Ss interval, the latch operation unit latches the real-time count value input by the counter unit at the current time point.

[0017] Further, the state judgment module comprises multiple first-level state judgment units and a second-level state judgment circuit, the first-level state judgment unit being configured to output a first state switching signal to the second-level state judgment circuit and the counter unit circuit according to an input enable signal and a comparator output signal.

[0018] The second-level state judgment circuit outputs a second state switching signal according to an input enable signal and a first state switching signal.

[0019] Further, the first stage state judging unit is composed of a plurality of OR gates connected in series, the number of OR gates is the same as the number of common columns of each counter unit, one input end of each OR gate is connected with the output signal of the corresponding column of comparator, the other input end of the first OR gate is connected with the enable signal, the output end of the first OR gate is used as the input end of the next OR gate, and the output result of the last OR gate is used as the first state switching signal.

[0020] Further, the second stage state judging circuit is composed of a plurality of OR gates connected in series, the number of OR gates is the same as the number of corresponding counter units, one input end of each OR gate is connected with the first state switching signal, the other input end of the first OR gate is connected with the enable signal, the output end of the first OR gate is used as the input end of the next OR gate, and the output result of the last OR gate is used as the second state switching signal.

[0021] Further, when the input enable signal is high level, the state judging module is in the closed or reset state, one end of the first segment of the OR gate of each unit of the first stage state judging unit and the first segment of the OR gate of the second stage state judging circuit is set to high level, the first state switching signal output by the first stage state judging circuit and the second state switching signal output by the second stage state judging circuit are both high level, and the power consumption of the column ADC remains in the normal state.

[0022] Further, when the input enable signal is low level, the state judging module is in the effective state, when the output signal of the comparator is all high level, the first state switching signal output by each first stage state judging unit is high level due to the existence of high level input in each OR gate in the first stage state judging unit, the first state switching signal is input to the second stage state judging circuit, the second state switching signal output by the second stage state judging circuit is high level due to the existence of high level input in each OR gate in the second stage state judging circuit, and the power consumption of the column ADC remains in the normal state.

[0023] Further, when the input enable signal is low level, the state judging module is in the effective state, when the output signal of the comparator is partially set to low level, and the output signal of the comparator corresponding to each first stage state judging unit is not all set to low level, the first state switching signal output by each first stage state judging unit is high level due to the existence of high level input in some OR gates in each unit, the first state switching signal is input to the second stage state judging circuit, the second state switching signal output by the second stage state judging circuit is high level due to the existence of high level input in each OR gate in the second stage state judging circuit, and the power consumption of the column ADC remains in the normal state.

[0024] Further, when the input enable signal is low, the state judging module is in effect state, when the comparator output signal is partially set from high level to low level, the comparator output signal corresponding to the partial first level state judging unit is set to low level, the first state switching signal output by the first level state judging unit is set to low level, the first state switching signal is input to the second level state judging circuit, the input of the second level state judging circuit is high level, the second state switching signal output by the second level state judging circuit is high level, in this state, the column ADC enters the first low power consumption state, the power consumption of the ADC clock generation module, the slope signal generation module and the comparator array module remains normal state.

[0025] Further, when the input enable signal is low, the state judging module is in effect state, the comparator output signal is set from high level to low level, the comparator output signal corresponding to the first level state judging unit is set to low level, the input of the or gate in the partial unit in the first level state judging circuit is low level, the first state switching signal output by the first level state judging unit is set to low level, the first state switching signal is input to the second level state judging circuit, the input of the second level state judging circuit is low level, the second state switching signal output by the second level state judging circuit is low level, in this state, the column ADC enters the second low power consumption state, the first state switching signal is low level, all the counter units stop working, the second state switching signal is low level, in this state, the ADC clock generation module, the slope signal generation module and the comparator array module enter the low power consumption mode.

[0026] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0027] The image sensor with dynamic low power consumption counter architecture provided by the embodiment of the present application can identify the reading state of the pixel by the column ADC, the speed of the corresponding comparator sampling flip time is different according to the brightness of the picture, the judgment result is obtained according to the actual comparator output signal flip state, so that the redundant power consumption generated in the interval of the effective reading action in the pixel reading process of the column ADC is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor. In the drawings:

[0029] Figure 1 A structural schematic diagram of an image sensor with a dynamic low-power consumption counter architecture provided by the first embodiment of the present application;

[0030] Figure 2 An action process schematic diagram of a normal action mode of the column ADC in the embodiment of the present application;

[0031] Figure 3 A structural schematic diagram of a state judging module and a counter latch operation array module in the embodiment of the present application;

[0032] Figure 4 A structural schematic diagram of the state judging module;

[0033] Figure 5 An internal structural schematic diagram of the state judging module;

[0034] Figure 6 A structural schematic diagram of the first stage state judging unit;

[0035] Figure 7 A MOS transistor structural schematic diagram of the OR gate;

[0036] Figure 8 A control timing diagram of the first stage state judging unit;

[0037] Figure 9 A structural schematic diagram of the second stage state judging circuit;

[0038] Figure 10 A control timing diagram of the second stage state judging circuit;

[0039] Figure 11 (A) in the figure is an internal structural schematic diagram of the clock control module;

[0040] Figure 11 (B) in the figure is a circuit structural schematic diagram of the LATCH circuit LT0 in the clock control module;

[0041] Figure 12 An action timing diagram of the clock control module;

[0042] Figure 13 A structural schematic diagram of the counter unit in the embodiment of the present application;

[0043] Figure 14 A structure schematic diagram of an ADC clock generation module in the embodiment of the present application is shown in the figure;

[0044] Figure 15 A power consumption schematic diagram of an image sensor with a dynamic low-power consumption counter architecture provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present application more clear and explicit, the present application is further described in detail below in combination with embodiments and drawings, the illustrative embodiments of the present application and the description thereof are only used to explain the present application, and do not limit the present application.

[0046] In the image sensor design stage, the interval length of the Rs interval and the Ss interval is designed with a certain margin, but the maximum range is needed to exclude a small part of extreme cases. Under most light scenes, the range of the ADC will have a certain redundancy. In the Rs interval and the Ss interval of the image sensor, the counter array in the column ADC completes the latching of all column count values, and the counter still keeps following the clock signal. In addition, the entire ADC clock path and the comparator array and the slope signal generation module also keep acting until the end of the Rs / Ss interval. Since the column ADC action has been essentially completed at this time, the power consumption of this part is wasted. The embodiment of the present application proposes a structure of an ADC action state judgment circuit and a systematic control scheme for other related circuits, aiming to reduce the redundant power consumption of the image sensor except the effective action interval as much as possible.

[0047] As shown in the figure, Figure 1 The basic working principle of the image sensor with a dynamic low-power consumption counter architecture provided by the first embodiment of the present application is a device for converting a light signal into a digital electronic signal. Based on a single-slope analog-to-digital converter architecture, the image sensor 100 includes a pixel array 200, a column ADC 300, a row selection module 400, a phase-locked loop module 500, a timing control module 600 and a digital signal processing and output module 700. The column ADC 300 includes a comparator array module 301, a state judgment module 302, a counter and latch operation array module 303, a slope signal generation module 304 and an ADC clock generation module 305. As the core part of the image sensor to complete the light signal quantization process, the power consumption of the column ADC accounts for a large part of the total power consumption of the image sensor. In order to reduce the power consumption of the column ADC, the embodiment of the present application adds a state judgment module to the usual image sensor structure to realize the low-power consumption of the column ADC according to different states.

[0048] The image sensor includes a clock system, which is provided with a reference low-speed clock CK0 by an oscillator outside the chip, and after frequency multiplication by the phase-locked loop module 500, clock signals used by each part are provided, including but not limited to the following clock signals: the first clock signal CK1 for the ADC clock generation module, the first clock signal CK1 being a high-speed clock signal, and the medium-speed clock signal CK4 for the timing control module. CK1 outputs the high-speed clock signals second clock signal CK2 and third clock signal CK3 that only act in the Rs stage and Ss interval after passing through the ADC clock generation module. The second clock signal CK2 provides a counting reference clock signal for the counter and latch operation module 303, and the third clock signal CK3 provides a slope reference clock signal for the slope signal generation module 304.

[0049] As Figure 2 shown, it is the action process diagram of the normal action mode of the column ADC of the image sensor. The image sensor in the embodiment of the application adopts a CDS (Correlated Double Sampling) mode for sampling processing, and the main sampling quantization process includes the Rs stage (Reset Sampling Phase) and the Ss stage (Signal Sampling Phase). The row selection module 400 outputs the pixel control signal Tx / Rx / Sx signal connected to the pixel array. When the row selection module 400 selects a row of pixels, the amount of light signal received by the pixel array 100 is converted into the pixel signal Vpix signal output to the column ADC 300. The timing control module provides timing control signals for the normal operation of the image sensor.

[0050] The slope signal generation module 304 outputs the slope reference signal Vramp output to the comparator array module 301 according to the third clock signal CK3. The comparator array module 301 compares the pixel signal Vpix and the reference slope signal Vramp, and the reference slope signal presents a certain slope decline in the time axis. At the same time of comparison, the counter counts with CK2. When the size relationship between the pixel signal Vpix and the reference signal Vramp is reversed, the comparator output signal Vcomp flips, triggering the latch in the counter and latch operation array module 303 to latch the count value of the Vcomp flip time. The counter quantizes the pixel signal by counting the time length (Time to Count).

[0051] As Figure 3This is a schematic diagram of the state judgment module and the counter latching operation array module in an embodiment of the present invention. The counter and latching operation array module 303 adopts the structure of a multi-column shared counter unit, which is currently mainstream in large-pixel-scale image sensors. That is, the count CNT*[x:0] output by one counter unit 3031 is simultaneously supplied to n column latching operation unit modules 3032, where n is typically set to several hundred, commonly around 500. The multi-column shared counter unit structure is a widely adopted counter architecture to address the increasing pixel count, compared to the traditional scheme of one counter per column, in order to reduce power consumption and increase operation frequency. The embodiments of the present invention propose a systematic solution based on this multi-column shared counter architecture, with the aim of further reducing power consumption.

[0052] The counter unit follows the second clock signal CK2 to perform counting operations in the Rs and Ss intervals, and outputs a real-time count value CNT*[x:0] of x+1 bits to the latching operation unit. The latching operation unit is connected to the output signal Vcomp of the comparator array module 301. When a column of comparator outputs reverses from high to low within the Rs and Ss intervals, the latching operation unit latches the count value of the counter unit at the current time point. In normal mode, the counter unit continues counting until the Rs and Ss intervals end.

[0053] like Figure 3 As shown, in this embodiment of the invention, a state judgment module 302 is added before the counter and latch operation array module 303. The output signal Vcomp of the comparator array module 301 is input to the state judgment module 302, and the state judgment module 302 outputs a first state switching signal S1 and a second state switching signal S2. The first state switching signal S1 is an m-bit enable signal, where m is the number of counter units divided in the counter and latch operation array module 303. For example, in a module with 4000 columns, where each counter shares 500 columns, m is 8. The first state switching signal S1 is connected to the corresponding numbered counter unit and controls it; the second state switching signal S2 is connected to the ADC clock generation module 305, the ramp signal generation module 304, and the comparator array module 301 and controls them.

[0054] Figure 4 This is a schematic diagram of the state judgment module 302, which includes m first-level state judgment units 3021 and a second-level state judgment circuit 3022. Figure 5 This is a schematic diagram of the internal structure of the status judgment module 302.

[0055] The first stage state judging unit 3021 inputs the enable signal LPEN and the comparator output signal Vcomp, and outputs the m-bit first state switching signal S1 to the second stage state judging circuit 3022 and the counter unit circuit 3031. In addition, the first stage state judging unit 3021 is divided into m parts according to the number of the counter units, and the number of the comparator output signals Vcomp connected to each first stage state judging unit corresponds to the number of the common columns of the corresponding counter. For example, the first stage state judging unit 0 is connected to the comparator output signals Vcomp[0]~[n-1] of the common column corresponding to the counter unit 0, and the first stage state judging unit m-1 is connected to the comparator output signals Vcomp[mn-n]~[mn-1] of the common column corresponding to the counter unit m. Each first stage state judging unit outputs a first state switching signal S1 to control the corresponding counter unit. The function realized is that when the n comparator output signals Vcomp corresponding to the first stage state judging unit all flip from high level to low level, the output first state switching signal S1 of the unit is low, and the low level state of the first state switching signal S1 enables the corresponding counter unit to stop counting. The enable signal LPEN and the output first state switching signal S1 of the first stage state judging unit 3021 are input to the second stage state judging circuit 3022, and the second stage state judging circuit 3022 outputs a second state switching signal S2.

[0056] Figure 6 The structure of the first stage state judging unit is shown in the figure, which corresponds to the number n of the common columns of each counter. Each first stage state judging unit 3021 is composed of n OR gates. The MOS structure of the OR gate is shown in the figure. Figure 7 As shown in the figure, one input end IN1 of each OR gate is connected to the comparator output signal Vcomp of the corresponding column, the first input end IN2 is connected to the enable signal LPEN, the second to nth input IN2 is connected to the output OUT of the previous stage, and the output of the last OR gate is the first state switching signal S1 output to the subsequent circuit (the subsequent circuit includes the counter unit and the second stage state judging circuit). According to the truth table of the OR gate, the output of the OR gate is low only when the two outputs of the OR gate are all low, otherwise the output of the OR gate is high. Therefore, the output first state switching signal S1 of the first stage state judging unit is low only when all the inputs of the OR gate are low, and the output first state switching signal S1 is high in other states.

[0057] Figure 8 The control timing of the first stage state judging unit 3021 is shown in the figure, and the action flow is as follows:

[0058] At the T0 time point, the comparator array module outputs the comparator output signal Vcomp to complete the reset from low to high with the comparator reset action.

[0059] At the T1 time point, the enable signal LPEN of the state judgment module changes from high level to low level, at which time the state judgment circuit enters the working state.

[0060] The interval from the T2 time point to the T4 time point is identified as the sampling action interval of the column ADC, during which the second clock signal CK2 and the third clock signal CK3 of the column ADC act.

[0061] During the sampling interval, the output signal Vcomp of the comparator will be flipped according to the sampling result of each column. Assuming that the n-column column ADC corresponding to the first-stage state judgment unit completes sampling at the T3 time point, that is, Vcomp[0]~[n-1] is all flipped, at which time the first state switching signal S1 output by the first-stage state judgment unit changes from high level to low level. It is indicated that the column ADC corresponding to the first-stage state judgment unit has completed sampling.

[0062] At the T5 time point, the state judgment module is reset, and according to the enable signal LPEN of the state judgment module changing from low level to high level, the first state switching signal S1 output by the first-stage state judgment unit is reset to high level.

[0063] Figure 9 The structural diagram of the second-stage state judgment circuit 3022 is shown in FIG. 3B. The second-stage state judgment circuit 3022 is composed of a plurality of OR gates connected in series, and the number of the OR gates corresponds to the number m of the counters. The MOS structure diagram of the OR gate is shown in FIG. 3C. One input end IN1 of each OR gate is connected to the output first state switching signal S1 of the first-stage state judgment circuit unit 3021, the first input end IN2 is connected to the enable signal LPEN, the second to m-th input IN2 is connected to the output OUT of the previous stage, and the output of the last OR gate is used as the state judgment result to output the second state switching signal S2 to the subsequent circuit (the subsequent circuit includes the ADC clock generation module, the slope signal generation module, and the comparator array module, etc.). According to the working principle of the OR gate, it can be obtained that only when the first state switching signal S1 input end and the LPEN end of all OR gates are set to low level, the output second state switching signal S2 of the second-stage state judgment circuit is set to low level, and the output second state switching signal S2 is high level in other states. Figure 7

[0064] Figure 10 The control timing of the second-stage state judgment circuit 3022 is shown in FIG. 3D, and the action flow is as follows:

[0065] ​At the T0 time point, the comparator array module outputs the comparator output signal Vcomp to complete the reset from low to high with the comparator reset action.

[0066] At the T1 time point, the enable signal LPEN of the state judgment module changes from high to low, and at this time, the state judgment circuit enters the working state.

[0067] The interval from the T2 time point to the T4 time point is identified as the sampling action interval of the column ADC, and the second clock signal CK2 and the third clock signal CK3 for the column ADC act in this interval.

[0068] In the sampling interval, the comparator output signal Vcomp will be flipped according to the sampling result of each column, and after each column ADC corresponding to the first-stage state judgment unit 3021 completes sampling, the output S1 of the first-stage state judgment unit 3021 is flipped immediately. Assuming that at the T3 time point, all column ADCs complete sampling, the comparator output signal Vcomp[0]~[mn-1] is flipped, at this time, the first state switching signal S1 output by the first-stage state judgment unit 3021 changes from high to low, and the second state switching signal S2 output by the second-stage state judgment circuit 3022 changes from high to low, indicating that the sampling of all column ADCs is completed.

[0069] At the T5 time point, the state judgment module 302 is reset, and according to the enable signal LPEN of the state judgment module 302 changing from low to high, the first state switching signal S1 output by the first-stage state judgment unit 3021 and the second state switching signal S2 output by the second-stage state judgment circuit 3022 are reset to high.

[0070] The state judgment module 302 has the following states, as shown in Table 1:

[0071] Table 1: Corresponding table of working states of the state judgment module

[0072]

[0073] 1) When the enable signal LPEN is high, the state judgment module is in the closed or reset state, and since one end of the first-stage or gate input of each unit of the first-stage state judgment circuit and the first-stage or gate input of the second-stage state judgment circuit is high, according to the principle of the or gate and the connection relationship, it is easy to obtain that the first-stage state judgment circuit and the second-stage state judgment circuit will output the first state switching signal S1 and the second state switching signal S2 as high regardless of the state of the comparator output signal Vcomp. In this state, the power consumption of the column ADC remains normal.

[0074] 2) When the enable signal LPEN is low, the state judging module is effective state, the comparator output signal Vcomp output is all high. First, the first level state judging unit in each or gate due to the presence of high input, output high, so that the output of each first level state judging unit first state switching signal S1 are high. First state switching signal S1 as input to the second level state judging circuit, due to the presence of high input in each or gate of the second level state judging circuit, so that the second level state judging circuit output second state switching signal S2 is high. In this state, the power consumption of the ADC remains normal state.

[0075] 3) When the enable signal LPEN is low, the state judging module is effective state, the comparator output signal Vcomp output part by high level to low, and each first level state judging unit corresponding to the comparator output is not all low. In this state, the first level state judging circuit in each unit in the individual or gate due to the presence of high input, output high, so that the output of each first level state judging unit first state switching signal S1 are still high. First state switching signal S1 as input to the second level state judging circuit, due to the presence of high input in each or gate of the second level state judging circuit, so that the second level state judging circuit output second state switching signal S2 is high. In this state, the power consumption of the ADC remains normal state.

[0076] 4) When the enable signal LPEN is low, the state judging module is effective state, the comparator output signal Vcomp output part by high level to low. Part of the first level state judging unit corresponding to the comparator output is all low. In this state, the first level state judging circuit in some units in the or gate due to the input of all low, output low, so that the output of this part of the first level state judging unit first state switching signal S1 is low, the output of the first state switching signal S1 of the remaining first level state judging unit still maintain high. First state switching signal S1 input to the second level state judging circuit, due to the presence of high input in some or gate of the second level state judging circuit, so that the second level state judging circuit output second state switching signal S2 is high. In this state, the ADC enters the first low power mode, due to part of the first state switching signal S1 is low, low state of the first state switching signal S1 signal corresponding to the counter unit will stop action, the remaining counter unit still maintain normal work. Because the second state switching signal S2 is still high, in this state, the power consumption of the ADC clock generation module and the slope signal generation module and the comparator array module remains normal state.

[0077] 5) when the enable signal LPEN is low, the state judging module is in effect, and the comparator output signal Vcomp is outputted from high to low. The comparator output corresponding to all the first stage state judging units is set to low. In this state, the or gate in some units of the first stage state judging circuit outputs low because the input is all low, so that the output first state switching signal S1 of the first stage state judging unit is set to low. The first state switching signal S1 is inputted to the second stage state judging circuit, and because the input of the second stage state judging circuit is all low, the second state switching signal S2 outputted from the second stage state judging circuit is set to low. In this state, the column ADC enters the second low power consumption mode, and because the first state switching signal S1 is low, all the counter units stop working. Because the second state switching signal S2 is low, the ADC clock generating module, the slope signal generating module and the comparator array module also enter the low power consumption state.

[0078] From the above, according to the action of the first state switching signal S1 and the second state switching signal S2 generated by the state judging module, the counter and the latch operation array module, the ADC clock generating module, the comparator array module and the slope signal generating module enter the low power consumption mode correspondingly, so that the column ADC can enter the low power consumption mode according to different states.

[0079] The state switching action in the embodiment involves the counter and the latch operation array module, the ADC clock generating module, the comparator array module and the slope signal generating module. The state switching of the counter and the latch operation array module, the ADC clock generating module and the slope signal generating module involves the stop action of the clock signal, so a clock control module is set to complete the switching of the state of the clock signal.

[0080] As shown in Figure 11 (A), the clock control module provided by the embodiment of the application comprises an input enable signal EN, an input clock CK and a state switching signal S, and outputs an enable signal ENO and an output clock signal CKO. The function is to stop outputting the clock after detecting that the input state switching signal S is from high to low, and to advance the closing action of the enable signal of the subsequent circuit, so that the subsequent circuit module stops working in advance. The internal structure of the clock control module is shown in Figure 11 (A), which is composed of a reset output LATCH circuit LT0, two NAND gate circuits NAND1 and NAND2 and two inverter circuits I1 and I2.

[0081] Figure 11 (B) is Figure 11The circuit structure of the LATCH circuit LT0 used in (A) comprises two tri-state inverters TI1 and TI2, a NAND gate NAND1 and an inverter I1. The states of the LATCH circuit are as follows:

[0082] 1) When the reset signal RST is high, the LATCH is in working state. At this time, when the CK is high, the tri-state inverter TI1 in the LATCH circuit is opened, and TI2 is closed. At this time, the input D of the LATCH can pass through TI1 and NAND1 directly, and the output Q of the LATCH circuit is equal to D.

[0083] 2) When the CK is low, the tri-state inverter TI1 in the LATCH circuit is closed, and TI2 is opened. At this time, the LATCH circuit is in holding state, and the input D cannot be transmitted to the output Q. The output Q of the LATCH circuit remains the last state of the input D.

[0084] 3) When the reset signal RST is low, the LATCH circuit is in reset state. The reset signal RST passes through the NAND gate NAND1 to make the output Q of the LATCH circuit high, and is not affected by the clock input CK and the input D.

[0085] The LATCH circuit LT0 in the clock control module plays a role of synchronizing the input signal with the clock and delaying the output. The input D end is connected with the state switching signal S, the input CK end is connected with the clock signal CK, and the input RST end is connected with the enable signal input EN. According to the states of the LATCH circuit, it can be concluded that only when the input clock CK is low, the input state switching signal S can be transmitted to the output S_MASK side of the LATCH circuit LT0. When the level state of the state switching signal S is switched from high to low or from low to high, after synchronization with the clock CK, the output signal Q of the LT0 outputs the state switching signal S_MASK synchronized with the falling edge of the clock CK.

[0086] The intermediate signal S_MASK and the EN signal pass through the combination logic composed of NAND1 and I1 to output the enable output signal ENO. The intermediate signal S_MASK and the EN signal pass through the combination logic composed of NAND1 and I1 to output the clock output signal CKO. When the intermediate signal S_MASK is high, the enable output signal ENO is equal to the enable input signal EN, and the clock output signal CKO is equal to the clock input signal CK. When the intermediate signal S_MASK is low, the enable output signal ENO and the clock output signal CKO are both low.

[0087] Figure 12 The following explains the function of the clock control module in combination with the timing diagram:

[0088] 1) At T0, the input enable signal EN changes from low to high, the clock control module enters the working mode from the reset mode.

[0089] 2) At T1~T4, the input clock signal CK, at T1, CKO starts to follow the action of CK.

[0090] 3) At T2, the state switching signal S changes from high to low, indicating that the working state is entered.

[0091] 4) At T3, the state switching signal S passes through the LATCH circuit LT0, and the state switching signal S_MASK synchronized with the falling edge of the clock signal is output. S_MASK and the clock signal CK pass through the AND logic of NAND2 and I2 combination, and the clock CKO is stopped and fixed to low level after S_MASK falls to low level. S_MASK and the input enable signal EN pass through the AND logic of NAND1 and I1 combination, and the enable signal ENO is fixed to low level after S_MASK falls to low level.

[0092] 5) At T5, the input enable signal EN changes from high to low, the LATCH circuit LT0 is reset, and S_MASK is reset to high level.

[0093] Figure 13 The structure diagram of the counter unit in the embodiment of the application is composed of a clock control module and a counter core circuit. The input signals include a second clock signal CK2, a counter enable signal CNT_EN and a first state switching signal S1 output by the first state judgment unit, and the output signal is a x-1 bit count output signal CNT. The input signals CK2, CNT_EN and S1 are input to the clock control module, and CNT_CK_IN and CNT_EN_IN are output after the clock control module processes and input to the counter core circuit. Specifically, the second clock signal CK2 of the counter is connected to the clock input end CK of the clock control module, the enable signal CNT_EN of the counter is connected to the input enable signal EN end of the clock control module, and the first state switching signal S1 is input to the S end of the clock control module. The enable signal ENO output by the clock control module is connected to the actual enable signal CNT_EN_IN end of the counter core circuit, and the clock signal CKO output is connected to the actual clock signal CNT_CK_IN end of the counter core circuit. The counter core circuit can be a binary counter or a Gray code counter commonly used in existing image sensors, and the specific structure refers to the prior art.

[0094] Figure 14The structure diagram of the ADC clock generation module is shown in Figure 1. The internal structure is composed of a clock control module and an ADC clock generation module core circuit. The input signals include an input first clock signal CK1, an enable signal ADC_CKGEN_EN and a second state switching signal S2 generated by the first clock signal CK1. The ADC clock generation module performs interception and frequency division on the clock signal CK1 output by the phase-locked loop module, and outputs a second clock signal CK2 and a third clock signal CK3 that only act in the Rs and Ss stages. The second clock signal CK2 is a reference clock provided for the counter and the latch operation array module, and the third clock signal CK3 is a reference clock provided for the slope signal generation module. The second clock signal CK2 and the third clock signal CK3 are clock signals with the same phase, but they can be clock signals with the same frequency or different frequencies according to different specific working modes.

[0095] The clock control module also generates the second state switching signal S2 according to the action timing shown in Figure 2. Figure 12 According to the action timing shown in Figure 2, the second state switching signal S2 is connected to the S terminal of the clock control module, the reference clock CK1 is connected to the CK terminal of the clock control module, and the enable signal ADC_CKGEN_EN is connected to the EN terminal of the clock control module. According to the action timing shown in Figure 2, Figure 12 After the second state switching signal S2 is switched from high to low, the first clock signal CK1 is truncated (i.e., the clock output is in a low fixed state after S2 is low), and the processed clock signal ADC_CKGEN_CK_IN is provided to the ADC clock generation module core circuit. The enable signal ENO output by the clock control module is connected to the actual enable signal ADC_GEN_EN_IN terminal of the ADC clock generation module core circuit, and the clock signal CKO output by the clock control module is connected to the actual clock signal ADC_CKGEN_CK_IN terminal of the ADC clock generation module core circuit.

[0096] Through the above switching action according to the second state switching signal S2, the ADC clock generation module can be caused to stop action in the redundant interval of the Rs stage and the Ss stage, and the power consumption is reduced. On the other hand, in the actual image sensor chip layout, the distance from the second clock signal CK2 and the third clock signal CK3 generated by the ADC clock generation module to the input end of the corresponding counter unit and the input end of the slope signal generation module will become longer and longer with the increase of the sensor scale. In order to ensure the driving ability, a sufficient number of clock signal repeaters (which can use the clock signal repeaters mentioned in CN216819967U) must be configured in the clock link, and the device size of the clock signal repeaters is often set to be relatively large in order to ensure the driving ability. Therefore, a certain power consumption will be consumed in the clock signal action interval. When the ADC clock generation module stops action in the redundant interval of the Rs stage and the Ss stage, the clock signal repeaters in the corresponding clock link also stop action. Therefore, the power consumption of the clock repeaters can also be reduced.

[0097] The overall working process of the column ADC in the embodiment of the application is as follows:

[0098] 1) The row pixel reading action starts, and the column ADC enters the reset and clear interval. The comparator works in the low-power consumption mode in the clear interval.

[0099] 2) After the clear action ends, the Rs sampling interval is entered.

[0100] 3) In the Rs sampling interval, the slope voltage signal Vramp reverses the size relationship with the pixel voltage signal Vpix after the time decreases, and the comparator output signal Vcomp flips low.

[0101] 4) In the Rs sampling interval, when the comparator output signals Vcomp of the column ADC shared by a counter unit all flip low, the first state switching signal S1 corresponding to the counter unit in the first state judgment circuit flips low. Then the counter unit stops action.

[0102] 5) When all the comparator output signals Vcomp of the columns flip low, the second state switching signal S2 output by the second state judgment circuit flips low. At this time, the ADC clock generation module stops outputting the third clock signal CK3 for slope signal generation and the second clock signal CK2 for the counter. At this time, all the counter units stop working, the slope signal generation circuit stops generating the slope and switches to the low-current high-gain mode, and the comparator array module also enters the low-power consumption mode.

[0103] 6) After the Rs sampling interval, the pixel voltage signal establishment interval is entered, the comparator output signal Vcomp is reset to high in this interval, and the output first state switching signal S1 and the second state switching signal S2 of the state judgment circuit module are reset to high. The slope signal generation module resumes the normal working mode after the second state switching signal S2 is set to high. When in this interval, the comparator array module remains in the low power consumption mode.

[0104] 7) In the Ss sampling interval, the relationship between the slope voltage signal Vramp and the pixel voltage signal Vpix is reversed after the slope voltage signal Vramp decreases with time, and the comparator output signal Vcomp is flipped to low.

[0105] 8) In the Ss sampling interval, when the comparator output signals Vcomp of the column ADC shared by a counter unit are all flipped to low, the first state switching signal S1 corresponding to the counter unit in the first stage state judgment circuit is flipped to low. Then the counter unit stops working.

[0106] 9) When all the comparator output signals Vcomp of the columns are flipped to low, the second state switching signal S2 output by the second stage state judgment circuit is flipped to low. At this time, the ADC clock generation module stops outputting the third clock signal CK3 for slope signal generation and the second clock signal CK2 for the counter. At this time, all the counter units stop working, the slope signal generation circuit stops generating the slope and switches to the low current high gain mode, and the comparator array module also enters the low power consumption mode.

[0107] 10) After the Rs sampling interval, the pixel voltage signal establishment interval is entered, the comparator output signal Vcomp is reset to high in this interval, and the output first state switching signal S1 and the second state switching signal S2 of the state judgment circuit module are reset to high. When in this interval, the slope signal generation module, the comparator array module remains in the low power consumption mode. The reading action of the column ADC to a row of pixels ends here.

[0108] The existing low-power image sensor scheme is similar to the AlwaysOn scheme, in which the super low-power picture motion monitoring mode is entered in the interval of no picture change, and the normal full-pixel motion mode is started only in the picture change state. The embodiment of the present application is a power reduction scheme for the normal full-pixel motion mode, which does not conflict with the AlwaysOn scheme, but is a further supplement to the low-power scheme, greatly reduces the redundant power consumption of the image sensor without affecting the performance, thereby reducing the power consumption in the normal working mode and further reducing the overall power consumption of the chip. The embodiment of the present application can be used alone in a conventional image sensor or can be used in combination with the super low-power image sensor using the AlwaysOn scheme. In the current era of popularization of mobile devices and Internet of Things, the devices are widely powered by batteries, so the embodiment of the present application can greatly increase the endurance time of the device and has wide application value.

[0109] Figure 15 The power consumption of the image sensor of the embodiment of the present application is shown in the figure. The embodiment of the present application distinguishes the reading state of the pixel by the column ADC, and the speed of the comparator sampling flip time is different according to the brightness of the picture. According to the judgment result of the actual comparator output signal Vcomp flip state, the redundant power consumption generated in the interval of the effective reading action of the pixel reading process by the column ADC is greatly reduced. According to the different brightness of the picture, it can be seen that in the case of low brightness, the comparator flip time is early, and the power consumption is the lowest. In the case of high brightness, the comparator flip time is late, and the power consumption is relatively high. However, since the embodiment of the present application also performs low-power mode processing on the interval outside the sampling interval of the comparator in the Rs interval and the Ss interval, even in the case of high brightness, the redundant power consumption is still greatly reduced compared with the normal mode. The actual performance of power reduction may be different according to the proportion of each action interval of the actual image sensor.

[0110] The above specific embodiments further illustrate the purpose, technical scheme and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and does not limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An image sensor having a dynamic low power counter architecture, characterized by, The application relates to an image sensor, which comprises a phase-locked loop module, a row selection module, a pixel array, a column ADC and a timing control module. The phase-locked loop module is used for frequency multiplication of a clock signal provided by an external crystal oscillator to provide corresponding clock signals for each module. The row selection module is used for selecting a row of pixels and outputting a pixel control signal to the pixel array. The pixel array is used for collecting light signals of a shooting object according to the pixel control signal and outputting pixel signals converted from the light signals to the column ADC. The column ADC comprises an ADC clock generation module, a slope signal generation module, a comparator array module and a state judgment module. The slope signal generation module is used for outputting a slope reference signal according to the third clock signal and inputting the slope reference signal to the comparator array module. The comparator array module is used for comparing the pixel signal and the slope reference signal to obtain a comparator output signal. The state judgment module is used for outputting a first state switching signal and a second state switching signal according to the comparator output signal. The first state switching signal is used for controlling the counter and the latch operation array module, and the second state switching signal is used for controlling the ADC clock generation module, the slope signal generation module and the comparator array module. The timing control module provides timing control signals for normal operation of the image sensor.

2. The image sensor with dynamic low power counter architecture of claim 1, wherein, The column ADC further comprises a counter and a latch operation array module. The counter and the latch operation array module adopts a structure of sharing a counter unit by multiple columns, and comprises a counter unit and a latch operation unit. The counter unit counts when the voltage signal and the slope reference signal are compared, and the counter is triggered to count the time when the comparator output signal is reversed and the latch operation unit latches the real-time count value input by the counter unit at the current time point.

3. The image sensor with dynamic low-power counter architecture of claim 2, wherein, The latch operation unit is connected with the comparator array module, and when the comparator output signal of a column is reversed in the Rs interval and the Ss interval, the latch operation unit latches the real-time count value input by the counter unit at the current time point. The state judgment module comprises multiple first-stage state judgment units and a second-stage state judgment circuit. The second-stage state judgment circuit outputs the second state switching signal according to the input enable signal and the first state switching signal.

4. The image sensor with a dynamic low-power counter architecture of claim 3, wherein, The first stage state judging unit is composed of a plurality of OR gates connected in series, the number of OR gates is the same as the number of common columns of each counter unit, one input end of each OR gate is connected with the output signal of the corresponding column of comparator, the other input end of the first OR gate is connected with the enable signal, the output end of the first OR gate is used as the input end of the next OR gate, and the output result of the last OR gate is used as the first state switching signal.

5. The image sensor with a dynamic low-power counter architecture of claim 4, wherein, The second stage state judging circuit is composed of a plurality of OR gates connected in series, the number of OR gates is the same as the number of corresponding counter units, one input end of each OR gate is connected with the first state switching signal, the other input end of the first OR gate is connected with the enable signal, the output end of the first OR gate is used as the input end of the next OR gate, and the output result of the last OR gate is used as the second state switching signal.

6. The image sensor with a dynamic low-power counter architecture of claim 5, wherein, When the input enable signal is high, the state judging module is in a closed or reset state, the first segment of each unit of the first stage state judging unit and the first segment of the OR gate of the second stage state judging circuit are set to high level, the first state switching signal output by the first stage state judging circuit and the second state switching signal output by the second stage state judging circuit are both high level, and the power consumption of the column ADC remains in a normal state.

7. The image sensor with a dynamic low-power counter architecture of claim 5, wherein, When the input enable signal is low, the state judging module is in an effective state, when the output signal of the comparator is all high level, the first state switching signal output by each first stage state judging unit is high level due to the existence of high level input in each OR gate in the first stage state judging unit, the first state switching signal is input to the second stage state judging circuit, the second state switching signal output by the second stage state judging circuit is high level due to the existence of high level input in each OR gate in the second stage state judging circuit, and the power consumption of the column ADC remains in a normal state.

8. The image sensor with a dynamic low-power counter architecture of claim 5, wherein, When the input enable signal is low, the state judging module is in an effective state, when the output signal of the comparator is partially set to low level, and the output signal of the comparator corresponding to each first stage state judging unit is not all set to low level, the first state switching signal output by each first stage state judging unit is high level due to the existence of high level input in some OR gates in each unit, the first state switching signal is input to the second stage state judging circuit, the second state switching signal output by the second stage state judging circuit is high level due to the existence of high level input in each OR gate in the second stage state judging circuit, and the power consumption of the column ADC remains in a normal state.

9. The image sensor with a dynamic low-power counter architecture of claim 5, wherein, When the input enable signal is low, the state judging module is in effect state, and when the comparator output signal is partially set to low from high, the comparator output signal corresponding to the partial first stage state judging unit is set to low, the first state switching signal output by the first stage state judging unit is set to low, the first state switching signal output by the rest of the first stage state judging unit remains high, the first state switching signal is input to the second stage state judging circuit, the input of the second stage state judging circuit is high, the second state switching signal output by the second stage state judging circuit is high, and the ADC in this state enters the first low power consumption state, and the power consumption of the ADC clock generating module, the slope signal generating module and the comparator array module remains normal.

10. The image sensor with a dynamic low-power counter architecture of claim 5, wherein, When the input enable signal is low, the state judging module is in effect state, and when the comparator output signal is set to low from high, the comparator output signal corresponding to the partial first stage state judging unit is set to low, the first state switching signal output by the first stage state judging unit is set to low, the first state switching signal output by the rest of the first stage state judging unit remains high, the first state switching signal is input to the second stage state judging circuit, the input of the second stage state judging circuit is low, the second state switching signal output by the second stage state judging circuit is low, and the ADC in this state enters the second low power consumption state, the first state switching signal is low, all the counter units stop working, and the second state switching signal is low, and the ADC clock generating module, the slope signal generating module and the comparator array module enter the low power consumption mode.

Images