Wafer level semiconductor package structure and method of making the same

Abstract

The embodiment of the application provides a wafer-level semiconductor packaging structure and a preparation method thereof, and relates to the technical field of photoelectric packaging.The wafer-level semiconductor packaging structure comprises an optical chip, an optical reflection layer, a plastic packaging layer and an electrical chip.Compared with the prior art, the embodiment of the application adopts a cavity structure with a side wall opening, and the optical reflection layer is formed above the cavity to reflect the optical signal, so that the optical signal can be directly conducted from the side, and therefore, a complex optical structure is not needed, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing period is shortened.Meanwhile, signal loss caused by the insufficient refractive index and light transmittance of the optical structure is avoided, the transmission signal loss is reduced, and the transmission efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photoelectric packaging, in particular to a wafer-level semiconductor packaging structure and a preparation method thereof. BACKGROUND

[0002] The light port packaging structure of the traditional photoelectric device presents a trench morphology, and the light signal needs to be conducted vertically to the light port trench. However, due to the trench morphology, the light signal receiving range is small, and the light port needs to be protected from pollution damage, so an optical lens or other optical bridging structure needs to be attached at the light port position to make an optical channel.

[0003] However, on the one hand, the optical structure needs to be designed additionally, and the structure is complex, which increases the processing difficulty and cost; on the other hand, due to the limitation of the refractive index and light transmittance of the optical structure and the material, the transmission signal loss exists when the light signal passes through the optical structure, which undoubtedly limits the transmission rate. SUMMARY

[0004] The present application aims to provide a wafer-level semiconductor packaging structure and a preparation method thereof, in which the light signal can be directly conducted from the side, without the need to make a complex optical structure, thereby reducing the transmission signal loss and improving the transmission efficiency.

[0005] In a first aspect, the present application provides a wafer-level semiconductor packaging structure, comprising:

[0006] an optical chip, one side edge of the optical chip being provided with a light port structure, the light port structure comprising a first optical surface, the first optical surface being exposed to the front surface of the optical chip and extending to the front surface edge of the optical chip;

[0007] a light reflection layer, provided on the front surface of the optical chip and corresponding to the first optical surface, and a reflection cavity being formed between the light reflection layer and the first optical surface, the reflection cavity extending to the front surface edge of the optical chip and having an optical opening, the opening direction of the optical opening being parallel to the front surface of the optical chip, the light reflection layer being configured to reflect a light signal;

[0008] a plastic encapsulation layer, provided at least on the front surface of the optical chip and covering the light reflection layer.

[0009] In an optional embodiment, the light port structure further comprises a second optical surface, the second optical surface being provided adjacent to the first optical surface and exposed to the sidewall of the optical chip, and the optical opening being joined to the second optical surface.

[0010] In an optional embodiment, the front surface edge of the optical chip further forms a light port groove, the light port groove being in communication with the optical opening, and the second optical surface being configured to constitute the sidewall of the light port groove.

[0011] In an optional embodiment, the wafer-level semiconductor package structure further comprises an electrical chip, which is disposed in the plastic encapsulation layer and electrically connected with the optical chip.

[0012] In an optional embodiment, the electrical chip is disposed on the front surface of the optical chip and electrically connected with the optical chip, the front surface of the optical chip is further provided with a conductive post, the plastic encapsulation layer is disposed on the front surface of the optical chip and covers the electrical chip and the conductive post, an end of the conductive post away from the optical chip is exposed to the plastic encapsulation layer and provided with a conductive bump, and the conductive bump is electrically connected with the optical chip through the conductive post.

[0013] In an optional embodiment, the front surface of the electrical chip is provided with a first micro bump corresponding to be soldered to the front surface of the optical chip, and the back surface of the electrical chip is exposed to the plastic encapsulation layer.

[0014] In an optional embodiment, the conductive post is arranged around the electrical chip, and the conductive post is spaced apart from the optical reflection layer.

[0015] In an optional embodiment, the wafer-level semiconductor package structure further comprises an interposer, the optical chip and the electrical chip are attached to one side surface of the interposer and electrically connected with the interposer, the plastic encapsulation layer is disposed on one side surface of the interposer and covers the optical chip and the electrical chip, the other side surface of the interposer is provided with a conductive bump, and the conductive bump is electrically connected with the interposer.

[0016] In an optional embodiment, the front surface of the electrical chip is provided with a first micro bump corresponding to be soldered to one side surface of the interposer, and the back surface of the electrical chip is exposed to the plastic encapsulation layer; the front surface of the optical chip is provided with a second micro bump corresponding to be soldered to one side surface of the interposer, and the back surface of the optical chip is exposed to the plastic encapsulation layer.

[0017] In an optional embodiment, the wafer-level semiconductor package structure further comprises a first redistribution layer and a second redistribution layer, the first redistribution layer is disposed on the front surface of the optical chip, the second redistribution layer is disposed on the back surface of the optical chip, and the first redistribution layer and the second redistribution layer are electrically connected, the electrical chip is attached to the first redistribution layer and electrically connected with the first redistribution layer, the plastic encapsulation layer is disposed on the front surface of the optical chip and covers the first redistribution layer and the electrical chip, and the second redistribution layer is further provided with a conductive bump away from one side of the first redistribution layer, and the conductive bump is electrically connected with the second redistribution layer.

[0018] In an optional embodiment, the optical chip is further provided with a conductive via filled with a conductive material, and the first redistribution layer is electrically connected with the second redistribution layer through the conductive via.

[0019] In an optional embodiment, the front surface of the electrical chip is provided with a first micro bump corresponding to be welded to the first redistribution layer, and the back surface of the electrical chip is exposed to the plastic encapsulation layer.

[0020] In an optional embodiment, the wafer-level semiconductor encapsulation structure further comprises a substrate, and the conductive bump is corresponding to be welded to the substrate.

[0021] In a second aspect, the present application provides a method for preparing a wafer-level semiconductor encapsulation structure, which is used to prepare the wafer-level semiconductor encapsulation structure as described in the foregoing embodiments, and the method comprises:

[0022] providing a wafer with a plurality of optical chips, wherein each of the optical chips is provided with an optical port structure and an optical port groove, the optical port structure comprises a first optical surface, the first optical surface is exposed to the front surface of the optical chip and extends to the optical port groove;

[0023] forming a protective layer covering the optical port structure and the optical port groove on the front surface of the optical chip;

[0024] forming an optical reflection layer on the protective layer, wherein the optical reflection layer corresponds to the optical port structure;

[0025] preparing a plastic encapsulation layer covering at least the optical reflection layer and the front surface of the optical chip;

[0026] cutting the plastic encapsulation layer to form a first cut, wherein the first cut corresponds to the optical port groove and exposes the optical reflection layer;

[0027] blind cutting the optical chip to form a second cut, wherein the second cut corresponds to the optical port groove and exposes the protective layer;

[0028] removing the protective layer to form a reflection cavity between the optical reflection layer and the first optical surface;

[0029] breaking the optical reflection layer along the optical port groove by a dicing process.

[0030] In an optional embodiment, the step of preparing a plastic encapsulation layer covering at least the optical reflection layer and the front surface of the optical chip comprises:

[0031] forming a conductive column on the front surface of the optical chip;

[0032] welding an electrical chip on the front surface of the optical chip;

[0033] forming a plastic encapsulation layer on the front surface of the optical chip, wherein the plastic encapsulation layer covers the conductive column, the electrical chip, the optical reflection layer and the front surface of the optical chip;

[0034] thinning the plastic encapsulation layer and exposing the conductive column;

[0035] forming a conductive bump on the conductive column.

[0036] In an optional embodiment, the step of preparing the plastic encapsulation layer covering at least the optical reflection layer and the front surface of the optical chip comprises:

[0037] cutting the wafer into a plurality of optical chips;

[0038] forming an intermediate layer on a glass slide;

[0039] soldering the optical chip and the electrical chip on the intermediate layer;

[0040] forming a plastic encapsulation layer on the intermediate layer, wherein the plastic encapsulation layer covers the optical reflection layer, the optical chip and the electrical chip;

[0041] removing the glass slide;

[0042] forming a conductive bump on the side of the intermediate layer away from the plastic encapsulation layer.

[0043] In an optional embodiment, the optical chip is internally made with a conductive via hole filled with conductive material, and before the step of preparing the plastic encapsulation layer covering at least the optical reflection layer and the front surface of the optical chip, the method further comprises:

[0044] forming a first redistribution layer on the front surface of the optical chip;

[0045] thinning the back surface of the optical chip and exposing the conductive via hole;

[0046] forming a second redistribution layer on the back surface of the optical chip, wherein the second redistribution layer is electrically connected with the first redistribution layer through the conductive via hole;

[0047] forming a conductive bump on the second redistribution layer.

[0048] In an optional embodiment, the step of preparing the plastic encapsulation layer covering at least the optical reflection layer and the front surface of the optical chip comprises:

[0049] soldering the electrical chip on the first redistribution layer;

[0050] forming a plastic encapsulation layer on the front surface of the optical chip, wherein the plastic encapsulation layer covers the electrical chip, the first redistribution layer and the optical reflection layer.

[0051] The beneficial effects of the embodiments of the present application include:

[0052] The wafer-level semiconductor package structure and the preparation method thereof provided by the embodiments of the present application are provided with an optical port structure at one side edge of an optical chip, a first optical surface of the optical port structure is exposed to a front surface of the optical chip and extends to an edge of the front surface of the optical chip. Meanwhile, a light reflection layer corresponding to the first optical surface is also provided on the front surface of the optical chip, a reflection cavity is formed between the light reflection layer and the first optical surface, the reflection cavity extends to the edge of the front surface of the optical chip, and an optical opening is formed, the opening direction of the optical opening is parallel to the front surface of the optical chip, that is, a side opening is formed. The light reflection layer is covered by a plastic encapsulation layer, the light reflection layer can reflect optical signals, and the transmission of the optical signals between the first optical surface and the optical opening is realized.

[0053] Compared with the prior art, the wafer-level semiconductor package structure and the preparation method thereof provided by the embodiments of the present application adopt a cavity structure with a side wall opening, a light reflection layer is formed above the cavity to reflect optical signals, so that the optical signals can be directly conducted from the side, and therefore, a complex optical structure does not need to be made, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing period is shortened. Meanwhile, signal loss caused by insufficient refractive index and light transmittance of the optical structure is avoided, the transmission signal loss is reduced, and the transmission efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0055] Figure 1 The schematic diagram of the wafer-level semiconductor package structure provided by the first embodiment of the present application is shown in the figure.

[0056] Figures 2 to 14 The process flow schematic diagram of the preparation method of the wafer-level semiconductor package structure provided by the first embodiment of the present application is shown in the figure.

[0057] Figure 15 The schematic diagram of the wafer-level semiconductor package structure provided by the second embodiment of the present application is shown in the figure.

[0058] Figures 16 to 24 The process flow schematic diagram of the preparation method of the wafer-level semiconductor package structure provided by the second embodiment of the present application is shown in the figure.

[0059] Figure 25 The schematic diagram of the wafer-level semiconductor package structure provided by the third embodiment of the present application is shown in the figure.

[0060] Figures 26 to 34 A process flow diagram of a preparation method of a wafer-level semiconductor package structure provided by a third embodiment of the present application is shown.

[0061] Figure: 100-wafer-level semiconductor package structure; 110-optical chip; 111-optical port structure; 112-first optical surface; 113-second optical surface; 114-optical port groove; 115-second micro bump; 116-conductive via; 120-optical reflection layer; 121-reflection cavity; 122-optical opening; 130-molding layer; 140-electrical chip; 141-first micro bump; 150-conductive column; 151-conductive bump; 160-intermediate layer; 170-first redistribution layer; 180-second redistribution layer; 200-protection layer; 300-first cutout; 400-second cutout; 600-glass slide. DETAILED DESCRIPTION

[0062] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0063] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0064] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0065] In the description of the present application, it should be noted that if the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is used, which is merely for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, therefore, it cannot be understood as a limitation on the present application.

[0066] In addition, if the terms "first", "second" and the like appear, they are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0067] As disclosed in the background art, the light port packaging structure of the conventional optoelectronic device, as disclosed in CN119095A, has a trench-shaped light port with the opening of the trench facing upward, and the light signal needs to be conducted vertically to the trench of the light port. However, due to the trench-shaped light port, the light signal receiving range is small, and the light port needs to be protected from pollution damage, so an optical lens or other optical bridging structure (collectively referred to as an optical structure) needs to be attached at the position of the light port to make an optical channel.

[0068] However, on the one hand, the optical structure needs additional design, and the structure is complex, which increases the processing difficulty and cost; on the other hand, due to the limitation of the refractive index and light transmittance of the optical structure and the material, the transmission signal loss exists when the light signal passes through the optical structure, and the signal loss is usually large, which undoubtedly limits the transmission rate.

[0069] To solve the above problems, the embodiments of the present application provide a novel wafer-level semiconductor packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0070] First embodiment

[0071] Referring to Figure 1 The embodiments of the present application provide a wafer-level semiconductor packaging structure 100, which can directly conduct light signals from the side without the need to make a complex optical structure, reducing the manufacturing difficulty and processing cost, and shortening the processing cycle. At the same time, it also avoids the signal loss caused by the insufficient refractive index and light transmittance of the optical structure, can reduce the transmission signal loss, and improves the transmission efficiency.

[0072] The wafer-level semiconductor packaging structure 100 provided by the embodiments of the present application includes an optical chip 110, an optical reflection layer 120, a plastic packaging layer 130, and an electrical chip 140. One side edge of the optical chip 110 is provided with a light port structure 111, and the light port structure 111 includes a first optical surface 112. The first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the front surface edge of the optical chip 110. The optical reflection layer 120 is arranged on the front surface of the optical chip 110 and corresponds to the first optical surface 112. A reflection cavity 121 is formed between the optical reflection layer 120 and the first optical surface 112. The reflection cavity 121 extends to the front surface edge of the optical chip 110 and has an optical opening 122. The opening direction of the optical opening 122 is parallel to the front surface of the optical chip 110. The optical reflection layer 120 is configured to reflect light signals. The plastic packaging layer 130 is arranged on the front surface of the optical chip 110 and covers the optical reflection layer 120. The electrical chip 140 is arranged in the plastic packaging layer 130 and electrically connected to the optical chip 110.

[0073] It should be noted that the front surface of the optical chip 110 in this embodiment refers to the surface of the optical chip 110 having electrical contact pads, which is electrically connected through the front surface, wherein the optical port structure 111 refers to the part of the optical chip 110 for realizing the input / output of the optical signal, which is located at the edge area of the front surface of the optical chip 110. The reflective cavity 121 can be formed between the light reflecting layer 120 and the first optical surface 112, and the reflective cavity 121 has a lateral opening optical opening 122, so as to realize a lateral opening cavity structure, and the light reflecting layer 120 is used to reflect the optical signal, so that the optical signal can be directly conducted laterally, without the need to make a complex optical structure, the structure is simple, the manufacturing difficulty and processing cost are reduced, and the processing cycle is shortened. At the same time, it also avoids the signal loss caused by the insufficient refractive index and light transmittance of the optical structure, reduces the transmission signal loss, and improves the transmission efficiency.

[0074] Further, the optical port structure 111 further comprises a second optical surface 113, which is arranged adjacent to the first optical surface 112 and exposed to the side wall of the optical chip 110, and the optical opening 122 is connected to the second optical surface 113. Specifically, the second optical surface 113 is perpendicular to the first optical surface 112, wherein the second optical surface 113 is exposed to the side wall of the optical chip 110 along the vertical direction, and the first optical surface 112 is exposed to the front surface of the optical chip 110 along the horizontal direction, and the range of the first optical surface 112 is limited within the reflective cavity 121. The first optical surface 112 and the second optical surface 113 can both realize the conduction of the optical signal, and since the second optical surface 113 is directly exposed to the side wall of the optical chip 110, the lateral conduction of the optical signal can be directly realized, avoiding signal loss. It should be noted that the first optical surface 112 and the second optical surface 113 can both realize the lateral conduction of the optical signal, further reducing the transmission signal loss and improving the transmission efficiency.

[0075] In this embodiment, the front surface edge of the optical chip 110 is further formed with an optical port groove 114, the optical port groove 114 is in communication with the optical opening 122, and the second optical surface 113 is configured to constitute the side wall of the optical port groove 114. Specifically, the second optical surface 113 can be inwardly limited relative to the side wall of the optical chip 110 and constitute the side wall of the optical port groove 114 close to the optical port structure 111. The arrangement of the optical port groove 114 can avoid damage to the second optical surface 113 during the formation of the single optical chip 110, ensuring the integrity and optical conduction performance of the second optical surface 113.

[0076] In the embodiment, the electric chip 140 is arranged on the front surface of the optical chip 110 and electrically connected with the optical chip 110, the front surface of the optical chip 110 is further provided with the conductive column 150, the plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the electric chip 140 and the conductive column 150, the conductive column 150 is exposed to the plastic encapsulation layer 130 at an end away from the optical chip 110 and is provided with the conductive bump 151, the conductive bump 151 is electrically connected with the optical chip 110 through the conductive column 150. Specifically, the electric chip 140 is attached to the front surface of the optical chip 110, the optical chip 110 is electrically connected with the outside through the conductive column 150 and the conductive bump 151, and the optoelectronic co-encapsulation structure is realized through the plastic encapsulation layer 130.

[0077] Further, the front surface of the electric chip 140 is provided with the first micro bump 141, the first micro bump 141 is welded to the front surface of the optical chip 110, and the back surface of the electric chip 140 is exposed to the plastic encapsulation layer 130. Specifically, the electric chip 140 can be flip-chip welded on the front surface of the optical chip 110 through a TCB (Thermocompression Bonding) or FC (Flip Chip) process and face-to-face attached with the optical chip 110. Since the electric chip 140 and the optical chip 110 can realize face-to-face vertical interconnection, high-speed transmission can be realized, the demand of high-speed optical transmission can be met, and the product performance can be improved.

[0078] In the embodiment, the conductive column 150 is arranged around the electric chip 140, and the conductive column 150 is arranged spaced apart from the light reflection layer 120. Specifically, the electric chip 140 can be multiple and attached to the middle region of the front surface of the optical chip 110, the conductive column 150 can be multiple, and the multiple conductive columns 150 are arranged around the multiple electric chips 140, and the specific number and distribution mode can be determined according to the circuit arrangement of the optical chip 110. The conductive column 150 is also arranged spaced apart from the light reflection layer 120 to avoid affecting the light port structure 111.

[0079] It should be noted that the wafer-level semiconductor packaging structure 100 provided by the embodiment of the present application can also be attached to a substrate or a PCB through an FC process, and the conductive bump 151 on the conductive column 150 can be welded to the substrate.

[0080] The embodiment of the present application further provides a preparation method of the wafer-level semiconductor packaging structure 100, which is used for preparing the wafer-level semiconductor packaging structure 100 described above, and the preparation method comprises the following steps:

[0081] S1: providing a wafer with multiple optical chips 110.

[0082] For reference Figure 2Each of the optical chips 110 is provided with an optical port structure 111 and an optical port groove 114, the optical port structure 111 includes a first optical surface 112 and a second optical surface 113, the first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the optical port groove 114, and the second optical surface 113 can constitute a side wall of the optical port groove 114 on the side close to the optical port structure 111.

[0083] It should be noted that one of the optical chips 110 is taken as an example to illustrate the entire process in the embodiment, and it can be understood that the wafer can be a PIC wafer (Photonic Integrated Circuit), and the wafer is formed with a plurality of optical chip 110 structures through a pre-process.

[0084] S2: Forming a protective layer 200 covering the optical port structure 111 and the optical port groove 114 on the front surface of the optical chip 110.

[0085] Referring to Figure 3 Specifically, the protective layer 200 can be a polyimide material, and the protective layer 200 only covers the optical port structure 111 and the optical port groove 114, and exposes other areas of the front surface of the optical chip 110. In actual preparation of the protective layer 200, a multifunctional polyimide glue can be first filled on the front surface of the optical chip 110 and the optical port groove 114 by a gluing process to protect the optical port structure 111 and the optical port groove 114, and the glue material can only be affected by a special developing liquid such as TMAH (Tetramethylammonium hydroxide). Then a photoresist layer is processed and patterned on the area above the optical port structure 111 and the optical port groove 114 by a photoetching process, and the photoresist layer protects the underlying multifunctional polyimide glue from being removed by the developing liquid. Then the polyimide layer outside the photoresist pattern layer is removed by a developing process using the developing liquid. Finally, the photoresist is removed by a photoetching process, leaving the protective layer 200.

[0086] S3: Forming an optical reflection layer 120 on the protective layer 200.

[0087] Referring to Figure 4The light reflection layer 120 corresponds to the light port structure 111. Specifically, the light reflection layer 120 can be a silicon dioxide layer deposited on the front surface of the protection layer 200 and the optical chip 110. In actual preparation, the light reflection layer 120 can be first deposited on the entire surface by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process; then a photoresist pattern is processed on the region above the light port structure 111 by a photolithography process, which protects the underlying light reflection layer 120 from being removed by RIE (Reactive Ion Etching) etching; finally, the regions except the pattern protected by the photoresist are developed and removed by the RIE etching process, and the photoresist is removed, thereby forming the light reflection layer 120 covered on the protection layer 200.

[0088] After the preparation of the light reflection layer 120 is completed, the plastic encapsulation layer 130 covering at least the light reflection layer 120 and the front surface of the optical chip 110 can be prepared, and the following steps can be performed.

[0089] S4: Forming a conductive column 150 on the front surface of the optical chip 110.

[0090] Referring to Figure 5 Specifically, the conductive column 150 can be a copper column, which can be processed by a photolithography and electroplating process to form a high copper column, thereby forming the conductive column 150. The height of the conductive column 150 is greater than the protruding height of the light reflection layer 120 and corresponds to the connection pad of the front surface region of the optical chip 110, which can realize the electrical conduction of the optical chip 110. Moreover, the conductive column 150 can be used to form a mounting area.

[0091] S5: Soldering the electrical chip 140 on the front surface of the optical chip 110.

[0092] Referring to Figure 6 Specifically, the electrical chip 140 can be soldered on the PIC wafer by a TCB (Thermocompression Bonding) or FC (Flip Chip) process, that is, soldered on the front surface of the optical chip 110, thereby realizing the face-to-face vertical interconnection between the electrical chip 140 and the optical chip 110.

[0093] S6: Forming a plastic encapsulation layer 130 on the front surface of the optical chip 110.

[0094] Referring to Figure 7 The plastic encapsulation layer 130 covers the conductive column 150, the electrical chip 140, the light reflection layer 120, and the front surface of the optical chip 110. Specifically, a wafer-level plastic encapsulation process can be used to encapsulate the wafer.

[0095] S7: thinning the plastic sealing layer 130 and exposing the conductive column 150.

[0096] Referring to Figure 8 , specifically, the plastic sealing layer 130 of the wafer can be thinned by a grinding process, and the copper column is exposed for subsequent processing. It should be noted that the height of the conductive column 150 can be the same as the height of the electric chip 140, so that the back of the conductive column 150 and the electric chip 140 can be exposed after grinding.

[0097] S8: Forming a conductive bump 151 on the conductive column 150.

[0098] Referring to Figure 9 , specifically, the conductive bump 151 is formed on the conductive column 150 by using a photoetching and electroplating process, which is used for welding with the PCB.

[0099] S9: Thinning the wafer.

[0100] Referring to Figure 10 , specifically, the PIC wafer can be thinned by a grinding process, that is, the back of the optical chip 110 is thinned.

[0101] S10: Cutting the plastic sealing layer 130 to form a first cutout 300.

[0102] Referring to Figure 11 , the first cutout 300 corresponds to the light slot 114 and exposes the light reflecting layer 120. Specifically, the wafer-level laser slotting process can be used to remove the plastic sealing material above the light reflecting layer 120 and stop on the surface of the light reflecting layer 120 to form the first cutout 300. The first cutout 300 can be precisely aligned with the light slot 114 by determining the cutting position through the pre-prepared alignment mark during actual preparation.

[0103] S11: Forming a second cutout 400 by hidden cutting the optical chip 110.

[0104] Referring to Figure 12 , the second cutout 400 corresponds to the light slot 114 and exposes the protective layer 200. Specifically, the PIC wafer at the bottom is cut along the light slot 114 position by using a hidden cutting process, thereby forming the second cutout 400. The second cutout 400 is aligned with the first cutout 300 and can expose the protective layer 200 located in the light slot 114.

[0105] Stealth Dicing (SD) is an advanced wafer cutting technology, mainly used for singulating chips on a wafer (i.e., cutting into independent chips). Unlike traditional mechanical blade cutting or laser ablation cutting, it achieves separation in a "stealthy" way, using infrared laser to form a modified layer inside the wafer, and then using mechanical stretching, thermal stress or film expansion to make the wafer separate along the modified layer, so that the chips are singulated, thereby significantly improving the strength, quality and production efficiency of the chips.

[0106] S12: Remove the protective layer 200 to form a reflection cavity 121 between the light reflection layer 120 and the first optical surface 112.

[0107] Referring to Figure 13 , specifically, through the development process, the exposed multifunctional polyimide glue is removed along the second cut 400 using a special developing solution, thereby forming a side wall open reflection cavity 121. The light reflection layer 120 is made above the reflection cavity 121 to reflect the light signal, so that the light signal can be directly conducted from the side after the subsequent process is completed, without the need to make a complex optical structure, avoiding signal loss due to insufficient refractive index and light transmission rate of the optical structure.

[0108] S13: The light reflection layer 120 is disconnected along the light port groove 114 by a splitting process.

[0109] Referring to Figure 14 , specifically, the light reflection layer 120 can be processed again using the stealth cutting + splitting process, and specifically, the film expansion method can be used to disconnect the light reflection layer 120, thereby preparing a single optical chip 110 and completing the process of the wafer-level semiconductor packaging structure 100.

[0110] Finally, the wafer-level semiconductor packaging structure 100 can be soldered on a PCB board or a substrate through an FC process.

[0111] In summary, the wafer-level semiconductor package structure 100 and the preparation method thereof provided by the embodiment of the present application are provided with the optical port structure 111 at one side edge of the optical chip 110, the first optical surface 112 of the optical port structure 111 is exposed to the front surface of the optical chip 110 and extends to the front surface edge of the optical chip 110. Meanwhile, the optical reflection layer 120 corresponding to the first optical surface 112 is also provided on the front surface of the optical chip 110, the reflection cavity 121 is formed between the optical reflection layer 120 and the first optical surface 112, the reflection cavity 121 extends to the front surface edge of the optical chip 110 and is formed with the optical opening 122, the opening direction of the optical opening 122 is parallel to the front surface of the optical chip 110, that is, the side opening is formed. The plastic package layer 130 covers the optical reflection layer 120, the optical reflection layer 120 can reflect the optical signal, and the optical signal transmission between the first optical surface 112 and the optical opening 122 is realized. Compared with the prior art, the wafer-level semiconductor package structure 100 and the preparation method thereof provided by the embodiment of the present application adopt the cavity structure with the side wall opening, the optical reflection layer 120 is formed above the cavity to reflect the optical signal, so that the optical signal can be directly conducted from the side, and therefore, the complex optical structure does not need to be made, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing period is shortened. At the same time, the signal loss caused by the insufficient refractive index and light transmittance of the optical structure is also avoided, the transmission signal loss is reduced, and the transmission efficiency is improved. Moreover, the electrical chip 140 and the optical chip 110 can realize the face-to-face vertical interconnection, so that the high-speed transmission can be realized, the demand of high-speed optical conduction is met, and the product performance is improved.

[0112] Second embodiment

[0113] Reference Figure 15 The wafer-level semiconductor package structure 100 provided by the embodiment of the present application has the same basic structure and principle, technical effect and the first embodiment, for brief description, the part not mentioned in the present embodiment can refer to the corresponding content in the first embodiment.

[0114] The wafer-level semiconductor package structure 100 provided by the embodiment of the present application comprises an optical chip 110, an optical reflection layer 120, a plastic encapsulation layer 130, an electrical chip 140 and an interposer 160. The optical chip 110 is provided with an optical port structure 111 at one side edge thereof. The optical port structure 111 comprises a first optical surface 112. The first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the front surface edge of the optical chip 110. The optical reflection layer 120 is arranged on the front surface of the optical chip 110 and corresponds to the first optical surface 112. A reflection cavity 121 is formed between the optical reflection layer 120 and the first optical surface 112. The reflection cavity 121 extends to the front surface edge of the optical chip 110 and has an optical opening 122. The opening direction of the optical opening 122 is parallel to the front surface of the optical chip 110. The optical reflection layer 120 is configured to reflect optical signals. The plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the optical reflection layer 120. The electrical chip 140 is arranged in the plastic encapsulation layer 130 and is electrically connected to the optical chip 110. The optical chip 110 and the electrical chip 140 are attached to one side surface of the interposer 160 and are electrically connected to the interposer 160. The plastic encapsulation layer 130 is arranged on one side surface of the interposer 160 and encapsulates the optical chip 110 and the electrical chip 140. The other side surface of the interposer 160 is provided with conductive bumps 151 which are electrically connected to the interposer 160.

[0115] In the embodiment, the interposer 160 is made of a high-density interconnection redistribution layer (RDL) which can realize high-density electrical interconnection between the electrical chip 140 and the optical chip 110. The electrical chip 140 and the optical chip 110 are attached to the interposer 160 at intervals, which can effectively reduce the package height.

[0116] Further, the front surface of the electrical chip 140 is provided with first micro-bumps 141 which are correspondingly soldered to one side surface of the interposer 160. The back surface of the electrical chip 140 is exposed to the plastic encapsulation layer 130. The front surface of the optical chip 110 is provided with second micro-bumps 115 which are correspondingly soldered to one side surface of the interposer 160. The back surface of the optical chip 110 is exposed to the plastic encapsulation layer 130. Specifically, the electrical chip 140 and the optical chip 110 can be soldered on the interposer 160 by TCB or FC process to realize soldering fixation and electrical interconnection. The plastic encapsulation layer 130 is arranged on the interposer 160 and protects the electrical chip 140 and the optical chip 110. The height of the electrical chip 140 and the optical chip 110 can be the same and they can be exposed to the plastic encapsulation layer 130 at the same time.

[0117] The embodiment of the present application further provides a preparation method of the wafer-level semiconductor package structure 100 for preparing the wafer-level semiconductor package structure 100 described above. The method comprises the following steps:

[0118] S1: provide a wafer with multiple optical chips 110.

[0119] S2: form a protective layer 200 on the front surface of the optical chip 110 covering the light port structure 111 and the light port groove 114.

[0120] S3: form a light reflection layer 120 on the protective layer 200.

[0121] Among them, the basic steps and process principles of steps S1 to S3 are the same as those of the first embodiment, and specific reference can be made to the first embodiment.

[0122] S4: cut the wafer into multiple optical chips 110.

[0123] Referring to Figure 16 , specifically, the second micro bump 115 can be first processed on the front surface of the optical chip 110 using photolithography and electroplating process, and the PIC wafer is cut into single pieces for soldering interconnection with the interlayer 160. Mechanical cutting or laser cutting process can be used for cutting, and the cutting path needs to avoid the light reflection layer 120. Among them, the height of the second micro bump 115 is greater than the protrusion height of the light reflection layer 120, which facilitates the subsequent encapsulation of the light reflection layer 120 by the plastic sealing material.

[0124] S5: form an interlayer 160 on a glass slide 600.

[0125] Referring to Figure 17 , specifically, the glass slide 600 can be used as a carrier, and other materials can also be used as a carrier. A bonding glue layer can be coated on the surface of the glass slide 600, then a medium material is spin-coated, and a high-density interconnection redistribution layer (RDL) is formed.

[0126] S6: solder the optical chip 110 and the electrical chip 140 on the interlayer 160.

[0127] Referring to Figure 18 , specifically, the TCB or FC process is used to mount the optical chip 110 and the electrical chip 140 on the interlayer 160, wherein the first micro bump 141 on the front surface of the electrical chip 140 is soldered on the interlayer 160, and the second micro bump 115 on the front surface of the optical chip 110 is soldered on the interlayer 160, realizing fixed connection and electrical connection.

[0128] S7: form a plastic sealing layer 130 on the interlayer 160.

[0129] Referring to Figure 19The plastic sealing layer 130 covers the light reflecting layer 120, the light chip 110 and the electric chip 140, and then the grinding exposes the light chip 110 and the electric chip 140. Specifically, the wafer is sealed by the wafer-level plastic sealing process, and the plastic sealing layer 130 can cover the light chip 110 and the electric chip 140 inside and fill the bottom area of the light chip 110 and the electric chip 140.

[0130] S8: Remove the glass slide 600.

[0131] Referring to Figure 20 Specifically, the glass slide 600 under the interlayer 160 can be removed by the debonding process to expose the surface of the interlayer 160.

[0132] S9: Form conductive bumps 151 on the side of the interlayer 160 away from the plastic sealing layer 130.

[0133] Referring to Figure 21 Specifically, after removing the glass slide 600, the surface of the interlayer 160 exposed is processed with photoetching and electroplating to form conductive bumps 151 on the back of the redistribution layer, which are used for subsequent connection with the PCB or substrate.

[0134] S10: Cut the plastic sealing layer 130 to form a first cut 300.

[0135] Referring to Figure 22 The first cut 300 corresponds to the light slot 114 and exposes the light reflecting layer 120. Specifically, the wafer-level laser slotting process can be used to remove the plastic sealing material and the dielectric layer above the light reflecting layer 120 and stop at the surface of the light reflecting layer 120 to form the first cut 300. In actual production, the cutting position can be determined by the pre-prepared alignment mark, and the first cut 300 is accurately aligned with the light slot 114.

[0136] S11: Form a second cut 400 by hidden cutting of the light chip 110.

[0137] Referring to Figure 23 The second cut 400 corresponds to the light slot 114 and exposes the protective layer 200. Specifically, the PIC wafer at the bottom is cut along the light slot 114 to form the second cut 400, which is aligned with the first cut 300 and can expose the protective layer 200 in the light slot 114.

[0138] S12: Break the light reflecting layer 120 along the light slot 114 by the cracking process.

[0139] Referring to Figure 24Specifically, the light reflection layer 120 can be processed again using the process of hidden cutting + split piece, and specifically, the light reflection layer 120 can be disconnected by using the film expansion method, so as to prepare a single optical chip 110, and complete the process of the wafer-level semiconductor packaging structure 100.

[0140] S13: Remove the protective layer 200 to form a reflection cavity 121 between the light reflection layer 120 and the first optical surface 112.

[0141] Please continue to see Figure 15 Specifically, by the developing process, the exposed multifunctional polyimide glue is removed by using a special developing solution, so as to form a side wall opening reflection cavity 121. The manufacturing sequence of step S12 and step S13 can be exchanged.

[0142] Finally, the wafer-level semiconductor packaging structure 100 can be welded on the PCB board or the substrate by the FC process.

[0143] In summary, the wafer-level semiconductor packaging structure 100 and the preparation method thereof provided by the embodiment of the present application adopt the cavity structure with the side wall opening, the light reflection layer 120 is formed above the cavity to reflect the light signal, so that the light signal can be directly conducted from the side, and therefore, a complex optical structure does not need to be manufactured, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing period is shortened. At the same time, the signal loss caused by the insufficient refractive index and light transmittance of the optical structure is avoided, the transmission signal loss is reduced, and the transmission efficiency is improved. Moreover, the electrical interconnection between the electrical chip 140 and the optical chip 110 is realized by using the interlayer 160, the wiring density is improved, and the packaging height is reduced.

[0144] Third embodiment

[0145] See Figure 25 The wafer-level semiconductor packaging structure 100 provided by the embodiment of the present application has the same basic structure, principle, and technical effects as the first embodiment, and for brief description, the part not mentioned in the present embodiment can refer to the corresponding content in the first embodiment.

[0146] The wafer-level semiconductor packaging structure 100 provided by the embodiment of the present application comprises an optical chip 110, an optical reflection layer 120, a plastic encapsulation layer 130, an electrical chip 140, a first redistribution layer 170 and a second redistribution layer 180. The optical chip 110 is provided with an optical port structure 111 at one side edge thereof. The optical port structure 111 comprises a first optical surface 112. The first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the front surface edge of the optical chip 110. The optical reflection layer 120 is arranged on the front surface of the optical chip 110 and corresponds to the first optical surface 112. A reflection cavity 121 is formed between the optical reflection layer 120 and the first optical surface 112. The reflection cavity 121 extends to the front surface edge of the optical chip 110 and has an optical opening 122. The opening direction of the optical opening 122 is parallel to the front surface of the optical chip 110. The optical reflection layer 120 is configured to reflect optical signals. The plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the optical reflection layer 120. The electrical chip 140 is arranged in the plastic encapsulation layer 130 and is electrically connected to the optical chip 110.

[0147] In the embodiment, the first redistribution layer 170 is arranged on the front surface of the optical chip 110, the second redistribution layer 180 is arranged on the back surface of the optical chip 110, and the first redistribution layer 170 and the second redistribution layer 180 are electrically connected. The electrical chip 140 is attached to the first redistribution layer 170 and is electrically connected to the first redistribution layer 170. The plastic encapsulation layer 130 is arranged on the front surface of the optical chip 110 and encapsulates the first redistribution layer 170 and the electrical chip 140. The second redistribution layer 180 is further provided with a conductive bump 151 away from one side of the first redistribution layer 170. The conductive bump 151 is electrically connected to the second redistribution layer 180. Specifically, the first redistribution layer 170 and the second redistribution layer 180 are both high-density interconnection redistribution layers (RDL). The first redistribution layer 170 can realize electrical interconnection between the electrical chip 140 and the optical chip 110.

[0148] Further, the optical chip 110 is further provided with a conductive via hole 116 filled with a conductive material. The first redistribution layer 170 is electrically connected to the second redistribution layer 180 through the conductive via hole 116. Specifically, the conductive via hole 116 can be a through-silicon via (TSV). The conductive material can be copper. Thus, a copper pillar can be formed in the optical chip 110.

[0149] In the embodiment, the front surface of the electrical chip 140 is provided with a first micro bump 141. The first micro bump 141 is welded to the first redistribution layer 170. The back surface of the electrical chip 140 is exposed to the plastic encapsulation layer 130. Specifically, the electrical chip 140 can be attached to the first redistribution layer 170 through a TBC process or an FC process. Specifically, the first micro bump 141 can be welded to a corresponding pad of the first redistribution layer 170. Thus, the electrical chip 140 can be fixed and electrically connected.

[0150] The embodiment of the present application also provides a preparation method of the wafer-level semiconductor package structure 100, which is used for preparing the wafer-level semiconductor package structure 100, and the method comprises the following steps:

[0151] S1: providing a wafer with a plurality of optical chips 110.

[0152] Each optical chip 110 is provided with an optical port structure 111 and an optical port groove 114, the optical port structure 111 comprises a first optical surface 112, the first optical surface 112 is exposed to the front surface of the optical chip 110 and extends to the optical port groove 114. And, the TSV conductive via 116 is made inside the optical chip 110, the conductive via 116 is filled with conductive material. Wherein, the conductive via 116 is arranged separately from the optical port structure 111.

[0153] S2: forming a protective layer 200 covering the optical port structure 111 and the optical port groove 114 on the front surface of the optical chip 110.

[0154] Specifically, the protective layer 200 can be a polyimide material, and the protective layer 200 only covers the optical port structure 111 and the optical port groove 114, and exposes other areas of the front surface of the optical chip 110.

[0155] S3: forming an optical reflection layer 120 on the protective layer 200.

[0156] The optical reflection layer 120 corresponds to the optical port structure 111. The optical reflection layer 120 can be a silicon dioxide layer, which can be deposited on the protective layer 200 and the front surface of the optical chip 110.

[0157] S4: forming a first rewiring layer 170 on the front surface of the optical chip 110.

[0158] Referring to Figure 26 Specifically, the rewiring layer is made on the surface of the PIC wafer through photolithography and electroplating process, so as to form the first rewiring layer 170 on the front surface of the optical chip 110, wherein the first rewiring layer 170 has a certain gap between the optical reflection layer 120, and can cover the conductive via 116 and realize electrical interconnection with the conductive via 116.

[0159] S5: thinning the back surface of the optical chip 110 and exposing the conductive via 116.

[0160] Referring to Figure 27Specifically, in actual preparation, a temporary glass slide 600 can be first attached to the front surface of the optical chip 110 through a bonding process, then the wafer is flipped, and the wafer is thinned by a grinding and CMP chemical mechanical polishing process, i.e. the back surface of the optical chip 110 is thinned, until the copper pillars in the conductive vias 116 are exposed.

[0161] S6: Forming a second redistribution layer 180 on the back surface of the optical chip 110.

[0162] Referring to Figure 28 , the second redistribution layer 180 is electrically connected to the first redistribution layer 170 through the conductive vias 116. Specifically, the RDL redistribution layer can be processed on the wafer surface again through a photolithography and electroplating process to form the second redistribution layer 180, wherein the second redistribution layer 180 is electrically interconnected with the first redistribution layer 170 through the conductive vias 116.

[0163] S7: Forming conductive bumps 151 on the second redistribution layer 180.

[0164] Referring to Figure 29 , specifically, the conductive bumps 151 can be formed on the second redistribution layer 180 again through a photolithography and electroplating process, which are electrically interconnected with the second redistribution layer 180 and used for connection with the PCB board or substrate.

[0165] Further, after the preparation of the conductive bumps 151 is completed, a temporary other glass slide 600 can be bonded to the back surface of the PIC wafer through a bonding process, and then the glass slide 600 is dissociated through a debonding process.

[0166] S8: Soldering the electrical chip 140 on the first redistribution layer 170.

[0167] Referring to Figure 30 , specifically, the first micro-bumps 141 on the front surface of the electrical chip 140 can be soldered on the pads on the surface of the first redistribution layer 170 through a TCB or FC process.

[0168] S9: Forming a plastic encapsulation layer 130 on the front surface of the optical chip 110.

[0169] Referring to Figure 31 , the plastic encapsulation layer 130 encapsulates the electrical chip 140, the first redistribution layer 170 and the light reflection layer 120. Specifically, the wafer is encapsulated through a wafer-level encapsulation process, so that the plastic encapsulation layer 130 can completely encapsulate the first redistribution layer 170, the light reflection layer 120 and the electrical chip 140, then the plastic encapsulation layer 130 is thinned through a grinding process to expose the back surface of the electrical chip 140, and the other glass slide 600 on the back surface of the wafer is dissociated through a debonding process.

[0170] S10: Cutting the plastic sealing layer 130 to form a first cut 300.

[0171] Referring to Figure 32 , the first cut 300 corresponds to the light port groove 114 and exposes the light reflection layer 120. Specifically, a wafer-level laser slotting process can be used to remove the plastic sealing material above the light reflection layer 120 and stop at the surface of the light reflection layer 120, forming the first cut 300.

[0172] S11: Hidden cutting the optical chip 110 to form a second cut 400.

[0173] Referring to Figure 33 , the second cut 400 corresponds to the light port groove 114 and exposes the protective layer 200. A hidden cutting process is used to cut the bottom PIC wafer along the light port groove 114, thereby forming the second cut 400, which is aligned with the first cut 300 and can expose the protective layer 200 located in the light port groove 114.

[0174] S12: Breaking the light reflection layer 120 along the light port groove 114 by a splitting process.

[0175] Referring to Figure 34 , specifically, the hidden cutting + splitting process can be used to process the light reflection layer 120, and the film expansion method can be used to break the light reflection layer 120, thereby preparing a single optical chip 110.

[0176] S13: Removing the protective layer 200 to form a reflection cavity 121 between the light reflection layer 120 and the first optical surface 112.

[0177] Please continue to refer to Figure 25 , specifically, by developing process, using special developing liquid to develop and remove the exposed multifunctional polyimide glue, thereby forming a side wall opening reflection cavity 121.

[0178] The order of steps S12 and S13 can be exchanged.

[0179] Finally, the wafer-level semiconductor packaging structure 100 can be soldered on the PCB board or the substrate by FC process.

[0180] In summary, the wafer-level semiconductor package structure 100 and the preparation method thereof provided by the embodiment of the present application adopt the cavity structure with the sidewall opening, the light reflection layer 120 is formed above the cavity to reflect the light signal, thus the light signal can be directly conducted from the side, and therefore the complex optical structure is not needed to be made, the structure is simple, the manufacturing difficulty and the processing cost are reduced, and the processing period is shortened. Meanwhile, the signal loss caused by the insufficient refractive index and light transmittance of the optical structure is avoided, the transmission signal loss is reduced, and the transmission efficiency is improved. Furthermore, the first redistribution layer 170 and the second redistribution layer 180 are adopted, so that the wiring density is improved, and the integration of the electrical chip 140 is higher. Meanwhile, the first redistribution layer 170 and the second redistribution layer 180 are electrically connected through the conductive via 116, the signal transmission path is shortened, the transmission efficiency is improved, and the package integration is further improved.

[0181] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, and all the changes or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A wafer level semiconductor package structure, comprising: The application relates to a wafer-level semiconductor packaging structure, which comprises the following components: a light chip, one side edge of which is provided with a light port structure, the light port structure comprising a first optical surface, the first optical surface being exposed to the front surface of the light chip and extending to the front surface edge of the light chip; a light reflection layer, which is arranged on the front surface of the light chip and corresponds to the first optical surface, and a reflection cavity is formed between the light reflection layer and the first optical surface, the reflection cavity extending to the front surface edge of the light chip and having an optical opening, the opening direction of the optical opening being parallel to the front surface of the light chip, and the light reflection layer being configured to reflect a light signal; a plastic encapsulation layer, which is arranged at least on the front surface of the light chip and encapsulates the light reflection layer; the light port structure further comprises a second optical surface, the second optical surface being arranged adjacent to the first optical surface and being exposed to the sidewall of the light chip, and the optical opening being connected to the second optical surface; wherein the first optical surface and the second optical surface can both realize lateral conduction of the light signal, the second optical surface being exposed to the sidewall of the light chip along a vertical direction, the first optical surface being exposed to the front surface of the light chip along a horizontal direction, and the second optical surface being perpendicular to the first optical surface.

2. The wafer-level semiconductor package structure of claim 1, wherein, The front surface edge of the light chip is further provided with a light port groove, the light port groove being communicated with the optical opening, and the second optical surface being configured to form a sidewall of the light port groove.

3. The wafer-level semiconductor package structure of claim 1, wherein, The wafer-level semiconductor packaging structure further comprises an electric chip, the electric chip being arranged in the plastic encapsulation layer and being electrically connected to the light chip.

4. The wafer-level semiconductor package structure of claim 3, wherein, The electric chip is arranged on the front surface of the light chip and is electrically connected to the light chip, the front surface of the light chip is further provided with a conductive column, the plastic encapsulation layer is arranged on the front surface of the light chip and encapsulates the electric chip and the conductive column, one end of the conductive column away from the light chip is exposed to the plastic encapsulation layer and is provided with a conductive bump, and the conductive bump is electrically connected to the light chip through the conductive column.

5. The wafer-level semiconductor package structure of claim 4, wherein, The front surface of the electric chip is provided with a first micro bump, the first micro bump is correspondingly welded to the front surface of the light chip, and the back surface of the electric chip is exposed to the plastic encapsulation layer.

6. The wafer-level semiconductor package structure of claim 4, wherein, The conductive column is arranged around the electric chip, and the conductive column is arranged at intervals with the light reflection layer.

7. The wafer-level semiconductor package structure of claim 3, wherein, The wafer-level semiconductor packaging structure further comprises an interlayer, the light chip and the electric chip are attached to one side surface of the interlayer and are electrically connected to the interlayer, the plastic encapsulation layer is arranged on one side surface of the interlayer and encapsulates the light chip and the electric chip, the other side surface of the interlayer is provided with a conductive bump, and the conductive bump is electrically connected to the interlayer.

8. The wafer-level semiconductor package structure of claim 7, wherein, The front surface of the electric chip is provided with a first micro bump, the first micro bump is correspondingly welded to one side surface of the interlayer, and the back surface of the electric chip is exposed to the plastic encapsulation layer; the front surface of the light chip is provided with a second micro bump, the second micro bump is correspondingly welded to one side surface of the interlayer, and the back surface of the light chip is exposed to the plastic encapsulation layer.

9. The wafer-level semiconductor package structure of claim 3, wherein, The wafer-level semiconductor package structure further comprises a first redistribution layer and a second redistribution layer, the first redistribution layer is arranged on the front surface of the optical chip, the second redistribution layer is arranged on the back surface of the optical chip, and the first redistribution layer and the second redistribution layer are electrically connected, the electronic chip is attached to the first redistribution layer and is electrically connected with the first redistribution layer, the plastic encapsulation layer is arranged on the front surface of the optical chip and encapsulates the first redistribution layer and the electronic chip, and the second redistribution layer is further provided with a conductive bump away from one side of the first redistribution layer, and the conductive bump is electrically connected with the second redistribution layer.

10. The wafer-level semiconductor package structure of claim 9, wherein, The optical chip is further provided with a conductive via hole filled with a conductive material, and the first redistribution layer is electrically connected with the second redistribution layer through the conductive via hole.

11. The wafer-level semiconductor package structure of claim 9, wherein, The front surface of the electronic chip is provided with a first micro bump corresponding to the first redistribution layer, and the back surface of the electronic chip is exposed to the plastic encapsulation layer.

12. A method of manufacturing a wafer level semiconductor package structure, for manufacturing the wafer level semiconductor package structure according to claim 1, characterized by, The method comprises: providing a wafer with a plurality of optical chips, wherein each optical chip is provided with an optical port structure and an optical port groove, the optical port structure comprises a first optical surface, the first optical surface is exposed to the front surface of the optical chip and extends to the optical port groove; forming a protective layer covering the optical port structure and the optical port groove on the front surface of the optical chip; forming an optical reflection layer on the protective layer, wherein the optical reflection layer corresponds to the optical port structure; preparing a plastic encapsulation layer encapsulating at least the optical reflection layer and the front surface of the optical chip; cutting the plastic encapsulation layer to form a first cut, wherein the first cut corresponds to the optical port groove and exposes the optical reflection layer; dicing the optical chip to form a second cut, wherein the second cut corresponds to the optical port groove and exposes the protective layer; removing the protective layer to form a reflection cavity between the optical reflection layer and the first optical surface; breaking the optical reflection layer along the optical port groove by a breaking process.

13. The method of claim 12, wherein the method further comprises: The step of preparing a plastic encapsulation layer encapsulating at least the optical reflection layer and the front surface of the optical chip comprises: forming a conductive column on the front surface of the optical chip; welding an electronic chip on the front surface of the optical chip; forming a plastic encapsulation layer on the front surface of the optical chip, wherein the plastic encapsulation layer encapsulates the conductive column, the electronic chip, the optical reflection layer and the front surface of the optical chip; thinning the plastic encapsulation layer and exposing the conductive column; forming a conductive bump on the conductive column.

14. The method of claim 12, wherein the method further comprises: The step of preparing a plastic encapsulation layer encapsulating at least the optical reflection layer and the front surface of the optical chip comprises: cutting the wafer into a plurality of optical chips; forming an intermediate layer on a glass slide; welding the optical chip and the electronic chip on the intermediate layer; forming a plastic encapsulation layer on the intermediate layer, wherein the plastic encapsulation layer encapsulates the optical reflection layer, the optical chip and the electronic chip; removing the glass slide; forming a conductive bump on the side of the intermediate layer away from the plastic encapsulation layer.

15. The method of claim 12, wherein the optical chip is internally formed with a conductive via, and the conductive via is filled with a conductive material. Before the step of preparing a plastic encapsulation layer encapsulating at least the optical reflection layer and the front surface of the optical chip, the method further comprises: forming a first redistribution layer on the front surface of the optical chip; thinning the back surface of the optical chip and exposing the conductive through hole; forming a second redistribution layer on the back surface of the optical chip, wherein the second redistribution layer is electrically connected with the first redistribution layer through the conductive through hole; forming a conductive bump on the second redistribution layer.

16. The method of claim 15, wherein: a step of preparing a plastic package layer covering at least the optical reflection layer and the front surface of the optical chip, comprising: soldering an electronic chip on the first redistribution layer; forming a plastic package layer on the front surface of the optical chip, wherein the plastic package layer covers the electronic chip, the first redistribution layer and the optical reflection layer.

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