Array server multi-channel temperature parallel acquisition system and method

Abstract

The invention discloses an array server multi-channel temperature parallel acquisition system and method, and relates to the technical field of temperature data acquisition, and the method comprises the steps: connecting with an FPGA through a single bus interface, distinguishing temperature sensors according to unique serial numbers, and generating a temperature sensor array; based on the temperature sensor array, the FPGA generates and manages a time sequence control signal according to a communication protocol of each temperature sensor, and the temperature sensors respond according to a unique serial number sequence and transmit temperature measurement data to obtain an accurate time sequence control signal; the FPGA performs data arrangement and storage operation on the temperature data set to form a cached temperature data set; and comparing the cached temperature data set with a temperature alarm threshold value, and when the standard-exceeding temperature data exceeds the temperature alarm threshold value, triggering an alarm signal and generating a temperature alarm report. The data acquisition efficiency, reliability and safety are improved, and the system is suitable for temperature monitoring of servers and industrial equipment.

Description

Technical Field

[0001] This invention relates to the field of temperature data acquisition technology, and in particular to a multi-channel parallel temperature acquisition system and method for an array server. Background Technology

[0002] With the continuous improvement of the performance of electronic devices and computer systems, temperature monitoring, as one of the key technologies to ensure the normal operation of equipment and extend its service life, has gradually been widely used. Temperature sensors play an important role in various fields, especially in high-performance computing equipment such as data centers and server arrays, where temperature monitoring is indispensable.

[0003] Although existing FPGA-based temperature acquisition solutions have improved data acquisition efficiency to some extent, some technical bottlenecks still exist. In existing technologies, most solutions lack efficient timing management in the communication protocol between the temperature sensor and the control unit. As a result, when acquiring multiple temperature data streams, the synchronization problem of timing control signals often affects the acquisition accuracy and response speed. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a method for parallel acquisition of multi-channel temperature on an array server, which solves the problems affecting data accuracy and transmission delay.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a method for parallel acquisition of multi-channel temperature data in an array server, comprising,

[0008] By connecting to the FPGA via a single bus interface, temperature sensors are distinguished by unique serial numbers to generate a temperature sensor array.

[0009] Based on the temperature sensor array, the FPGA generates and manages timing control signals according to the communication protocol of each temperature sensor. The temperature sensors respond and transmit temperature measurement data in sequence according to their unique serial numbers, thereby obtaining accurate timing control signals.

[0010] Based on precise timing control signals, the FPGA communicates with each temperature sensor sequentially to generate sensor temperature readings, performs CRC checks, and obtains temperature datasets.

[0011] The FPGA performs data processing and storage operations on the temperature dataset to form a cached temperature dataset;

[0012] The cached temperature dataset is compared with the temperature alarm threshold. When the temperature exceeds the threshold, an alarm signal is triggered and a temperature alarm report is generated.

[0013] As a preferred embodiment of the multi-channel parallel temperature acquisition method for the array server described in this invention, the steps of connecting to the FPGA via a single bus interface and distinguishing temperature sensors according to their unique serial numbers to generate a temperature sensor array are as follows:

[0014] Select a temperature sensor and connect it to the FPGA via a single bus interface to establish a signal transmission channel and generate a temperature sensor connection channel.

[0015] Based on the temperature sensor connection channel, the FPGA assigns a temperature sensor identifier according to the unique serial number of each temperature sensor.

[0016] Based on the temperature sensor identifier, the FPGA checks the unique serial number and connection status of each temperature sensor to generate a temperature sensor array.

[0017] In a preferred embodiment of the multi-channel parallel temperature acquisition method for the array server described in this invention, the unique serial number of the temperature sensor is generated through the hardware identification code of the temperature sensor.

[0018] As a preferred embodiment of the multi-channel parallel temperature acquisition method for the array server described in this invention, the FPGA generates and manages timing control signals according to the communication protocol of each temperature sensor based on the temperature sensor array. The temperature sensors respond and transmit temperature measurement data in sequence according to their unique serial numbers to obtain accurate timing control signals. The specific steps are as follows.

[0019] Based on the temperature sensor array, the FPGA formulates and manages the timing control signals according to the communication protocol of each temperature sensor, and manages the timing control signals by synchronizing the response order of each temperature sensor through an internal clock; the timing control signals include DQ bus reset pulse, write time slot and read time slot;

[0020] The FPGA controls each temperature sensor to respond sequentially and collect temperature measurement data according to the timing control signal;

[0021] The FPGA extracts temperature values ​​from the temperature measurement data of each temperature sensor, performs outlier detection and correction on the temperature values, and generates precise timing control signals.

[0022] As a preferred embodiment of the multi-channel parallel temperature acquisition method for the array server described in this invention, the FPGA communicates sequentially with each temperature sensor according to a precise timing control signal, generates sensor temperature readings, performs CRC verification, and obtains a temperature dataset. The specific steps are as follows:

[0023] The system communicates with each temperature sensor individually based on precise timing control signals to obtain sensor temperature readings.

[0024] The FPGA calculates the CRC check value of the sensor temperature reading and compares it with the basic check value of the original temperature measurement data to generate a temperature check reading.

[0025] Temperature calibration readings are summarized and categorized to form a temperature dataset.

[0026] As a preferred embodiment of the multi-channel parallel temperature acquisition method for the array server described in this invention, the basic verification value of the original temperature measurement data is obtained by performing byte-by-byte differential calculation on the original temperature measurement data using the CRC-16 verification algorithm.

[0027] As a preferred embodiment of the multi-channel parallel temperature acquisition method for the array server described in this invention, the FPGA performs data processing and storage operations on the temperature dataset to form a cached temperature dataset. The specific steps are as follows:

[0028] The FPGA sorts the temperature verification readings in the temperature dataset according to the unique serial number and timestamp, and corrects missing data and uniformly formats them to generate the sorted temperature dataset.

[0029] The processed temperature dataset is stored in an internal cache and then integrated to generate a cached temperature dataset.

[0030] As a preferred embodiment of the multi-channel parallel temperature acquisition method for array servers described in this invention, the following steps are taken: comparing the cached temperature dataset with a temperature alarm threshold; when the temperature data exceeds the temperature alarm threshold, an alarm signal is triggered and a temperature alarm report is generated.

[0031] Valid temperature verification readings are filtered from the cached temperature dataset, outlier removal and format standardization are performed, and valid temperature readings are obtained.

[0032] When the effective temperature reading does not exceed the temperature alarm threshold, it indicates that the temperature is within the normal range, and the FPGA continues to monitor and maintain the current state.

[0033] When the effective temperature reading exceeds the temperature alarm threshold, it indicates that the temperature is abnormal and exceeds the safe range. The FPGA will immediately trigger an alarm signal and generate a temperature alarm report.

[0034] As a preferred embodiment of the multi-channel parallel temperature acquisition method for array servers described in this invention, the temperature alarm threshold is set by analyzing the temperature range of the device during normal operation and the device malfunction, calculating the average and standard deviation of the temperature through statistical methods, and combining the maximum safe operating temperature of the device.

[0035] Secondly, the present invention provides a multi-channel parallel temperature acquisition system for an array server, comprising,

[0036] The sensor array module is used to connect to the FPGA via a single bus interface, distinguishing temperature sensors according to their unique serial numbers and generating a temperature sensor array.

[0037] The timing control module is used to generate and manage timing control signals based on the temperature sensor array. The FPGA generates and manages timing control signals according to the communication protocol of each temperature sensor. The temperature sensors respond and transmit temperature measurement data in sequence according to their unique serial numbers, thereby obtaining accurate timing control signals.

[0038] The data acquisition module is used to communicate with each temperature sensor sequentially according to the precise timing control signal, generate sensor temperature readings, perform CRC verification, and obtain temperature dataset.

[0039] The data storage module is used by the FPGA to perform data processing and storage operations on the temperature dataset, forming a cached temperature dataset.

[0040] The alarm reporting module compares the cached temperature dataset with the temperature alarm threshold. When the temperature exceeds the threshold, an alarm signal is triggered and a temperature alarm report is generated.

[0041] The beneficial effects of this invention are as follows: It generates a temperature sensor array by connecting to an FPGA via a single bus interface and precisely manages timing control signals to ensure that each sensor collects temperature data sequentially. CRC checksums and data processing ensure the accuracy and integrity of the data. By comparing the data with a temperature alarm threshold, an alarm is triggered and a report is generated, thereby enabling real-time monitoring of the equipment temperature and ensuring safe operation. This improves data acquisition efficiency, reliability, and security, making it suitable for temperature monitoring in servers and industrial equipment. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1This is a flowchart of a method for parallel acquisition of multi-channel temperature data in an array server.

[0044] Figure 2 This is a schematic diagram of a multi-channel parallel temperature acquisition system for an array server.

[0045] Figure 3 A flowchart for establishing and managing the temperature sensor array.

[0046] Figure 4 This is a flowchart of the temperature data acquisition and verification process. Detailed Implementation

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0049] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0050] Reference Figures 1-4 As one embodiment of the present invention, this embodiment provides a method for parallel acquisition of multi-channel temperature on an array server, comprising the following steps:

[0051] S1. Connect to the FPGA via a single bus interface to distinguish temperature sensors according to their unique serial numbers and generate a temperature sensor array.

[0052] It should be noted that existing methods typically connect multiple temperature sensors to the FPGA via physical connections. However, the identification of each temperature sensor usually relies on hardware location allocation or a fixed connection order, which may lead to signal interference or sequence confusion. Temperature sensor identification management is often simplistic and lacks flexible management and optimization mechanisms, potentially resulting in temperature sensor loss during data acquisition based on connection status.

[0053] This invention precisely distinguishes each temperature sensor based on its unique serial number using a single-bus interface, and establishes an independent communication link for each temperature sensor through an FPGA. This ensures that each temperature sensor can transmit data independently and accurately, avoiding signal interference and data conflicts. The FPGA can generate a temperature sensor array based on each temperature sensor's unique serial number, ensuring clear identification of each sensor, thereby improving the accuracy and reliability of data acquisition.

[0054] S1.1 Select a temperature sensor and connect it to the FPGA via a single-bus interface to establish a signal transmission channel and generate a temperature sensor connection channel.

[0055] It should be noted that each temperature sensor is identified by a unique serial number and connected to the FPGA via a single-bus interface. During the connection process, the FPGA establishes a communication link based on the unique serial number of each temperature sensor, ensuring that each temperature sensor can independently transmit data to the FPGA. A temperature sensor connection channel is established to ensure that temperature data can be transmitted from the temperature sensors to the FPGA for subsequent processing.

[0056] S1.2 Based on the temperature sensor connection channel, the FPGA assigns a temperature sensor identifier according to the unique serial number of each temperature sensor.

[0057] It should be noted that a unique serial number is used as an identifier for each temperature sensor, and the FPGA assigns a corresponding identifier to each temperature sensor. This identifier is closely associated with the connection channel of each temperature sensor, ensuring the uniqueness of the temperature sensor during data transmission. During identifier generation, the FPGA not only considers the unique serial number of each temperature sensor but also manages it based on the communication protocol and connection status to ensure the accuracy and sequence of data transmission. In this way, the FPGA can accurately distinguish the measurement data from different temperature sensors during subsequent temperature data acquisition and processing.

[0058] It should also be noted that the connection status is monitored in real time by the FPGA to check the physical connection of each temperature sensor, detect the connection of the temperature sensor and respond to the signal, ensuring that data transmission is not interfered with. The FPGA updates the connection status by periodically sending connection detection signals and receiving feedback. If a connection is abnormal, fault handling is triggered.

[0059] The communication protocol is acquired by the FPGA through real-time interaction with the temperature sensors, recording the protocol version, data transmission method, rate, and verification rules for each sensor. The FPGA manages data transmission according to the data exchange requirements of the communication protocol, dynamically adjusting the transmission rate and verification method to ensure the accuracy and integrity of data transmission.

[0060] S1.3. Based on the temperature sensor identifier, the FPGA checks the unique serial number and connection status of each temperature sensor and generates a temperature sensor array.

[0061] It should be noted that the FPGA checks the connection status of each temperature sensor based on its unique serial number, ensuring that each temperature sensor is in a normal connected state. After completing the identification and connection checks, the FPGA organizes all the checked temperature sensors into a complete temperature sensor array according to their unique serial numbers. This temperature sensor array not only contains the identification information of each temperature sensor, but also its connection status and communication channel information, ensuring that subsequent data acquisition and transmission can proceed smoothly. Through this process, the FPGA can ensure that the position and status of each temperature sensor in the array are clearly defined.

[0062] S2. Based on the temperature sensor array, the FPGA generates and manages timing control signals according to the communication protocol of each temperature sensor. The temperature sensors respond and transmit temperature measurement data in sequence according to their unique serial numbers, thereby obtaining accurate timing control signals.

[0063] It should be noted that in existing methods, temperature sensor data acquisition typically relies on simple polling or synchronization mechanisms, resulting in a relatively fixed response order and timing control for the temperature sensors. Due to the lack of precise timing management, temperature sensors may experience conflicts during temperature measurement data transmission, especially when there are a large number of temperature sensors. This makes it impossible to effectively guarantee the acquisition order and accuracy of each temperature sensor, leading to unstable temperature measurement data.

[0064] This invention is based on a temperature sensor array. An FPGA calculates the communication protocol for each temperature sensor and generates precise timing control signals, ensuring that each sensor responds and transmits temperature data in the correct order. An internal clock synchronization mechanism within the FPGA manages the response time of each sensor, avoiding temperature data conflicts and timing overlaps. The FPGA can adjust the timing control signals in real time to adapt to different operating states and external interference, ensuring efficient and accurate temperature data acquisition.

[0065] S2.1 Based on the temperature sensor array, the FPGA formulates and manages the timing control signals according to the communication protocol of each temperature sensor, and manages the timing control signals by synchronizing the response order of each temperature sensor through the internal clock.

[0066] It should be noted that timing control signals need to be generated according to the communication protocol of each temperature sensor. The FPGA calculates the response timing of each temperature sensor during temperature data acquisition based on the operating mode, temperature data transmission requirements, and communication protocol of each sensor in the temperature sensor array. The FPGA uses an internal clock signal to synchronize the timing control signals, ensuring that each temperature sensor responds sequentially and avoiding data transmission conflicts or time overlaps. This process, through precise timing control, ensures that the temperature sensors acquire temperature data in the correct order, guaranteeing the integrity and accuracy of the temperature data. During the management of the timing control signals, the FPGA continuously monitors the response status of each temperature sensor, ensuring that each sensor transmits temperature data according to the temperature sensor timing control signals, and adjusts the timing control signals in real time to adapt to possible changes or external interference, ultimately ensuring the efficiency and stability of the temperature data acquisition process.

[0067] It should also be noted that the temperature sensor timing control signal is generated by the FPGA according to the communication protocol and operating status of each temperature sensor, ensuring that each temperature sensor responds and transmits data in sequence.

[0068] S2.2 The FPGA controls each temperature sensor to respond sequentially and collect temperature measurement data according to the timing control signal.

[0069] It should be noted that the FPGA sequentially sends timing signals to the temperature sensors to ensure that each sensor responds in a predetermined order and begins acquiring temperature measurement data. Upon receiving the timing control signal, each temperature sensor activates its own temperature measurement function and acquires the current temperature measurement data. The FPGA strictly controls the response time and data transmission order of each temperature sensor according to the timing control signal arrangement, avoiding data conflicts caused by multiple sensors responding simultaneously. In this way, the FPGA ensures that each temperature sensor can independently and accurately acquire temperature measurement data at its location, and that the data acquisition process of all sensors can be completed within an ordered time frame. After each response, the FPGA verifies the accuracy of the sensor's temperature measurement data.

[0070] S2.3 The FPGA extracts the temperature value from the temperature measurement data of each temperature sensor, performs outlier detection and correction on the temperature value, and generates a precise timing control signal.

[0071] It should be noted that the FPGA performs outlier detection on temperature values. By comparing the temperature values ​​with the normal range, the FPGA can identify abnormal temperature data. For detected outliers, the FPGA corrects them according to predetermined rules, which can be achieved through interpolation and smoothing. The corrected temperature data ensures the accuracy and consistency of the data. The FPGA then generates precise timing control signals based on the corrected temperature data.

[0072] It should also be noted that the normal range is determined by analyzing historical temperature data and considering the sensor's operating characteristics, setting a reasonable temperature range as the normal value interval. In practical applications, the normal range can also be adjusted according to environmental changes to ensure the accuracy and real-time performance of temperature detection.

[0073] Predefined rules are set based on the operating characteristics of the temperature sensor and the results of historical data analysis. These rules typically include: setting minimum and maximum temperature values ​​for normal sensor operation as anomaly criteria based on the temperature fluctuation range; allowing a certain range of measurement error considering sensor accuracy and response characteristics; and predefined correction methods for detected outliers, such as interpolation and data smoothing, to ensure that the corrected data maintains consistency and continuity with surrounding data. Through these rules, the FPGA can automatically identify and correct outliers, ensuring the accuracy and reliability of temperature data.

[0074] S3. Based on the precise timing control signal, the FPGA communicates with each temperature sensor sequentially to generate sensor temperature readings, performs CRC verification, and obtains the temperature dataset.

[0075] S3.1. Communicate with each temperature sensor individually based on the precise timing control signal to obtain the sensor temperature readings.

[0076] It should be noted that the FPGA communicates with each temperature sensor sequentially, according to a precise timing control signal arrangement. During each communication, the FPGA establishes a connection with the designated temperature sensor based on the timing control signal, sends a data acquisition request to the sensor, and receives the temperature data fed back by the sensor. Each temperature sensor transmits its measured temperature value sequentially according to the response order, and the FPGA receives and records these temperature readings one by one. Throughout the process, the FPGA ensures the accuracy of the temperature readings from each temperature sensor, while managing the data transmission order according to the timing control signal to avoid data conflicts and loss, thus acquiring the temperature readings from each temperature sensor.

[0077] S3.2 The FPGA calculates the CRC check value of the sensor temperature reading and compares it with the basic check value of the original temperature measurement data to generate a temperature check reading.

[0078] It should be noted that the FPGA uses a CRC algorithm to calculate the checksum of the received temperature readings and compares it with the baseline checksum of the original temperature measurement data from each temperature sensor. Through this comparison, the FPGA can verify whether errors or damage occurred during the transmission of the temperature readings. If the checksums match, it indicates that the sensor temperature measurement data is complete and accurate; if there are discrepancies, it indicates that the sensor temperature measurement data contains errors and needs to be re-acquired and corrected. The FPGA generates the temperature checksum reading.

[0079] S3.3 Summarize and classify the temperature calibration readings to form a temperature dataset.

[0080] It should be noted that all calibrated temperature readings need to be collected. The FPGA organizes the temperature calibration readings transmitted by each temperature sensor, ensuring that the data from each temperature sensor is correctly categorized into its appropriate location. The FPGA classifies all temperature calibration readings according to certain rules, such as by temperature value, temperature sensor serial number, and timestamp. In this way, the temperature calibration readings are aggregated into a unified temperature dataset. The temperature dataset contains all calibrated and sorted temperature readings.

[0081] S4 and FPGA perform data processing and storage operations on the temperature dataset to form a cached temperature dataset.

[0082] S4.1 The FPGA sorts the temperature verification readings in the temperature dataset according to the unique serial number and timestamp, organizes them, corrects missing data and uniformly formats them, and generates the organized temperature dataset.

[0083] It should be noted that the FPGA sorts all temperature calibration readings in ascending order by unique serial number and timestamp to ensure data sequence and temporal consistency. The FPGA checks for missing data in the temperature dataset and corrects missing temperature readings using predetermined correction rules, such as interpolation or other methods to fill in missing values. After correcting the missing data, the FPGA formats all data to ensure that the units, precision, and timestamp format of each temperature reading are consistent.

[0084] It should also be noted that the predetermined correction rules are defined based on the sensor's operating characteristics, data acquisition environment, and application requirements.

[0085] S4.2 Store the organized temperature dataset in the internal cache and integrate it to generate a cached temperature dataset.

[0086] It should be noted that the stored temperature calibration readings are formatted uniformly to ensure that the sequence number, timestamp, and temperature value information of each reading conform to the format. The FPGA sorts the temperature calibration readings according to their unique sequence number and timestamp, ensuring that the data is arranged in order and removing duplicate records to avoid redundant data affecting subsequent processing. The FPGA integrates the temperature data in the cache, classifying and organizing all valid temperature readings according to time order and sequence number, ensuring that the reading of each temperature sensor is accurately mapped to the corresponding time point. The integrated data generates a complete cached temperature dataset.

[0087] S5. Compare the cached temperature dataset with the temperature alarm threshold. When the temperature data exceeds the temperature alarm threshold, trigger the alarm signal and generate a temperature alarm report.

[0088] S5.1 Filter valid temperature verification readings from the cached temperature dataset, remove outliers and unify the format to obtain valid temperature readings.

[0089] It should be noted that the FPGA stores all processed temperature readings according to a specified storage format, ensuring that the data is securely and efficiently stored in the cache. The FPGA then integrates the temperature dataset in the cache, ensuring the integrity and consistency of the temperature data. During the integration process, the FPGA integrates the temperature data according to chronological order and timing integration rules, removing duplicate temperature data and processing inconsistent records to ensure that the cached temperature dataset meets the requirements for subsequent processing and to obtain valid temperature readings.

[0090] It should also be noted that the timing integration rules were formulated after analyzing the operating characteristics of the temperature sensors, data acquisition requirements, and the environment. Based on the response time, data transmission rate, and acquisition frequency of each sensor, and combined with the real-time operating status of the system, the FPGA sets appropriate timing integration rules. These rules ensure that data acquisition from each sensor is performed sequentially, avoiding timing conflicts and data loss. Through continuous monitoring of historical data and environmental changes, the FPGA can dynamically adjust the timing integration rules to cope with changes in the number of sensors, external interference, and system load, ensuring efficient and accurate data acquisition.

[0091] S5.2 When the effective temperature reading does not exceed the temperature alarm threshold, it indicates that the temperature is within the normal range, and the FPGA continues to monitor and maintain the current state.

[0092] It should be noted that by comparing the effective temperature reading with the temperature alarm threshold, if the effective temperature reading does not exceed the temperature alarm threshold, it indicates that the temperature is maintained within a safe range. The FPGA will not trigger any alarm signals but will continue to monitor temperature changes. The FPGA continuously observes the readings fed back by the temperature sensor to ensure that the temperature value remains stable within the normal range and continuously tracks the temperature change trend. Under normal temperature conditions, the FPGA maintains real-time monitoring of the temperature sensor.

[0093] It should also be noted that the temperature alarm threshold is set by analyzing the temperature range of the equipment during normal operation and the occurrence of equipment failures, calculating the average and standard deviation of the temperature through statistical methods, and combining this with the maximum safe operating temperature of the equipment.

[0094] S5.3 When the effective temperature reading exceeds the temperature alarm threshold, it indicates that the temperature is abnormal and exceeds the safe range. The FPGA will immediately trigger an alarm signal and generate a temperature alarm report.

[0095] It should be noted that the FPGA checks the valid temperature readings. If the reading exceeds the temperature alarm threshold, it indicates that the temperature has exceeded the safe range. The FPGA immediately issues an alarm signal to notify relevant personnel to take action. Simultaneously, the FPGA summarizes relevant information such as temperature readings, alarm status, and the time of the alarm to generate a temperature alarm report.

[0096] This embodiment also provides a multi-channel parallel temperature acquisition system for an array server, including:

[0097] The sensor array module is used to connect to the FPGA via a single bus interface, distinguishing temperature sensors according to their unique serial numbers and generating a temperature sensor array.

[0098] The timing control module is used to generate and manage timing control signals based on the temperature sensor array. The FPGA generates and manages timing control signals according to the communication protocol of each temperature sensor. The temperature sensors respond and transmit temperature measurement data in sequence according to their unique serial numbers, thereby obtaining accurate timing control signals.

[0099] The data acquisition module is used to communicate with each temperature sensor sequentially according to the precise timing control signal, generate sensor temperature readings, perform CRC verification, and obtain temperature dataset.

[0100] The data storage module is used by the FPGA to perform data processing and storage operations on the temperature dataset, forming a cached temperature dataset.

[0101] The alarm reporting module compares the cached temperature dataset with the temperature alarm threshold. When the temperature exceeds the threshold, an alarm signal is triggered and a temperature alarm report is generated.

[0102] This embodiment also provides a computer device applicable to the multi-channel temperature parallel acquisition method for array servers, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the multi-channel temperature parallel acquisition method for array servers as proposed in the above embodiment.

[0103] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0104] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the method for parallel acquisition of multi-channel temperature data in an array server as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0105] In summary, this invention achieves the following: A temperature sensor array is generated via a single-bus interface connected to an FPGA, and precise timing control signals are managed to ensure that each sensor collects temperature data sequentially. CRC checksums and data processing ensure the accuracy and integrity of the data. By comparing the data with a temperature alarm threshold, an alarm is triggered and a report is generated, thereby enabling real-time monitoring of equipment temperature and ensuring safe operation. This improves data acquisition efficiency, reliability, and security, making it suitable for temperature monitoring in servers and industrial equipment.

[0106] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for parallel acquisition of multi-channel temperature data in an array server, characterized in that: include, By connecting to the FPGA via a single bus interface, temperature sensors are distinguished by unique serial numbers to generate a temperature sensor array. Based on the temperature sensor array, the FPGA generates and manages timing control signals according to the communication protocol of each temperature sensor. The temperature sensors respond and transmit temperature measurement data in sequence according to their unique serial numbers, thereby obtaining accurate timing control signals. Based on precise timing control signals, the FPGA communicates with each temperature sensor sequentially to generate sensor temperature readings, performs CRC checks, and obtains temperature datasets. The FPGA performs data processing and storage operations on the temperature dataset to form a cached temperature dataset; The cached temperature dataset is compared with the temperature alarm threshold. When the temperature exceeds the threshold, an alarm signal is triggered and a temperature alarm report is generated.

2. The method for parallel acquisition of multi-channel temperature in an array server as described in claim 1, characterized in that: The process involves connecting to the FPGA via a single-bus interface, differentiating temperature sensors by unique serial numbers, and generating a temperature sensor array. The specific steps are as follows: Select a temperature sensor and connect it to the FPGA via a single bus interface to establish a signal transmission channel and generate a temperature sensor connection channel. Based on the temperature sensor connection channel, the FPGA assigns a temperature sensor identifier according to the unique serial number of each temperature sensor. Based on the temperature sensor identifier, the FPGA checks the unique serial number and connection status of each temperature sensor to generate a temperature sensor array.

3. The method for parallel acquisition of multi-channel temperature in an array server as described in claim 2, characterized in that: The unique serial number of the temperature sensor is generated through the hardware identification code of the temperature sensor.

4. The method for parallel acquisition of multi-channel temperature in an array server as described in claim 2, characterized in that: The aforementioned temperature sensor array involves the FPGA generating and managing timing control signals according to the communication protocol of each temperature sensor. The temperature sensors respond sequentially according to their unique serial numbers and transmit temperature measurement data to obtain precise timing control signals. The specific steps are as follows: Based on the temperature sensor array, the FPGA formulates and manages the timing control signals according to the communication protocol of each temperature sensor, and manages the timing control signals by synchronizing the response order of each temperature sensor through an internal clock; the timing control signals include DQ bus reset pulse, write time slot and read time slot; The FPGA controls each temperature sensor to respond sequentially and collect temperature measurement data according to the timing control signal; The FPGA extracts temperature values ​​from the temperature measurement data of each temperature sensor, performs outlier detection and correction on the temperature values, and generates precise timing control signals.

5. The method for parallel acquisition of multi-channel temperature in an array server as described in claim 4, characterized in that: According to the precise timing control signal, the FPGA communicates with each temperature sensor sequentially to generate sensor temperature readings, performs CRC checks, and obtains the temperature dataset. The specific steps are as follows. The system communicates with each temperature sensor individually based on precise timing control signals to obtain sensor temperature readings. The FPGA calculates the CRC check value of the sensor temperature reading and compares it with the basic check value of the original temperature measurement data to generate a temperature check reading. Temperature calibration readings are summarized and categorized to form a temperature dataset.

6. The method for parallel acquisition of multi-channel temperature in an array server as described in claim 5, characterized in that: The basic verification value of the original temperature measurement data is obtained by performing CRC-16 checksum calculations on each byte of the original temperature measurement data.

7. The method for parallel acquisition of multi-channel temperature in an array server as described in claim 5, characterized in that: The FPGA performs data processing and storage operations on the temperature dataset to form a cached temperature dataset. The specific steps are as follows. The FPGA sorts the temperature verification readings in the temperature dataset according to the unique serial number and timestamp, and corrects missing data and uniformly formats the data to generate the sorted temperature dataset. The processed temperature dataset is stored in an internal cache and then integrated to generate a cached temperature dataset.

8. The method for parallel acquisition of multi-channel temperature in an array server as described in claim 7, characterized in that: The process involves comparing the cached temperature dataset with a temperature alarm threshold. When the temperature exceeds the threshold, an alarm signal is triggered and a temperature alarm report is generated. The specific steps are as follows: Valid temperature verification readings are filtered from the cached temperature dataset, outlier removal and format standardization are performed, and valid temperature readings are obtained. When the effective temperature reading does not exceed the temperature alarm threshold, it indicates that the temperature is within the normal range, and the FPGA continues to monitor and maintain the current state; When the effective temperature reading exceeds the temperature alarm threshold, it indicates that the temperature is abnormal and exceeds the safe range. The FPGA will immediately trigger an alarm signal and generate a temperature alarm report.

9. The method for parallel acquisition of multi-channel temperature in an array server as described in claim 8, characterized in that: The temperature alarm threshold is set by analyzing the temperature range of the equipment during normal operation and when the equipment malfunctions, calculating the average and standard deviation of the temperature using statistical methods, and combining this with the equipment's maximum safe operating temperature.

10. A multi-channel parallel temperature acquisition system for an array server, based on the multi-channel parallel temperature acquisition method for an array server according to any one of claims 1 to 9, characterized in that: include, The sensor array module is used to connect to the FPGA via a single bus interface, distinguishing temperature sensors according to their unique serial numbers and generating a temperature sensor array. The timing control module is used to generate and manage timing control signals based on the temperature sensor array. The FPGA generates and manages timing control signals according to the communication protocol of each temperature sensor. The temperature sensors respond and transmit temperature measurement data in sequence according to their unique serial numbers, thereby obtaining accurate timing control signals. The data acquisition module is used to communicate with each temperature sensor sequentially according to the precise timing control signal, generate sensor temperature readings, perform CRC verification, and obtain temperature dataset. The data storage module is used by the FPGA to perform data processing and storage operations on the temperature dataset, forming a cached temperature dataset. The alarm reporting module compares the cached temperature dataset with the temperature alarm threshold. When the temperature exceeds the threshold, an alarm signal is triggered and a temperature alarm report is generated.

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