A hardware acceleration deployment method of an ultrasound full-focus algorithm on an FPGA platform

Abstract

The application discloses a hardware acceleration deployment method of an ultrasonic full-focusing algorithm on an FPGA platform, relates to the technical field of deployment of an acoustic imaging algorithm on an FPGA platform, adopts a master-slave structure with an FPGA platform as a master, controls multiple FPGA slaves in parallel acquisition and parameter calculation through channel gating, modularly divides a full-focusing parameter calculation flow, improves the calculation throughput through a pipeline method, and transmits the calculation results of the multiple FPGA slaves to an FPGA master for imaging; further, a mirror full-focusing calculation method is adopted, parameter reuse is realized through reorganization of a calculation flow, and parameter calculation time is shortened by half. The application can solve the problems of complex calculation, long time consumption and difficulty in deployment on a lower computer platform of the ultrasonic full-focusing imaging algorithm, is favorable for development of a low-cost and light-weight ultrasonic phased array full-focusing online detection instrument, and has important significance for maintenance and health monitoring of pressure vessels.

Description

Technical Field

[0001] This invention relates to the technical field of acoustic imaging algorithm deployment on FPGA platform, and in particular to a hardware acceleration deployment method for ultrasonic total focusing algorithm on FPGA platform. Background Technology

[0002] With the development of the petroleum refining industry in various countries, the requirements for the safety of oil transportation and refining pipelines are becoming increasingly stringent. Non-destructive testing (NDT) of oil pipelines is of great significance for ensuring production safety and improving economic efficiency. Ultrasonic phased array total focusing (TDS) testing methods are highly accurate and versatile, and have been widely used in the field of NDT. However, existing ultrasonic phased array TDS instruments are expensive and bulky, often requiring high-performance GPUs in PCs for cluster computing.

[0003] An FPGA platform is a low-cost, low-power main control platform composed of basic units such as lookup tables, multiplexers, and carry chains. Dedicated computing circuits built upon these basic units can accurately and stably execute complex parallel operations, simultaneously achieving pipelined parallelism, data parallelism, and task parallelism. It is suitable for processing and computing multi-channel signals from ultrasonic phased arrays. FPGA hardware acceleration uses customized dedicated hardware circuits generated by FPGAs to replace general-purpose software instructions on general-purpose processors such as PCs, achieving high parallelism and energy efficiency with nanosecond-level real-time response, thereby obtaining orders-of-magnitude performance improvements on specific computing tasks. However, FPGA cache resources are relatively limited compared to PCs, and the FPGA logic implementation of some functions is difficult, posing numerous challenges to algorithm deployment and online imaging. Conventional FPGA internal cache resources are <13.1Mb (taking the Artix-7 200T as an example), which cannot meet the cache requirements for phased array matrix acquisition data computation. While external DDR3 / 4 storage expansion can solve the problem of insufficient cache and computing space, it also involves data transfer time issues. The DDR3 / 4 bus width is limited, and the process of writing and reading data during continuous complex operations takes too long, far exceeding the time requirements of online testing. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this invention provides a hardware acceleration deployment method for ultrasound total focusing algorithm on an FPGA platform. The aim is to reduce the cache and computing resource requirements of the host, improve data throughput and computing efficiency, and achieve efficient hardware acceleration online imaging of ultrasound total focusing by using a master-slave hardware architecture, data splitting and caching strategy, pipelined parallel computing method, and optimized computing and storage scheme.

[0005] To achieve the above objectives, the present invention adopts the following technical solution, including:

[0006] A hardware acceleration deployment method for an ultrasonic total focusing algorithm on an FPGA platform is disclosed. The FPGA platform adopts a master-slave architecture, utilizing multiple FPGA slaves to receive and buffer data and calculate parameters in parallel. The FPGA master then aggregates the parameters calculated by each FPGA slave and performs imaging. The specific process is as follows:

[0007] S1, through channel selection, splits the full matrix data collected by the phased array probe into multiple sets of data, and uses multiple FPGA slaves to receive these multiple sets of data respectively and buffer them;

[0008] S2, each FPGA slave determines the coordinates of the currently traversed imaging pixel;

[0009] S3, each FPGA slave calculates the full focusing parameters of the pixel based on the pixel coordinates and the cached data;

[0010] S4, each FPGA slave transmits the full focusing parameters of the pixel to the FPGA host. The FPGA host accumulates the parameters to obtain the amplitude of the currently traversed imaging pixel, thereby realizing online imaging.

[0011] Preferably, in step S1, signal acquisition is performed based on an ultrasonic phased array probe with n channels, where the first n / 2 channels are array A. n / 2 Let the last n / 2 channels be array B. n / 2 The entire matrix data is split into 4 groups of data, namely: A n / 2 A n / 2 Received data, A n / 2 Send B n / 2 Received data, B n / 2 A n / 2 Received data, B n / 2 Send B n / 2 The received data is received in parallel by four FPGA slave devices.

[0012] Preferably, in step S2, a pair of registers are defined inside the FPGA slave device to dynamically calculate and update the pixel coordinates based on the current timing and pixel counter. for:

[0013] ;

[0014] in, These are the x and y coordinates of the pixel, respectively. These represent the total number of pixels on the horizontal and vertical axes, respectively.

[0015] Preferably, online imaging is performed using an onboard screen on the FPGA host. The transmission of image data between the FPGA host and the screen is controlled by four signal control lines, namely the frame synchronization signal VSYNC, the line synchronization signal HSYNC, the data valid signal DE, and the additional flag signal FLAG.

[0016] The screen images are captured by progressive scanning. The line synchronization signal is valid during the validity period of one line of pixel data, and the frame synchronization signal is valid during the validity period of one frame of image data.

[0017] The additional flag signal has a bit width of 3 bits. The highest bit represents the start of a frame, the middle bit represents the start of a row of pixels, and the lowest bit represents the end of a row of pixels. The additional flag signal is used for pixel calibration during high-frequency driving.

[0018] Preferably, in step S3, the calculation process of the fully focused parameters is modularly divided into m calculation steps. Each calculation step is deployed using a pipeline method, calling m operation modules. Each operation module executes one of the m calculation steps in parallel, thereby accelerating the calculation, as shown below:

[0019] Let the currently traversed imaging pixel be the q-th pixel. The m calculation modules perform the following calculations in parallel: calculation step 1 for pixel q, calculation step 2 for pixel q-1, calculation step 3 for pixel q-2, ..., calculation step m for pixel q-(m-1). After the calculations are completed, the data from the first m-1 calculation modules will be passed to the next calculation module, while the data from the m-th calculation module will be directly output.

[0020] Next, the m calculation modules perform the following calculations in parallel: step 1 for pixel q+1, step 2 for pixel q, step 3 for pixel q-1, ..., step m for pixel q-(m-2).

[0021] Preferably, the calculation process of the full focusing parameter in step S3 is as follows:

[0022] S31, Calculate the time required for sound wave propagation:

[0023] Currently a channel Incentives and pathways Receive, channel The center of the piezoelectric crystal and the currently traversed imaging pixel, i.e., the current pixel. The distance is ,aisle piezoelectric chip to the current pixel The distance is :

[0024] ;

[0025] ;

[0026] in, The width of each pixel, The spacing between piezoelectric crystals in different channels on the transducer array;

[0027] The speed of sound in the object being measured is c Then from the channel Up to the current pixel Then from the current pixel To the passage The time required for sound waves to travel along the path for;

[0028] ;

[0029] S32, address index and fitting parameters:

[0030] Calculate the time required for sound wave propagation Afterwards, during the collection Find the number of points corresponding to the transmission time among the points. Represented as:

[0031] ;

[0032] in, T p The reference time for the sound wave transmission distance and the corresponding data; t s The time for each signal acquisition and reception. f s The sampling rate is [value], and each set of data contains [number] samples. One point;

[0033] Using the least squares method The corresponding signal amplitude is estimated, and the estimation process can be expressed as follows:

[0034] ;

[0035] in, for The corresponding signal amplitude, Addr For address index, Indicates to n ab Perform a round-down operation;

[0036] Regression parameters k The calculation method is as follows:

[0037] ;

[0038] S33, set the excitation channel to The receiving channel is set to Repeated calculation V ab In addition, registers are defined in the FPGA slave device to store the amplitudes corresponding to different excitation and reception channels.

[0039] Preferably, in step S31, the CORDIC algorithm is called within the FPGA slave device. and The calculation is converted into a square root pattern for successive approximation.

[0040] Preferably, in step S3, when calculating the image of a row of pixels, the parallel computing characteristics of the FPGA slave are utilized to reorganize the calculation paths in the algorithm that rely on the same intermediate variable. The leftmost and rightmost image parameters are simultaneously calculated from both ends of the row of images, and the corresponding pixel values ​​are mirrored. The parameters are the same.

[0041] Preferably, in step S4, the image data is converted from RGB format to a custom binary encoding for storage in the FPGA host; when the image is displayed, the binary encoding corresponding to each pixel is translated into the corresponding RGB data and then transmitted to the imaging protocol bus, and the image is displayed by traversing each pixel through the imaging protocol.

[0042] The present invention also provides an ultrasonic full-focusing FPGA online imaging system, the system comprising: an ultrasonic phased array probe and an FPGA platform;

[0043] The ultrasonic phased array probe is used to acquire full matrix data;

[0044] The FPGA platform is equipped with an ultrasonic total focusing algorithm, which, together with a data acquisition chip, is used to receive full matrix data acquired by an ultrasonic phased array probe and perform online imaging. The FPGA platform employs a hardware acceleration deployment method for the ultrasonic total focusing algorithm on the FPGA platform.

[0045] The advantages of this invention are:

[0046] (1) This invention relates to an acoustic imaging algorithm deployment strategy suitable for FPGA platforms, which can realize the deployment of ultrasonic phased array full-focus acoustic imaging algorithms on FPGA platforms. The hardware architecture adopts a master-slave structure with FPGA as the main controller, and multiple FPGA slaves are controlled to acquire and calculate parameters in parallel through channel selection; the full-focus parameter calculation process is modularly divided, and the calculation throughput is improved by pipeline method. The calculation results of multiple FPGA slaves are transmitted to the FPGA host in parallel for imaging; furthermore, a mirror full-focus calculation method is proposed, which realizes parameter reuse by reorganizing the calculation process and reduces the parameter calculation time by half.

[0047] (2) This invention can solve the problems of complex calculation, long time consumption and difficulty in deployment in the lower-level computer platform of ultrasonic full-focusing imaging algorithm, which is conducive to the development of low-cost and lightweight ultrasonic phased array full-focusing online detection instrument, and is of great significance for the maintenance and health monitoring of pressure vessels.

[0048] (3) The present invention adopts a master-slave cooperative architecture, which splits the full matrix data into 4 groups and receives and processes them in parallel by four FPGA slaves. The cache space and computing power requirements of a single FPGA are reduced to 1 / 4 of those in the non-slave receiving mode, which significantly reduces the requirements for hardware resources of a single FPGA and provides a hardware foundation for online imaging.

[0049] (4) The present invention uses dual-port RAM as a cache space. Compared with the traditional FIFO module, it can freely write and read data along the selected address, which meets the requirements of the ultrasonic full-focusing algorithm to quickly read and match the corresponding data. At the same time, through the cross-clock domain design, the stability and efficiency of data transmission are guaranteed.

[0050] (5) The present invention uses a pipelined approach to deploy the full-focus parameter calculation steps, calls multiple computing modules to process the calculation tasks of different pixels in parallel, and shortens the data processing time to 1 / m of that without pipelined deployment, which greatly improves the data throughput and computing efficiency. Combined with the mirror full-focus calculation method, the calculation is performed simultaneously from both ends of a line of image, which further shortens the calculation time to 1 / 2 of the original. Then, by calling multiple computing modules in parallel to calculate multiple sets of channel data simultaneously, the calculation time is shortened to 1 / 8 of the original. The total calculation time is shortened to 1 / 16m of the original, which effectively meets the real-time requirements of online imaging.

[0051] (6) This invention calls the CORDIC algorithm to perform square root operation, and replaces multiplication and square root operation with basic addition and shift operation, avoiding the problem of traditional square root operation occupying a lot of hardware resources. Moreover, when the pipelined calculation mode is adopted, one data can be output per clock cycle, with small delay and no impact on the overall online imaging rate.

[0052] (7) The present invention also optimizes the pixel coordinate storage and image data storage scheme, dynamically calculates the pixel coordinates, avoids the need to open up additional storage space, and reduces hardware overhead; it uses 3-bit binary numbers to store image data, which reduces the storage space from about 5.86Mb to about 1.1Mb compared with RGB565 format, further reducing the cache space burden of FPGA. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of the architecture of an ultrasound total focusing FPGA online imaging system.

[0054] Figure 2 The timing diagram is displayed to indicate the calibration line.

[0055] Figure 3 This is a timing diagram for displaying the calibration frame.

[0056] Figure 4 This is a diagram comparing different pipeline calculation methods.

[0057] Figure 5 This is a schematic diagram of the mirror full-focus calculation method. Detailed Implementation

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] like Figure 1 As shown, the ultrasonic total focusing FPGA online imaging system includes: an ultrasonic phased array probe and an FPGA platform; the ultrasonic phased array probe is used to acquire full matrix data; the FPGA platform deploys the ultrasonic total focusing algorithm, which, together with the acquisition chip, is used to receive the full matrix data acquired by the ultrasonic phased array probe and perform online imaging; the FPGA platform uses a master-slave architecture, employing a strategy where the FPGA slave receives, caches, and calculates parameters in parallel, while the FPGA master aggregates and performs imaging, reducing the master's cache and computing resource requirements. The various steps of caching and parameter calculation are modularized, and within the FPGA slave, as many computation modules as possible are called in parallel through timing coordination for calculation. A pipelined approach is used to improve data throughput, and a mirrored total focusing calculation method is employed to shorten parameter calculation time and improve the utilization efficiency of computing resources.

[0060] The ultrasonic total focusing algorithm requires acquiring the full matrix data of an n-channel phased array probe. When performing detection using an ultrasonic phased array probe with n channels, the n channels are excited in turn, and after each excitation, the received signals from all channels, including the excitation channel itself, are acquired. Let the excitation channel be... The receiving channel is The amplitude of any point in the data matrix is ​​collected. It can be represented as:

[0061] , ;

[0062] in, A For full matrix data, t s The time for each signal acquisition and reception. f s The sampling rate.

[0063] A structure is adopted in which one FPGA master controls four FPGA slaves, with a quantity of n. 2 The entire matrix data is split. Let the first n / 2 probes be array A. n / 2 The last n / 2 probes are array B n / 2 The entire matrix data is split into four groups, which are received by four FPGA slave devices respectively. The four groups of data are array A. n / 2 Transmitter Array A n / 2 Receive, Array A n / 2 Array B n / 2 Receive, Array B n / 2 Transmitter Array A n / 2 Receive, Array B n / 2 Array B n / 2 Receive. Call four slave devices to receive these four sets of data in parallel and store them in the buffer space. The buffer space and computing power requirements of a single FPGA are reduced to 1 / 4 of those in the non-slave receiving mode.

[0064] The parallel execution of data acquisition, buffering, preprocessing, parameter calculation, and data transmission by the four FPGA slave devices, along with the aggregation and imaging process by the FPGA host, can be summarized as follows:

[0065] S1, through channel gating, splits the full matrix data collected by the phased array probe into multiple groups of data, and uses multiple FPGA slaves to classify, receive and buffer the collected data from multiple channels;

[0066] S2, each FPGA slave determines the coordinates of the currently traversed imaging pixel;

[0067] S3, each FPGA slave calculates the full focusing parameters of the pixel based on the pixel coordinates and the cached data;

[0068] S4, each FPGA slave transmits the full focusing parameters of the pixel to the FPGA host. The FPGA host accumulates the parameters to obtain the amplitude of the currently traversed imaging pixel, thereby realizing online imaging.

[0069] Specifically, the process of step S1 is as follows:

[0070] In this embodiment, each of the n channels of the phased array probe is connected to a single-pole double-throw switch, and array A... n / 2 Array B is connected to slave 1 and slave 2 via a single-pole double-throw switch group. n / 2 Connected to slave 3 and slave 4 via a single-pole double-throw switch group, the full matrix data is split into 4 groups according to the array where the excitation channel and the receiving channel are located: A n / 2 A n / 2 Receive, A n / 2 Send B n / 2 Receive, B n / 2 A n / 2 B n / 2 Send B n / 2 Received. The total storage space required for the data cached by each FPGA slave is:

[0071] ;

[0072] in, This represents the total storage space required for slave device cached data, in bits. This refers to the bit width of the acquired signal. The ultrasonic total focusing algorithm needs to quickly read and match the corresponding data from the buffer space; this is stored in Block RAM resources within the FPGA. Groups of data, each group of data contains a total of t s f s There are 1 point, and the width of each point is 1. The clock for writing to the cache space must be synchronized with the clock of the acquisition module. f ad Consistent with the read clock of the cache space and the master clock of the FPGA slave device. f clk Consistent. The caching method based on dual-port RAM differs from the FIFO (First-In-First-Out) module commonly used in cross-clock domain data processing. Dual-port RAM can freely write and read data along selected addresses, while the data written first in the FIFO IP core will be read first. Writing and reading must be performed sequentially from beginning to end, and addresses cannot be arbitrarily selected.

[0073] Specifically, the process of calculating the coordinates of the currently traversed imaging pixels in step S2 can be represented as:

[0074] This invention, when iterating through and retrieving the parameters of each pixel in an image frame, does not allocate additional storage space to cache the horizontal and vertical coordinates corresponding to the pixel image parameters, thus avoiding additional hardware overhead. Let the coordinates of the pixel be:

[0075] , ;

[0076] in, These are the x and y coordinates of the pixel, respectively. These represent the total number of pixels on the horizontal and vertical axes, respectively. A pair of registers is defined inside the FPGA slave device to dynamically calculate and update pixel coordinates based on the current timing and pixel counter. The hardware resources required for this dynamic pixel coordinate calculation scheme are limited to the computational unit overhead needed to calculate the coordinates.

[0077] Online imaging is achieved using an LCD screen on the FPGA host board. Image data transmission between the FPGA host and the screen is controlled by four signal control lines: VSYNC (frame synchronization signal), HSYNC (line synchronization signal), DE (data valid signal), and FLAG (additional flag signal). The DE signal is only valid when both the frame valid display area and the line valid display area are scanned simultaneously. The LCD screen performs imaging by scanning line by line. The line synchronization signal is valid during the validity period of one line of data, and the frame synchronization signal is valid during the validity period of one frame of image. The additional flag signal (FLAG) is 3 bits wide, with the most significant bit representing the start of one frame of image, the middle bit representing the start of one line of pixels, and the least significant bit representing the end of one line of pixels. Increasing the imaging module's drive clock frequency can improve imaging speed, but it also increases the data error rate. The additional flag signal can be used for pixel position calibration to reduce the error rate.

[0078] like Figure 2 As shown, the LCD screen has a leading edge HFP and a trailing edge HBP before and after the effective row area HOZVAL, respectively. The lower two bits of FLAG, FLGA[1] and [0], mark the start and end of a row of pixel data, respectively. Figure 3 As shown, the corresponding effective display area LINE also has a frame display leading edge VFP and a frame display trailing edge VBP, respectively. The highest bit FLAG[2] marks the start of a frame image. The actual number of pixels traversed is more than The range is large. One pixel's image is updated on the rising edge of each clock cycle (CLOCK), and the LCD screen's driving clock is... f lcd Screen refresh rate V refresh It can be calculated using the following formula:

[0079] ;

[0080] Where VSPW is the interval of one frame of image, and HSPW is the interval of one line of image.

[0081] After all the acquired data is stored in the dual-port RAM cache space of each FPGA slave and the horizontal and vertical coordinates of the currently traversed imaging pixels are calculated, the next step is to calculate the full focusing parameters based on the coordinates and the acquired data in the cache space.

[0082] Specifically, the process of calculating the full focus parameters of the pixel in step S3 can be divided into:

[0083] The calculation process of the fully focused parameters is modularly broken down into several calculation steps, and these steps are deployed using a pipelined approach. If the calculation of the fully focused parameters consists of m calculation steps, the average number of time cycles occupied by each calculation step is... n m Calculate the time taken to capture one frame of an image. t pic for:

[0084] ;

[0085] in, f clk This is the master clock frequency of the FPGA slave device;

[0086] like Figure 4 As shown, Figure 4 (a) is a schematic diagram of the traditional calculation method, and (b) is a schematic diagram of the pipeline calculation method of the present invention. Figure 4 In this invention, "step" represents a computational step. When deployed using a pipelined approach, this invention leverages the parallel computing capabilities of FPGA slave devices, simultaneously calling m computation modules, with each module executing one of the m computational steps in parallel. Assume that during image computation, the currently traversed imaging pixel is... The q-th and m-th calculation modules perform parallel calculations for pixel q: step 1, step 2, step 3, ..., step m for pixel q-(m-1). After calculation, the data from the first m-1 calculation modules is passed to the next calculation module, while the data from the m-th calculation module is directly output. The next m calculation modules then perform parallel calculations for pixel q+1: step 1, step 2, step 3, ..., step m for pixel q-(m-2). Therefore, the time spent calculating all parameters... t pic It can be represented as:

[0087] ;

[0088] Since a single frame of an image contains a large number of pixels, it should satisfy the following conditions: Data processing time is reduced to 1 / m of that without pipelined deployment. The pipelined approach is a hardware deployment strategy that trades area for speed; the parallel computing capabilities of FPGAs are suitable for calling additional computing modules to improve data throughput and computation speed.

[0089] The ultrasonic total focusing algorithm is deployed using a pipeline approach, and the algorithm can be divided into the following three steps:

[0090] S31, Calculate the sound wave propagation time

[0091] Assuming that during the calculation of full-focus imaging, the current channel is... Incentives and pathways Receive, channel The center of the piezoelectric chip and the current pixel The distance is ,aisle piezoelectric chip to the current pixel The distance is They can be represented as:

[0092] ;

[0093] ;

[0094] in, The width of each pixel, Let be the spacing between the piezoelectric crystals in different channels of the transducer array. Assume the speed of sound in the object under test is . c Then from the channel Up to the current pixel Then from the current pixel to the channel The time required for sound waves to travel in the path for:

[0095] ;

[0096] in, This represents the time required for sound waves to travel. The calculation process in the formula involves both square root operations and division operations, due to the speed of sound... c Fixed, divided by the speed of sound c The operation can be transformed into two steps: multiplying by a constant and then performing a shift division. This process can be represented as:

[0097] ;

[0098] in, F = d a +d b , G For constants in the multiplication, H The value is equal to 2. h The exponentiation is equivalent to a right shift operation in binary. h Second-rate.

[0099] d a and d b The calculation process requires square root operations. The CORDIC (Coordinate Rotation Digital Computer) algorithm is a coordinate rotation digital calculation method. This algorithm replaces multiplication operations with basic addition and shift operations, so that the calculation of vector rotation and orientation no longer requires trigonometric functions, multiplication, square root, inverse trigonometric functions, exponential functions, etc. In this invention, the CORDIC algorithm is called internally within the FPGA. and The calculation can be converted into a square root approach for successive approximation.

[0100] In the vector pattern of the CORDIC algorithm, with Represents the x-coordinate, Represents the ordinate, Indicates the number of iterations, initialization vector , In each iteration The sign of the vector determines the direction of rotation, and the vector is ultimately rotated to the positive half of the X-axis. y n tending towards 0, with Indicates the modulus length. The control operator is represented, and the iterative process can be expressed as:

[0101] ;

[0102] ;

[0103] The final iteration result is:

[0104] ;

[0105] ;

[0106] in, x 0 and y 0 is the initial value for the iteration; x n and y n This is the final value of the iteration; xn correspond The numerical value can be solved similarly. .

[0107] When the CORDIC algorithm adopts pipelined computing mode, it can output one data point per clock cycle with a delay of less than 12 clock cycles, which does not affect the overall online imaging rate.

[0108] S32, Address Index and Fitting Parameters

[0109] Calculate the time required for sound wave propagation Afterwards, during the collection Find the number of points corresponding to the transmission time among the points. Represented as:

[0110] ;

[0111] in, T p This represents the reference time corresponding to the sound wave transmission distance and the data. The collected data points must be integers, while... The result is not necessarily an integer; it needs to be determined by nearby points, using the least squares method. The corresponding signal amplitude is estimated, and the estimation process can be expressed as follows:

[0112] ;

[0113] in, for The corresponding signal amplitude, Addr For address index; Indicates to n ab Perform rounding down to the nearest integer; regression parameters k The calculation method is as follows:

[0114] ;

[0115] S33, Change of excitation and reception channels

[0116] Set the incentive channel to The receiving channel is set to Repeated calculation V ab The FPGA slave device defines registers to store the amplitudes corresponding to different excitation and reception channels. This process continues, with the next excitation channel set to... The receiving channel is set to Taking a 64-channel image as an example, a single full-focus imaging dataset includes 64 channels excited and 64 channels acquired separately, totaling 64 channels. 2 Group data.

[0117] like Figure 5 As shown, when calculating the image parameters of a row of pixels, the parallel computing capabilities of the FPGA are utilized to reorganize the computational paths that rely on the same intermediate variable in the algorithm. The leftmost and rightmost image parameters are simultaneously calculated by mirroring from both ends of the row of images. When calculating pixel parameters from both ends using the full-focusing method, the mirrored pixels correspond to... t ab With the same parameters, only one calculation is needed during the imaging process, which can further reduce the calculation time to half of the original.

[0118] Eight computation modules are invoked in parallel within each FPGA slave device to calculate the full-focus parameters eight times simultaneously. For example, the full-focus data for transmitting from channel 1 and receiving from channels 1 to 8 is calculated simultaneously, and the full-focus data for transmitting from channel 1 to channels 9 to 16 is calculated in the next iteration. This operation further reduces the computation time to 1 / 8 of the original time, and the total time to 1 / 16 of the original time.

[0119] Specifically, the data transmission between the FPGA slave and the image display between the FPGA master in step S4 are as follows:

[0120] Multiple FPGA slave devices calculate the parameters of the current pixel in parallel. Registers are defined in each slave device, and the accumulated parameters are updated in real time. The calculated data is then transmitted to the FPGA master for parameter accumulation and summarization. The accumulated signal is graded based on its amplitude to determine the color of the pixel displayed on the screen. Each pixel in a frame of image is equivalent to a small RGB light; different colors can be displayed by controlling the proportions of R (red), G (green), and B (blue). The color data is stored in RGB565 format, with 800×480 pixels stored at a time. X pos × Y pos The storage space required for each pixel is approximately 5.86Mb. The host's BRAM space is insufficient to handle the 5.86Mb cache space requirement for storing images. To further reduce hardware overhead, the image data storage format was changed from RGB565 to 3-bit binary encoding. Since the displayed colors in panfocus imaging are not rich, the 3-bit binary number from 000 to 111 corresponds to the corresponding cloud image colors. For example, 000 corresponds to blue with the lowest energy amplitude, and 111 corresponds to red with the highest energy amplitude. Therefore, the storage space requirement was further reduced from 5.86Mb to approximately 1.1Mb, which further alleviated the cache space burden on the FPGA.

[0121] During image display, the 3-bit binary code corresponding to each pixel is translated into the corresponding RGB565 data and transmitted to the imaging protocol bus. The image is then displayed by traversing each pixel through the imaging protocol.

[0122] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A hardware-accelerated deployment method for an ultrasonic total focusing algorithm on an FPGA platform, characterized in that, The FPGA platform adopts a master-slave architecture, utilizing multiple FPGA slaves to receive and buffer data and calculate parameters in parallel. The FPGA master then aggregates the parameters calculated by each FPGA slave and performs imaging. The specific process is as follows: S1, through channel selection, splits the full matrix data collected by the phased array probe into multiple sets of data, and uses multiple FPGA slaves to receive these multiple sets of data respectively and buffer them; S2, each FPGA slave determines the coordinates of the currently traversed imaging pixel; S3, each FPGA slave calculates the full focusing parameters of the pixel based on the pixel coordinates and the cached data; S4, each FPGA slave transmits the full focusing parameters of the pixel to the FPGA master. The FPGA master accumulates the parameters to obtain the amplitude of the currently traversed imaging pixel, thereby realizing online imaging; In step S3, the calculation process of the fully focused parameters is modularly divided into m calculation steps. The calculation steps are deployed using a pipeline method, calling m operation modules. Each operation module executes one of the m calculation steps in parallel, thereby accelerating the calculation, as shown below: Let the currently traversed imaging pixel be the q-th pixel. The m calculation modules perform the following calculations in parallel: calculation step 1 for pixel q, calculation step 2 for pixel q-1, calculation step 3 for pixel q-2, ..., calculation step m for pixel q-(m-1). After the calculations are completed, the data from the first m-1 calculation modules will be passed to the next calculation module, while the data from the m-th calculation module will be directly output. Next, the m calculation modules perform the following calculations in parallel: step 1 for pixel q+1, step 2 for pixel q, step 3 for pixel q-1, ..., step m for pixel q-(m-2); In step S3, the calculation process of the total focusing parameter is as follows: S31, Calculate the time required for sound wave propagation: Currently a channel Incentives and pathways Receive, channel The center of the piezoelectric crystal and the currently traversed imaging pixel, i.e., the current pixel. The distance is ,aisle piezoelectric chip to the current pixel The distance is : ； ； in, The width of each pixel, The spacing between piezoelectric crystals in different channels on the transducer array; The speed of sound in the object being measured is c Then from the channel Up to the current pixel Then from the current pixel To the passage The time required for sound waves to travel along the path for; ； S32, address index and fitting parameters: Calculate the time required for sound wave propagation Afterwards, during the collection Find the number of points corresponding to the transmission time among the points. Represented as: ； in, T p The reference time for the sound wave transmission distance and the corresponding data; t s The time for each signal acquisition and reception. f s The sampling rate is [value], and each set of data contains [number] samples. One point; Using the least squares method The corresponding signal amplitude is estimated, and the estimation process can be expressed as follows: ； in, for The corresponding signal amplitude, Addr For address index, Indicates to n ab Perform a round-down operation; Regression parameters k The calculation method is as follows: ； S33, set the excitation channel to The receiving channel is set to Repeated calculation V ab In addition, registers are defined in the FPGA slave device to store the amplitudes corresponding to different excitation and receiving channels.

2. The hardware acceleration deployment method for an ultrasonic total focusing algorithm on an FPGA platform according to claim 1, characterized in that, In step S1, signal acquisition is performed using an ultrasonic phased array probe with n channels, where the first n / 2 channels are array A. n / 2 Let the last n / 2 channels be array B. n / 2 The entire matrix data is split into 4 groups of data, namely: A n / 2 A n / 2 Received data, A n / 2 Send B n / 2 Received data, B n / 2 A n / 2 Received data, B n / 2 Send B n / 2 The received data is received in parallel by four FPGA slave devices.

3. The hardware acceleration deployment method for the ultrasonic total focusing algorithm on an FPGA platform according to claim 1, characterized in that, In step S2, a pair of registers are defined inside the FPGA slave device to dynamically calculate and update the pixel coordinates based on the current timing and pixel counter. for: ； in, These are the x and y coordinates of the pixel, respectively. These represent the total number of pixels on the horizontal and vertical axes, respectively.

4. The hardware acceleration deployment method of the ultrasonic total focusing algorithm on an FPGA platform according to claim 3, characterized in that, Online imaging is performed using an onboard screen on the FPGA host. The transmission of image data between the FPGA host and the screen is controlled by four signal control lines: frame synchronization signal VSYNC, line synchronization signal HSYNC, data valid signal DE, and additional flag signal FLAG. The screen images are captured by progressive scanning. The line synchronization signal is valid during the validity period of one line of pixel data, and the frame synchronization signal is valid during the validity period of one frame of image data. The additional flag signal has a bit width of 3 bits. The highest bit represents the start of a frame, the middle bit represents the start of a row of pixels, and the lowest bit represents the end of a row of pixels. The additional flag signal is used for pixel calibration during high-frequency driving.

5. The hardware acceleration deployment method for the ultrasonic total focusing algorithm on an FPGA platform according to claim 1, characterized in that, In step S31, the CORDIC algorithm is called internally within the FPGA slave device. and The calculation is converted into a square root pattern for successive approximation.

6. The hardware acceleration deployment method for an ultrasonic total focusing algorithm on an FPGA platform according to claim 1, characterized in that, In step S3, when calculating the image of a row of pixels, the parallel computing characteristics of the FPGA slave device are utilized to reorganize the calculation paths in the algorithm that rely on the same intermediate variable. The leftmost and rightmost image parameters are simultaneously calculated from both ends of the row of images, and the corresponding pixel values ​​are mirrored. The parameters are the same.

7. The hardware acceleration deployment method for an ultrasonic total focusing algorithm on an FPGA platform according to claim 1, characterized in that, In step S4, the image data is converted from RGB format to a custom binary encoding for storage in the FPGA host. When the image is displayed, the binary encoding of each pixel is translated into the corresponding RGB data and then transmitted to the imaging protocol bus. The image is displayed by traversing each pixel through the imaging protocol.

8. An ultrasound total focusing FPGA online imaging system, characterized in that, The system includes: an ultrasonic phased array probe and an FPGA platform; The ultrasonic phased array probe is used to acquire full matrix data; The FPGA platform is equipped with an ultrasonic total focusing algorithm, which, together with a data acquisition chip, is used to receive full matrix data acquired by an ultrasonic phased array probe and perform online imaging. The FPGA platform employs a hardware acceleration deployment method for the ultrasonic total focusing algorithm as described in any one of claims 1-7.

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