Core memory read reference circuit architecture design method and system

Abstract

The application provides a magnetic core random memory read reference circuit architecture design method and system, relates to the technical field of circuit architecture, and comprises the following steps: setting high resistance and low resistance reference unit columns in each storage array, which respectively contain transistor and polysilicon resistance series connection structures; configuring a reference bit line, adjusting the line width to make the square resistance equal to that of a common bit line, and the number of transistors in a read path is the same as that of a target unit; obtaining a target read current and high and low resistance reference currents in a read operation; calculating the intermediate value of the high and low resistance reference currents as a dynamic reference current, which is adaptively adjusted with the change of parasitic resistance on the path; and judging the data of the storage unit by comparing the target read current with the dynamic reference current through a sensitive amplifier. The application improves the read reliability and fault tolerance of the magnetic core random memory system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit architecture, and particularly relates to a magnetic core random memory read reference circuit architecture design method and system. BACKGROUND

[0002] Magnetic core random memory (MRAM) is a non-volatile memory technology that stores information through magnetic tunnel junction (MTJ), with advantages of high speed, low power consumption, high durability, and non-volatility. In an MRAM system, data is read by detecting the resistance state of the magnetic tunnel junction, which can be in a high resistance state or a low resistance state, representing different logic values.

[0003] In the reading process of MRAM, the design of the reference circuit is crucial, as it directly affects the reliability and accuracy of the reading operation. Traditional MRAM reading circuits usually use a fixed reference current or voltage to compare with the reading current or voltage of the storage unit, to determine the logic state of the storage unit.

[0004] However, the existing MRAM reference circuit design has the following defects and deficiencies:

[0005] Firstly, the traditional reference circuit is sensitive to process variations and operating conditions. Under different temperature, voltage conditions, or due to manufacturing process fluctuations, the reference value may have a large deviation, leading to reading errors. Especially in large-scale storage arrays, this deviation may be amplified with the increase of array size, seriously affecting the reading reliability.

[0006] Secondly, the existing reference generation circuit usually cannot effectively cope with the changes of parasitic resistance and transistor on-resistance on the reading path. These parasitic factors will change with the change of working environment, causing the comparison result between the reading signal and the reference signal to be unstable, and further affecting the reading accuracy. SUMMARY

[0007] The magnetic core random memory read reference circuit architecture design method and system provided by the embodiments of the present application can solve the problems in the prior art.

[0008] In a first aspect, the present application provides a magnetic core random memory read reference circuit architecture design method, which is applied to a magnetic core random memory system including a plurality of storage arrays, each storage array including a plurality of rows and columns of storage units, each storage unit including a transistor and a magnetic tunnel junction in series, comprising:

[0009] In each memory array, a high resistance reference cell column and a low resistance reference cell column are arranged, the high resistance reference cell column comprises a transistor and a first polysilicon resistor in series, and the low resistance reference cell column comprises a transistor and a second polysilicon resistor in series, the resistance of the first polysilicon resistor is equivalent to the resistance of the high resistance state of the magnetic tunnel junction, and the resistance of the second polysilicon resistor is equivalent to the resistance of the low resistance state of the magnetic tunnel junction.

[0010] A high resistance reference bit line and a low resistance reference bit line are configured for the high resistance reference cell column and the low resistance reference cell column respectively, by adjusting the metal line width of the high resistance reference bit line and the low resistance reference bit line, the sheet resistance of the two reference bit lines is equal to the sheet resistance of the ordinary bit line, and the number of transistors in the read path of the two reference bit lines is equal to the number of transistors in the read path of the target memory cell.

[0011] In the read operation, the resistance values of the target memory cell, the high resistance reference cell and the low resistance reference cell are read at the same time to obtain a target read current, a high resistance reference current and a low resistance reference current.

[0012] The intermediate value of the high resistance reference current and the low resistance reference current is calculated by a differential operation circuit as a dynamic reference current, and the dynamic reference current is self-adaptively adjusted according to the parasitic resistance and the transistor on-resistance in the path of the high resistance reference cell and the low resistance reference cell.

[0013] The target read current and the dynamic reference current are compared by a sensitive amplifier to determine whether data is stored in the target memory cell.

[0014] In each memory array, a high resistance reference cell column and a low resistance reference cell column are arranged, the high resistance reference cell column comprises a transistor and a first polysilicon resistor in series, and the low resistance reference cell column comprises a transistor and a second polysilicon resistor in series, the resistance of the first polysilicon resistor is equivalent to the resistance of the high resistance state of the magnetic tunnel junction, and the resistance of the second polysilicon resistor is equivalent to the resistance of the low resistance state of the magnetic tunnel junction.

[0015] The magnetic tunnel junctions in the memory array are tested for batch resistance characteristics, the resistance distribution curve of the magnetic tunnel junction in the anti-parallel magnetization state and the resistance distribution curve of the magnetic tunnel junction in the parallel magnetization state are measured under multiple process angles and temperature conditions, and the statistical median and the standard deviation of the resistance distribution curve are extracted.

[0016] The nominal resistance of the first polysilicon resistor is determined according to the statistical median in the anti-parallel magnetization state, and the nominal resistance of the second polysilicon resistor is determined according to the statistical median in the parallel magnetization state.

[0017] The metal line width of the high resistance reference bit line and the low resistance reference bit line is adjusted, including:

[0018] The metal layer thickness and the material resistivity of the ordinary bit line are measured, and the sheet resistance of the ordinary bit line is calculated according to the metal layer thickness and the material resistivity.

[0019] The metal line width of the high-resistance reference bit line and the low-resistance reference bit line is adjusted so that the deviation of the square resistance of the high-resistance reference bit line and the low-resistance reference bit line from the square resistance of the common bit line is within the minimum tolerance range allowed by the manufacturing process, and the high-resistance reference bit line, the low-resistance reference bit line, and the common bit line use the same metal layer and the same routing topology, so that the parasitic resistance of the high-resistance reference bit line and the low-resistance reference bit line matches the parasitic resistance of the common bit line.

[0020] The number of transistors in the two reference bit lines in the read path is equal to the number of transistors in the target memory cell read path, which includes:

[0021] A first gating transistor is connected in series between the high-resistance reference bit line and the high-resistance reference cell column, and a second gating transistor is connected in series between the low-resistance reference bit line and the low-resistance reference cell column, and the size, threshold voltage, and bias condition of the first gating transistor and the second gating transistor are the same as the gating transistor connected between the common bit line and the target memory cell in the target memory cell read path, so that the on-resistance of the transistors in the high-resistance reference bit line read path and the low-resistance reference bit line read path and their drift characteristics with process, voltage, and temperature are consistent with the target memory cell read path.

[0022] The intermediate value of the high-resistance reference current and the low-resistance reference current is calculated as the dynamic reference current by a differential operation circuit, which includes:

[0023] The high-resistance reference current is input to the first current input terminal of the differential operation circuit, and the low-resistance reference current is input to the second current input terminal of the differential operation circuit;

[0024] A first current mirror branch and a second current mirror branch are provided in the differential operation circuit, the first current mirror branch mirrors and copies the high-resistance reference current and multiplies it by a first weight coefficient, and the second current mirror branch mirrors and copies the low-resistance reference current and multiplies it by a second weight coefficient;

[0025] The first weight coefficient and the second weight coefficient are determined according to the tunnel magnetoresistance ratio of the magnetic tunnel junction, the average resistance value in the anti-parallel magnetization state and the average resistance value in the parallel magnetization state of the magnetic tunnel junction are measured, the tunnel magnetoresistance ratio is calculated as the ratio of the average resistance value in the anti-parallel magnetization state to the average resistance value in the parallel magnetization state, the first weight coefficient is set as the ratio of the tunnel magnetoresistance ratio to the sum of the tunnel magnetoresistance ratio and one, and the second weight coefficient is set as the difference between one and the first weight coefficient;

[0026] The weighted high-resistance reference current output by the first current mirror branch and the weighted low-resistance reference current output by the second current mirror branch are converged to a summing node, and the weighted high-resistance reference current and the weighted low-resistance reference current are subjected to current-domain summing operation through the summing node to obtain the dynamic reference current.

[0027] The first current mirror branch and the second current mirror branch are arranged in the differential operation circuit, and the first current mirror branch and the second current mirror branch comprise:

[0028] The first reference transistor and the first mirror transistor are arranged in the first current mirror branch, the drain of the first reference transistor is connected to the first current input end to receive the high-resistance reference current, the gate and the drain of the first reference transistor are short-circuited to form a diode connection structure, the gate of the first mirror transistor is connected to the gate of the first reference transistor, and the source of the first mirror transistor and the source of the first reference transistor are commonly connected to a power supply voltage.

[0029] The second reference transistor and the second mirror transistor are arranged in the second current mirror branch, the drain of the second reference transistor is connected to the second current input end to receive the low-resistance reference current, the gate and the drain of the second reference transistor are short-circuited to form a diode connection structure, the gate of the second mirror transistor is connected to the gate of the second reference transistor, and the source of the second mirror transistor and the source of the second reference transistor are commonly connected to a power supply voltage.

[0030] The second aspect of the embodiment of the application provides a magnetic core random memory read reference circuit architecture design system, and the method is applied to a system comprising:

[0031] The first unit is configured to arrange a high-resistance reference cell column and a low-resistance reference cell column in each memory array, the high-resistance reference cell column comprises a transistor and a first polysilicon resistor in series, the low-resistance reference cell column comprises a transistor and a second polysilicon resistor in series, the resistance value of the first polysilicon resistor is equivalent to the resistance value of the high-resistance state of the magnetic tunnel junction, and the resistance value of the second polysilicon resistor is equivalent to the resistance value of the low-resistance state of the magnetic tunnel junction.

[0032] The second unit is configured to arrange a high-resistance reference bit line and a low-resistance reference bit line for the high-resistance reference cell column and the low-resistance reference cell column respectively, adjust the metal line width of the high-resistance reference bit line and the low-resistance reference bit line, so that the sheet resistance of the two reference bit lines is equal to the sheet resistance of the ordinary bit line, and the number of transistors in the read path of the two reference bit lines is equal to the number of transistors in the read path of the target memory cell.

[0033] The third unit is configured to simultaneously read the resistance values of the target memory cell, the high-resistance reference cell and the low-resistance reference cell in the read operation, and obtain a target read current, a high-resistance reference current and a low-resistance reference current.

[0034] The fourth unit is configured to calculate, by a differential operation circuit, an intermediate value of the high-resistance reference current and the low-resistance reference current as a dynamic reference current, which is self-adaptively adjusted according to changes in parasitic resistance and transistor on-resistance on the high-resistance reference unit and the low-resistance reference unit.

[0035] The fifth unit is configured to compare, by a sensitive amplifier, the target reading current with the dynamic reference current to determine whether data is stored in the target storage unit.

[0036] The third aspect of the embodiment of the present application,

[0037] An electronic device is provided, comprising:

[0038] A processor;

[0039] A memory for storing processor-executable instructions;

[0040] The processor is configured to invoke the instructions stored in the memory to perform the method described above.

[0041] The fourth aspect of the embodiment of the present application,

[0042] A computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method described above.

[0043] The present application has the following advantages:

[0044] The high-resistance reference unit and the low-resistance reference unit are provided, and the polysilicon resistances are respectively equivalent to simulate the high-resistance state and the low-resistance state of the magnetic tunnel junction, so that a stable and reliable reference benchmark is realized, and the problem of unstable reference current caused by process fluctuation in the traditional reference circuit is solved.

[0045] The metal line width of the reference bit line is adjusted so that the square resistance is equal to that of the ordinary bit line, and the number of transistors in the reference path is equal to that in the reading path of the storage unit, so that the parasitic resistance of the reading path is effectively balanced, and the reading accuracy is improved.

[0046] The intermediate value of the high-resistance reference current and the low-resistance reference current is calculated by a differential operation circuit as a dynamic reference current, so that the self-adaptive adjustment of the reference current is realized, and the dynamic adjustment of the reference current according to changes in parasitic resistance and transistor on-resistance on the high-resistance reference unit and the low-resistance reference unit is realized, so that the influence of process deviation, temperature change, power fluctuation and other factors on the reading decision is effectively eliminated. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1The flowchart of the method for designing the architecture of the read reference circuit of the magnetic core random memory according to the embodiment of the present application is shown in

[0048] Figure 2 The schematic diagram of the array architecture of the novel magnetic core random memory read reference circuit according to the present application is shown in

[0049] Figure 3 The schematic diagram of the structure of the circuit on both sides of the sense amplifier is shown in DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the embodiment of the present application more clear, the technical scheme of the embodiment of the present application will be described clearly and completely below in combination with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiment in the present application, all the other embodiments obtained by the person skilled in the art without creative labor fall within the protection scope of the present application.

[0051] The technical scheme of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described repeatedly in some embodiments.

[0052] Figure 1 The flowchart of the method for designing the architecture of the read reference circuit of the magnetic core random memory according to the embodiment of the present application is shown in Figure 1 The method comprises the following steps:

[0053] A high-resistance reference cell column and a low-resistance reference cell column are arranged in each memory array, the high-resistance reference cell column comprises a transistor and a first polysilicon resistor in series, and the low-resistance reference cell column comprises a transistor and a second polysilicon resistor in series, the resistance value of the first polysilicon resistor is equivalent to the resistance value of the high-resistance state of the magnetic tunnel junction, and the resistance value of the second polysilicon resistor is equivalent to the resistance value of the low-resistance state of the magnetic tunnel junction;

[0054] A high-resistance reference bit line and a low-resistance reference bit line are configured for the high-resistance reference cell column and the low-resistance reference cell column respectively, the metal wire width of the high-resistance reference bit line and the low-resistance reference bit line is adjusted, so that the sheet resistance of the two reference bit lines is equal to the sheet resistance of the ordinary bit line, and the number of transistors in the read path of the two reference bit lines is equal to the number of transistors in the read path of the target memory cell;

[0055] In the read operation, the resistance values of the target memory cell, the high-resistance reference cell and the low-resistance reference cell are read at the same time, and the target read current, the high-resistance reference current and the low-resistance reference current are obtained;

[0056] The intermediate value of the high-resistance reference current and the low-resistance reference current is calculated by a differential operation circuit as a dynamic reference current, which is self-adaptively adjusted according to the parasitic resistance and the transistor on-resistance on the pass of the high-resistance reference unit and the low-resistance reference unit;

[0057] The target read current is compared with the dynamic reference current by a sensitive amplifier to determine whether data is stored in the target storage unit.

[0058] In an alternative embodiment, the arrangement of the high-resistance reference unit column and the low-resistance reference unit column in each storage array comprises:

[0059] The magnetic tunnel junctions in the storage array are subjected to batch resistance characteristic testing, and the resistance distribution curves of the magnetic tunnel junctions in the anti-parallel magnetization state and the parallel magnetization state are measured respectively under multiple process angles and temperature conditions, and the statistical median and the standard deviation of the resistance distribution curves are extracted.

[0060] The nominal resistance of the first polysilicon resistor is determined according to the statistical median in the anti-parallel magnetization state, and the nominal resistance of the second polysilicon resistor is determined according to the statistical median in the parallel magnetization state.

[0061] In the manufacture of magnetic random access memory (MRAM), it is first necessary to perform batch resistance characteristic testing on the magnetic tunnel junctions (MTJs) in the storage array. This testing is usually performed under multiple process angles and temperature conditions to ensure that the device can work normally under various environments.

[0062] The batch resistance characteristic testing first requires the MTJ elements to be placed in an anti-parallel magnetization state and a parallel magnetization state. In the anti-parallel magnetization state, the magnetic moments of the free layer and the fixed layer are opposite, at which time the MTJ exhibits a high resistance state. In the parallel magnetization state, the magnetic moments of the free layer and the fixed layer are consistent, at which time the MTJ exhibits a low resistance state.

[0063] During the testing process, a small bias voltage is applied to each MTJ element, usually between 100 millivolts and 500 millivolts, and then the current flowing through the MTJ is measured. The resistance value of the MTJ is calculated according to Ohm's law. In a typical MRAM array, thousands of MTJ elements may need to be tested, forming a large data set.

[0064] The testing needs to be performed under different process angle conditions, including typical conditions (TT), fast conditions (FF), slow conditions (SS), and fast N / slow P (FS) and slow N / fast P (SF) conditions. In addition, testing needs to be performed at multiple temperature points, usually including low temperature (such as -40°C), room temperature (about 25°C), and high temperature (such as 125°C).

[0065] The collected resistance data is used to generate resistance distribution curves. For the anti-parallel magnetization state (high resistance state), one resistance distribution curve is plotted; for the parallel magnetization state (low resistance state), another resistance distribution curve is plotted. These distribution curves typically exhibit a nearly Gaussian shape.

[0066] Next, statistical analysis is performed on these distribution curves to extract the statistical median and standard deviation. The statistical median represents the center position of the resistance distribution, while the standard deviation reflects the dispersion of resistance values. A smaller standard deviation indicates that the resistance values of the MTJ elements are more concentrated, which generally means that the manufacturing process is more stable.

[0067] Based on the extracted statistical median for the anti-parallel magnetization state, the nominal resistance of the first polysilicon resistor is determined. This polysilicon resistor will serve as the high resistance reference cell column. Similarly, based on the statistical median for the parallel magnetization state, the nominal resistance of the second polysilicon resistor is determined as the low resistance reference cell column.

[0068] When determining the nominal resistance of the polysilicon resistors, a certain margin needs to be considered. For example, the resistance value of the high resistance reference cell column can be set between 95% to 105% of the statistical median for the anti-parallel magnetization state, while the resistance value of the low resistance reference cell column can be set between 95% to 105% of the statistical median for the parallel magnetization state. This setting can ensure that the reference cell columns accurately represent the high and low resistance states of the actual MTJ elements.

[0069] The actual fabrication of the polysilicon resistors usually employs doping adjustment. By adjusting the doping concentration, the resistivity of the polysilicon can be precisely controlled. For example, the high resistance reference cell column can use polysilicon with a lower doping concentration, while the low resistance reference cell column uses polysilicon with a higher doping concentration. In addition, the resistance value of the polysilicon resistors can be further fine-tuned by adjusting their geometric dimensions (such as length and width).

[0070] The finished polysilicon reference resistors need to be verified to ensure that their resistance values meet the design requirements. Verification tests typically include resistance value measurement, temperature coefficient measurement, and long-term stability testing, etc.

[0071] These reference cell columns play a crucial role in the read operation of the MRAM. When reading a storage cell, the resistance value of the storage cell is compared with the high resistance reference cell and the low resistance reference cell. If the resistance value of the storage cell is closer to the high resistance reference value, it is judged as a "1" state; if it is closer to the low resistance reference value, it is judged as a "0" state.

[0072] The high-resistance reference unit column and the low-resistance reference unit column set by the method can accurately reflect the resistance characteristics of the actual MTJ element in the two magnetization states, thereby improving the reading reliability and reading margin of the MRAM, reducing the reading error rate, and ultimately improving the overall performance of the MRAM.

[0073] In an alternative embodiment, the metal line width of the high-resistance reference bit line and the low-resistance reference bit line is adjusted by adjusting the metal line width of the high-resistance reference bit line and the low-resistance reference bit line, including:

[0074] The metal layer thickness and material resistivity of the ordinary bit line are measured, and the sheet resistance of the ordinary bit line is calculated according to the metal layer thickness and material resistivity;

[0075] The metal line width of the high-resistance reference bit line and the low-resistance reference bit line is adjusted so that the deviation of the sheet resistance of the high-resistance reference bit line and the low-resistance reference bit line from the sheet resistance of the ordinary bit line is within the minimum tolerance range allowed by the manufacturing process, and the high-resistance reference bit line, the low-resistance reference bit line and the ordinary bit line use the same metal layer level and the same trace topology, so as to match the parasitic resistance of the high-resistance reference bit line and the low-resistance reference bit line with the parasitic resistance of the ordinary bit line.

[0076] First, the metal layer characteristics are measured to obtain the metal layer thickness and material resistivity of the ordinary bit line. The four-probe method is used to measure the metal layer sample. The test probe is placed on the surface of the metal layer, and a constant current is applied through the external two probes while the voltage drop between the internal two probes is measured. According to Ohm's law, combined with the known distance between the probes, the resistivity of the metal layer is calculated. For the metal layer thickness, a scanning electron microscope or an atomic force microscope can be used for cross-section observation and measurement.

[0077] When designing the high-resistance reference bit line, a narrower line width is selected under the premise of ensuring the minimum deviation of the sheet resistance from the sheet resistance of the ordinary bit line. Assuming that the minimum line width allowed by the process is 0.18 microns and the line width of the ordinary bit line is 0.5 microns, the high-resistance reference bit line can be designed to be 0.18 to 0.2 microns wide. In this way, the total resistance of the high-resistance reference bit line is about 2.5 to 2.8 times that of the ordinary bit line, while maintaining the consistency of the sheet resistance.

[0078] Correspondingly, when designing the low-resistance reference bit line, a wider line width, such as 0.8 to 1 micron, is selected so that the total resistance is about 0.5 to 0.625 times that of the ordinary bit line. Through circuit simulation verification, it is ensured that the designed line width can make the deviation of the sheet resistance of the high-resistance reference bit line and the low-resistance reference bit line from the sheet resistance of the ordinary bit line controlled within ±5%, meeting the minimum tolerance requirements allowed by the process.

[0079] In the layout and routing stage, the high resistance reference bit line, the low resistance reference bit line and the normal bit line should use the same metal layer. For example, if the normal bit line uses Metal 3 layer, the high resistance reference bit line and the low resistance reference bit line should also use Metal 3 layer. In addition, the three bit lines should have the same topology, including the similar number of turns, the similar turn angle and the similar cross mode with other metal layers.

[0080] In the implementation, the three bit lines can be designed in the "serpentine" topology, so that they have the same number of 90 degree turns in the same area. For example, in a 4mm2 area, each bit line is designed to have 4 90 degree turns, forming a "U" shaped topology. In this way, the consistency of the parasitic capacitance and inductance among the bit lines can be ensured, and the matching performance can be further enhanced.

[0081] By precisely adjusting the width of the high resistance reference bit line and the low resistance reference bit line, and ensuring that they have the same metal layer and topology as the normal bit line, the parasitic resistance of the three bit lines can be highly matched. In practical applications, such as differential amplifier design, the mismatch error can be controlled within 1% by using this method, and the circuit performance can be significantly improved.

[0082] To verify the design effect, the parasitic parameters after actual routing can be extracted by a post-simulation tool, and the parasitic resistance ratio between different bit lines can be calculated. Ideally, the parasitic resistance ratio between the high resistance reference bit line and the normal bit line should be close to the design value of 2.5 to 2.8, and the parasitic resistance ratio between the low resistance reference bit line and the normal bit line should be close to the design value of 0.5 to 0.625. If the actual extraction value deviates from the design target by more than 10%, the line width parameters need to be adjusted again.

[0083] By this method, the parasitic resistance matching among the high resistance reference bit line, the low resistance reference bit line and the normal bit line is achieved under the premise of ensuring the consistency of the sheet resistance, which provides effective support for the high precision design of integrated circuits.

[0084] In an alternative embodiment, making the number of transistors in the read path of the two reference bit lines equal to the number of transistors in the read path of the target memory cell includes:

[0085] A first pass transistor is connected in series between the high resistance reference bit line and the high resistance reference cell column, and a second pass transistor is connected in series between the low resistance reference bit line and the low resistance reference cell column. The size, threshold voltage and bias condition of the first and second pass transistors are the same as those of the pass transistor connecting the normal bit line and the target memory cell in the read path of the target memory cell, so that the on-resistance of the transistors in the read path of the high resistance reference bit line and the low resistance reference bit line and the drift characteristics with process, voltage and temperature are consistent with those of the read path of the target memory cell.

[0086] As the technology of memory chip develops, it is necessary to design efficient read pass structures to ensure the reliability and stability of memory read. The present embodiment provides a method to make the number of transistors in the read pass of both reference bit lines equal to the number of transistors in the read pass of the target memory cell.

[0087] In actual memory read operation, it is usually necessary to compare the resistance value of the target memory cell with the reference resistance value to determine the logic state of the memory cell. The reference resistance value is usually provided by a high resistance reference cell and a low resistance reference cell. In order to ensure the accuracy of the comparison, it is necessary to ensure that the target memory cell read pass and the reference bit line read pass have the same electrical characteristics.

[0088] In the design stage of the memory structure, the structure of the target memory cell read pass is determined. The target memory cell is connected to a common bit line through a pass transistor, which controls whether the target memory cell is selected for read operation. The number and type of transistors in the target memory cell read pass directly affect the size and stability of the read current.

[0089] A high resistance reference bit line read pass is designed. A first pass transistor is connected in series between the high resistance reference bit line and the high resistance reference cell column. The design of the first pass transistor needs to ensure that its size, threshold voltage and bias condition are the same as those of the pass transistor in the target memory cell read pass. The high resistance reference cell is usually programmed to a high resistance state, representing a certain logic value (such as logic "1").

[0090] At the same time, a low resistance reference bit line read pass is designed. A second pass transistor is connected in series between the low resistance reference bit line and the low resistance reference cell column. The size, threshold voltage and bias condition of the second pass transistor also need to be consistent with those of the pass transistor in the target memory cell read pass. The low resistance reference cell is usually programmed to a low resistance state, representing another logic value (such as logic "0").

[0091] To ensure the consistency of the pass transistors, the same process parameters and mask patterns are used in the transistor manufacturing process. The key parameters of the transistor, such as gate width, length and channel doping concentration, need to be strictly controlled to ensure that the pass transistors in the three read passes have the same electrical characteristics.

[0092] In terms of bias design, the same gate voltage and drain voltage are provided for the pass transistors in the three read passes. For example, during read operation, the gate voltage of the pass transistor can be set to the positive supply voltage VDD, while the source voltage is set to near ground potential, ensuring that the transistor works in the linear region or saturation region, depending on the design requirements of the memory.

[0093] By the above design, the transistor on-resistance in the high-resistance reference bit line read path and the transistor on-resistance in the low-resistance reference bit line read path and their drift characteristics with process, voltage, and temperature are consistent with those of the target memory cell read path. This consistency is crucial for the read margin of the memory and can effectively reduce read errors caused by process fluctuations, voltage fluctuations, or temperature changes.

[0094] In actual applications, when a read operation is performed, the target memory cell read path, the high-resistance reference bit line read path, and the low-resistance reference bit line read path are activated simultaneously. By comparing the current generated by the target memory cell with the currents generated by the two reference paths, the logic state of the target memory cell can be determined. Since the number of transistors in the three read paths is equal and their characteristics are consistent, any deviation caused by process, voltage, or temperature changes will be consistent in the three paths, thereby ensuring the accuracy of the read decision.

[0095] In addition, to further improve the matching of the read paths, a common centroid layout technique can be used in the layout design stage. The transistors in the three read paths are placed in similar positions and use the same direction and surrounding environment, minimizing the transistor characteristic deviation caused by layout position differences.

[0096] In the test and verification stage, the effectiveness of the design can be verified by the corner analysis method. Under different process corners (such as fast corner, typical corner, and slow corner), different supply voltages (such as minimum voltage, typical voltage, and maximum voltage), and different temperature conditions (such as minimum operating temperature, room temperature, and maximum operating temperature), the electrical characteristics of the three read paths are tested to ensure that they maintain good matching under various conditions.

[0097] The read path design achieved by the above method can effectively improve the read reliability of the memory, enhance the stability of the memory under different working conditions, and ultimately improve the overall performance and yield of the memory chip.

[0098] In an optional embodiment, the intermediate value of the high-resistance reference current and the low-resistance reference current is calculated as the dynamic reference current by a differential operation circuit, including:

[0099] The high-resistance reference current is input to the first current input end of the differential operation circuit, and the low-resistance reference current is input to the second current input end of the differential operation circuit;

[0100] A first current mirror branch and a second current mirror branch are set in the differential operation circuit, the first current mirror branch mirrors and copies the high-resistance reference current and multiplies it by a first weight coefficient, and the second current mirror branch mirrors and copies the low-resistance reference current and multiplies it by a second weight coefficient;

[0101] The first weight coefficient and the second weight coefficient are determined according to a tunnel magnetoresistance ratio of the magnetic tunnel junction, the average resistance value of the magnetic tunnel junction in an anti-parallel magnetization state and the average resistance value of the magnetic tunnel junction in a parallel magnetization state are measured, the tunnel magnetoresistance ratio is calculated as a ratio of the average resistance value in the anti-parallel magnetization state to the average resistance value in the parallel magnetization state, the first weight coefficient is set as a ratio of the tunnel magnetoresistance ratio to a sum of the tunnel magnetoresistance ratio and one, and the second weight coefficient is set as a difference between one and the first weight coefficient.

[0102] The weighted high-resistance reference current output by the first current mirror branch and the weighted low-resistance reference current output by the second current mirror branch are converged to a summing node, the weighted high-resistance reference current and the weighted low-resistance reference current are subjected to current-domain summing operation through the summing node, and the dynamic reference current is obtained.

[0103] In a sensing application of a magnetic tunnel junction (MTJ), the design of a reference current is crucial to reading accuracy and reliability. The present application provides a method for calculating an intermediate value of a high-resistance reference current and a low-resistance reference current as a dynamic reference current through a differential operation circuit, and the specific implementation process is as follows:

[0104] First, the high-resistance reference current is input to a first current input end of the differential operation circuit. The high-resistance reference current is usually generated by a reference MTJ unit in an anti-parallel magnetization state (AP state), at which time the MTJ presents a high-resistance state. At the same time, the low-resistance reference current is input to a second current input end of the differential operation circuit. The low-resistance reference current is generated by a reference MTJ unit in a parallel magnetization state (P state), at which time the MTJ presents a low-resistance state.

[0105] Two key current mirror branches are provided in the differential operation circuit: a first current mirror branch and a second current mirror branch. The first current mirror branch is mainly composed of a PMOS transistor pair, the gate of which is connected to the high-resistance reference current input end, the source of which is connected to a power supply voltage, and the drain of which outputs a mirror current. By adjusting the width-length ratio of the mirror transistor, the first current mirror branch mirrors and multiplies the high-resistance reference current by a first weight coefficient. In specific implementation, if the width-length ratio of the design reference transistor is (W / L)1 and the width-length ratio of the mirror transistor is (W / L)2, the current amplification factor, i.e., the first weight coefficient, is (W / L)2 / (W / L)1.

[0106] The second current mirror branch adopts a similar structure and is mainly composed of an NMOS transistor pair, the gate of which is connected to the low-resistance reference current input end, the source of which is connected to ground, and the drain of which outputs a mirror current. By adjusting the width-length ratio of the mirror transistor, the second current mirror branch mirrors and multiplies the low-resistance reference current by a second weight coefficient.

[0107] A key step is to determine the first weight coefficient and the second weight coefficient according to a tunnel magnetoresistance ratio (TMR) of the magnetic tunnel junction. First, MTJ characteristic measurement is performed. The average value RAP of the resistance values of a plurality of magnetic tunnel junctions in an anti-parallel magnetization state is calculated by measuring the resistance values of the plurality of magnetic tunnel junctions in the anti-parallel magnetization state. The average value RP of the resistance values of the plurality of magnetic tunnel junctions in a parallel magnetization state is calculated by measuring the resistance values of the plurality of magnetic tunnel junctions in the parallel magnetization state. The tunnel magnetoresistance ratio TMR is defined as the ratio of RAP to RP, i.e., TMR = RAP / RP.

[0108] Based on the measured TMR value, the first weight coefficient a is set as the ratio of TMR to the sum of (TMR + 1), i.e., a = TMR / (TMR + 1). For example, if TMR = 2 is measured, a = 2 / (2 + 1) = 2 / 3. Correspondingly, the second weight coefficient b is set as the difference between 1 and the first weight coefficient, i.e., b = 1 - a = 1 / (TMR + 1). In the above example, b = 1 - 2 / 3 = 1 / 3.

[0109] The weight coefficient setting makes the dynamic reference current closer to the theoretically optimal reference point, effectively improving the sensing margin. Specifically, when the resistance values of the MTJ present a nonlinear distribution between RAP and RP, the above-mentioned weighting manner can obtain a more optimized reference point position.

[0110] After the weight coefficient setting is completed, the weighted high-resistance reference current output by the first current mirror branch and the weighted low-resistance reference current output by the second current mirror branch are converged to a summation node. The summation node is usually a common connection point inside a differential operation circuit, such as a drain connection point of the two mirror circuits. At this node, the weighted high-resistance reference current and the weighted low-resistance reference current naturally perform current domain summation operation, i.e., Iref_dynamic = a Iref_high + b Iref_low, where Iref_high is the high-resistance reference current and Iref_low is the low-resistance reference current.

[0111] In actual implementation, a simple current buffer can be added at the later stage of the differential operation circuit to provide sufficient driving capability, so as to ensure that the dynamic reference current can be stably provided to the subsequent comparator circuit. The current buffer can be implemented by a simple current mirror circuit, which keeps the output current proportional to the dynamic reference current.

[0112] In order to improve system stability, a temperature compensation circuit can also be added in the differential operation circuit to offset the influence of temperature change on the resistance value of the MTJ. The compensation circuit usually includes a bandgap reference circuit and a temperature coefficient adjustable current source, which can dynamically adjust the weight coefficient according to temperature change, so as to ensure that the dynamic reference current can be kept at the optimal position in a wide temperature range.

[0113] The dynamic reference current obtained by the method can effectively adapt to the changes of MTJ device characteristics under different processes and temperature conditions, and improves the reading stability and reliability of the magnetic random access memory (MRAM).

[0114] In an alternative embodiment, the first current mirror branch and the second current mirror branch are arranged in the differential operational circuit, comprising:

[0115] The first reference transistor and the first mirror transistor are arranged in the first current mirror branch, the drain of the first reference transistor is connected to the first current input end to receive a high resistance reference current, the gate and the drain of the first reference transistor are shorted to form a diode connection structure, the gate of the first mirror transistor is connected to the gate of the first reference transistor, and the source of the first mirror transistor and the source of the first reference transistor are commonly connected to a power supply voltage.

[0116] The second reference transistor and the second mirror transistor are arranged in the second current mirror branch, the drain of the second reference transistor is connected to the second current input end to receive a low resistance reference current, the gate and the drain of the second reference transistor are shorted to form a diode connection structure, the gate of the second mirror transistor is connected to the gate of the second reference transistor, and the source of the second mirror transistor and the source of the second reference transistor are commonly connected to a power supply voltage.

[0117] The method for arranging the current mirror branch in the differential operational circuit relates to the field of analog integrated circuit design, in particular, the design of high-precision differential amplifiers. In this embodiment, the first current mirror branch and the second current mirror branch are first arranged in the differential operational circuit to achieve accurate current replication and matching.

[0118] In the first current mirror branch, the first reference transistor and the first mirror transistor are arranged. The first reference transistor is a PMOS transistor, and its drain is connected to the first current input end to receive a high resistance reference current. The high resistance reference current is usually derived from a bandgap reference circuit or other stable current source circuit. The gate and the drain of the first reference transistor are shorted to form a diode connection structure, which makes the transistor work in the saturation region and can generate a gate-source voltage proportional to the current. The first mirror transistor is also a PMOS transistor with the same size as the first reference transistor, and its gate is connected to the gate of the first reference transistor to share the same gate-source voltage. The source of the first mirror transistor and the source of the first reference transistor are commonly connected to the power supply voltage VDD to ensure that the two transistors have the same source potential.

[0119] In the second current mirror branch, a second reference transistor and a second mirror transistor are configured. The second reference transistor is a PMOS transistor, whose drain is connected to the second current input terminal for receiving a low-impedance reference current. The low-impedance reference current can come from a resistor bias network or other low-impedance current source. The gate of the second reference transistor is shorted to its drain to form a diode-connected structure, ensuring the transistor operates in the saturation region. The second mirror transistor is also a PMOS transistor with the same size as the second reference transistor, whose gate is connected to the gate of the second reference transistor, sharing the same gate-source voltage. The source of the second mirror transistor is connected to the source of the second reference transistor, which is connected to the power supply voltage VDD.

[0120] After the current mirror branches are set up, accurate current replication is performed. In the first current mirror branch, when the high-impedance reference current flows through the first reference transistor, a voltage is established between its gate and source, which is also applied between the gate and source of the first mirror transistor. Since the two transistors share the same gate-source voltage and have the same size ratio, the first mirror transistor will generate a mirror current proportional to the high-impedance reference current. The size of the mirror current depends on the size ratio of the two transistors, and if they have the same size, the mirror current is equal to the reference current.

[0121] Similarly, in the second current mirror branch, when the low-impedance reference current flows through the second reference transistor, a voltage is established between its gate and source, which is also applied between the gate and source of the second mirror transistor. The second mirror transistor will generate a mirror current proportional to the low-impedance reference current.

[0122] To improve the accuracy of current mirroring, the channel length and width of the transistors can be adjusted. In practical implementation, choosing a longer channel length can reduce the channel modulation effect, increase the output impedance, and thus improve the accuracy of current mirroring. For example, transistors with a channel length of 2 μm or longer can be selected, and the channel width can be adjusted to meet the required current level.

[0123] To address the impact of temperature changes on the accuracy of current mirroring, a common centroid layout technique can be used when laying out the transistors, ensuring that the temperature gradient is symmetrically distributed on the reference transistor and the mirror transistor. In addition, a guard ring can be added around the transistors to reduce the impact of parasitic effects on the accuracy of current mirroring.

[0124] In practical applications, it may be necessary to adjust the current ratio of the first current mirror branch and the second current mirror branch. By changing the width-to-length ratio of the mirror transistor and the reference transistor, different mirroring ratios can be achieved. For example, if the current of the first mirror transistor needs to be twice that of the first reference transistor, the width-to-length ratio of the first mirror transistor can be designed to be twice that of the first reference transistor.

[0125] After the current mirror branch is established, it needs to be connected with other parts of the differential operation circuit. The drain of the first mirror transistor can be connected to the first load resistance of the differential operation circuit, and the drain of the second mirror transistor is connected to the second load resistance of the differential operation circuit. Through this connection mode, the differential operation circuit can be provided with a matched bias current, thereby improving the common-mode rejection ratio and power supply rejection ratio of the differential operation circuit.

[0126] For high-precision applications, the current mirror branch can be further optimized. By adding a cascade transistor between the first reference transistor and the first mirror transistor, the output impedance can be increased, and the influence of the drain voltage change on the mirror current can be reduced. Similarly, a cascade transistor can also be added between the second reference transistor and the second mirror transistor.

[0127] In actual circuits, in order to prevent the current mirror branch from being affected by power supply noise, a decoupling capacitor can be added between the power supply voltage VDD and the connection point of the first and second current mirror branches to filter out power supply noise and improve the stability of the current mirror.

[0128] The present application also provides another specific embodiment:

[0129] Reference Figure 2 and Figure 3 As shown in Figure 2 , the new array architecture proposed by the present application includes a storage array, a dedicated reference cell column, and a sensitive amplifier. The core innovation of this architecture is that a column of dedicated reference cells is additionally provided for each group of storage arrays to provide stable reference current during read operation.

[0130] Specifically, the storage array adopts a conventional 1T1R (one transistor one resistance) structure, and each storage cell includes a MOS transistor and a magnetic tunnel junction (MTJ). The drain of the MOS transistor in the storage cell is connected to one end of the MTJ, the other end of the MTJ in each column of storage cells is connected through a bit line (BL), and the source of the MOS transistor in each column of storage cells is connected through a source line (SL); the reference cell column is connected to the node between the drain of the MOS transistor and the MTJ through a reference bit line (REFBL), and the source of the MOS transistor in each storage cell is connected through a reference source line (REFSL).

[0131] The structure design of the reference cell column is as follows:

[0132] Implementation of reference resistance: In order to avoid the initialization difficulty problem caused by using MTJ as reference resistance, the reference resistance in this design is completely realized by poly resistance. The resistance value of the reference resistance is set to an intermediate value between the high resistance state and the low resistance state of the MTJ, so as to ensure that the two storage states of the storage cell can be accurately distinguished.

[0133] Connection of reference bit line (REFBL): The reference bit line is connected to the node between the MOS tube drain and MTJ of all cells in the reference cell column. During the read operation, the reference bit line is directly connected to the reference source line through a MOS tube in the reference array, which depends on which word line is selected.

[0134] Processing of original bit line: The original bit line (BLR) of the reference cell column is set to be floating, and does not participate in the current path of the read operation, so as to avoid interference to the reference signal.

[0135] Connection of reference source line (REFSL): The reference source line is grounded through a MOS tube M2, which is consistent with the grounding mode of the conventional source line.

[0136] As shown in FIG. 2, the figure shows the detailed structure of the circuit on both sides of the sense amplifier, including the storage cell side and the reference cell side. During the read operation, one input end of the sense amplifier is connected to the bit line of the target storage cell, and the other input end is connected to the reference bit line. Figure 3

[0137] Analysis of circuit path:

[0138] The read path of the target storage cell is: MOS tube → bit line (BL) → MTJ → MOS tube → source line (SL) → MOS tube → ground. The total resistance on the path includes: bit line parasitic resistance RBL, MOS tube on-resistance, MTJ resistance, source line parasitic resistance RSL.

[0139] The read path of the reference cell is: MOS tube → reference bit line (REFBL) → MOS tube → MTJ → reference source line (SL) → MOS tube → ground. The total resistance on the path includes: reference bit line parasitic resistance RREFBL, MOS tube on-resistance, reference resistance (RREF) reference source line parasitic resistance RREFSL.

[0140] Parasitic resistance matching design:

[0141] The key technical feature of the present application is that the metal line width of the reference bit line (REFBL) is adjusted so that the unit length resistance (i.e. sheet resistance) is consistent with that of the ordinary bit line (BL). At the same time, the length of the reference bit line is designed to be the same as that of the bit line where the target cell is located. In this way, the parasitic line resistance (RREFBL, RREFSL) on the reference resistance path can be accurately matched with the parasitic resistance (RBL, RSL) on the read path of the target cell.

[0142] ​In addition, the number of MOS transistors in the two paths is completely consistent: the target cell path passes through the MOS transistors in the storage cell, and the reference path also passes through the MOS transistors in the reference cell and the MOS transistor M2. By reasonably setting the size of the MOS transistor, the total on-resistance of the MOS transistors in the two paths can be kept consistent.

[0143] Read operation flow:

[0144] When a certain storage cell needs to be read, first, the storage cell is selected through the word line, so that the internal MOS transistor is turned on; at the same time, the MOS transistor in the corresponding row of the reference cell column is enabled. Subsequently, read voltages are applied on the bit line and the reference bit line, and read currents flow through the target cell and the reference cell respectively. Due to the matching of parasitic resistance and MOS transistor on-resistance, the current on both sides only fluctuates due to the influence of process, temperature on MTJ and poly resistance. By comparing the two currents through the sensitive amplifier, it can be determined whether the storage cell stores "0" or "1".

[0145] Through the above design, no matter whether the target storage cell is located at the near end or the far end of the array, the parasitic resistance on the reference path can be kept consistent with the target path, thereby eliminating the near-far end cell read window deviation caused by the difference in parasitic resistance of the bit line and the source line. At the same time, due to the complete matching of the number and size of the MOS transistors in the two paths, even when the process, voltage, and temperature (PVT) conditions change, the drift of the MOS transistor on-resistance will occur synchronously in the two paths, which will not affect the stability of the read window, thereby significantly reducing the read error rate.

[0146] The magnetic core random memory read reference circuit architecture design system of the embodiment of the application comprises:

[0147] The first unit is configured to set a high-resistance reference cell column and a low-resistance reference cell column in each storage array, wherein the high-resistance reference cell column comprises a transistor and a first polysilicon resistance in series, and the low-resistance reference cell column comprises a transistor and a second polysilicon resistance in series, the resistance value of the first polysilicon resistance is equivalent to the high-resistance state resistance value of the magnetic tunnel junction, and the resistance value of the second polysilicon resistance is equivalent to the low-resistance state resistance value of the magnetic tunnel junction.

[0148] The second unit is configured to configure a high-resistance reference bit line and a low-resistance reference bit line for the high-resistance reference cell column and the low-resistance reference cell column respectively, and adjust the metal line width of the high-resistance reference bit line and the low-resistance reference bit line, so that the square resistance of the two reference bit lines is equal to the square resistance of the ordinary bit line, and the number of transistors in the two reference bit lines in the read path is equal to the number of transistors in the target storage cell read path.

[0149] The third unit is configured to read resistance values of the target storage unit, the high-resistance reference unit and the low-resistance reference unit simultaneously in a read operation to obtain a target read current, a high-resistance reference current and a low-resistance reference current;

[0150] The fourth unit is configured to calculate an intermediate value of the high-resistance reference current and the low-resistance reference current as a dynamic reference current through a difference operation circuit, and the dynamic reference current is self-adaptively adjusted according to changes in parasitic resistance and transistor on-resistance on paths of the high-resistance reference unit and the low-resistance reference unit.

[0151] The fifth unit is configured to compare the target read current with the dynamic reference current through a sensitive amplifier to determine whether data is stored in the target storage unit.

[0152] In a third aspect, an electronic device is provided, including:

[0153] a processor;

[0154] a memory for storing processor-executable instructions;

[0155] The processor is configured to invoke the instructions stored in the memory to execute the method described above.

[0156] In a fourth aspect, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method described above.

[0157] The present application can be a method, device, system and / or computer program product. The computer program product can include a computer-readable storage medium having stored thereon computer-readable program instructions that, when executed by a computer, cause the computer to carry out various aspects of the present application.

[0158] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for designing a read reference circuit architecture for a magnetic core random access memory, characterized in that, The method is applied to a magnetic core random access memory system comprising multiple memory arrays, each memory array comprising multiple rows and columns of memory cells, each memory cell comprising a transistor and a magnetic tunnel junction connected in series, including: Each memory array includes a high-resistance reference cell column and a low-resistance reference cell column. The high-resistance reference cell column comprises a transistor connected in series with a first polysilicon resistor, and the low-resistance reference cell column comprises a transistor connected in series with a second polysilicon resistor. The resistance of the first polysilicon resistor is equivalent to the high-resistance state resistance of the magnetic tunnel junction, and the resistance of the second polysilicon resistor is equivalent to the low-resistance state resistance of the magnetic tunnel junction. High-resistance reference bit lines and low-resistance reference bit lines are respectively configured for the high-resistance reference cell column and the low-resistance reference cell column. By adjusting the metal line width of the high-resistance reference bit lines and the low-resistance reference bit lines, the sheet resistance of the two reference bit lines is made equal to the sheet resistance of the ordinary bit lines, and the number of transistors in the read path of the two reference bit lines is made equal to the number of transistors in the read path of the target memory cell. During the read operation, the resistance values ​​of the target memory cell, the high-impedance reference cell, and the low-impedance reference cell are read simultaneously to obtain the target read current, the high-impedance reference current, and the low-impedance reference current. The intermediate value between the high-resistance reference current and the low-resistance reference current is calculated by a differential operational circuit and used as a dynamic reference current. The dynamic reference current is adaptively adjusted according to the parasitic resistance and transistor on-resistance on the paths of the high-resistance reference cell and the low-resistance reference cell. The target read current is compared with the dynamic reference current by a sensitive amplifier to determine whether data is stored in the target storage unit.

2. The method according to claim 1, characterized in that, Setting up high-impedance reference cell columns and low-impedance reference cell columns in each memory array includes: Batch resistance characteristic tests were performed on the magnetic tunnel junctions in the memory array. The resistance distribution curves of the magnetic tunnel junctions in the antiparallel magnetization state and the parallel magnetization state were measured under multiple process angles and temperature conditions. The statistical median and standard deviation of the resistance distribution curves were extracted. The nominal resistance value of the first polysilicon resistor is determined based on the statistical median value under the antiparallel magnetization state, and the nominal resistance value of the second polysilicon resistor is determined based on the statistical median value under the parallel magnetization state.

3. The method according to claim 1, characterized in that, By adjusting the metal line widths of the high-resistivity reference bit line and the low-resistivity reference bit line, including: Measure the metal layer thickness and material resistivity of a common bit line, and calculate the sheet resistance of the common bit line based on the metal layer thickness and material resistivity; The metal line widths of the high-resistance reference bit line and the low-resistance reference bit line are adjusted so that the deviation between their sheet resistance and the sheet resistance of the ordinary bit line is within the minimum tolerance range allowed by the manufacturing process. The high-resistance reference bit line, the low-resistance reference bit line and the ordinary bit line adopt the same metal layer and the same routing topology to achieve matching between the parasitic resistance of the high-resistance reference bit line and the low-resistance reference bit line and the parasitic resistance of the ordinary bit line.

4. The method according to claim 3, characterized in that, Ensuring that the number of transistors in both reference bit lines in the read path is equal to the number of transistors in the read path of the target memory cell includes: A first gate transistor is connected in series between the high-resistance reference bit line and the high-resistance reference cell column, and a second gate transistor is connected in series between the low-resistance reference bit line and the low-resistance reference cell column. The size, threshold voltage, and bias conditions of the first and second gate transistors are the same as those of the gate transistors connecting the ordinary bit line and the target memory cell in the target memory cell read path, so that the on-resistance of the transistors in the high-resistance reference bit line read path and the drift characteristics of the transistors with process, voltage, and temperature are consistent with those of the target memory cell read path.

5. The method according to claim 1, characterized in that, The intermediate value between the high-impedance reference current and the low-impedance reference current is calculated using a differential operational circuit as the dynamic reference current, including: A high-impedance reference current is input to the first current input terminal of the differential operational circuit, and a low-impedance reference current is input to the second current input terminal of the differential operational circuit. In the differential operation circuit, a first current mirror branch and a second current mirror branch are set up. The first current mirror branch mirrors and copies the high-impedance reference current and multiplies it by a first weighting coefficient. The second current mirror branch mirrors and copies the low-impedance reference current and multiplies it by a second weighting coefficient. The first weighting coefficient and the second weighting coefficient are determined based on the tunnel reluctance ratio of the magnetic tunnel junction. The tunnel reluctance ratio is calculated by measuring the average resistance of the magnetic tunnel junction in the antiparallel magnetization state and the average resistance in the parallel magnetization state. Based on the tunnel reluctance ratio, the first weighting coefficient is set as the ratio of the tunnel reluctance ratio to the sum of the tunnel reluctance ratio and one. The second weighting coefficient is set as the difference between one and the first weighting coefficient. The weighted high-resistance reference current output from the first current mirror branch and the weighted low-resistance reference current output from the second current mirror branch are converged to a summing node. The weighted high-resistance reference current and the weighted low-resistance reference current are summed in the current domain through the summing node to obtain the dynamic reference current.

6. The method according to claim 5, characterized in that, In a differential operational circuit, a first current mirror branch and a second current mirror branch are set up, including: In the first current mirror branch, a first reference transistor and a first mirror transistor are configured. The drain of the first reference transistor is connected to the first current input terminal to receive a high-impedance reference current. The gate and drain of the first reference transistor are shorted to form a diode connection structure. The gate of the first mirror transistor is connected to the gate of the first reference transistor. The source of the first mirror transistor and the source of the first reference transistor are connected to the power supply voltage. A second reference transistor and a second mirror transistor are configured in the second current mirror branch. The drain of the second reference transistor is connected to the second current input terminal to receive a low-impedance reference current. The gate and drain of the second reference transistor are shorted to form a diode connection structure. The gate of the second mirror transistor is connected to the gate of the second reference transistor. The source of the second mirror transistor and the source of the second reference transistor are connected to the power supply voltage.

7. A magnetic core random access memory read reference circuit architecture design system for implementing the method as described in any one of claims 1-6, characterized in that, include: The first unit is used to set a high-resistance reference cell column and a low-resistance reference cell column in each memory array. The high-resistance reference cell column includes a transistor and a first polysilicon resistor connected in series. The low-resistance reference cell column includes a transistor and a second polysilicon resistor connected in series. The resistance value of the first polysilicon resistor is equivalent to the high-resistance state resistance value of the magnetic tunnel junction, and the resistance value of the second polysilicon resistor is equivalent to the low-resistance state resistance value of the magnetic tunnel junction. The second unit is used to configure high-resistance reference bit lines and low-resistance reference bit lines for the high-resistance reference cell column and the low-resistance reference cell column, respectively. By adjusting the metal line width of the high-resistance reference bit lines and the low-resistance reference bit lines, the sheet resistance of the two reference bit lines is made equal to the sheet resistance of the ordinary bit lines, and the number of transistors in the read path of the two reference bit lines is made equal to the number of transistors in the read path of the target memory cell. The third unit is used to simultaneously read the resistance values ​​of the target memory cell, the high-impedance reference cell, and the low-impedance reference cell during a read operation, thereby obtaining the target read current, the high-impedance reference current, and the low-impedance reference current. The fourth unit is used to calculate the intermediate value between the high-resistance reference current and the low-resistance reference current through a differential operation circuit as a dynamic reference current. The dynamic reference current is adaptively adjusted according to the changes in parasitic resistance and transistor on-resistance on the paths of the high-resistance reference unit and the low-resistance reference unit. The fifth unit is used to compare the target read current with the dynamic reference current through a sensitive amplifier to determine whether data is stored in the target storage unit.

8. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 6.

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