Modulation method for increasing double-continuation time of ANPC topology and improving power quality
By monitoring the voltage period at the output of the ANPC three-level topology circuit, controlling the switching state and delay filtering, the complexity of dual-loop freewheeling modulation and power quality issues in the ANPC three-level topology are solved, achieving loss balance and power quality optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 天津瑞源电气有限公司
- Filing Date
- 2026-01-13
- Publication Date
- 2026-07-03
AI Technical Summary
The existing dual-loop freewheeling modulation method of the ANPC three-level topology is complex and has low reliability. It requires the selection of specific wave generation methods for different operating conditions, which leads to complex control and introduces additional losses and power quality degradation.
By monitoring the AC voltage cycle at the output of the ANPC three-level topology circuit, the switching states of the inner tube, outer tube, and clamping tube are controlled to extend the dual freewheeling time. The modulation signal is processed by delay filtering, and the pulse width control of the clamping tube is optimized to form a stable bidirectional dual-loop freewheeling.
It achieves loss balancing and reduction under all operating conditions, reduces diode reverse recovery loss, optimizes power quality, simplifies control logic, and extends dual-loop freewheeling time.
Smart Images
Figure CN121530205B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics, and more specifically to a modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology. Background Technology
[0002] The ANPC (Active Neutral Point Clamped) three-level topology is a dual-loop freewheeling modulation method in the existing topology. Its core is to configure two parallel freewheeling loops for the inductor current in the zero-level (O) state of the ANPC three-level topology. By distributing the losses through dual-loop freewheeling, the device's local overheating caused by single-branch freewheeling is avoided, and the internal temperature of the three-level topology drops significantly.
[0003] Current dual-loop freewheeling modulation methods are complex because the ANPC three-level topology needs to be adapted to various operating conditions such as rectification, inversion, and power factor less than 1. The current direction, power flow direction, and voltage polarity differ significantly under different operating conditions, which requires the design of different waveform generation methods. This makes the existing dual-loop freewheeling modulation methods quite complex, requiring the selection of specific waveform generation methods under specific operating conditions. This method is not only complex to control but also has low reliability.
[0004] Furthermore, while current dual-loop freewheeling modulation methods achieve current shunting and loss sharing by adding an extra freewheeling branch, this design also introduces new sources of loss. Current flowing through the additional branch causes reverse recovery losses in the diodes on that branch. Simultaneously, due to the dead-time issue, dual-loop freewheeling starts relatively late, and loss optimization fails to achieve optimal results.
[0005] Current dual-loop freewheeling modulation methods introduce more dead zones due to the addition of dual-loop freewheeling states, and are also limited by the narrowest pulse width. The existence of these dead zones affects the output power quality. Summary of the Invention
[0006] This invention overcomes the shortcomings of the prior art and provides a modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology.
[0007] The objective of this invention is achieved through the following technical solution.
[0008] A modulation method for increasing the double freewheeling time and improving power quality of an ANPC topology is disclosed. This method involves connecting a single ANPC three-level topology circuit or multiple ANPC three-level topology circuits in parallel. The ANPC three-level topology circuit is monitored to determine the period of the AC voltage at its output terminal. Based on this period, the inner transistor, outer transistor, and clamping transistor in the ANPC three-level topology circuit are controlled at the start and end times of the non-zero level state, the start and end times of the zero-level freewheeling, thereby modulating the circuit.
[0009] The ANPC three-level topology circuit includes capacitors C1 and C2 connected in series on the DC input side of the circuit. The negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2. The collector of switching transistor T1 is connected to the positive terminal of capacitor C1. The emitter of switching transistor T1 is connected to the collector of switching transistor T2. The emitter of switching transistor T2 is connected to the collector of switching transistor T3. The emitter of switching transistor T3 is connected to the collector of switching transistor T4. The emitter of switching transistor T4 is connected to the capacitor C2. Negative terminal connection; Switches T5 and T6 are connected in series, with the emitter of T5 connected to the collector of T6, the midpoint of T5 and T6 connected to the midpoint of capacitors C1 and C2, the collector of T5 connected to the midpoint of T1 and T2, and the emitter of T6 connected to the midpoint of T3 and T4; the midpoint of T2 and T3 is connected to the AC output side.
[0010] Switching transistors T2 and T3 are inner transistors; switching transistors T1 and T4 are outer transistors; switching transistors T5 and T6 are clamping transistors; switching transistors T1, T2, and T5 are located in the upper bridge arm; switching transistors T3, T4, and T6 are located in the lower bridge arm.
[0011] When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the positive half-cycle, the switching transistor T2 is normally on.
[0012] When the non-zero level state begins, switch T1 is turned on first, and after a preset time t1, switch T6 is turned on.
[0013] When the non-zero level state ends, switch T6 remains on and turns off switch T1.
[0014] When the zero-level freewheeling starts, switch T6 remains on and does not operate. Switch T5 is turned on first, and after a preset time t2, switch T3 is turned on to form a bidirectional dual-loop freewheeling.
[0015] When the zero-level freewheeling ends, switch T3 is turned off first, and after a preset time t3, switches T5 and T6 are turned off.
[0016] When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the negative half-cycle, the switching transistor T3 is normally on.
[0017] When the non-zero level state begins, switch T4 is turned on first, and after a preset time t1, switch T5 is turned on.
[0018] When the non-zero level state ends, switch T5 remains on and turns off switch T4;
[0019] When the zero-level freewheeling starts, switch T5 remains on and does not operate. Switch T6 is turned on first, and after a preset time t2, switch T2 is turned on to form a bidirectional dual-loop freewheeling.
[0020] When the zero-level freewheeling ends, switch T2 is turned off first, and after a preset time t3, switches T5 and T6 are turned off.
[0021] When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the positive half-cycle, the switching transistor T2 is normally on.
[0022] When the positive level state begins, switch T1 is turned on first, and after a preset time t1, switch T6 is turned on.
[0023] When the positive level state ends, switch T6 is turned off first, and after a preset time t2, switch T1 is turned off.
[0024] When the zero-level freewheeling starts, switch transistors T5 and T6 are turned on first. After a preset time t3, switch transistor T3 is turned on to form a bidirectional dual-loop freewheeling.
[0025] When the zero-level freewheeling ends, switch T3 is turned off first, and after a preset time t4, switches T5 and T6 are turned off.
[0026] When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the negative half-cycle, the switching transistor T3 is normally on.
[0027] When the negative level state begins, switch T4 is turned on first, and switch T5 is turned on after a preset time t1.
[0028] When the negative level state ends, switch T5 is turned off first, and after a preset time t2, switch T4 is turned off.
[0029] When the zero-level freewheeling starts, switch transistors T5 and T6 are turned on first. After a preset time t3, switch transistor T2 is turned on to form a bidirectional dual-loop freewheeling.
[0030] When the zero-level freewheeling ends, switch T2 is turned off first, and after a preset time t4, switches T5 and T6 are turned off.
[0031] The modulation signal generated by the ANPC three-level topology circuit during modulation is the original modulation signal. The generated original modulation signal is then subjected to delay filtering, and the processed signal is used as the final modulation signal and sent to the corresponding switching transistor.
[0032] The original modulation signal and the final modulation signal are a low-level signal and a high-level signal, respectively. The high-level signal is the turn-on signal of the switching transistor, and the low-level signal is the turn-off signal of the switching transistor. After the signal is flipped, it remains unchanged and waits for the next flip.
[0033] When the original modulation signal flips from low to high, the delay filtering process begins with a delay of a preset time t4. After the delay ends, if the original modulation signal remains high, the final modulation signal flips from low to high. If the original modulation signal flips to low after the delay ends, the final modulation signal remains low. When the original modulation signal flips from high to low, the delay filtering process begins with a delay of a preset time t4. After the delay ends, the final modulation signal flips to low.
[0034] The beneficial effects of this invention are as follows:
[0035] This application overcomes the following three technical problems by improving the existing method.
[0036] 1. This solution, while achieving loss balancing in dual-loop freewheeling, overcomes the technical problems inherent in existing technologies that require specific waveforms to be used under specific operating conditions due to the need to modulate the dual-loop freewheeling under different conditions such as rectification, inversion, and low power factor (power factor less than 1). This technical problem leads to the complexity of existing dual-loop freewheeling modulation methods and lower control reliability.
[0037] 2. Existing dual-loop freewheeling modulation methods, while achieving current shunting and loss sharing by adding an extra freewheeling branch, also introduce new sources of loss. Current flowing through the extra branch causes reverse recovery losses in the diodes of that branch. The modulation method provided in this application controls the corresponding clamping transistor switch of the ANPC three-level topology circuit at the start and end times of the non-zero-level state, the start and end times of the zero-level freewheeling, thus cutting off the extra branch current generated at the corresponding times. This not only reduces the reverse recovery losses of the diodes in the dual freewheeling loop but also, by controlling the clamping transistor switch, advances the start time of the dual-loop freewheeling, further balancing and reducing losses.
[0038] 3. Existing dual-loop freewheeling modulation methods introduce significant dead time during switching between single and dual freewheeling in the zero-level freewheeling state due to the dual-loop freewheeling. This forces the clamping transistor's pulse width to exceed the sum of its internal pulse width and the dead time. The limitation imposed by the narrowest pulse width on the internal transistor lengthens the clamping transistor's narrowest pulse width, further increasing the minimum zero-level freewheeling time and degrading power quality. The modulation method provided in this application, through software delay filtering, ensures that the clamping transistor's pulse width is limited only by the device's narrowest pulse width, thereby optimizing the power quality issues caused by the large dead time in the dual freewheeling loop. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of the ANPC three-level topology circuit;
[0040] Figure 2 This is a schematic diagram of the modulation signals of each switch in the ANPC three-level topology circuit during the positive half-cycle of the voltage in Embodiment 2.
[0041] Figure 3 This is a schematic diagram of the modulation signals of each switch in the ANPC three-level topology circuit during the negative half-cycle of the voltage in Embodiment 2.
[0042] Figure 4 This is a diagram showing the state changes of the ANPC three-level topology circuit in Example 2 under inverter or power factor 1 conditions.
[0043] Figure 5 This is a diagram showing the state changes of the ANPC three-level topology circuit in Example 2 under rectification or low power factor conditions.
[0044] Figure 6 This is a schematic diagram of the modulation signals of each switch in the positive half-cycle of the voltage in the ANPC three-level topology of Embodiment 3;
[0045] Figure 7 This is a schematic diagram of the modulation signals of each switch in the negative half-cycle of the voltage in the ANPC three-level topology of Embodiment 3;
[0046] Figure 8 This is a diagram showing the state changes of the ANPC three-level topology in Example 3 under inverter or power factor 1 operating conditions;
[0047] Figure 9 This is a diagram showing the state changes of the ANPC three-level topology in Example 3 under rectification or low power factor conditions.
[0048] Figure 10 This is a schematic diagram illustrating the effect of delay filtering on the original modulated signal.
[0049] Figure 11 This is a schematic diagram illustrating the effect of time delay filtering on the original modulation signal during the positive half-cycle of the voltage to generate the final modulation signal. Detailed Implementation
[0050] The technical solution of the present invention will be further described below through specific embodiments.
[0051] Example 1
[0052] A modulation method for increasing the double freewheeling time and improving power quality of an ANPC topology is disclosed. This method involves connecting a single ANPC three-level topology circuit or multiple ANPC three-level topology circuits in parallel. The ANPC three-level topology circuit is monitored to determine the period of the AC voltage at its output terminal. Based on this period, the inner transistor, outer transistor, and clamping transistor in the ANPC three-level topology circuit are controlled at the start and end times of the non-zero level state, the start and end times of the zero-level freewheeling, thereby modulating the circuit.
[0053] This solution implements zero-level bidirectional dual-loop freewheeling in the ANPC three-level topology circuit, achieving loss balance and reduction under all operating conditions. By controlling the switching state of the clamping transistor at the start and end times of the non-zero-level state, the start and end times of the zero-level freewheeling, the reverse recovery loss generated by the diode in the dual-loop freewheeling is reduced, allowing the dual-loop freewheeling state to be entered earlier, i.e., two independent current loops exist simultaneously. This method extends the dual-loop freewheeling time, further balancing and reducing energy loss.
[0054] like Figure 1As shown, the ANPC three-level topology circuit includes capacitors C1 and C2 connected in series on the DC input side of the ANPC three-level topology circuit. The negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2. The collector of switch T1 is connected to the positive terminal of capacitor C1. The emitter of switch T1 is connected to the collector of switch T2. The emitter of switch T2 is connected to the collector of switch T3. The emitter of switch T3 is connected to the collector of switch T4. The emitter of switch T4 is connected to the negative terminal of capacitor C2. 5 is connected in series with switch T6. The emitter of switch T5 is connected to the collector of switch T6. The midpoint connection point of switch T5 and switch T6 is connected to the midpoint connection point of capacitor C1 and capacitor C2. The collector of switch T5 is connected to the midpoint connection point of switch T1 and switch T2. The emitter of switch T6 is connected to the midpoint connection point of switch T3 and switch T4. The midpoint connection point of switch T2 and switch T3 is connected to the AC side of the output terminal, which is used to output a three-level AC voltage.
[0055] Switching transistors T2 and T3 are inner transistors; switching transistors T1 and T4 are outer transistors; switching transistors T5 and T6 are clamping transistors; switching transistors T1, T2, and T5 are located in the upper bridge arm; switching transistors T3, T4, and T6 are located in the lower bridge arm.
[0056] The switching transistors are IGBT or MOSFET semiconductor switching devices.
[0057] The full operating conditions of the ANPC three-level topology circuit can be summarized into four operating conditions:
[0058] Positive voltage half-cycle: Half a power frequency cycle during which the voltage on the AC side of the output terminal switches between "positive level VDC" and "zero level VDC / 2".
[0059] Voltage negative half-cycle: Half a power frequency cycle during which the voltage on the AC side of the output terminal switches between "negative level 0" and "zero level VDC / 2".
[0060] Positive half-cycle of current: half a power frequency cycle of current flowing out from the DC side of the input terminal, through the ANPC three-level topology circuit, and then out from the AC side of the output terminal.
[0061] Negative half-cycle of current: The current flows in from the AC side of the output terminal, flows through the ANPC three-level topology circuit, and then flows into the DC side of the input terminal for half a power frequency cycle.
[0062] The above four cycles can be combined in pairs to cover all operating conditions of the ANPC three-level topology, namely the positive half-cycle of voltage and the positive half-cycle of current, the positive half-cycle of voltage and the negative half-cycle of current, the negative half-cycle of voltage and the positive half-cycle of current, and the negative half-cycle of voltage and the negative half-cycle of current, covering all operating conditions of rectification, inversion, and power factor between 0 and 1.
[0063] In summary, this solution can achieve bidirectional dual-circuit freewheeling without considering the positive and negative half-cycles of the current; only the half-cycle of the voltage needs to be determined to achieve the above functions.
[0064] Example 2
[0065] Based on Example 1, such as Figure 2 As shown, when the power factor is 1, the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the positive half-cycle, and the switching transistor T2 is normally on.
[0066] like Figure 2 As shown in the circle on the right, when the zero-level freewheeling ends, switch T3 is turned off first, and after a preset delay t3, switches T5 and T6 are turned off. During this period, the current path changes from the original four current paths to one current path.
[0067] The original four current paths specifically included:
[0068] 1. Input DC side to diode D5 to switch T2 to output AC side.
[0069] 2. The input DC side leads to the switching transistor T6, then to the diode D3, and finally to the output AC side.
[0070] 3. Output AC side to diode D2 to switch T5 to input DC side.
[0071] 4. The AC side of the output terminal connects to the switching transistor T3, the diode D6, and the DC side of the input terminal.
[0072] The switched path is: from the DC side of the input terminal to diode D5, to the switch T2, to the AC side of the output terminal.
[0073] When the non-zero level state begins, switch T1 is turned on first, and after a preset delay t1, switch T6 is turned on. During this period, the current path changes from the original path from the DC side of the input terminal to diode D5 to switch T2 to the AC side of the output terminal to the DC side of the input terminal to switch T1 to switch T2 to the AC side of the output terminal.
[0074] In the two steps above, the zero-level current freewheeling path is switched from two current paths to one current path, and only one current freewheeling path is retained when the switching transistor T1 is turned on.
[0075] This operation reduces the reverse recovery loss of diodes. Of the two diodes that should have performed reverse recovery in the two freewheeling circuits, namely diode D5 and diode D3, only diode D5 needs to perform reverse recovery.
[0076] Therefore, when switching between non-zero level and zero level states, it is necessary to shut down the additional branch in a timely manner to reduce the reverse recovery loss of the diode in the dual freewheeling circuit.
[0077] like Figure 2 As shown in the left circle, when the non-zero level state ends, switch T6 remains on and switches T1 are off. During this period, the current path changes from the original path from the DC input side to switch T1 to switch T2 to the AC output side to two paths: the DC input side to diode D5 to switch T2 to the AC output side, and the DC input side to switch T6 to diode D3 to the AC output side.
[0078] In this step, after switch T1 is turned off, since switch T6 remains on, a dual freewheeling circuit can be formed immediately to enable early entry into the dual freewheeling circuit, thereby extending the freewheeling time of the dual circuit and further balancing and reducing energy loss.
[0079] When the zero-level freewheeling begins, switch T6 remains on without operating. Switch T5 is turned on first, and after a preset delay of t2, switch T3 is turned on.
[0080] During this period, the current path changes from the original two paths—from the DC side of the input terminal to diode D5 to switch T2 to the AC side of the output terminal and from the DC side of the DC input terminal to switch T6 to diode D3 to the AC side of the output terminal—to the following four current paths, forming a bidirectional dual-loop freewheeling current.
[0081] The four switching current paths are as follows:
[0082] 1. Input DC side to diode D5 to switch T2 to output AC side.
[0083] 2. The input DC side leads to the switching transistor T6, then to the diode D3, and finally to the output AC side.
[0084] 3. Output AC side to diode D2 to switch T5 to input DC side.
[0085] 4. The DC side of the input terminal connects to the switching transistor T3, the diode D6, and the DC side of the input terminal.
[0086] In summary, the modulation method provided in this application only needs to determine the positive and negative half-cycles of the AC side voltage at the output terminal of the ANPC three-level topology circuit to generate a wave. By simultaneously turning on the switching transistors T2, T3, T5, and T6, a stable bidirectional dual-loop freewheeling current is formed. There is no need to adjust the switching transistor operation logic according to the current direction, which achieves the effect of fixing the switching transistor operation logic.
[0087] like Figure 3 As shown, when the power factor is 1 and the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the negative half-cycle, the switching transistor T3 is normally on.
[0088] When the zero-level freewheeling ends, switch T2 is turned off first, and after a preset delay t3, switches T5 and T6 are turned off. During this period, the current path changes from four current paths to one current path.
[0089] The four current paths before the switch were as follows:
[0090] 1. Input DC side to diode D5 to switch T2 to output AC side.
[0091] 2. The input DC side leads to the switching transistor T6, then to the diode D3, and finally to the output AC side.
[0092] 3. Output AC side to diode D2 to switch T5 to input DC side.
[0093] 4. The DC side of the input terminal connects to the switching transistor T3, the diode D6, and the DC side of the input terminal.
[0094] The current path after switching is from the AC side of the output terminal to the switching transistor T3, then to the diode D6, and finally to the DC side of the input terminal.
[0095] When the non-zero level state begins, switch T4 is turned on first, and after a preset delay t1, switch T5 is turned on. During this period, the current path changes from the original path from the AC side of the output terminal to switch T3 to diode D6 to the DC side of the input terminal to the AC side of the output terminal to switch T3 to switch T4 to the DC side of the input terminal.
[0096] In the two steps above, the zero-level current freewheeling path is switched from two current paths to one current path, and only one current freewheeling path is retained when the switching transistor T4 is turned on.
[0097] This operation reduces the reverse recovery loss of diodes D6 and D2, which would normally require reverse recovery in the two freewheeling circuits. Therefore, during the transition between non-zero and zero-level states, the additional branch needs to be shut down to further reduce the reverse recovery loss of the diodes in the dual freewheeling circuits.
[0098] When the non-zero level state ends, switch T5 remains on and switches T4 are off. During this period, the current path changes from the original AC output side to switch T3 to switch T4 to DC input side to two current paths.
[0099] The switched current path specifically includes:
[0100] 1. Output AC side to diode D2 to switch T5 to input DC side.
[0101] 2. The AC side of the output terminal connects to the switching transistor T3, the diode D6, and the AC side of the output terminal.
[0102] In this step, after switch T4 is turned off, since switch T5 remains on, a dual freewheeling circuit can be formed immediately. This allows for early entry into the dual freewheeling circuit, which extends the freewheeling time and further balances and reduces energy loss.
[0103] When the zero-level freewheeling starts, switch T5 remains on and does not operate. Switch T6 is turned on first, and after a preset delay t2, switch T2 is turned on.
[0104] During this period, the current path changes from two current paths to four current paths, forming a bidirectional dual-loop freewheeling current.
[0105] The path before the switch specifically includes:
[0106] 1. Output AC side to diode D2 to switch T5 to input DC side.
[0107] 2. The input DC side leads to the switch T3, which leads to the diode D6, which leads to the output AC side.
[0108] The switched paths specifically include:
[0109] 1. Input DC side to diode D5 to switch T2 to output AC side.
[0110] 2. The input DC side leads to the switching transistor T6, then to the diode D3, and finally to the output AC side.
[0111] 3. Output AC side to diode D2 to switch T5 to input DC side.
[0112] 4. The AC side of the output terminal connects to the switching transistor T3, the diode D6, and the DC side of the input terminal.
[0113] Controlling the switching transistor using the above modulation method can achieve bidirectional dual-loop freewheeling under all operating conditions, thus extending the freewheeling time of the dual loop.
[0114] like Figure 4 and Figure 5 As shown, Figure 4 The diagram shows the state changes of the ANPC three-level topology circuit under inverter or power factor 1 operating conditions. Figure 5 This diagram shows the state changes of the ANPC three-level topology circuit under rectification or power factor less than 1 conditions. (The diagram is presented in the original text.) Figure 4 and Figure 5 It can display the state changes of the outer transistor, inner transistor, and clamping transistor in the ANPC three-level topology circuit under different operating conditions.
[0115] Both figures cover the start time of the non-zero level state, the end time of the non-zero level state, the start time of the zero-level freewheeling, the end time of the zero-level freewheeling, and all dead time stages. The switching combination of the switching transistors does not change with the operating conditions.
[0116] Example 3
[0117] Based on Example 1, an alternative modulation method is provided, which differs from Example 2.
[0118] When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the positive half-cycle, the switching transistor T2 is normally on.
[0119] like Figure 6 As shown in the circle, when the zero-level freewheeling ends, switch T3 is turned off first, and after a preset time t4, switches T5 and T6 are turned off.
[0120] During this period, the current path changed from four current paths to one current path.
[0121] The current path before switching specifically includes:
[0122] 1. Input DC side to diode D5 to switch T2 to output AC side.
[0123] 2. The input DC side leads to the switching transistor T6, then to the diode D3, and finally to the output AC side.
[0124] 3. Output AC side to diode D2 to switch T5 to input DC side.
[0125] 4. The AC side of the output terminal connects to the switching transistor T3, the diode D6, and the DC side of the input terminal.
[0126] The current path after switching is: DC side of input terminal to diode D5 to switch T2 to AC side of output terminal.
[0127] When the positive level state begins, switch T1 is turned on first, and after a preset delay t1, switch T6 is turned on. During this period, the current path changes from the original DC side of the input terminal to diode D5 to switch T2 to AC side of the output terminal to DC side of the input terminal to switch T1 to switch T2 to AC side of the output terminal.
[0128] In the two steps described above, the zero-level freewheeling path is switched from two paths to one, and only one freewheeling path is retained when switch T1 is turned on. This operation means that of the two diodes that would normally perform reverse recovery in the two freewheeling loops, namely diode D5 and diode D3, only diode D5 needs to perform reverse recovery, thereby reducing diode reverse recovery losses. Therefore, when switching between non-zero and zero-level states, it is necessary to shut down the additional branch in a timely manner to reduce the reverse recovery losses of the diodes in the dual freewheeling loop.
[0129] When the positive level state ends, switch T6 is turned off first, and after a preset time t2, switch T1 is turned off. During this period, the current path changes from the original DC input side to switch T1 to switch T2 to AC output side to the DC input side to diode D5 to switch T2 to AC output side.
[0130] When the zero-level freewheeling starts, switch transistors T5 and T6 are turned on first. After a preset time t3, switch transistor T3 is turned on to form a bidirectional dual-loop freewheeling.
[0131] During this period, the current path changes from one current path to four current paths, forming a bidirectional dual-loop freewheeling current.
[0132] The current path before switching is: DC side of input terminal to diode D5 to switch T2 to AC side of output terminal.
[0133] The switched current path specifically includes:
[0134] 1. Input DC side to diode D5 to switch T2 to output AC side.
[0135] 2. The input DC side leads to the switching transistor T6, then to the diode D3, and finally to the output AC side.
[0136] 3. Output AC side to diode D2 to switch T5 to input DC side.
[0137] 4. The AC side of the output terminal connects to the switching transistor T3, the diode D6, and the DC side of the input terminal.
[0138] like Figure 7 As shown, when the power factor is 1 and the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the negative half-cycle, the switching transistor T3 is normally on.
[0139] When the zero-level freewheeling ends, switch T2 is turned off first, and after a preset time t4, switches T5 and T6 are turned off.
[0140] During this period, the current path changed from four current paths to one current path.
[0141] The current path before switching specifically includes:
[0142] 1. Input DC side to diode D5 to switch T2 to output AC side.
[0143] 2. The input DC side leads to the switching transistor T6, then to the diode D3, and finally to the output AC side.
[0144] 3. Output AC side to diode D2 to switch T5 to input DC side.
[0145] 4. The AC side of the output terminal connects to the switching transistor T3, the diode D6, and the DC side of the input terminal.
[0146] The current path after switching is: AC side of output terminal to switch T3 to diode D6 to DC side of input terminal.
[0147] When the negative level state begins, switch T4 is turned on first, and after a preset delay t1, switch T5 is turned on. During this period, the current path changes from the original path from the AC side of the output terminal to switch T3 to diode D6 to the DC side of the input terminal to the AC side of the output terminal to switch T3 to switch T4 to the DC side of the input terminal.
[0148] In the two steps described above, the zero-level freewheeling path is switched from two paths to one, and only one freewheeling path is retained when switch T4 is turned on. This means that of the two diodes that would normally perform reverse recovery in the two freewheeling loops, namely diode D6 and diode D2, only diode D6 needs to perform reverse recovery, thus reducing diode reverse recovery losses. Therefore, when switching between non-zero and zero-level states, it is necessary to shut down the additional branch in a timely manner to reduce the reverse recovery losses of the diodes in the dual freewheeling loop.
[0149] When the negative level state ends, switch T5 is turned off first, and after a preset time t2, switch T4 is turned off. During this period, the current path changes from the original AC side of the output terminal to switch T3 to switch T4 to DC side of the input terminal to AC side of the output terminal to switch T3 to diode D6 to DC side of the input terminal.
[0150] When the zero-level freewheeling begins, switching transistors T5 and T6 are turned on first. After a preset delay of t3, switching transistor T2 is turned on to form a bidirectional dual-loop freewheeling. During this period, the current path changes from one current path to four current paths, forming a bidirectional dual-loop freewheeling.
[0151] The current path before switching is: AC side of the output terminal to switching transistor T3 to diode D6 to AC side of the output terminal.
[0152] The switched current path specifically includes:
[0153] 1. Input DC side to diode D5 to switch T2 to output AC side.
[0154] 2. The input DC side leads to the switching transistor T6, then to the diode D3, and finally to the output AC side.
[0155] 3. Output AC side to diode D2 to switch T5 to input DC side.
[0156] 4. The AC side of the output terminal connects to the switching transistor T3, the diode D6, and the DC side of the input terminal.
[0157] like Figure 8 and Figure 9 As shown, the modulation method in this embodiment achieves bidirectional dual-loop freewheeling under all operating conditions by controlling the switching transistor.
[0158] According to Embodiments 2 and 3, it can be seen that the modulation method provided by this application has the effect of fixing the switching logic. It is only necessary to determine the positive and negative half-cycles of the AC side voltage at the output terminal of the ANPC three-level topology circuit to generate a wave and form a bidirectional dual-loop freewheeling current. There is no need to change the switching logic according to the positive and negative signs of the current.
[0159] In summary, this solution, through a fixed waveform transmission method, enables the ANPC three-level topology circuit to achieve bidirectional dual-loop freewheeling under all operating conditions, including rectification, inversion, and low power factor, thereby balancing and reducing energy loss in the circuit.
[0160] The existing technology for zero-level dual-loop freewheeling current has been optimized to address the issues of complex judgment and control under different operating conditions.
[0161] This application controls the clamping transistor of the ANPC three-level topology circuit. Based on the period of the AC side voltage at the output of the ANPC three-level topology circuit, the application switches the external branch in a timely manner at the start, end, and end times of the non-zero level state, as well as the start and end times of the zero-level freewheeling state. This reduces the reverse recovery loss of the diode in the dual-loop freewheeling. Furthermore, due to the conduction state of the corresponding clamping transistor in the ANPC three-level topology circuit, the dual-loop freewheeling state can be entered earlier after the external transistor is turned off, effectively extending the dual-loop freewheeling time and further balancing and reducing energy loss.
[0162] Example 4
[0163] Furthermore, the modulation signal generated by the ANPC three-level topology circuit during modulation is the original modulation signal. The generated original modulation signal is then subjected to delay filtering, and the processed signal is used as the final modulation signal and sent to the corresponding switching transistor.
[0164] The original modulation signal and the final modulation signal have only low-level signals and high-level signals. The high-level signal is the turn-on signal of the switching transistor, and the low-level signal is the turn-off signal of the switching transistor. After the signal is flipped, it remains unchanged and waits for the next flip.
[0165] like Figure 10 As shown, when the original modulation signal flips from low level to high level, the delay filtering process begins, and the delay time is a preset time t4. After the delay ends, if the original modulation signal is still at a high level, the final modulation signal flips from low level to high level. After the delay ends, if the original modulation signal flips to a low level, the final modulation signal remains at a low level.
[0166] When the original modulation signal flips from high level to low level, the delay filtering process begins, and the delay time is a preset time t4; after the delay ends, the final modulation signal flips to low level.
[0167] Existing modulation methods introduce significant dead time when switching between single and dual freewheeling in zero-level freewheeling mode due to the dual-loop freewheeling. For this reason, the clamping transistor's pulse width must be greater than the sum of its internal pulse width and the dead time. Furthermore, the limitation imposed on the internal transistor by the narrowest pulse width leads to a longer minimum pulse width for the clamping transistor, increasing the minimum time for zero-level freewheeling and resulting in a degraded power quality.
[0168] like Figure 7 As shown in the figure, this embodiment takes a modulated signal with voltage as the positive half-cycle as an example to demonstrate the effect of processing by delay filtering.
[0169] When the conduction time of the inner transistor in the ANPC three-level topology circuit is less than the set value t4, the conduction drive signal of that inner transistor will be filtered out by the delay filter. For example... Figure 11 As shown in the box, the narrowest pulse width of this clamping transistor can be further reduced, limited only by the narrowest pulse width of the device itself.
[0170] Furthermore, in this application, Embodiments 2, 3, and 4 all involve delay times t1, t2, t3, and t4. These delay times t1, t2, t3, and t4 are independent delay time groups in each embodiment and do not affect each other. The delay times t1, t2, t3, and t4 involved in each embodiment are preset times and can be adjusted to any value according to actual needs.
[0171] Preferably, in this embodiment, the delay filtering of the original modulation signal to generate the final modulation signal is performed using software.
[0172] The embodiments of the present invention have been described in detail above, but the content described is only a preferred embodiment of the present invention and should not be considered as limiting the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the patent coverage of the present invention.
Claims
1. A modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology, characterized in that: A single ANPC three-level topology circuit or multiple ANPC three-level topology circuits are connected in parallel. The ANPC three-level topology circuit is monitored to determine the period of the AC side voltage at the output terminal of the ANPC three-level topology circuit. Based on the period, the inner transistor, outer transistor, and clamping transistor in the ANPC three-level topology circuit are controlled at the start time node of the non-zero level state, the end time node of the non-zero level state, the start time node of the zero-level freewheeling current, and the end time node of the zero-level freewheeling current to complete the modulation of the circuit. The ANPC three-level topology circuit includes capacitors C1 and C2 connected in series on the DC input side of the circuit. The negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2. The collector of switching transistor T1 is connected to the positive terminal of capacitor C1. The emitter of switching transistor T1 is connected to the collector of switching transistor T2. The emitter of switching transistor T2 is connected to the collector of switching transistor T3. The emitter of switching transistor T3 is connected to the collector of switching transistor T4. The emitter of switching transistor T4 is connected to the capacitor C2. Negative terminal connection; Switches T5 and T6 are connected in series, with the emitter of T5 connected to the collector of T6, the midpoint of T5 and T6 connected to the midpoint of capacitors C1 and C2, the collector of T5 connected to the midpoint of T1 and T2, and the emitter of T6 connected to the midpoint of T3 and T4; the midpoint of T2 and T3 is connected to the AC output side. When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the positive half-cycle, the switching transistor T2 is normally on. When the non-zero level state begins, switch T1 is turned on first, and after a preset time t1, switch T6 is turned on. When the non-zero level state ends, switch T6 remains on and turns off switch T1. When the zero-level freewheeling starts, switch T6 remains on and does not operate. Switch T5 is turned on first, and after a preset time t2, switch T3 is turned on to form a bidirectional dual-loop freewheeling. When the zero-level freewheeling ends, switch T3 is turned off first, and after a preset time t3, switches T5 and T6 are turned off.
2. The modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology according to claim 1, characterized in that: When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the negative half-cycle, the switching transistor T3 is normally on. When the non-zero level state begins, switch T4 is turned on first, and after a preset time t1, switch T5 is turned on. When the non-zero level state ends, switch T5 remains on and turns off switch T4; When the zero-level freewheeling starts, switch T5 remains on and does not operate. Switch T6 is turned on first, and after a preset time t2, switch T2 is turned on to form a bidirectional dual-loop freewheeling. When the zero-level freewheeling ends, switch T2 is turned off first, and after a preset time t3, switches T5 and T6 are turned off.
3. A modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology, characterized in that: A single ANPC three-level topology circuit or multiple ANPC three-level topology circuits are connected in parallel. The ANPC three-level topology circuit is monitored to determine the period of the AC side voltage at the output terminal of the ANPC three-level topology circuit. Based on the period, the inner transistor, outer transistor, and clamping transistor in the ANPC three-level topology circuit are controlled at the start time node of the non-zero level state, the end time node of the non-zero level state, the start time node of the zero-level freewheeling current, and the end time node of the zero-level freewheeling current to complete the modulation of the circuit. The ANPC three-level topology circuit includes capacitors C1 and C2 connected in series on the DC input side of the circuit. The negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2. The collector of switching transistor T1 is connected to the positive terminal of capacitor C1. The emitter of switching transistor T1 is connected to the collector of switching transistor T2. The emitter of switching transistor T2 is connected to the collector of switching transistor T3. The emitter of switching transistor T3 is connected to the collector of switching transistor T4. The emitter of switching transistor T4 is connected to the capacitor C2. Negative terminal connection; Switches T5 and T6 are connected in series, with the emitter of T5 connected to the collector of T6, the midpoint of T5 and T6 connected to the midpoint of capacitors C1 and C2, the collector of T5 connected to the midpoint of T1 and T2, and the emitter of T6 connected to the midpoint of T3 and T4; the midpoint of T2 and T3 is connected to the AC output side. When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the positive half-cycle, the switching transistor T2 is normally on. When the positive level state begins, switch T1 is turned on first, and after a preset time t1, switch T6 is turned on. When the positive level state ends, switch T6 is turned off first, and after a preset time t2, switch T1 is turned off. When the zero-level freewheeling starts, switch transistors T5 and T6 are turned on first. After a preset time t3, switch transistor T3 is turned on to form a bidirectional dual-loop freewheeling. When the zero-level freewheeling ends, switch T3 is turned off first, and after a preset time t4, switches T5 and T6 are turned off.
4. The modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology according to claim 3, characterized in that: When the AC side voltage at the output terminal of the ANPC three-level topology circuit is in the negative half-cycle, the switching transistor T3 is normally on. When the negative level state begins, switch T4 is turned on first, and switch T5 is turned on after a preset time t1. When the negative level state ends, switch T5 is turned off first, and after a preset time t2, switch T4 is turned off. When the zero-level freewheeling starts, switch transistors T5 and T6 are turned on first. After a preset time t3, switch transistor T2 is turned on to form a bidirectional dual-loop freewheeling. When the zero-level freewheeling ends, switch T2 is turned off first, and after a preset time t4, switches T5 and T6 are turned off.
5. The modulation method for increasing the dual freewheeling time and improving power quality of an ANPC topology according to any one of claims 1-4, characterized in that: Switching transistors T2 and T3 are inner transistors; switching transistors T1 and T4 are outer transistors; switching transistors T5 and T6 are clamping transistors; switching transistors T1, T2, and T5 are located in the upper bridge arm; switching transistors T3, T4, and T6 are located in the lower bridge arm.
6. A modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology according to any one of claims 1-4, characterized in that: The modulation signal generated by the ANPC three-level topology circuit during modulation is the original modulation signal. The generated original modulation signal is then subjected to delay filtering, and the processed signal is used as the final modulation signal and sent to the corresponding switching transistor.
7. The modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology according to claim 6, characterized in that: The original modulation signal and the final modulation signal are a low-level signal and a high-level signal, respectively. The high-level signal is the turn-on signal of the switching transistor, and the low-level signal is the turn-off signal of the switching transistor. After the signal is flipped, it remains unchanged and waits for the next flip.
8. The modulation method for increasing the dual freewheeling time and improving power quality in an ANPC topology according to claim 7, characterized in that: When the original modulation signal flips from low to high, the delay filtering process begins with a delay of a preset time t4. After the delay ends, if the original modulation signal remains high, the final modulation signal flips from low to high. If the original modulation signal flips to low after the delay ends, the final modulation signal remains low. When the original modulation signal flips from high to low, the delay filtering process begins with a delay of a preset time t4. After the delay ends, the final modulation signal flips to low.