Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. A first dielectric layer on the substrate; the dielectric buffer layer is located on the first dielectric layer, and the anti-breakdown strength of the dielectric buffer layer is larger than that of the first dielectric layer; the multiple electrode layers are sequentially stacked on the dielectric buffer layer from bottom to top; the dielectric layers are located between the adjacent electrode layers in the longitudinal direction; the second dielectric layer is located on the substrate and covers the multi-layer electrode layer. The anti-breakdown strength of the dielectric buffer layer is greater than the anti-breakdown strength of the first dielectric layer, so that the anti-breakdown voltage of a capacitor (MiM) formed by the multi-layer electrode layer and the dielectric layer is increased, the anti-breakdown capability of the capacitor is improved, the capacitor can be suitable for a high-voltage working environment, and the device performance of the semiconductor structure is further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in materials and design have led to generation after generation of integrated circuits. Each generation features smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of fabricating and manufacturing integrated circuits, requiring similar developments in IC fabrication and manufacturing to achieve these advancements. Throughout the development of integrated circuits, functional density (the number of interconnect devices per chip area) has gradually increased, while geometric dimensions (the smallest components that can be manufactured using specific processes) have gradually decreased.

[0003] One type of capacitor is the metal-insulator-metal (MIM) capacitor, which is commonly used in mixed-signal and logic devices (such as embedded memories and radio frequency devices). MIM capacitors are typically used to store charge in various semiconductor devices. To meet the performance requirements of these devices, the capacitance density of MIM capacitors is also gradually increasing.

[0004] However, the breakdown strength of MIM capacitors still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the device performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a first dielectric layer located on the substrate; a dielectric buffer layer located on the first dielectric layer, wherein the breakdown strength of the dielectric buffer layer is greater than that of the first dielectric layer; multiple electrode layers stacked sequentially from bottom to top on the dielectric buffer layer; a dielectric layer located longitudinally between adjacent electrode layers; and a second dielectric layer located on the substrate and covering the multiple electrode layers.

[0007] Optionally, the material of the dielectric buffer layer includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0008] Optionally, the thickness of the dielectric buffer layer is 20 nanometers to 60 nanometers in the normal direction of the substrate surface.

[0009] Optionally, the semiconductor structure further comprises an interconnection structure on the substrate and sequentially penetrating through the second dielectric layer, the plurality of electrode layers, the dielectric buffer layer and the first dielectric layer, and the interconnection structure is electrically connected with the electrode layers.

[0010] Optionally, the semiconductor structure further comprises a bottom metal layer in the substrate, and the substrate exposes a top surface of the bottom metal layer; and the interconnection structure is further electrically connected with the top surface of the bottom metal layer exposed by the substrate.

[0011] Optionally, the semiconductor structure further comprises a top metal layer on the top of the interconnection structure, and the top metal layer is electrically connected with the top of the interconnection structure.

[0012] Optionally, the semiconductor structure further comprises a first etching stop layer between the substrate and the first dielectric layer; and the interconnection structure further penetrates through the first etching stop layer.

[0013] Optionally, the material of the dielectric layer comprises one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; and the material of the electrode layer comprises one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0014] Correspondingly, the embodiment of the present application further provides a forming method of a semiconductor structure, comprising: providing a substrate, and forming a first dielectric layer on the substrate; forming a dielectric buffer layer on the first dielectric layer, and the dielectric buffer layer has a higher breakdown strength than the first dielectric layer; forming a plurality of electrode layers stacked from bottom to top on the dielectric buffer layer, and forming a dielectric layer between adjacent electrode layers in the longitudinal direction; and forming a second dielectric layer on the substrate to cover the plurality of electrode layers.

[0015] Optionally, the process of forming the dielectric buffer layer on the first dielectric layer comprises an atomic layer deposition process or a chemical vapor deposition process.

[0016] Optionally, the material of the dielectric buffer layer comprises one or more of silicon nitride, silicon oxynitride and silicon carbon nitride.

[0017] Optionally, in the normal direction of the surface of the substrate, the thickness of the dielectric buffer layer is 20-60 nanometers.

[0018] Optionally, after the second dielectric layer covering the multilayer electrode layers is formed on the substrate, the forming method further comprises: forming an interconnection structure on the substrate, the interconnection structure penetrating through the second dielectric layer, the multilayer electrode layers, the dielectric buffer layer and the first dielectric layer in sequence, and the interconnection structure being electrically connected with the electrode layers.

[0019] Optionally, in the step of providing the substrate, a bottom metal layer is formed in the substrate, and the substrate exposes a top surface of the bottom metal layer; in the step of forming the interconnection structure, the interconnection structure is further electrically connected with the top surface of the bottom metal layer exposed by the substrate.

[0020] Optionally, after the interconnection structure is formed, the forming method further comprises: forming a top metal layer on the top of the interconnection structure, the top metal layer being electrically connected with the top of the interconnection structure.

[0021] Optionally, the step of forming the top metal layer comprises: forming a conductive material layer on the top of the interconnection structure and the second dielectric layer; and performing a patterning process on the conductive material layer, so as to reserve the conductive material layer on the top of the interconnection structure, and take the conductive material layer on the top of the interconnection structure as the top metal layer.

[0022] Optionally, in the step of providing the substrate, a first etching stop layer is further formed between the substrate and the first dielectric layer; in the step of forming the interconnection structure, the interconnection structure further penetrates through the first etching stop layer.

[0023] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0024] In the semiconductor structure provided by the embodiment of the present application, the first dielectric layer is on the substrate, the dielectric buffer layer is on the first dielectric layer, and the multilayer electrode layers are stacked on the dielectric buffer layer from bottom to top in sequence. Compared with the prior art in which the multilayer electrode layers are stacked on the first dielectric layer from bottom to top in sequence, the dielectric buffer layer can alleviate the stress in the capacitor (MiM) composed of the multilayer electrode layers and the dielectric layer, so that the anti-breakdown capability of the capacitor is improved, the breakdown voltage of the capacitor (MiM) composed of the multilayer electrode layers and the dielectric layer is increased, the anti-breakdown capability of the capacitor is enhanced, and the capacitor can be applied to a high-voltage working environment, thereby improving the device performance of the semiconductor structure.

[0025] The forming method of the semiconductor structure provided by the embodiment of the present application comprises the following steps: providing a substrate, forming a first dielectric layer on the substrate, forming a dielectric buffer layer on the first dielectric layer, and forming a plurality of electrode layers stacked in sequence from bottom to top on the dielectric buffer layer and a dielectric layer between adjacent electrode layers in the vertical direction. Compared with the prior art in which a plurality of electrode layers are stacked in sequence from bottom to top on a first dielectric layer, the plurality of electrode layers are stacked in sequence from bottom to top on the dielectric buffer layer in the embodiment of the present application. The dielectric buffer layer can slow down the stress in the capacitor (MiM) formed by the plurality of electrode layers and the dielectric layer, so that the anti-breakdown capability of the capacitor is improved, the breakdown voltage of the capacitor (MiM) formed by the plurality of electrode layers and the dielectric layer is increased, the anti-breakdown capability of the capacitor is enhanced, and the capacitor can be applied to a high-voltage working environment, thereby improving the device performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 FIG. 1 is a structural schematic diagram of a semiconductor structure.

[0027] Figure 2 FIG. 2 is a structural schematic diagram of an embodiment of the semiconductor structure of the present application.

[0028] Figures 3 to 9 FIG. 3 is a structural schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0029] At present, the anti-breakdown strength of the MIM capacitor still needs to be improved. The reasons why the anti-breakdown strength of the MIM capacitor still needs to be improved are analyzed in combination with a semiconductor structure.

[0030] Figure 1 FIG. 1 is a structural schematic diagram of a semiconductor structure.

[0031] The semiconductor structure comprises: a substrate 20; a first dielectric layer 22 located on the substrate 20; a plurality of electrode layers 21 stacked in sequence from bottom to top on the first dielectric layer 22; a dielectric layer 23 located between adjacent electrode layers 21 in the vertical direction; and a second dielectric layer 26 located on the substrate 20 and covering the plurality of electrode layers 21.

[0032] It is found through research that the commonly used material of the first dielectric layer 22 is oxide at present. The oxide can easily increase the stress in the capacitor (MiM) formed by the plurality of electrode layers 21 and the dielectric layer 23, so that the anti-breakdown capability of the capacitor is affected, the breakdown voltage of the capacitor is too small, the probability that the MIM capacitor formed by the plurality of electrode layers 21 and the dielectric layer 23 is voltage breakdown in a high-voltage working environment is increased, the probability that the MIM capacitor is invalid is greatly increased, and the device performance of the semiconductor structure is affected.

[0033] To solve the technical problem, the embodiment of the present application provides a semiconductor structure, comprising: a substrate; a first dielectric layer located on the substrate; a dielectric buffer layer located on the first dielectric layer, the dielectric buffer layer having a higher breakdown strength than the first dielectric layer; a multilayer electrode layer stacked on the dielectric buffer layer from bottom to top; a dielectric layer located between adjacent electrode layers in the longitudinal direction; and a second dielectric layer located on the substrate and covering the multilayer electrode layer.

[0034] In the embodiment of the present application, the first dielectric layer is located on the substrate, the dielectric buffer layer is located on the first dielectric layer, and the multilayer electrode layer is stacked on the dielectric buffer layer from bottom to top. Compared with the prior art in which the multilayer electrode layer is stacked on the first dielectric layer from bottom to top, the dielectric buffer layer in the embodiment of the present application can alleviate the stress in the capacitor (MiM) composed of the multilayer electrode layer and the dielectric layer, thereby improving the breakdown resistance of the capacitor and increasing the breakdown voltage of the capacitor (MiM) composed of the multilayer electrode layer and the dielectric layer. The breakdown resistance of the capacitor is enhanced, and the capacitor can be applied to a high-voltage working environment, thereby improving the device performance of the semiconductor structure.

[0035] To make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings. Figure 2 FIG. 1 shows a structure schematic diagram of an embodiment of the semiconductor structure of the present application.

[0036] Reference Figure 2 The semiconductor structure comprises: a substrate 200; a first dielectric layer 202 located on the substrate 200; a dielectric buffer layer 206 located on the first dielectric layer 202; a multilayer electrode layer 210 stacked on the dielectric buffer layer 206 from bottom to top; a dielectric layer 212 located between adjacent electrode layers 210 in the longitudinal direction; and a second dielectric layer 216 located on the substrate 200 and covering the multilayer electrode layer 210.

[0037] It should be noted that the first dielectric layer 202 is located on the substrate 200, the dielectric buffer layer 206 is located on the first dielectric layer 202, and the dielectric buffer layer 206 can alleviate the stress in the capacitor (MiM) composed of the multilayer electrode layer 210 and the dielectric layer 212, thereby improving the breakdown resistance of the capacitor and increasing the breakdown voltage of the capacitor (MiM) composed of the multilayer electrode layer 210 and the dielectric layer 212. The breakdown resistance of the capacitor is enhanced, and the capacitor can be applied to a high-voltage working environment, thereby improving the device performance of the semiconductor structure.

[0038] Specifically, the substrate 200 is used to provide a process platform for setting the MIM capacitor.

[0039] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0040] It should be noted that the first dielectric layer 202 is used to provide a process operation platform for setting the dielectric buffer layer 206, and the first dielectric layer 202 also plays an electrical isolation role for the interconnection structure 240.

[0041] In this embodiment, the material of the first dielectric layer 202 includes silicon oxide.

[0042] In this embodiment, the semiconductor structure further includes a bottom metal layer 203 located in the substrate 200, and the substrate 200 exposes the top surface of the bottom metal layer 203.

[0043] Specifically, the bottom metal layer 203 is used to realize a normal circuit structure, so that the bottom metal layer 203 can be electrically connected with the interconnection structure 240.

[0044] In this embodiment, the material of the bottom metal layer 203 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.

[0045] In this embodiment, the semiconductor structure further includes a first etching stop layer 201 located between the substrate 200 and the first dielectric layer 202.

[0046] Specifically, in the forming process of the interconnection structure 240, the first etching stop layer 201 is used as an etching stop position for forming the interconnection structure 240, so as to reduce the probability of damage to the bottom metal layer 203, and also facilitate to improve the consistency of the height of the interconnection structure 240 in the semiconductor structure.

[0047] As an example, the material of the first etching stop layer 201 is silicon nitride. In other embodiments, the first etching stop layer can also be other materials with high etching selectivity with the substrate material, such as one or more of silicon nitride, aluminum oxide, aluminum nitride, and NDC (nitride doped carbon).

[0048] It should be noted that, compared with the scheme that the multilayer electrode layer 210 is sequentially stacked on the first dielectric layer 202 from bottom to top, the multilayer electrode layer 210 in the embodiment is sequentially stacked on the medium buffer layer 206 from bottom to top, and the medium buffer layer 206 can slow down the stress in the capacitor (MiM) composed of the multilayer electrode layer 210 and the medium layer 212, so that the breakdown voltage of the capacitor is increased, the capacitor can be applied to a high-voltage working environment, and the device performance of the semiconductor structure is improved.

[0049] In the embodiment, the material of the medium buffer layer 206 includes one or more of silicon nitride, silicon oxynitride and silicon nitrocarbon.

[0050] Specifically, the silicon nitride, the silicon oxynitride and the silicon nitrocarbon are all nitride materials, and the stress generated by the nitride material is smaller than the stress generated by the silicon oxide material selected for the first dielectric layer 202. After the multilayer electrode layer 210 is formed on the medium buffer layer 206 from bottom to top, and the medium layer 212 is formed between the electrode layers 210 adjacent in the longitudinal direction, the breakdown voltage of the capacitor (MiM) composed of the multilayer electrode layer 210 and the medium layer 212 is increased, thereby increasing the breakdown voltage of the capacitor. At the same time, the silicon nitride, the silicon oxynitride and the silicon nitrocarbon are all dielectric materials, which can reduce the risk of leakage current between the capacitor composed of the multilayer electrode layer 210 and the medium layer 212 and the bottom metal layer 203, and play a good electrical isolation effect on the capacitor.

[0051] It should be noted that, in the normal direction of the surface of the substrate 200, the thickness of the medium buffer layer 206 should not be too large or too small. If the thickness of the medium buffer layer 206 is too large, the etching difficulty of forming the interconnection structure 240 is increased in the process of forming the interconnection structure 240, which affects the process efficiency of forming the interconnection structure 240. If the thickness of the medium buffer layer 206 is too small, the breakdown voltage of the capacitor cannot be increased, the breakdown voltage of the capacitor cannot be increased, and the device performance of the semiconductor structure is affected. Therefore, in the embodiment, in the normal direction of the surface of the substrate 200, the thickness of the medium buffer layer 206 is 20 nanometers to 60 nanometers.

[0052] It should also be noted that, compared with the scheme that the multilayer electrode layer 210 is sequentially stacked on the first dielectric layer 202 from bottom to top, the multilayer electrode layer 210 is formed on the medium buffer layer 206 after the medium buffer layer 206 is formed on the first dielectric layer 202, which has high process compatibility with the existing process.

[0053] It should be noted that the multi-layer electrode layer 210 and the dielectric layer 212 located between adjacent electrode layers 210 form a MIM capacitor.

[0054] Specifically, the electrode layer 210 is used as an electrode plate of the MIM capacitor.

[0055] In this embodiment, the material of the electrode layer 210 is a conductive material. As an example, the material of the electrode layer 210 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0056] The dielectric layer 212 is used as a dielectric buffer layer 206 in the MIM capacitor, and is used to isolate adjacent electrode layers 210 in the longitudinal direction.

[0057] Specifically, each dielectric layer 212 conformally covers the underlying electrode layer 210.

[0058] In this embodiment, the material of the dielectric layer 212 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. By selecting a high-k dielectric material, the capacitance value of the MIM capacitor can be improved, and the capacitance density can be improved accordingly.

[0059] Specifically, in this embodiment, the material of the dielectric layer 212 includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0060] In this embodiment, the semiconductor structure further includes an interconnection structure 240 located on the substrate 200 and sequentially penetrating the second dielectric layer 216, the multi-layer electrode layer 210, the dielectric buffer layer 206 and the first dielectric layer 202, and the interconnection structure 240 is electrically connected with the electrode layer 210.

[0061] Specifically, the interconnection structure 240 is used to be electrically connected with the electrode layer 210, so as to realize the electrical connection between the electrode layer 210 and an external circuit structure through the interconnection structure 240.

[0062] In this embodiment, the material of the interconnection structure 240 includes one or more of aluminum, copper, titanium nitride, cobalt and tantalum nitride.

[0063] In this embodiment, the interconnection structure 240 is also electrically connected with the top surface of the bottom metal layer 203 exposed by the substrate 200.

[0064] In this embodiment, the interconnection structure 240 also penetrates the first etching stop layer 201.

[0065] In this embodiment, the semiconductor structure further comprises: a top metal layer 250, located on top of the interconnection structure 240, and the top metal layer 250 is electrically connected with the top of the interconnection structure 240.

[0066] Specifically, the top metal layer 250 is used to realize electrical connection with other circuit structures, so as to realize the normal function of the semiconductor structure.

[0067] In this embodiment, the material of the top metal layer 250 includes one or more of aluminum, copper, titanium nitride, cobalt and tantalum nitride.

[0068] Correspondingly, the application also provides a forming method of a semiconductor structure. Figures 3 to 9 is the structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the application.

[0069] The forming method of the semiconductor structure of the embodiment will be described in detail below with reference to the accompanying drawings.

[0070] Reference Figure 3 , a substrate 100 is provided, and a first dielectric layer 102 is formed on the substrate 100.

[0071] Specifically, the substrate 100 is used to provide a process platform for forming an MIM capacitor.

[0072] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, and other types of substrates.

[0073] It should be noted that the first dielectric layer 102 is used to provide a process operation platform for the subsequent formation of a dielectric buffer layer, and at the same time, the first dielectric layer 102 also plays an electrical isolation role for the subsequent formation of the interconnection structure.

[0074] In this embodiment, the material of the first dielectric layer 102 includes silicon oxide.

[0075] In this embodiment, a bottom metal layer 103 is formed in the substrate 100, and the substrate 100 exposes the top surface of the bottom metal layer 103.

[0076] Specifically, the bottom metal layer 103 is used to realize a normal circuit structure, so that the bottom metal layer 103 can be electrically connected with the interconnection structure.

[0077] In this embodiment, the material of the bottom metal layer 103 includes one or more of aluminum, copper, titanium nitride, cobalt and tantalum nitride.

[0078] In this embodiment, the first etching stop layer 101 is further formed between the substrate 100 and the first dielectric layer 102.

[0079] Specifically, the first etching stop layer 101 is used as an etching stop position for forming a subsequent interconnection structure, so as to reduce the probability of causing damage to the underlying metal layer 103, and also facilitate improving the consistency of the height of the interconnection structure in the semiconductor structure.

[0080] As an example, the material of the first etching stop layer 101 is silicon nitride. In other embodiments, the first etching stop layer can also be other materials having higher etching selectivity with the substrate material, such as one or more of silicon nitride, aluminum oxide, aluminum nitride, and NDC (nitride doped carbon).

[0081] Reference Figure 4 A dielectric buffer layer 106 is formed on the first dielectric layer 102, and the dielectric buffer layer 106 has a higher breakdown strength than the first dielectric layer 102.

[0082] It should be noted that, after the dielectric buffer layer 106 is formed on the first dielectric layer 102, and then a plurality of electrode layers are formed on the dielectric buffer layer 106 in a bottom-up stacking manner, and a dielectric layer is formed between adjacent electrode layers in the longitudinal direction, compared with a scheme in which the plurality of electrode layers are formed on the first dielectric layer 102 in a bottom-up stacking manner, the dielectric buffer layer 106 can alleviate the stress in the capacitor (MiM) formed by the plurality of electrode layers and the dielectric layer, so that the breakdown resistance of the capacitor is improved, and the breakdown voltage of the capacitor (MiM) formed by the plurality of electrode layers and the dielectric layer is increased, thereby increasing the breakdown resistance of the capacitor, so that the capacitor can be applied to a high-voltage working environment, and thus the device performance of the semiconductor structure is improved.

[0083] In this embodiment, the process of forming the dielectric buffer layer 106 on the first dielectric layer 102 includes an atomic layer deposition process or a chemical vapor deposition process.

[0084] Specifically, the atomic layer deposition process and the chemical vapor deposition process are common deposition processes for forming the dielectric buffer layer 106.

[0085] Taking the atomic layer deposition process as an example, the atomic layer deposition process has good film deposition performance, which can improve the formation quality of the dielectric buffer layer 106 and reduce the risk of voids in the dielectric buffer layer 106.

[0086] In this embodiment, the material of the dielectric buffer layer 106 includes one or more of silicon nitride, silicon oxynitride, and silicon carbon nitride.

[0087] Specifically, the silicon nitride, the silicon oxynitride and the silicon carbon nitride are all nitride materials, and the stress generated by the nitride materials is smaller than the stress generated by the silicon oxide material selected by the first dielectric layer 102. After the multi-layer electrode layer and the dielectric layer are formed on the dielectric buffer layer 106, the breakdown voltage of the capacitor (MiM) formed by the multi-layer electrode layer and the dielectric layer is increased, thereby increasing the anti-breakdown capability of the capacitor. Meanwhile, the silicon nitride, the silicon oxynitride and the silicon carbon nitride are all dielectric materials, which can reduce the risk of generating a leakage current between the capacitor formed by the multi-layer electrode layer and the dielectric layer and the bottom metal layer 103, and play a good electrical isolation effect on the capacitor.

[0088] It should be noted that the thickness of the dielectric buffer layer 106 should not be too large or too small in the normal direction of the surface of the substrate 100. If the thickness of the dielectric buffer layer 106 is too large, the etching difficulty of forming the interconnection structure is increased in the process of forming the interconnection structure, which affects the process efficiency of forming the interconnection structure. If the thickness of the dielectric buffer layer 106 is too small, the breakdown voltage of the capacitor cannot be increased, the anti-breakdown capability of the capacitor cannot be enhanced, and the device performance of the semiconductor structure is affected. Therefore, in the embodiment, the thickness of the dielectric buffer layer 106 is 20 nanometers to 60 nanometers in the normal direction of the surface of the substrate 100.

[0089] It should be further noted that, compared with the scheme that the multi-layer electrode layer is sequentially stacked on the first dielectric layer 102 from bottom to top, the multi-layer electrode layer is formed on the dielectric buffer layer 106 in the embodiment, which has high process compatibility with the existing process.

[0090] Reference Figure 5 The multi-layer electrode layer 110 is formed on the dielectric buffer layer 106, and the dielectric layer 112 is formed between the adjacent electrode layers 110 in the longitudinal direction.

[0091] It should be noted that the multi-layer electrode layer 110 and the dielectric layer 112 between the adjacent electrode layers 110 form a MIM capacitor.

[0092] Specifically, the electrode layer 110 is used as an electrode plate of the MIM capacitor.

[0093] In the embodiment, the material of the electrode layer 110 is a conductive material in the step of forming the electrode layer 110. As an example, the material of the electrode layer 110 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0094] The medium layer 112 is used as the medium buffer layer 106 in forming the MIM capacitor, and is used to isolate the electrode layers 110 adjacent in the longitudinal direction.

[0095] Specifically, each medium layer 112 conformally covers the electrode layer 110 thereunder.

[0096] In the embodiment, the material of the medium layer 112 is a high-k medium material; wherein the high-k medium material refers to a medium material with a relative dielectric constant greater than that of silicon oxide. By selecting the high-k medium material, the capacitance value of the MIM capacitor can be improved, and the capacitance density is correspondingly improved.

[0097] Specifically, in the embodiment, the material of the medium layer 112 includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0098] Reference Figure 6 The second dielectric layer 116 covering the plurality of electrode layers 110 is formed on the substrate 100.

[0099] Specifically, the second dielectric layer 116 is used to protect the plurality of electrode layers 110, and at the same time, the second dielectric layer 116 also plays an electrical isolation role for the subsequently formed interconnection structure.

[0100] In the embodiment, the material of the second dielectric layer 116 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0101] Reference Figures 7 to 8 After the second dielectric layer 116 covering the plurality of electrode layers 110 is formed on the substrate 100, the forming method further includes: forming an interconnection structure 140 on the substrate 100, the interconnection structure 140 penetrating through the second dielectric layer 116, the plurality of electrode layers 110, the medium buffer layer 106 and the first dielectric layer 102 in sequence, and the interconnection structure 140 is electrically connected with the electrode layers 110.

[0102] Specifically, the interconnection structure 140 is used to be electrically connected with the electrode layers 110, so as to realize the electrical connection between the electrode layers 110 and the external circuit structure through the interconnection structure 140.

[0103] In the embodiment, the material of the interconnection structure 140 includes one or more of aluminum, copper, titanium nitride, cobalt and tantalum nitride.

[0104] In this embodiment, the step of forming the interconnection structure 140 includes: forming an interconnection opening 130 through the second dielectric layer 116, the multi-layer electrode layer 110, the dielectric buffer layer 106 and the first dielectric layer 102 on the substrate 100; filling the interconnection opening 130 with a conductive material, and taking the conductive material in the interconnection opening 130 as the interconnection structure 140.

[0105] It should be noted that in the process of forming the interconnection opening 130, the interconnection opening 130 also penetrates the first etching stop layer 101.

[0106] It should also be noted that in the process of forming the interconnection opening 130, the interconnection opening 130 exposes the top surface of the bottom metal layer 103, and accordingly, the interconnection structure 140 penetrates the first etching stop layer 101.

[0107] In this embodiment, in the step of forming the interconnection structure 140, the interconnection structure 140 is also electrically connected to the top surface of the bottom metal layer 103 exposed by the substrate 100.

[0108] Reference Figure 9 After forming the interconnection structure 140, the forming method further includes: forming a top metal layer 150 on the top of the interconnection structure 140, and the top metal layer 150 is electrically connected to the top of the interconnection structure 140.

[0109] Specifically, the top metal layer 150 is used to electrically connect with other circuit structures, so as to realize the normal function of the semiconductor structure.

[0110] In this embodiment, the material of the top metal layer 150 includes one or more of aluminum, copper, titanium nitride, cobalt and tantalum nitride.

[0111] In this embodiment, the step of forming the top metal layer 150 includes: forming a conductive material layer on the top of the interconnection structure 140 and the second dielectric layer 116; and performing a patterning process on the conductive material layer, so as to retain the conductive material layer on the top of the interconnection structure 140, and take the conductive material layer on the top of the interconnection structure 140 as the top metal layer 150.

[0112] Specifically, the process of performing the patterning process on the conductive material layer includes a dry etching process.

[0113] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A first dielectric layer is located on the substrate; A dielectric buffer layer is located on the first dielectric layer; Multiple electrode layers are stacked sequentially on the dielectric buffer layer from bottom to top; A dielectric layer is located longitudinally between adjacent electrode layers; A second dielectric layer is located on the substrate and covers multiple electrode layers.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the dielectric buffer layer includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

3. The semiconductor structure as described in claim 1, characterized in that, The thickness of the dielectric buffer layer is 20 nanometers to 60 nanometers in the normal direction of the substrate surface.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an interconnect structure located on the substrate and sequentially penetrating the second dielectric layer, multiple electrode layers, a dielectric buffer layer, and the first dielectric layer, wherein the interconnect structure is electrically connected to the electrode layers.

5. The semiconductor structure as described in claim 4, characterized in that, The semiconductor structure further includes: a bottom metal layer located in the substrate, wherein the substrate exposes the top surface of the bottom metal layer; The interconnect structure is also electrically connected to the top surface of the exposed bottom metal layer of the substrate.

6. The semiconductor structure as described in claim 4, characterized in that, The semiconductor structure further includes a top metal layer located on top of the interconnect structure, and the top metal layer is electrically connected to the top of the interconnect structure.

7. The semiconductor structure as described in claim 4, characterized in that, The semiconductor structure further includes: a first etch stop layer located between the substrate and the first dielectric layer; The interconnect structure also extends through the first etch stop layer.

8. The semiconductor structure as described in claim 1, characterized in that, The material of the dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; The electrode layer is made of one or more of the following materials: W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a first dielectric layer is formed; A dielectric buffer layer is formed on the first dielectric layer; A multilayer electrode layer is formed on the dielectric buffer layer, which is stacked sequentially from bottom to top, and a dielectric layer is formed between adjacent electrode layers in the longitudinal direction; A second dielectric layer is formed on the substrate, covering multiple layers of the electrode layers.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process of forming a dielectric buffer layer on the first dielectric layer includes atomic layer deposition or chemical vapor deposition.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the dielectric buffer layer includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, The thickness of the dielectric buffer layer is 20 nanometers to 60 nanometers in the normal direction of the substrate surface.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming a second dielectric layer covering multiple electrode layers on the substrate, the forming method further includes: forming an interconnect structure on the substrate that sequentially penetrates the second dielectric layer, multiple electrode layers, a dielectric buffer layer, and a first dielectric layer, wherein the interconnect structure is electrically connected to the electrode layers.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, a bottom metal layer is formed in the substrate, and the top surface of the bottom metal layer is exposed in the substrate; In the step of forming the interconnect structure, the interconnect structure is also electrically connected to the top surface of the exposed bottom metal layer of the substrate.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the interconnect structure, the forming method further includes: forming a top metal layer on top of the interconnect structure, the top metal layer being electrically connected to the top of the interconnect structure.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The step of forming the top metal layer includes: forming a conductive material layer on top of the interconnect structure and the second dielectric layer; patterning the conductive material layer, retaining the conductive material layer located on top of the interconnect structure, and using the conductive material layer located on top of the interconnect structure as the top metal layer.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, a first etch stop layer is also formed between the substrate and the first dielectric layer; In the step of forming the interconnect structure, the interconnect structure also extends through the first etch stop layer.

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