Semiconductor package and package on package including same

Abstract

The present disclosure relates to a semiconductor package and a package on package including the same, the semiconductor package including: a redistribution structure; a semiconductor chip on the redistribution structure and electrically connected to the redistribution structure; an encapsulant encapsulating at least a portion of the semiconductor chip; one or more conductive pads on the encapsulation and electrically connected to the redistribution structure; and a passivation layer on the encapsulation, the passivation layer including an opening exposing a portion of the one or more conductive pads, where each of the one or more conductive pads includes: a first edge region covered by the passivation layer; and a second edge region exposed by the opening of the passivation layer and separated from the passivation layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0106757, filed on August 9, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor package and a package-on-package including the semiconductor package. Background Technology

[0004] In electronic products such as mobile devices, various types of semiconductor packages are used to integrate a variety of functions into a single device. Among these semiconductor packages, PoP (Positioning on Packaging) is a method of vertically stacking application processor (AP) packages and memory packages, and it has the advantage of improving performance while making efficient use of space. Recently, with the increasing demand for high-performance and high-capacity PoPs, semiconductor chips of various sizes and structures are being used in packages, and there is a requirement to reduce the gap between solder balls used for electrical connections between AP packages and memory packages. Summary of the Invention

[0005] One or more embodiments provide a semiconductor package that can prevent electrical short circuits between conductive bumps by controlling solder flow, and can provide a stacked package including the semiconductor package.

[0006] According to one aspect of this disclosure, a semiconductor package includes: a redistribution structure; a semiconductor chip on and electrically connected to the redistribution structure; an encapsulation encapsulating at least a portion of the semiconductor chip; one or more conductive pads on the encapsulation and electrically connected to the redistribution structure; and a passivation layer on the encapsulation, the passivation layer including an opening exposing a portion of the one or more conductive pads, wherein each of the one or more conductive pads includes: a first edge region covered by the passivation layer; and a second edge region exposed by the opening in the passivation layer and separated from the passivation layer.

[0007] According to one aspect of this disclosure, a semiconductor package includes: a redistribution structure including a first surface and a second surface opposite to each other, and the redistribution structure further including conductive pads on the first surface; a passivation layer on the first surface of the redistribution structure, the passivation layer including an opening that exposes a portion of the conductive pads; a semiconductor chip on the second surface of the redistribution structure; an encapsulator on the second surface of the redistribution structure and encapsulating at least a portion of the semiconductor chip; and conductive bumps on the passivation layer and filling at least a portion of the openings, wherein the conductive pads include: a first edge region covered by the passivation layer; and a second edge region exposed by the openings of the passivation layer and separated from the passivation layer.

[0008] According to one aspect of this disclosure, a stacked package includes: a first semiconductor package including: a first redistribution structure; a first semiconductor chip on the first redistribution structure; a first encapsulation encapsulating at least a portion of the first semiconductor chip; a first conductive pad on the first encapsulation and electrically connected to the first redistribution structure; and a first passivation layer on the first encapsulation, the first passivation layer including a first opening that exposes a portion of the first conductive pad; and a second semiconductor package on the first semiconductor package, the second semiconductor package including: a second redistribution structure including a first surface and a second surface opposite to each other, the second redistribution structure further including a second conductive pad on the first surface. The first conductive pad includes: a first edge region covered by the first passivation layer; a second edge region exposed by the first opening of the first passivation layer and separated from the first passivation layer; and a conductive bump on the second passivation layer; a second semiconductor chip on the second surface of the second redistribution structure; and a second encapsulation on the second surface of the second redistribution structure and encapsulating at least a portion of the second semiconductor chip, wherein the first conductive pad includes: a first edge region covered by the first passivation layer; and a second edge region exposed by the first opening of the first passivation layer and separated from the first passivation layer, and wherein the conductive bump fills at least a portion of each of the first opening and the second opening. Attached Figure Description

[0009] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 It is a cross-sectional view of the stacked package (POP) based on the comparison example;

[0011] Figure 2 This is a diagram illustrating the warping shape that occurs in a stacked package according to a comparative example;

[0012] Figure 3 It is a diagram showing the shape of an electrical short circuit that occurs on a conductive bump in an actual product;

[0013] Figure 4 This is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure;

[0014] Figure 5 yes Figure 4 A top view of the semiconductor package shown;

[0015] Figure 6 yes Figure 4 A magnified view of region A;

[0016] Figure 7 yes Figure 4 Enlarged view of an example variant of region A;

[0017] Figure 8 yes Figure 5 A magnified view of region B;

[0018] Figure 9 It includes Figure 4 A cross-sectional view of the stacked semiconductor package shown;

[0019] Figure 10 It shows Figure 9 The diagram shows warping occurring in the stacked package.

[0020] Figure 11 This is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure;

[0021] Figure 12 This is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure;

[0022] Figure 13 This is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure;

[0023] Figure 14 This is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure;

[0024] Figure 15 yes Figure 14 A magnified view of region C;

[0025] Figure 16 yes Figure 14 Enlarged view of an example variant of region C;

[0026] Figure 17 It includes Figure 14 A cross-sectional view of the stacked semiconductor package shown;

[0027] Figure 18 It shows Figure 17 The diagram shows warping occurring in the stacked package; and

[0028] Figures 19 to 30 It is shown Figure 12 A diagram illustrating a method for manufacturing a semiconductor package. Detailed Implementation

[0029] In the following description, non-limiting exemplary embodiments of the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are illustrated. As those skilled in the art will recognize, the described exemplary embodiments can be modified in various ways without departing from the spirit and scope of the present disclosure.

[0030] To clearly illustrate exemplary embodiments of this disclosure, parts not directly related to the embodiments may be omitted, and the same reference numerals may be attached to the same or similar constituent elements throughout the specification.

[0031] Furthermore, for better understanding and ease of description, the dimensions and thicknesses of each configuration shown in the accompanying drawings may be arbitrarily illustrated, but the embodiments of this disclosure are not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc., may be exaggerated for clarity. In the drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0032] Throughout this specification and the following claims, when an element is described as being “coupled” to another element, that element may be “directly coupled” to the other element or “indirectly coupled” to the other element via a third element. From a similar perspective, this includes not only “physical connection” but also “electrical connection.”

[0033] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. In contrast, when an element is referred to as being "directly above" another element, there are no intermediate elements present. Furthermore, in this specification, the terms "on" or "above" do not necessarily mean located on the upper side of the object portion based on the direction of gravity.

[0034] Furthermore, unless otherwise expressly stated, the words “including” (or “contains”) and variations such as “including” (or “contains”) or “includes” (or “contains”) should be understood as implying the inclusion of the stated element but excluding any other element.

[0035] Furthermore, in this specification, the phrase "in a plane" refers to the portion of the object viewed from above, and the phrase "in a cross section" refers to the cross section of the vertically cut portion of the object viewed from the side.

[0036] Additionally, throughout this specification, ordinal numbers such as "first," "second," etc., are used to distinguish components from other identical or similar components and do not necessarily refer to a specific component. Therefore, a component referred to as a first component in a particular part of this specification may be referred to as a second component in another part of this specification.

[0037] Additionally, throughout this specification, unless otherwise stated, a singular reference to any component includes a plural reference to that component. For example, "insulating layer" can be used not only to refer to one insulating layer, but also to refer to multiple insulating layers, such as two, three, or more.

[0038] Additionally, throughout this specification, references to directions such as upper surface, upper part, upper side, above, lower surface, lower side, and below are provided with reference to the accompanying drawings to aid in explanation and understanding.

[0039] In the following description, a semiconductor package according to a non-limiting example embodiment of the present disclosure is illustrated with reference to the accompanying drawings.

[0040] Figure 1 It is a cross-sectional view of the stacked package (POP) based on the comparison example;

[0041] Figure 2 This is a diagram illustrating the warping shape that occurs in a stacked package according to a comparative example.

[0042] Figure 3 This is a diagram showing the shape of an electrical short circuit that occurs on a conductive bump in an actual product.

[0043] Reference Figure 1 A stacked package (POP) may include a first semiconductor package 100 as the lower package and a second semiconductor package 200 as the upper package. The first semiconductor package 100 and the second semiconductor package 200 may be connected via conductive bumps 260 (e.g., solder balls), and the first semiconductor package 100 and the second semiconductor package 200 may each include conductive pads 152P and 212P (e.g., copper (Cu) pads) for connection to the conductive bumps 260. SMD pads may be used as conductive pads 152P and 212P for the first semiconductor package 100 and the second semiconductor package 200.

[0044] There are two types of conductive pads: solder mask defined (SMD) pads and non-solder mask defined (NSMD) pads. SMD pads have an opening in the solder mask that is smaller than the pad diameter, allowing the edge areas to be covered by the solder mask. On the other hand, NSMD pads have a solder mask larger than the pad diameter, separating the edge areas from the Cu pad.

[0045] Reference Figure 2Due to the difference in the coefficient of thermal expansion (CTE) between the first semiconductor package 100 and the second semiconductor package 200 in the POP, warping may occur. For example, the first semiconductor package 100 may bend into a furrowed shape with the central area bulging upwards, and the second semiconductor package 200 may bend into a smiling shape with the central area bulging downwards. When warping occurs, adjacent solder balls may be subjected to pressure, causing an electrical short circuit between them (see reference). Figure 3 Additionally, when the solder balls in the edge area of ​​the POP are subjected to pressure, the thickness of the central area of ​​the POP may increase, causing a deviation from the reference specifications.

[0046] Embodiments of this disclosure introduce semi-non-solder resist layer defined (NSMD) pads that combine SMD and NSMD pads in a semiconductor package to control solder flow and prevent electrical short circuits when adjacent solder balls come into contact with each other during warpage. Furthermore, embodiments of this disclosure mitigate the problem of increased maximum POP thickness due to solder ball compression. The semi-NSMD pads according to embodiments of this disclosure can be introduced into at least one of a first semiconductor package 100 and a second semiconductor package 200.

[0047] The following will describe in detail a semiconductor package according to embodiments of the present disclosure, including half NSMD pads.

[0048] Figure 4 This is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0049] Figure 5 yes Figure 4 The top view of the semiconductor package shown.

[0050] Figure 6 yes Figure 4 A magnified view of region A.

[0051] Figure 7 yes Figure 4 A magnified view of an example variant of region A.

[0052] Figure 8 yes Figure 5 A magnified view of region B.

[0053] In one embodiment, a half NSMD pad may be incorporated into a first semiconductor package, which is the lower package of a stacked package.

[0054] The first semiconductor package 100A may include a redistribution structure 110, a core substrate 120 disposed on the redistribution structure 110 and having a via 120h, a semiconductor chip 130 disposed on the redistribution structure 110 within the via 120h, an encapsulation member 140 encapsulating at least a portion of the semiconductor chip 130 and extending on the core substrate 120, one or more conductive pads (e.g., a first conductive pad 152P1 and a second conductive pad 152P2) disposed on the encapsulation member 140, and a passivation layer 160 disposed on the encapsulation member 140 and having openings (e.g., a first opening 160h1 and a second opening 160h2) that expose a portion of the conductive pads (e.g., the first conductive pad 152P1 and the second conductive pad 152P2).

[0055] The redistribution structure 110 may include an insulating layer 111, a wiring layer 112, and vias 113. For example, the redistribution structure 110 may include a first insulating layer 111A, a first wiring layer 112A disposed on the first insulating layer 111A, a first via 113A that electrically connects the first wiring layer 112A to the semiconductor chip 130 and the core substrate 120 through the first insulating layer 111A, a second insulating layer 111B disposed on the first insulating layer 111A and covering the second wiring layer 112B, a second wiring layer 112B disposed on the second insulating layer 111B, a second via 113B that connects the first wiring layer 112A and the second wiring layer 112B through the second insulating layer 111B, a third insulating layer 111C disposed on the second insulating layer 111B and covering the second wiring layer 112B, a third wiring layer 112C disposed on the third insulating layer 111C, and a third via 113C that penetrates the third insulating layer 111C to connect the second wiring layer 112B and the third wiring layer 112C.

[0056] The redistribution structure 110 may have an upper surface 110u and a lower surface 110l, and the upper surface 110u of the redistribution structure 110 may be the surface where the first insulating layer 111A is located, and the lower surface 110l may be the surface where the third insulating layer 111C and the third wiring layer 112C are located.

[0057] Insulating layers 111 may be located between wiring layers 112 to prevent electrical short circuits between wiring layers 112. The insulating layers 111 may or may not have visible boundaries, depending on their materials and manufacturing processes. Insulating materials may be used as the materials for insulating layers 111, and may include, for example, polyimide (PI), epoxy resin, photoimageable dielectric (PID), etc.

[0058] Wiring layer 112 may include wiring patterns, and these patterns may be interconnected to perform various functions depending on the configuration. For example, wiring layer 112 may include at least one of a signal pattern performing a signal transmission function, a power pattern performing a power transmission function, and a ground pattern performing a grounding function. A third wiring layer 112C located at the bottom of wiring layer 112 may include conductive pads for electrical connection to conductive bumps 182. The number of wiring layers 112 is not limited and may be more or less than the number shown in the figures. Conductive materials may be used as the material for wiring layer 112, and examples include copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), tin (Sn), chromium (Cr), palladium (Pd), lead (Pb), titanium (Ti), tungsten (W), or alloys thereof.

[0059] Via 113 can provide electrical connections between wiring layers 112 located on different layers. A first via 113A located at the top can contact the semiconductor chip 130 and the core substrate 120 respectively to electrically connect them to the wiring layer 112. A conductive material can be used as the material for the via 113, and the same material as the wiring layer 112 can be used. Depending on the manufacturing process, the via 113 can be integrally formed with the wiring layer 112, so that there is no boundary between them. Additionally, the via 113 can have a tapered, cylindrical, or other shape, with its width narrowing from one side to the other.

[0060] The core substrate 120 can be placed on the upper surface 110u of the redistribution structure 110.

[0061] The core substrate 120 can provide electrical connections between the redistribution structure 110 and the wiring layer 152, which includes conductive pads (e.g., a first conductive pad 152P1 and a second conductive pad 152P2). Therefore, the core substrate 120 can be electrically connected to each of the redistribution structure 110 and the wiring layer 152.

[0062] The core substrate 120 may have a via 120h. The via 120h can penetrate between the upper and lower surfaces of the core substrate 120. In an embodiment, the first semiconductor package 100A may include a plurality of semiconductor chips 130, and the core substrate 120 may include a plurality of vias 120h for placing each of the semiconductor chips 130.

[0063] The core substrate 120 may include an insulating layer 121, a wiring layer 122, and a via 123. For example, the core substrate 120 may include an insulating layer 121, a first wiring layer 122A disposed on the lower surface of the insulating layer 121, a second wiring layer 122B disposed on the upper surface of the insulating layer 121, and a via 123 penetrating the insulating layer 121 to electrically connect the first wiring layer 122A and the second wiring layer 122B. According to some exemplary embodiments of this disclosure, additional building layers including the insulating layer and the wiring layer may be placed on the upper and / or lower surfaces of the insulating layer 111.

[0064] The insulating layer 121 can provide rigidity to the core substrate 120 and prevent electrical short circuits between the wiring layers 122. The insulating layer 121 can be made of insulating materials such as polyimide (PI), epoxy resin, prepreg, etc.

[0065] Wiring layer 122 may include wiring patterns, and these wiring patterns may be interconnected to perform various functions depending on the configuration. For example, wiring layer 112 may include at least one of a signal pattern performing a signal transmission function, a power pattern performing a power transmission function, and a ground pattern performing a grounding function. Depending on the manufacturing process, the first wiring layer 122A may be at least partially embedded within the first insulating layer 111A of the redistribution structure 110. Conductive materials may be used as the material for wiring layer 122, such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), tin (Sn), chromium (Cr), palladium (Pd), lead (Pb), titanium (Ti), tungsten (W), or alloys thereof.

[0066] Via 123 can provide electrical connections between wiring layers 122 located on different layers. A conductive material can be used as the material for via 123, and the same material as the wiring layer 122 can be used. Depending on the manufacturing process, via 123 can be integrally formed with the wiring layer 122, so that there is no boundary between them. Additionally, via 123 can have shapes such as hourglass, cone, or cylinder, with its width narrowing from one side to the other.

[0067] According to an embodiment, conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) can be electrically connected to the redistribution structure 110 via conductive pillars, conductive balls, etc. (instead of the core substrate 120), and such embodiments should also be considered to be included in this disclosure.

[0068] Semiconductor chip 130 can be placed on the upper surface 110u of redistribution structure 110 within via 120h and electrically connected to redistribution structure 110. First semiconductor package 100A may include a plurality of semiconductor chips 130, and each semiconductor chip 130 may be placed within each via 120h.

[0069] Semiconductor chip 130 may include connection pads 130P, which may be arranged face-down to face the redistribution structure 110. Semiconductor chip 130 may be connected by contact with the redistribution structure 110, but is not limited thereto, and may be connected by other configurations such as conductive bumps.

[0070] Semiconductor chip 130 may include a logic chip. The logic chip may include one or more of an application processor (AP), a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), an application-specific integrated circuit (ASIC), and a system-on-a-chip (SoC).

[0071] According to some embodiments of this disclosure, the semiconductor chip 130 may also include a power management IC (PMIC) chip. For example, the semiconductor chip 130 may consist of multiple semiconductor chips, including a logic chip and a PMIC chip.

[0072] Encapsulation 140 can encapsulate at least a portion of semiconductor chip 130 and can extend onto core substrate 120. Additionally, encapsulation 140 can fill a portion of via 120h (e.g., an area where semiconductor chip 130 is not placed). As the material for encapsulation 140, insulating materials such as Ajinomoto deposited film (ABF) and epoxy molding compound (EMC) can be used.

[0073] Conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) may be placed on the encapsulation 140 and may be electrically connected to the core substrate 120. The conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) may be arranged in a fan-out region (i.e., a region that does not overlap with the semiconductor chip 130 in the vertical direction), but are not limited thereto.

[0074] The conductive pads may include a first conductive pad 152P1 and a second conductive pad 152P2.

[0075] According to some embodiments of this disclosure, the first conductive pad 152P1 may be a semi-NSMD pad. The first conductive pad 152P1 may include a first edge region ER1 (similar to an SMD pad) covered by a passivation layer 160 and a second edge region ER2 (similar to an NSMD pad) exposed by a first opening 160h1 of the passivation layer 160 and spaced apart from the passivation layer 160.

[0076] In one embodiment, the second conductive pad 152P2 may be an SMD pad. The edge region of the second conductive pad 152P2 may be covered by a passivation layer 160, and the central region of the second conductive pad 152P2 surrounded by the edge region may be exposed by a second opening 160h2 of the passivation layer 160. In another embodiment, the second conductive pad 152P2 may be an NSMD pad.

[0077] According to some embodiments of this disclosure, by selectively placing the first conductive pad 152P1 in areas of the semiconductor package requiring solder flow control, adjacent conductive bumps 260 can be prevented from contacting each other and causing a short circuit when warping occurs. Furthermore, the problem of increased maximum thickness of the POP due to pressure on the conductive bumps 260 can be mitigated.

[0078] When warping occurs, because both sides (or four sides) of the first semiconductor package 100A bend in the same direction, the first conductive pad 152P1 can be placed on each portion of the peripheral region PR1 on both sides of the first semiconductor package 100A. For example, see also Figure 4 and Figure 5 The first conductive pads 152P1 may be spaced apart from each other and from the central region CR1 between the peripheral regions PR1. In other words, a portion of the first conductive pads 152P1 may be arranged on the left side of the peripheral region PR1 of the first semiconductor package 100A, and other first conductive pads 152P1 may be arranged on the right side of the peripheral region PR1. According to some embodiments of this disclosure, the first conductive pads 152P1 may be arranged around the central region CR1 along the peripheral region PR1 of the first semiconductor package 100A.

[0079] In an embodiment, for each of the first conductive pads 152P1 disposed on both sides of the peripheral region PR1 of the first semiconductor package 100A, the first edge region ER1 may be arranged toward (e.g., adjacent to) the central region CR1. In other words, each of the first conductive pads 152P1 disposed on the peripheral region PR1 on both sides of the first semiconductor package 100A may be arranged such that the second edge region ER2 faces outward of the first semiconductor package 100A. By arranging the second edge region ER2 of the first conductive pad 152P1 toward outward of the first semiconductor package 100A, solder flow can be controlled in the outward direction of the first semiconductor package 100A.

[0080] To prevent short circuits with other conductive pads located outside the first conductive pad 152P1, the first conductive pad 152P1 may be placed on the outermost side of the first semiconductor package 100A among the conductive pads (e.g., the first conductive pad 152P1 and the second conductive pad 152P2). For example, in the first semiconductor package 100A, the first conductive pad 152P1 may be placed further outward than the second conductive pad 152P2.

[0081] In this disclosure, the central region CR1 and the peripheral region PR1 of the first semiconductor package 100A are described as being different from each other, but this is only used to describe an example location where conductive pads (e.g., the first conductive pad 152P1 and the second conductive pad 152P2) are arranged, and the central region CR1 and the peripheral region PR1 may not have significantly different boundaries.

[0082] Reference Figure 6 The first opening 160h1 can expose the region 140e of the encapsulation 140 adjacent to the second edge region ER2. Additionally, the wall surface a2 of the first opening 160h1 can be spaced apart from the second edge region ER2 of the first conductive pad 152P1.

[0083] The side of the first conductive pad 152P1 can be exposed in the second edge region ER2 through the first opening 160h1. The exposed side can be bonded to the conductive bump 260, which can improve the bonding strength and reliability between the first conductive pad 152P1 and the conductive bump 260.

[0084] In an embodiment, the first opening 160h1 can be formed by machining the passivation layer 160 to the interface between the passivation layer 160 and the encapsulation 140. Therefore, the bottom surface a1 of the first opening 160h1 can be located at substantially the same height L1 as the upper surface of the encapsulation 140. In this disclosure, "substantially the same" means not only identical but also includes tolerances in the manufacturing process. By positioning the bottom surface a1 of the first opening 160h1 at substantially the same height as the top surface of the encapsulation 140, the contact area between the conductive bump 260 and the first conductive pad 152P1 can be maximized while ensuring sufficient solder flow control space.

[0085] The width of the first opening 160h1 can be narrower, the same, or in some cases wider in the direction toward the bottom surface a1. Furthermore, the shape of the first opening 160h1 in the plane is not particularly limited, and it can have shapes such as ellipse, quadrilateral with rounded corners, etc.

[0086] Reference Figure 7 In another embodiment, the encapsulation 140 may have a recessed portion 140g extending from the first opening 160h1. The recessed portion 140g may be formed by further processing a portion of the encapsulation 140 during the formation of the first opening 160h1. The depth d1 of the recessed portion 140g may be equal to or less than 10 μm. If the depth d1 of the recessed portion 140g exceeds 10 μm, the area of ​​the conductive bump 260 in contact with the encapsulation 140 may widen, resulting in weakened bonding strength. According to some embodiments of this disclosure, a metal (e.g., Cu) pattern, serving as a processing stop layer, may be placed within the encapsulation 140 to control the depth d1 of the recessed portion 140g.

[0087] The conductive material can be used as the material for the first conductive pad 152P1 and the second conductive pad 152P2, and can be, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), tin (Sn), chromium (Cr), palladium (Pd), lead (Pb), titanium (Ti), tungsten (W) or alloys thereof.

[0088] Refer again Figure 4The conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) may consist of multiple metal layers, such as a first metal layer m1 and a second metal layer m2 disposed on the first metal layer m1. The first metal layer m1 may include copper (Cu), and the thickness of the first metal layer m1 may be approximately 10 μm. The second metal layer m2 may improve the reliability of the conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) and prevent corrosion. The second metal layer m2 may include multiple layers, such as a nickel (Ni) layer and a gold (Au) layer on the nickel layer. The thickness of the second metal layer m2 may be approximately 5 μm to 6 μm, and / or the diameter of the second metal layer m2 may be formed to be smaller than the diameter of the first metal layer m1, but is not limited thereto.

[0089] Conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) can be configured to be included in a wiring layer 152 disposed on the encapsulation 140. The wiring layer 152 may include wiring patterns in addition to the conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2). The wiring patterns may include at least one of a signal pattern performing a signal transmission function, a power pattern performing a power transmission function, and a ground pattern performing a grounding function. The wiring layer 152 may use the same material as the conductive pads 152P. The wiring patterns of the wiring layer 152, excluding the conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2), may include only the first metal layer m1 and may not include the second metal layer m2.

[0090] The first semiconductor package 100A may further include a connection via 153 for electrically connecting conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) and the core substrate 120. The connection via 153 may penetrate a portion of the package 140 and contact the conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) and the core substrate 120, respectively. For example, the connection via 153 may be connected to a second wiring layer 122B of the core substrate 120. The material of the connection via 153 may be the same as that of the wiring layer 152.

[0091] A passivation layer 160 may be disposed on the encapsulation 140 and has openings (e.g., a first opening 160h1 and a second opening 160h2) exposing portions of conductive pads (e.g., a first conductive pad 152P1 and a second conductive pad 152P2). For example, the passivation layer 160 may have a first opening 160h1 exposing a portion of the first conductive pad 152P1 and a second opening 160h2 exposing a portion of the second conductive pad 152P2. The first opening 160h1 may be formed to be larger than the second opening 160h2 to expose a second edge region ER2 of the first conductive pad 152P1. Insulating materials such as solder mask and ABF can be used as the material for the passivation layer 160.

[0092] The first semiconductor package 100A may further include a passivation layer 170 disposed on the lower surface 110l of the redistribution structure 110. The passivation layer 170 may have an opening that exposes conductive pads contained in the third wiring layer 112C at the bottom of the redistribution structure 110. Insulating materials such as solder mask and ABF may also be used as the material for the passivation layer 170.

[0093] Additionally, the first semiconductor package 100A may also include conductive bumps 182 disposed on a passivation layer 170 on the lower surface 110l of the redistribution structure 110 to electrically connect the first semiconductor package 100A to other components such as a motherboard. The conductive bumps 182 may fill openings in the passivation layer 170 and be electrically connected to the redistribution structure 110. The conductive bumps 182 may be, for example, solder balls. The number, spacing, and arrangement of the conductive bumps 182 are not particularly limited and can be implemented in various forms.

[0094] According to some embodiments, an under-bump metal (UBM) layer 181 may be formed between the conductive bump 182 and the redistribution structure 110. The UBM layer 181 may improve the bonding strength between the redistribution structure 110 and the conductive bump 182 and perform the function of a diffusion barrier layer. According to some embodiments, the UBM layer 181 may be configured with multiple layers.

[0095] Figure 9 It includes Figure 4 The diagram shows a cross-sectional view of a stacked semiconductor package.

[0096] The stacked package may include a first semiconductor package 100A according to an embodiment, and a second semiconductor package 200 disposed on and electrically connected to the first semiconductor package 100A.

[0097] The second semiconductor package 200 may include: a redistribution structure 210 including conductive pads 212P disposed on the lower surface of the redistribution structure 210; a semiconductor chip 220 disposed on the upper surface of the redistribution structure 210; an encapsulator 230 encapsulating at least a portion of the semiconductor chip 220 on the upper surface of the redistribution structure 210; a passivation layer 250 disposed on the lower surface of the redistribution structure 210 and having an opening 250h exposing a portion of the conductive pads 212P; and conductive bumps 260 disposed on the passivation layer 250.

[0098] The conductive bump 260 can electrically connect the second semiconductor package 200 to the first semiconductor package 100A. The conductive bump 260 can fill at least a portion of each of the openings in the passivation layer 160 of the first semiconductor package 100A (e.g., first opening 160h1 and second opening 160h2) and the openings 250h of the passivation layer 250 of the second semiconductor package 200, and can be connected to the conductive pads of the first semiconductor package 100A (e.g., first conductive pad 152P1 and second conductive pad 152P2) and the conductive pad 212P of the second semiconductor package 200, respectively. According to embodiments of this disclosure, by introducing the first conductive pad 152P1, solder flow can be controlled during the formation of the conductive bump 260. In embodiments, solder flow can be controlled in a direction outward from the stacked package.

[0099] The following will refer to Figure 14 The other configurations of the second semiconductor package 200 are described in detail.

[0100] Figure 10 It shows Figure 9 The diagram shows warping occurring in the stacked package.

[0101] According to embodiments of this disclosure, by selectively placing the first conductive pad 152P1 in areas where solder flow control is required, it is possible to prevent adjacent conductive bumps 260 from contacting each other and causing a short circuit when warping occurs. Furthermore, it can alleviate the problem of excessive maximum thickness of the POP due to pressure on the conductive bumps 260.

[0102] Figure 11 This is a cross-sectional view of a semiconductor package according to an embodiment.

[0103] The second semiconductor package 100B may include a single through-hole 120h and a single semiconductor chip 130.

[0104] For other configurations of the second semiconductor package 100B, unless there is a specific contradiction, the same provisions as those for the first semiconductor package 100A described above may be applied.

[0105] Figure 12This is a cross-sectional view of a semiconductor package according to an embodiment.

[0106] Semiconductor package 100C may have a core substrate 120 with an embedded wiring substrate (ETS) structure. For example, the core substrate 120 may include a first wiring layer 122A, a first insulating layer 121A covering the first wiring layer, a second wiring layer 122B disposed on the first insulating layer 121A, a first via 123A electrically connecting the first wiring layer 122A and the second wiring layer 122B by penetrating the first insulating layer 121A, a second insulating layer 121B disposed on the first insulating layer 121A and covering the second wiring layer 122B, a third wiring layer 122C disposed on the second insulating layer 121B, and a second via 123B electrically connecting the second wiring layer 122B and the third wiring layer 122C by penetrating the second insulating layer 121B.

[0107] For other configurations of semiconductor package 100C, unless there is a specific contradiction, the above description can also be applied to the description of the first semiconductor package 100A and the second semiconductor package 100B.

[0108] Figure 13 This is a cross-sectional view of a semiconductor package according to an embodiment.

[0109] For each first conductive pad 152P1 disposed on a portion of the peripheral region PR1 on both sides of the semiconductor package 100D, a second edge region ER2 may be disposed toward (e.g., adjacent to) the central region CR1. In other words, each first conductive pad 152P1 disposed on a portion of the peripheral region PR1 on both sides of the semiconductor package 100D may be disposed such that the second edge region ER2 faces the interior of the semiconductor package 100D. By disposing the second edge region ER2 of the first conductive pad 152P1 toward the interior of the semiconductor package 100D, solder flow in the inward direction of the semiconductor package 100D can be controlled.

[0110] To prevent short circuits with other conductive pads located outside the first conductive pad 152P1, the first conductive pad 152P1 can be placed on the innermost side of the semiconductor package 100D among the conductive pads (e.g., the first conductive pad 152P1 and the second conductive pad 152P2). For example, the first conductive pad 152P1 can be placed inside the semiconductor package 100D at a location farther away than the second conductive pad 152P2.

[0111] For other configurations of semiconductor package 100D, unless there is a specific contradiction, the same provisions as those for the first semiconductor package 100A described above may be applied.

[0112] Figure 14This is a cross-sectional view of a semiconductor package according to an embodiment.

[0113] Figure 15 yes Figure 14 A magnified view of region C.

[0114] Figure 16 yes Figure 14 A magnified view of an example variant of region C.

[0115] In one embodiment, a half-NSMD pad may be incorporated into a second semiconductor package, which is the upper package of a stacked package.

[0116] The second semiconductor package 200A may include: a redistribution structure 210 including conductive pads (e.g., third conductive pad 212P1 and fourth conductive pad 212P2) disposed on the lower surface of the redistribution structure 210; a semiconductor chip 220 disposed on the upper surface 210u of the redistribution structure 210; an encapsulator 230 encapsulating at least a portion of the semiconductor chip 220 on the upper surface 210u of the redistribution structure 210; a passivation layer 250 disposed on the lower surface 210l of the redistribution structure 210 and having openings (e.g., third opening 250h1 and fourth opening 250h2) exposing a portion of the conductive pads (e.g., third conductive pad 212P1 and fourth conductive pad 212P2); and conductive bumps 260 disposed on the passivation layer 250.

[0117] The redistribution structure 210 may include an insulating layer 211, a wiring layer 212, and a via 213. For example, the redistribution structure 210 may include: a first insulating layer 211A; a first wiring layer 212A disposed on the upper surface of the first insulating layer 211A; a second insulating layer 211B disposed on and covering the first insulating layer 211A; a second wiring layer 212B disposed on the second insulating layer 211B; a third insulating layer 211C disposed on and covering the second insulating layer 212B; and a third wiring layer 212C disposed on the third insulating layer 211A. On the insulating layer 211C; a fourth wiring layer 212D is disposed on the lower surface of the first insulating layer 211A; a first via 213A penetrates the first insulating layer 211A to connect the first wiring layer 212A and the fourth wiring layer 212D; a second via 213B penetrates the second insulating layer 211B to connect the second wiring layer 212B and the third wiring layer 212C; and a third via 213C penetrates the third insulating layer 211C to connect the third wiring layer 212C and the fourth wiring layer 212D.

[0118] The upper surface 210u of the redistribution structure 210 may be the surface on which the third insulating layer 211C and the third wiring layer 212C are arranged, and the lower surface 210l of the redistribution structure 210 may be the surface on which the first insulating layer 211A and the fourth wiring layer 212D are arranged.

[0119] Insulating layers 211 may be located between wiring layers 212 to prevent electrical short circuits between them. Insulating layers 211 may or may not have visible boundaries, depending on their materials and manufacturing processes. Insulating materials may be used as the materials for insulating layers 211, such as polyimide (PI), epoxy resin, photoimageable dielectric (PID), etc.

[0120] Wiring layer 212 may include wiring patterns, and these wiring patterns may be connected to each other to perform various functions according to configuration. For example, wiring layer 212 may include at least one of a signal pattern performing a signal transmission function, a power pattern performing a power transmission function, and a ground pattern performing a grounding function. The top third wiring layer 212C and the bottom fourth wiring layer 212D of wiring layer 212 may each include conductive pads for electrical connection to semiconductor chip 220 and conductive bump 260. The number of wiring layers 212 is not limited and may be more or less than the number shown in the figures. Conductive materials may be used as the material for wiring layer 212, and examples include copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), tin (Sn), chromium (Cr), palladium (Pd), lead (Pb), titanium (Ti), tungsten (W), or alloys thereof.

[0121] Via 213 can provide electrical connections between wiring layers 212 located on different layers. A conductive material can be used as the material for via 213, and the same material as the wiring layer 212 can be used. Depending on the manufacturing process, via 213 can be integrally formed with the wiring layer 212, so that there is no boundary between them. Additionally, via 213 can have a tapered shape, cylindrical shape, etc., that narrows from one side to the other.

[0122] The conductive pads may include a third conductive pad 212P1 and a fourth conductive pad 212P2.

[0123] According to embodiments of this disclosure, the third conductive pad 212P1 may be a semi-NSMD pad. The third conductive pad 212P1 may include a third edge region ER3 covered by the passivation layer 250, and a fourth edge region ER4 exposed by the third opening 250h1 of the passivation layer 250 and spaced apart from the passivation layer 250.

[0124] In one embodiment, the fourth conductive pad 212P2 may be an SMD pad. The edge region of the fourth conductive pad 212P2 may be covered by a passivation layer 250, and the central region of the fourth conductive pad 212P2 surrounded by the edge region may be exposed by a fourth opening 250h2 of the passivation layer 250. In another embodiment, the fourth conductive pad 212P2 may be an NSMD pad.

[0125] When warping occurs, both sides (or all four sides) of the second semiconductor package 200A can warp in the same direction, allowing the third conductive pads 212P1 to be positioned on portions of the peripheral regions PR2 on both sides of the second semiconductor package 200A. For example, portions of the third conductive pads 212P1 can be spaced apart from each other in the peripheral regions PR2 via the central region CR2. According to some embodiments, the third conductive pads 212P1 can be arranged around the central region CR2 along the peripheral regions PR2 of the second semiconductor package 200A.

[0126] In an embodiment, each third conductive pad 212P1 disposed on two portions of the peripheral region PR2 of the second semiconductor package 200A may have a third edge region ER3 disposed toward (e.g., adjacent to) the central region CR2. In this case, to prevent electrical short circuits with other conductive pads disposed outside the third conductive pad 212P1, among the conductive pads (e.g., the third conductive pad 212P1 and the fourth conductive pad 212P2), the third conductive pad 212P1 may be placed on the outermost side of the second semiconductor package 200A. For example, in the second semiconductor package 200A, the third conductive pad 212P1 may be placed further outward than the fourth conductive pad 212P2.

[0127] In another embodiment, each third conductive pad 212P1 disposed on two portions of the peripheral region PR2 of the second semiconductor package 200A may have a fourth edge region ER4 disposed toward (e.g., adjacent to) the central region CR2. In this case, to prevent electrical short circuits with other conductive pads disposed inside the third conductive pad 212P1, among the conductive pads (e.g., the third conductive pad 212P1 and the fourth conductive pad 212P2), the third conductive pad 212P1 may be placed at the innermost part of the second semiconductor package 200A. For example, the third conductive pad 212P1 may be placed further inside the second semiconductor package 200A than the fourth conductive pad 212P2.

[0128] Meanwhile, the second semiconductor package 200A, the central region CR2, and the peripheral region PR2 may not have a clearly defined boundary.

[0129] Reference Figure 15The third opening 250h1 can expose the region 211e adjacent to the fourth edge region ER4 of the first insulating layer 211A. Additionally, the wall surface b2 of the third opening 250h1 can be spaced apart from the fourth edge region ER4 of the third conductive pad 212P1.

[0130] One side of the third conductive pad 212P1 in the fourth edge region ER4 can be exposed through the third opening 250h1. The exposed side can be bonded to the conductive bump 260, which can improve the bonding strength and reliability between the third conductive pad 212P1 and the conductive bump 260.

[0131] In this embodiment, the third opening 250h1 can be formed by machining the passivation layer 250 up to the interface between the passivation layer 250 and the first insulating layer 211A. Therefore, the bottom surface b1 of the third opening 250h1 can be located at a height L2 substantially the same as the lower surface of the first insulating layer 211A. By positioning the bottom surface b1 of the third opening 250h1 and the lower surface of the first insulating layer 211A at substantially the same height, the contact area between the conductive bump 260 and the third conductive pad 212P1 can be maximized while ensuring sufficient space for solder flow control.

[0132] The width of the third opening 250h1 can be narrower, the same, or in some cases wider in the direction toward the bottom surface b1. Furthermore, the shape of the third opening 250h1 in the plane is not particularly limited, and it can have shapes such as ellipse, quadrilateral with rounded corners, etc.

[0133] Reference Figure 16 In another embodiment, the first insulating layer 211A may have a recessed portion 211g extending from the third opening 250h1. The recessed portion 211g can be formed by further processing a portion of the first insulating layer 211A during the formation of the third opening 250h1. The depth d2 of the recessed portion 211g may be equal to or less than 10 μm. If the depth d2 of the recessed portion 211g exceeds 10 μm, the area of ​​the conductive bump 260 in contact with the first insulating layer 211A may increase, thereby weakening the bonding strength. According to some embodiments, a metal (e.g., Cu) pattern used as a processing stop layer may be placed within the first insulating layer 211A to control the depth d2 of the recessed portion 211g.

[0134] Semiconductor chip 220 can be placed on the upper surface 210u of redistribution structure 210 and electrically connected to redistribution structure 210. Semiconductor chip 220 may include connection pads 220P and can be arranged facing upwards so that connection pads 220P can face upwards for bonding via wires 240. Alternatively, semiconductor chip 220 can be placed facing downwards so that connection pads 220P face downwards. The number of semiconductor chips 220 is not particularly limited and can be a single semiconductor chip or multiple semiconductor chips.

[0135] Semiconductor chip 220 may include a memory chip. The memory chip may include one or more of the following: dynamic random access memory (DRAM) chip, static random access memory (SRAM) chip, flash memory chip, high bandwidth memory (HBM) chip, read-only memory (ROM) chip, and magnetic random access memory (MRAM) chip.

[0136] Encapsulation 230 can encapsulate at least a portion of the semiconductor chip 220 on the upper surface 210u of the redistribution structure 210. As the material of encapsulation 230, insulating materials such as Ajinomoto film (ABF) and epoxy molding compound (EMC) can be used.

[0137] Passivation layer 250 may be disposed on the lower surface 210l of redistribution structure 210 and may have openings (e.g., third opening 250h1 and fourth opening 250h2) exposing some areas of conductive pads (e.g., third conductive pad 212P1 and fourth conductive pad 212P2). For example, passivation layer 250 may have a third opening 250h1 exposing a portion of third conductive pad 212P1 and a fourth opening 250h2 exposing a portion of fourth conductive pad 212P2. Third opening 250h1 may be formed to have a larger dimension than fourth opening 250h2 in order to expose a fourth edge region ER4 of third conductive pad 212P1. Insulating materials such as solder mask and ABF may be used as materials for passivation layer 250.

[0138] Conductive bumps 260 may be disposed on passivation layer 250 to electrically connect the second semiconductor package 200A to the first semiconductor package 100. The conductive bumps 260 may fill at least a portion of the openings in passivation layer 250 (e.g., third opening 250h1 and fourth opening 250h2) and be electrically connected to redistribution structure 210. The conductive bumps 260 may be, for example, solder balls. The number, spacing, and arrangement of the conductive bumps 260 are not particularly limited and can be implemented in various forms.

[0139] Figure 17 It includes Figure 14 The diagram shows a cross-sectional view of a stacked semiconductor package.

[0140] According to an embodiment, the stacked package may include a first semiconductor package 100 and a second semiconductor package 200A.

[0141] The conductive bump 260 can electrically connect the second semiconductor package 200A to the first semiconductor package 100. The conductive bump 260 can fill at least a portion of each of the openings 160h of the passivation layer 160 of the first semiconductor package 100 and the openings (e.g., a third opening 250h1 and a fourth opening 250h2) of the passivation layer 250 of the second semiconductor package 200A, and connect to the conductive pads 152P of the first semiconductor package 100 and the conductive pads (e.g., a third conductive pad 212P1 and a fourth conductive pad 212P2) of the second semiconductor package 200A. According to embodiments of this disclosure, by introducing the third conductive pad 212P1, solder flow can be controlled during the formation of the conductive bump 260. In embodiments, solder flow can be controlled in the outward direction of the stacked packages.

[0142] According to an embodiment, the first semiconductor package 100 may be composed of a plurality of semiconductor packages (e.g., first semiconductor package 100A, second semiconductor package 100B, semiconductor package 100C, and semiconductor package 100D) including a first conductive pad 152P1. That is, a half-NSMD pad according to an embodiment of the present disclosure may be introduced into both the first semiconductor package and the second semiconductor package. At this time, the second edge region ER2 of the first conductive pad 152P1 and the fourth edge region ER4 of the third conductive pad 212P1 may overlap each other in a plane (vertically). By exposing the edge regions ER2 and ER4 of the conductive pads at the overlapping location via openings (e.g., the first opening 160h1 and the third opening 250h1), solder flow can be controlled in the same direction.

[0143] Figure 18 It shows Figure 17 The diagram shows warping occurring in the stacked package.

[0144] According to embodiments of this disclosure, by selectively placing the third conductive pad 212P1 in areas requiring solder flow control, it is possible to prevent adjacent conductive bumps 260 from connecting to each other and causing a short circuit when warping occurs. Furthermore, it can alleviate the problem of increased maximum thickness of the POP due to pressure on the conductive bumps 260.

[0145] Figures 19 to 30 It is shown Figure 12 A diagram illustrating a method for manufacturing a semiconductor package.

[0146] In the following description, an exemplary method for manufacturing a semiconductor package 100C is described.

[0147] First, refer to Figure 19 and Figure 20 A core substrate 120 can be formed, and then vias 120h can be formed in the core substrate 120. The core substrate 120 can be manufactured by sequentially forming a wiring layer 122, an insulating layer 121, and vias 123. There are no particular limitations on the method of forming vias 120h; they can be formed by laser processing, machining, etc.

[0148] Next, refer to Figure 21 and Figure 22 The semiconductor chip 130 can be placed within the via 120h of the core substrate 120, and an encapsulation 140 can be formed. The semiconductor chip 130 can be fixed by attaching an adhesion member 10 (e.g., a die-attachment film (DAF)) to the lower surface of the core substrate 120 and attaching it to the adhesion member 10 within the via 120h of the core substrate 120. The method of forming the encapsulation 140 is not particularly limited, and it can be formed by compression molding, transfer molding, etc.

[0149] Next, refer to Figure 23 The encapsulation member 140 can be attached to the first carrier structure 20, and the adhesion member 10 can be removed. The adhesion member 10 can be removed by methods such as heat treatment or ultraviolet treatment.

[0150] Next, refer to Figure 24 and Figure 25 A redistribution structure 110 can be formed on the surface of the adhesion member 10 from which the core substrate 120 and semiconductor chip 130 are removed, and a passivation layer 170 and a UBM layer 181 can be formed on the redistribution structure 110. The redistribution structure 110 can be fabricated by sequentially forming an insulating layer 111, vias 113, and a wiring layer 112. When a PID is used as the insulating layer 111, vias 113 with fine pitch can be formed by photolithography.

[0151] Next, refer to Figure 26 The first carrier structure 20 can be removed, and the second carrier structure 30 can be attached to the lower surface of the redistribution structure 110.

[0152] According to some embodiments of this disclosure, after the first carrier structure 20 is removed, an additional encapsulation can be formed on the encapsulation 140. The additional encapsulation can be formed by laminating, for example, ABF, and can be integral with the encapsulation 140 such that there are no boundaries between them. The additional encapsulation can be attached to the cured encapsulation 140 in a semi-cured state to improve the bonding strength between the encapsulation 140 and the wiring layer 152.

[0153] Next, refer to Figure 27 and Figure 28 A connection via 153 can be formed, and a wiring layer 152 including conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2) can be formed. The connection via 153 can be formed by laser processing of the encapsulation 140 to form the via 153h and filling the interior of the via 153h via an electroplating process. The wiring layer 152 can be formed on the encapsulation 140 by an electroplating process and can be integrally formed with the connection via 153. When forming the conductive pads (e.g., first conductive pad 152P1 and second conductive pad 152P2), a second metal layer m2 can be additionally formed on the first metal layer m1.

[0154] Next, refer to Figure 29 A passivation layer 160 may be formed to cover the wiring layer 152 on the encapsulation 140, and openings (e.g., a first opening 160h1 and a second opening 160h2) may be formed in the passivation layer 160. The passivation layer 160 may be formed by laminating, for example, ABF. The openings (e.g., the first opening 160h1 and the second opening 160h2) may be formed by physical (e.g., laser) or chemical treatment of the passivation layer 160, and the first opening 160h1 may be formed to expose a second edge region ER2 of the first conductive pad 152P1.

[0155] Finally, refer to Figure 30 The second carrier structure 30 can be removed and conductive bumps 182 can be formed on the UBM layer 181, thereby manufacturing a semiconductor package 100C according to the embodiment.

[0156] Although non-limiting exemplary embodiments have been described, it should be understood that this disclosure is not limited to the exemplary embodiments, and rather, various modifications and equivalent arrangements are included within the spirit and scope of this disclosure.

[0157] Additionally, the exemplary embodiments of this disclosure are not independent of each other and can be combined with each other unless there is a specific contradiction between them. Therefore, combinations of embodiments of this disclosure should also be considered as included in this disclosure.

Claims

1. A semiconductor package comprising: a redistribution structure; a semiconductor chip on and electrically connected to the redistribution structure; an encapsulant encapsulating at least a portion of the semiconductor chip; one or more electrically conductive pads on and electrically connected to the redistribution structure; and a passivation layer on the encapsulant, the passivation layer including an opening exposing a portion of the one or more electrically conductive pads, wherein each of the one or more electrically conductive pads includes: a first edge region covered by the passivation layer; and a second edge region exposed by the opening of the passivation layer and separated from the passivation layer. The opening exposes a region of the encapsulant adjacent to the second edge region.

2. The semiconductor package of claim 1, wherein, A bottom surface of the opening has a same height as a top surface of the encapsulant.

3. The semiconductor package of claim 2, wherein, The encapsulant includes a recessed portion extending from the opening.

4. The semiconductor package of claim 2, wherein, A depth of the recessed portion is equal to or less than 10 pm.

5. The semiconductor package of claim 4, wherein, The semiconductor package includes a peripheral region and a central region surrounded by the peripheral region, and 6. The semiconductor package of claim 1, wherein, wherein the one or more electrically conductive pads include a first electrically conductive pad and a second electrically conductive pad on the peripheral region, and the first electrically conductive pad and the second electrically conductive pad are spaced apart from each other with the central region therebetween. The first edge region of each of the first electrically conductive pad and the second electrically conductive pad is on a side of the first electrically conductive pad and the second electrically conductive pad facing the central region.

7. The semiconductor package of claim 6, wherein, The second edge region of each of the first electrically conductive pad and the second electrically conductive pad is on a side of the first electrically conductive pad and the second electrically conductive pad facing the central region.

8. The semiconductor package of claim 6, wherein, 9. The semiconductor package of claim 1, further comprising: a core substrate on and electrically connected to the redistribution structure, the core substrate including a via, wherein the semiconductor chip is in the via. The core substrate includes:

10. The semiconductor package of claim 9, wherein, an insulating layer including a first surface and a second surface opposite to each other; a first wiring layer disposed on the first surface of the insulating layer; a second wiring layer on the second surface of the insulating layer; and a via penetrating the insulating layer and electrically connecting the first wiring layer and the second wiring layer. The core substrate includes:

11. The semiconductor package of claim 9, wherein, a first wiring layer; a first insulating layer on the first wiring layer; a second wiring layer on the first insulating layer; a first via penetrating the first insulating layer and electrically connecting the first wiring layer and the second wiring layer; a second insulating layer on the first insulating layer and the second wiring layer; a third wiring layer on the second insulating layer; and a second via penetrating the second insulating layer and electrically connecting the second wiring layer and the third wiring layer. A connection pad of the semiconductor chip faces the redistribution structure.

12. The semiconductor package of claim 1, wherein, The semiconductor chip is on a first surface of the redistribution structure, and 13. The semiconductor package of claim 1, wherein, wherein the semiconductor package further includes: an electrically conductive bump on a second surface of the redistribution structure, the second surface opposite to the first surface. ​ 14. A semiconductor package comprising: a redistribution structure including a first surface and a second surface opposite each other, and the redistribution structure further includes a conductive pad on the first surface; a passivation layer on the first surface of the redistribution structure, the passivation layer including an opening exposing a portion of the conductive pad; a semiconductor chip on the second surface of the redistribution structure; an encapsulant on the second surface of the redistribution structure and encapsulating at least a portion of the semiconductor chip; and a conductive bump on the passivation layer and filling at least a portion of the opening, wherein the conductive pad includes: a first edge region covered by the passivation layer; and a second edge region exposed by the opening of the passivation layer and separated from the passivation layer. the redistribution structure further includes an insulating layer, 15. The semiconductor package of claim 14, wherein, wherein the insulating layer is on the conductive pad, and wherein the opening exposes a region of the insulating layer adjacent to the second edge region. the insulating layer includes a recessed portion extending from the opening.

16. The semiconductor package of claim 15, wherein, 17. A stacked package comprising: a first semiconductor package including: a first redistribution structure; a first semiconductor chip on the first redistribution structure; a first encapsulant encapsulating at least a portion of the first semiconductor chip; a first conductive pad on the first encapsulant and electrically connected to the first redistribution structure; and a first passivation layer on the first encapsulant, the first passivation layer including a first opening exposing a portion of the first conductive pad; and a second semiconductor package on the first semiconductor package, the second semiconductor package including: a second redistribution structure including a first surface and a second surface opposite each other, the second redistribution structure further includes a second conductive pad on the first surface; a second passivation layer on the first surface of the second redistribution structure, the second passivation layer including a second opening exposing a portion of the second conductive pad; a conductive bump on the second passivation layer; a second semiconductor chip on the second surface of the second redistribution structure; and a second encapsulant on the second surface of the second redistribution structure and encapsulating at least a portion of the second semiconductor chip, wherein the first conductive pad includes: a first edge region covered by the first passivation layer; and a second edge region exposed by the first opening of the first passivation layer and separated from the first passivation layer, and wherein the conductive bump fills at least a portion of each of the first opening and the second opening. the second conductive pad includes:

18. The package-on-package of claim 17, wherein, a third edge region covered by the second passivation layer; and a fourth edge region exposed by the second opening in the second passivation layer and spaced apart from the second passivation layer. the second edge region and the fourth edge region vertically overlap each other.

19. The package-on-package of claim 18, wherein, the first semiconductor chip includes a logic chip, and 20. The package of claim 17, wherein, wherein the second semiconductor chip includes a memory chip. ​

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