Stack structure of hybrid packaging technology and manufacturing method thereof
By using hybrid packaging technology, chips are stacked on top of each other, combining wire bonding and flip-chip technologies. This solves the problems of complex connections and high costs in chip packaging, achieving lower packaging difficulty and cost, and improving heat dissipation performance and signal quality.
Patent Information
- Application Number
- CN202511596946.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-04
- Publication Date
- 2026-02-13
AI Technical Summary
Existing technologies for chip packaging suffer from problems such as complex connections, high costs, difficulty in meeting heat dissipation requirements, and difficulty in effectively packaging complex and cost-sensitive chips, especially in multi-layer interposers and chip connections, where the requirements for low cost and efficient heat dissipation are not met.
By employing hybrid packaging technology, chips are stacked on top of each other. Combining wire bonding and flip-chip technologies, electrical connections and thermal management between chips are achieved through the use of redistribution layers, underfill adhesives, and organic epoxy resin adhesives, thereby reducing packaging difficulty and cost.
It saves PCB layout area, reduces trace distance, lowers signal delay, electromagnetic interference and resistance, reduces power consumption and voltage drop, and reduces overall packaging cost.
Smart Images
Figure CN121532060A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a stacked structure of hybrid packaging technology and a manufacturing method thereof. BACKGROUND
[0002] With the semiconductor technology entering the post-moore era, the breakthrough of threads is more and more difficult, and people turn their eyes to advanced packaging technology. Using advanced packaging technology, a single chip or multiple chips are combined together to form a chip module. Users have more functional requirements for electronic products, and more and more chips and components are needed, the circuit is more and more complex, the space of the pcb board is less and less, the development difficulty is increased, and so on. The advantages of the combined chip are obvious.
[0003] The difficulty lies in how to connect all the parts. Monolithic integration depends on effective back-end-of-line (BEOL) metallization processes. When components are packaged separately, manufacturers will turn to ball grid array and similar designs. However, when two or more dies are assembled into a single chip package, the process used to connect them is in a poorly defined middle ground between the two. Many system-on-chip package designs rely on solder connections, and pick-and-place tools will put chips with solder bumps onto a specific carrier.
[0004] Flip-chip soldering, which has poor mechanical properties, further limits Cu-Sn solder joints, which can lead to cracks, fatigue failure, and electromigration. The industry is looking for an alternative solid-state bonding technology to facilitate further pitch scaling, but there are not many processes that meet the speed, low cost, and flexibility of soft soldering. For example, whichever bonding solution is chosen must be able to accommodate variations in the height of the bonding pads and interposers. The process temperature must also be low enough to protect all components of the device stack. When the chip packaging scheme involves multiple layers of interposers and connected chips, the base layer will face particularly challenging thermal dissipation requirements. Each layer above the base may require a separate adhesion step.
[0005] The existing sealing scheme mostly adopts the full flip-chip mode, but it does not mean that all chips are suitable for flip-chip sealing: ① The flip-chip sealing process is complex, and requires high-precision equipment and advanced technology, so the production cost is high. For some cost-sensitive chips that need mass production, such as simple logic chips in ordinary consumer electronics, low-end microcontrollers, etc., using flip-chip sealing will significantly increase the cost and reduce the market competitiveness of the product; ② For chips with fewer pins, such as some simple sensor chips and switch chips, flip-chip sealing cannot fully exert its advantages, but will increase the cost due to the complex process. ③ If the chip itself has low power consumption and generates little heat, the heat dissipation requirement is not high, so it is unnecessary to use flip-chip sealing to improve the heat dissipation performance. For example, some low-power Bluetooth chips and radio frequency identification (RFID) chips generate almost no heat that will affect the performance and reliability of the chips, so a simpler and lower-cost sealing form can be used. SUMMARY
[0006] The present application aims to provide a hybrid packaging technology stack structure and its manufacturing method, which stacks a chip on another chip, compares the wire bonding of two chips on the same plane and flip-chip, saves the layout area of the carrier board, and reduces the wire routing distance. In the case of reduced lines, signal delay, electromagnetic interference, and resistance will be reduced, and power consumption and voltage drop will be reduced.
[0007] To achieve the above-mentioned purpose, the present application provides the following technical solutions: A hybrid packaging technology stack structure and its manufacturing method, comprising a second bare chip and a carrier board, the second bare chip is flip-chip arranged, and the bottom of the second bare chip is provided with a rewiring layer, the bottom of the rewiring layer is provided with a second bare chip solder bump, and the second bare chip solder bump is connected with the pins at the top end of the carrier board, and the rewiring layer and the carrier board are filled with a bottom filling adhesive at the periphery of the second bare chip solder bump; The top end of the second bare chip is coated with an organic epoxy resin adhesive, and the top end of the organic epoxy resin adhesive is adhered with a first bare chip, the top end of the first bare chip is provided with a first bare chip solder joint, and the first bare chip solder joint is connected with a gold wire, and the first bare chip solder joint is connected with the pins of the carrier board through the gold wire.
[0008] As a further technical solution of the present application, the inside of the carrier board is provided with a carrier board internal wire, and the bottom end of the carrier board is connected with a tin ball solder joint through tin paste, and the top end of the carrier board is covered with a plastic packaging film through pressing.
[0009] As a further technical solution of the present application, the following steps are included: S1: incoming inspection, confirm wafer chip model, and clean and automatically optically inspect the product to check whether there are incoming defects of the product; S2: re-wiring process, second flip-chip pin is inverted, the pin is connected to the corresponding second flip-chip solder bump by re-wiring, so as to facilitate the inversion and signal connection; S3: wafer grinding and cutting, the first flip-chip and the second flip-chip are respectively ground and cut, and the wafer is picked up and placed on a corresponding carrier for classified management and storage; S4: carrier plate confirmation, the carrier plate shipment report is compared with the product specification book, the carrier plate model, size, layer number, surface treatment process, sampling point size parameter are confirmed, and the automatic optical inspection is used to check the incoming defects and size deviation; S5: wafer inversion, the second flip-chip is taken out, the second flip-chip is inverted with the front face downward, the second flip-chip solder bump on the second flip-chip is aligned with the pin position on the carrier plate and is pressed and heated, the second flip-chip solder bump is dissolved and solidified, the second flip-chip is fixed on the carrier plate, and the second flip-chip solder bump establishes electrical connection with the carrier plate pin; S6: underfill curing, the thermal expansion coefficients of the second flip-chip solder bump and the carrier plate are different, and the tin ball and the carrier plate connection point are prone to breakage under extreme conditions. The underfill adhesive is injected at the connection between the second flip-chip solder bump and the carrier plate, the gap is filled by using the capillary effect or the preforming method, and after the material is solidified, an adhesive layer and a support structure are formed, so as to relieve the stress caused by the difference in thermal expansion coefficients, thereby improving the impact resistance and thermal fatigue resistance of the package; S7: dispensing, the organic epoxy resin adhesive is uniformly dispensed on the back surface of the second flip-chip; S8: binding, the first flip-chip is taken out, the back surface of the first flip-chip is attached to the back surface of the second flip-chip with the front surface welding point upward, and the welding point on the first flip-chip is connected to the pin on the carrier plate by using the gold wire to establish electrical connection; S9: plastic packaging, the technology of tightly wrapping the plastic film on the surface of the object by heating or pressurizing is mainly used for protecting, sealing or beautifying the product; S10: ball planting, the solder paste is printed on the carrier plate, and then the tin ball welding point with a certain size is added thereon.
[0010] As a further technical scheme of the application, the automatic optical inspection in steps S1 and S4 is to image the physical characteristics of the product by optical scanning, and then compare with the standard parameter database, recognize the defect position by image processing and mark the display, finally output the result, and propose unqualified products.
[0011] As a further technical scheme of the application, the re-wiring process in step S2 comprises the following operation steps: 1), the first layer of insulating layer preparation, the second bare chip (5) front coating a layer of polyimide layer, then in the chip corresponding aluminum pad above exposure development window, the aluminum pad is exposed, this window as the second bare chip (5) and the re-wiring layer connection window; 2), the first UBM barrier layer preparation, using sputtering or plating method, the barrier layer metal is plated on the first layer of polyimide; 3), the preparation of the circuit layer, coating photoresist, exposure development according to the designed circuit, copper electroplating solution electroplating circuit, according to the specification book, product requirements, process specification matching, adjust the corresponding specification parameters, plating solution specification is ph 6-9; Temperature 50-60 ℃; Electroplating time is 30 min-1h; 4), the second layer of insulating layer preparation, coating a layer of polyimide layer on the above processed wafer, the height requirement is higher than the height of the circuit layer, covering the circuit layer, isolating the circuit layer from the outside contact, playing a protective role, then exposure development in the corresponding position window, this window as the circuit layer and the external electrical connection channel; 5), the second UBM barrier layer preparation, the preparation method is consistent with the preparation method of the first UBM barrier layer preparation; 6), tin silver bump preparation, copper column, nickel barrier layer and tin alloy three layer structure are formed through electroplating process, realizing the vertical interconnection of the chip and the interposer or the circuit board.
[0012] Compared with the prior art, the beneficial effects of the present application are: 1. In the present application, the chip is stacked on another chip, and compared with the wire bonding and flip-chip packaging of two chips in the same plane, the layout area of the carrier board is saved, and the wire routing distance is reduced. In the case of reduced circuit, signal delay, electromagnetic interference and resistance will be reduced, and at the same time, power consumption and voltage drop will be reduced; 2. In the present application, the wire bonding technology and flip-chip packaging are combined together, and the overall packaging difficulty and cost are reduced. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 It is the structural schematic diagram of the present application.
[0014] 1-First bare chip solder joint; 2. Gold wire; 3. First bare chip; 4. Organic epoxy resin adhesive; 5. Second bare chip; 6. Re-wiring layer; 7. Second bare chip solder bump; 8. Carrier board; 9. Carrier board internal wire; 10. Solder ball solder joint; 11. Bottom filling glue; 12. Plastic encapsulation film. DETAILED DESCRIPTION
[0015] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.
[0016] Please refer to Figure 1 In the embodiments of the present application, a mixed packaging technology stack structure and a manufacturing method thereof include a second die 5 and a carrier plate 8. The second die 5 is flip-chip mounted, and the bottom of the second die 5 is provided with a redistribution layer 6. The bottom of the redistribution layer 6 is provided with a second die solder bump 7, and the second die solder bump 7 is connected to the pins at the top of the carrier plate 8. The periphery of the second die solder bump 7 between the redistribution layer 6 and the carrier plate 8 is filled with a bottom filling adhesive 11. The top of the second die 5 is coated with an organic epoxy resin adhesive 4, and the top of the organic epoxy resin adhesive 4 is bonded to a first die 3. The top of the first die 3 is provided with a first die solder joint 1, and the first die solder joint 1 is connected to a gold wire 2. The first die solder joint 1 is connected to the pins of the carrier plate 8 through the gold wire 2.
[0017] In the embodiments, the inside of the carrier plate 8 is provided with a carrier plate internal wiring 9, and the bottom end of the carrier plate 8 is connected to a tin ball solder joint 10 through tin paste. The top of the carrier plate 8 is covered with a plastic packaging film 12 through pressing.
[0018] The embodiments include the following steps: S1: incoming inspection, confirming wafer chip model, and cleaning and automatic optical inspection of the product to check whether there are incoming defects of the product; S2: redistribution process, flip-chip second die 5 pins are connected to corresponding second die solder bumps 7 through redistribution, facilitating flip-chip and signal connection; S3: wafer grinding and cutting, the first die 3 and the second die 5 are respectively ground and cut, and the bare chips are picked up and placed on corresponding carriers for classified management and storage; S4: carrier plate confirmation, carrier plate 8 shipment report is compared with product specification book to confirm carrier plate model, size, layer number, surface treatment process, sampling point size parameter, and automatic optical inspection incoming defect and size deviation; S5: Wafer flip, take out the second die 5, flip 180° face down, the second die solder bumps 7 on the second die 5 are aligned with the pin positions on the carrier board 8, and are pressed down and heated, the second die solder bumps 7 are dissolved and solidified, the second die 5 is fixed on the carrier board 8, and the second die solder bumps 7 establish electrical connection with the pins of the carrier board 8; S6: Underfill curing, the thermal expansion coefficients of the second die solder bumps 7 and the carrier board 8 are different, and the tin balls and the carrier board connection points are prone to breakage under extreme conditions. The underfill adhesive 11 is injected at the connection between the second die solder bumps 7 and the carrier board 8, the gap is filled by capillary effect or preforming, and after the material is cured, an adhesive layer and a support structure are formed, which can relieve the stress caused by the difference in thermal expansion coefficients, thereby improving the impact resistance and thermal fatigue resistance of the package; S7: Dispensing, uniformly dispensing the organic epoxy resin adhesive 4 on the back of the second die 5; S8: Binding: take out the first die 3, paste the back of the first die 3 on the back of the second die 5 with the front solder joints facing up; at the same time, use gold wires 2 to connect the solder joints 1 on the first die 3 with the pins on the carrier board 8 to establish electrical connection; S9: Plastic packaging, a technology that tightly wraps a plastic film 12 on the surface of an object by heating or pressurizing, mainly used for protecting, sealing or beautifying products; S10: Ball planting, tin paste is first printed on the carrier board 8, and then tin ball solder joints 10 of a certain size are added on top.
[0019] In this embodiment, the automatic optical inspection in steps S1 and S4 is to image the physical characteristics of the product by optical scanning, and then compare with the standard parameter database, recognize the defect position by image processing and mark display, finally output the result, and propose unqualified products.
[0020] In this embodiment, the re-wiring process in step S2 includes the following operation steps: 1) First insulating layer preparation, a layer of polyimide is coated on the front surface of the second die (5) to isolate the circuit layer and the chip protection layer from direct contact, thereby playing a buffering protection role, and then a window is exposed and developed above the aluminum pad corresponding to the chip to expose the aluminum pad, which serves as a connection window between the second die (5) and the re-wiring circuit layer; 2) First UBM barrier layer preparation, using sputtering or electroplating method, the barrier layer metal is plated on the first layer of polyimide, generally using titanium and copper metal as the barrier layer, or using nickel gold, which is selected according to the product and process, and the metal must have the characteristics of high barrier to metal diffusion; 3) Circuit layer preparation, coating photoresist, according to the designed circuit for exposure and development, copper electroplating solution electroplating circuit, according to the specification of plating solution, product requirements, process specification matching, adjusting the corresponding specification parameters, plating solution specification is PH value 6-9; Temperature 50-60℃; Electroplating time is 30min-1h; 4) The second layer of the insulating layer is prepared, and a polyimide layer is coated on the processed wafer, the height requirement is higher than that of the circuit layer, the circuit layer is covered, the circuit layer is isolated from the outside, and the protection effect is achieved, and then exposure and development are carried out at the corresponding position. The windowing is used as a circuit layer and external electrical connection channel; 5) The second UBM barrier layer is prepared, and the preparation method is the same as that of the first UBM barrier layer, copper and tin silver are prone to metal diffusion after long-term use, and a barrier layer is needed to block the reaction of the two metals; 6) Tin silver bump preparation, copper column, nickel barrier layer and tin alloy three-layer structure are formed by electroplating process, vertical interconnection of chip and interposer or circuit board is realized, tin silver bump is mainly used for electrical connection in semiconductor packaging process, and the core purpose is to provide high reliability connection, improve packaging density and optimize heat dissipation performance to meet the needs of advanced packaging technology.
[0021] For those skilled in the art, it is obvious that the present application is not limited to the details of the above exemplary embodiments, and the present application can be realized in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, the scope of the present application is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims involved.
[0022] In addition, it should be understood that although the present specification is described in terms of embodiments, each embodiment does not contain only one independent technical solution, and the description manner of the specification is only for the sake of clarity, and the skilled person should regard the specification as a whole, and the technical solutions in each embodiment can be combined to form other embodiments which can be understood by the skilled person.
Claims
1. A hybrid package technology stacking structure, characterized by: It includes a second bare chip (5) and a carrier plate (8), the second bare chip (5) is flip-chip arranged, and the bottom of the second bare chip (5) is provided with a rewiring layer (6), the bottom of the rewiring layer (6) is provided with a second bare chip solder bump (7), and the second bare chip solder bump (7) is connected with the pin at the top of the carrier plate (8), and the rewiring layer (6) and the carrier plate (8) are filled with a bottom filling glue (11) at the periphery of the second bare chip solder bump (7); The top of the second bare chip (5) is coated with an organic epoxy resin adhesive (4), and the top of the organic epoxy resin adhesive (4) is adhered with a first bare chip (3), the top of the first bare chip (3) is provided with a first bare chip solder joint (1), and the first bare chip solder joint (1) is connected with a gold wire (2), and the first bare chip solder joint (1) is connected with the pin of the carrier plate (8) through the gold wire (2).
2. The hybrid package technology stacking structure according to claim 2, characterized in that: The inside of the carrier plate (8) is provided with a carrier plate internal wiring (9), and the bottom of the carrier plate (8) is connected with a tin ball solder joint (10) through tin paste, and the top of the carrier plate (8) is covered with a plastic packaging film (12) through pressing.
3. The method of claim 1, wherein: It includes the following steps: S1: incoming inspection, confirming wafer chip model, and cleaning and automatic optical inspection of products to check whether there are product incoming defects; S2: rewiring process, flip-chip second bare chip (5) pin, connect the pin to the corresponding second bare chip solder bump (7) through rewiring, facilitate flip-chip and signal connection; S3: wafer grinding and cutting, the first bare chip (3) and the second bare chip (5) are respectively ground and cut, and the bare crystal is picked up and placed on the corresponding carrier for classification management and storage; S4: carrier plate confirmation, carrier plate (8) shipment report is compared with product specification book to confirm carrier plate model, size, layer number, surface treatment process, sampling point size parameter, and automatic optical inspection incoming defect and size deviation; S5: wafer flip-chip, take out the second bare chip (5), turn over 180° with the front down, align the second bare chip solder bump (7) on the second bare chip (5) with the pin position on the carrier plate (8), press down and heat, the second bare chip solder bump (7) is dissolved and solidified, the second bare chip (5) is fixed on the carrier plate (8), and the second bare chip solder bump (7) and the pin of the carrier plate (8) establish electrical connection; S6: Underfill bottom filling solidification, the thermal expansion coefficient of the second bare chip solder bump (7) and the carrier plate (8) is different, the tin ball and the carrier plate connection point is easy to break under extreme conditions. Inject the bottom filling glue 11 at the connection between the second bare chip solder bump (7) and the carrier plate (8), fill the gap by using capillary effect or preforming method, form an adhesive layer and a support structure after the material is solidified, relieve the stress caused by the difference in thermal expansion coefficient, thereby improve the performance of packaging impact resistance and thermal fatigue resistance; S7: dispensing, uniformly dispensing the organic epoxy resin adhesive 4 on the back of the second bare chip (5); S8: Binding: take out the first die (3), stick the back of the first die (3) to the back of the second die (5), with the front solder joints facing up; at the same time, use gold wires (2) to connect the solder joints (1) on the first die (3) to the pins on the carrier board (8), establishing an electrical connection; S9: Plastic encapsulation, a technique that tightly wraps a plastic film 12 around the surface of an object through heating or pressure, mainly used to protect, seal, or beautify products; S10: Ball planting, first print solder paste onto the carrier board (8), then add solder balls (10) of a certain size on top.
4. The method of claim 3, wherein: The automatic optical inspection in steps S1 and S4 is an optical scanning imaging of the physical characteristics of the product, which is then compared with a standard parameter database, and the defect position is identified and marked through image processing, and the final output result is obtained, and unqualified products are proposed.
5. The method of claim 3, wherein: The re-wiring process in step S2 includes the following operation steps: 1) First insulation layer preparation: coat a layer of polyimide on the front surface of the second die (5), then expose and develop a window on the aluminum pad to expose the aluminum pad, which serves as a connection window between the second die (5) and the re-wiring layer; 2) First UBM barrier layer preparation: use sputtering or chemical plating to plate the barrier layer metal on the first layer of polyimide; 3) Circuit layer preparation: coat photoresist, expose and develop according to the designed circuit, and electroplate the circuit with copper electroplating solution, according to the specifications of the plating solution, product requirements, process specifications, and corresponding specification parameters, the plating solution specifications are PH 6-9; temperature 50-60°C; electroplating time 30min-1h; 4) Second insulation layer preparation: coat a layer of polyimide on the processed wafer, with a higher height than the circuit layer, covering the circuit layer and isolating the circuit layer from external contact, and then expose and develop at the corresponding position to form a window, which serves as an electrical connection channel between the circuit layer and the outside; 5) Second UBM barrier layer preparation: the preparation method is the same as that of the first UBM barrier layer preparation; 6) Tin-silver bump preparation: form a three-layer structure of copper pillar, nickel barrier layer, and tin alloy through electroplating process to realize vertical interconnection between the chip and the interposer or circuit board.