Methods to reduce resource overhead during data resampling
By calculating the sampling rate ratio and difference to control the FIFO read/write pointers, interpolation and decimation operations are transformed into FIFO read/write operations, solving the problem of high resource consumption in existing technologies, achieving rate matching with low resource overhead, and improving system flexibility and scalability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI QIMINGXIN SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2026-01-21
- Publication Date
- 2026-05-26
AI Technical Summary
Existing technologies often rely on high-frequency clocks and large-capacity FIFOs during data resampling, especially when the difference between input and output sampling rates is small. This leads to problems such as excessive resource consumption, difficulty in timing convergence, and increased circuit design complexity.
By calculating the ratio and absolute difference between the input and output sampling rates, the read and write pointer operations of the FIFO are controlled to achieve rate matching, avoid using high-frequency clocks and large-depth FIFOs, and transform interpolation and decimation operations into FIFO read and write pointer scheduling, thereby reducing resource overhead.
Without relying on high-frequency clocks and large-capacity FIFOs, low-resource-overhead rate matching is achieved, improving system flexibility and scalability while reducing chip resource consumption.
Smart Images
Figure CN121541820B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital circuit technology, and in particular to a method for reducing resource overhead during data resampling. Background Technology
[0002] In digital signal processing systems, data resampling is a fundamental operation that converts the sampling rate of an input data stream to another sampling rate. It is widely used in communication signal links, audio and video processing, circuit system clock matching, and data exchange between modules within digital chips. Typically, the resampling process includes three stages: interpolation, filtering, and decimation. Among these, the interpolation and decimation steps are used to achieve rate matching and are the key steps in the entire resampling process.
[0003] In existing technologies, common solutions for achieving rate conversion between input and output sampling rates include using high-frequency clock-triggered polyphase filter structures, Farrow-structured variable fractional delay filters, or using large-depth FIFOs (First-In-First-Out) for data buffering and rate balancing. However, these solutions often suffer from the following drawbacks when the sampling rate conversion ratio changes or the difference between input and output sampling rates is small:
[0004] 1. Multiphase interpolators or decimators based on high-frequency clocks typically require generating a high-frequency clock signal corresponding to the least common multiple of the input and output sampling rates to schedule interpolation or decimation operations. As the difference between the input and output rates decreases, the frequency of this least common multiple clock may increase dramatically, leading to a surge in system clock design complexity and significantly increasing the chip's clock tree load, dynamic power consumption, and timing convergence pressure.
[0005] 2. While the variable fractional delay filter scheme based on the Farrow structure can adapt to arbitrary sampling rate conversion, its hardware implementation requires multiple fixed-coefficient FIR branches, power calculations of μ, and multi-way weighted summation structures, resulting in significant overall resource overhead. In small digital chips with limited resources or low power requirements, this type of structure is often uneconomical.
[0006] 3. For scenarios where the difference between the input and output sampling rates is small, traditional solutions often rely on FIFOs with larger depths to absorb the cumulative offset of small differences in sampling rates. However, larger capacity FIFOs not only increase on-chip storage resources but also require more complex full / empty management and clock domain traversal designs, thereby increasing overall design cost and area overhead.
[0007] In summary, existing rate matching techniques typically rely on high-frequency clocks, complex interpolation filtering structures, or large-capacity FIFOs. In systems where the sampling rate difference is small but resampling is still required, these methods can lead to excessive resource consumption, timing convergence difficulties, or increased circuit design complexity. Therefore, it is necessary to propose a low-resource-overhead method for achieving rate matching during data resampling that does not rely on high-frequency clocks and large-depth FIFOs.
[0008] This section is intended to provide background or context for understanding the implementation of this application and is for reference only. It should not be construed as an admission by the applicant that this section pertains to prior art that was disclosed before the filing date of this application. Summary of the Invention
[0009] The purpose of this application is to provide a method for reducing resource overhead during data resampling, achieving low resource overhead for rate matching during data resampling without relying on high-frequency clocks and large-depth FIFOs.
[0010] In a first aspect of this application, a method for reducing resource overhead during data resampling is provided, comprising:
[0011] Calculate the ratio between the input sampling rate and the output sampling rate of the rate matching module, and calculate the absolute difference between 1 and the ratio;
[0012] When the input sampling rate is less than the output sampling rate, the rate matching module is controlled to read data from its FIFO buffer according to the read enable signal and the read pointer. After each read, the read pointer is moved forward by one position, and the difference is accumulated successively with the initial value of the absolute difference as the increment. When the accumulated difference is greater than or equal to 1, the read pointer is kept unchanged and read again, and then the accumulated difference is subtracted by 1.
[0013] When the input sampling rate is greater than or equal to the output sampling rate, the rate matching module is controlled to write data into its FIFO buffer according to the write enable signal and the write pointer. After each write, the write pointer is moved forward by one bit, and the absolute difference is accumulated successively with the initial value of the absolute difference as the increment. When the accumulated result of the absolute difference is greater than or equal to 1, the write enable signal is pulled low and the currently written data is discarded. Then, the accumulated result of the absolute difference is subtracted by 1.
[0014] In a preferred embodiment, it also includes:
[0015] The rate matching module outputs the data in its FIFO buffer to a polynomial filter, and the data output by the rate matching module is filtered by the polynomial filter.
[0016] In a preferred embodiment, the method further includes setting a flag based on the relationship between the input sampling rate and the output sampling rate.
[0017] In a preferred embodiment, the step of setting the flag based on the magnitude relationship between the input sampling rate and the output sampling rate further includes:
[0018] When the ratio is less than 1, the flag is set to 0 and indicates that the input sampling rate is less than the output sampling rate;
[0019] When the ratio is greater than or equal to 1, the flag is set to 1 and indicates that the input sampling rate is greater than or equal to the output sampling rate.
[0020] In a preferred embodiment, the least common multiple of the input sampling rate and the output sampling rate is much greater than the input sampling rate and the output sampling rate.
[0021] In a preferred embodiment, the difference between the input sampling rate and the output sampling rate is less than a preset threshold.
[0022] In a preferred embodiment, the preset threshold is 1.
[0023] In a preferred embodiment, after subtracting 1 from the accumulated result of the absolute differences, the method further includes:
[0024] After each read or write operation, the accumulated result of the absolute difference after subtracting 1 is still accumulated, using the initial value of the absolute difference as the increment.
[0025] In a second aspect of this application, a digital circuit is provided, the digital circuit including a rate matching module and a polynomial filter;
[0026] The rate matching module includes a FIFO buffer. The rate matching module receives data at an input sampling rate and stores it in the FIFO buffer, and outputs data from the FIFO buffer at an output sampling rate. The polynomial filter performs filtering processing on the data output by the FIFO buffer.
[0027] The rate matching module further includes a control unit, which calculates the ratio between the input sampling rate and the output sampling rate and calculates the small absolute difference between 1 and the ratio;
[0028] When the input sampling rate is less than the output sampling rate, the control unit reads data from the FIFO buffer according to the read enable signal and the read pointer. After each read, the read pointer is moved forward by one position, and the absolute difference is accumulated successively with the initial value of the absolute difference as the increment. When the accumulated result of the absolute difference is greater than or equal to 1, the control unit keeps the read pointer unchanged and reads again, and then subtracts 1 from the accumulated result of the absolute difference.
[0029] When the input sampling rate is greater than or equal to the output sampling rate, the control unit writes data into the FIFO buffer according to the write enable signal and the write pointer. After each write, the write pointer is moved forward by one bit, and the absolute difference is accumulated successively with the initial value of the absolute difference as the increment. When the accumulated result of the absolute difference is greater than or equal to 1, the control unit pulls the write enable signal low and discards the currently written data, and then subtracts 1 from the accumulated result of the absolute difference.
[0030] In a third aspect of this application, a non-transitory computer-readable storage medium is provided, wherein computer-executable instructions are stored therein, which, when executed by a processor, implement the steps of the aforementioned method.
[0031] In a fourth aspect of this application, a computer program product is provided, the computer program product including computer-executable instructions that, when executed by a processor, implement the steps in the aforementioned method.
[0032] It should be understood that, within the scope of this invention, the above-described technical features of this invention and the technical features specifically described below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be described in detail here. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. It should be understood that the accompanying drawings described below are merely some implementation examples of the present invention, and those skilled in the art can obtain other implementation examples based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the structure of a digital circuit according to one embodiment of this application.
[0035] Figure 2 This is a flowchart illustrating a method for reducing resource overhead during data resampling according to one embodiment of this application.
[0036] Figure 3 This is the operation flow of the data resampling process according to one embodiment of this application. Detailed Implementation
[0037] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0038] Explanation of some concepts:
[0039] Farrow architecture: A digital filter design for achieving high performance and variable fractional delay. Its core structure consists of a set of parallel sub-filters with fixed coefficients (typically polynomial coefficients) and an adjustable fractional delay parameter control unit. The input signal is passed through each sub-filter in parallel, and the outputs of each sub-filter are then polynomially weighted (e.g., using Lagrange interpolation) by the delay parameter. The function of this architecture is to adjust the signal delay in real-time and continuously with low computational complexity (accuracy up to a fraction of the sampling period), and it is widely used in applications requiring fine-grained time-domain tuning, such as digital signal synchronization, sampling rate conversion, and modulation / demodulation.
[0040] Rate matching module: In digital signal processing and communication systems, it is used to adjust the input rate and output rate of data streams to keep data continuous, stable and orderly during cross-rate or cross-clock domain transmission, and to avoid data overflow, underread or timing mismatch.
[0041] Polynomial filter: A digital filtering structure that uses polynomial functions to approximate, smooth, or interpolate signals.
[0042] FIFO: A buffer queue based on the "first-in, first-out" rule. Its core structure includes storage units, write pointers, read pointers, and empty / full status flags. It is used to buffer and match rates between data producers and consumers, and can safely realize cross-clock domain data transmission, thereby effectively decoupling system modules and ensuring that data flows in an orderly and reliable manner even in scenarios where the data stream is out of sync or the rate is mismatched.
[0043] The following is a summary of some of the innovative aspects of the implementation methods of this application:
[0044] This invention transforms the interpolation and decimation operations in traditional resampling processes into FIFO read / write pointer scheduling by accumulating the fractional difference between the input and output sampling rates. In interpolation mode, the read pointer is kept stationary to repeatedly read data; in decimation mode, write enable is suppressed to skip input data. This achieves rate matching at extremely low hardware cost without relying on a high-frequency clock corresponding to the least common multiple of the input and output sampling rates, or requiring a large-capacity FIFO or complex polyphase or Farrow filter structures. This significantly reduces resource overhead and enhances the flexibility and scalability of the system implementation. In practical applications, when the input and output sampling rates are in the hundreds of MHz range and differ by only kHz, a FIFO depth of only 8 is sufficient to achieve rate matching.
[0045] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0046] The first embodiment of this application relates to a method for reducing resource overhead during data resampling, applicable to digital circuits including a fractional rate conversion module and a farrow filter, the structure of which is as follows: Figure 1 As shown, the rate matching module includes a FIFO buffer. The rate matching module receives data at the input sampling rate and stores it in the FIFO buffer, and outputs data from the FIFO buffer at the output sampling rate. A polynomial filter performs filtering processing on the data output by the FIFO buffer.
[0047] In digital design, a FIFO (First-In, First-Out) buffer connects the data initiator and the data receiver. The data initiator sends write control signals to the FIFO buffer, and the data receiver sends read control signals. Based on its internal write and read address relationship, the FIFO buffer returns a "full" status indicator to the data initiator and a "empty" status indicator to the data receiver. When the initiator detects an invalid "full" status indicator (i.e., the FIFO is not full), it initiates a write enable signal to the FIFO buffer to write data and move the write pointer. When the receiver detects an invalid "empty" status indicator (i.e., the FIFO is not empty), it initiates a read enable signal to the FIFO buffer to read data from the FIFO buffer and move the read pointer.
[0048] The rate matching module operates on two paths: the data initiator to the FIFO buffer and the FIFO buffer to the data receiver, modifying the write and read enable functions twice. Only one path is active at a time. When the input sampling rate is lower than the output sampling rate, indicating a faster data reading speed at the receiver, the rate matching module operates on the FIFO buffer to the data receiver path, performing secondary control on the read enable according to the aforementioned rules. Conversely, it operates on the data initiator to the FIFO buffer path, performing secondary control on the write enable according to the aforementioned rules. The rate matching module may also include a control unit, which implements the operations on both paths: data initiator to FIFO buffer and FIFO buffer to data receiver.
[0049] The method for reducing resource consumption is as follows: Figure 1 As shown, the method includes the following steps:
[0050] Step 101: Calculate the ratio between the input sampling rate and the output sampling rate of the rate matching module, and calculate the absolute difference between 1 and the ratio (i.e., the absolute value of the difference between 1 and the ratio, hereinafter also referred to as the difference). It should be noted that the least common multiple of the input and output sampling rates is much larger than the input and output sampling rates themselves. For example, if the input and output sampling rates are 9 or 10 (in MHz, for example), they are both much smaller than their least common multiple of 90. Similarly, if the input and output sampling rates are 4 or 5 (in MHz, for example), they are both smaller than their least common multiple of 20. The difference between the input and output sampling rates is less than a preset threshold. For example, the preset threshold can be set to 1 (in MHz, for example, or even kHz). For example, if the input and output sampling rates are 9.999 or 10, the difference is 0.001MHz, or 1kHz. The preset threshold can also be set to tens or hundreds of kHz. It should be understood that the preset threshold can be set according to the specific circuit, and this invention does not limit this.
[0051] The method of the present invention further includes setting a flag based on the relationship between the input sampling rate and the output sampling rate. Specifically, the ratio is compared with 1 and a flag is set according to the comparison result. When the result of the ratio is less than 1, the flag is set to 0 and indicates that the input sampling rate is less than the output sampling rate. When the result of the ratio is greater than or equal to 1, the flag is set to 1 and indicates that the input sampling rate is greater than or equal to the output sampling rate.
[0052] First, calculate the ratio of the sampling rates before and after data resampling, denoted as the ratio δ, where δ = fs_in / fs_out, and fs_in is the input sampling rate and fs_out is the output sampling rate. Take the absolute value of the difference between the ratio δ and 1, denoted as the absolute difference γ. The relationship between the ratio δ and 1 is denoted as flag, which represents the relationship between the input sampling rate and the output sampling rate. If δ < 1, flag = 0; otherwise, flag = 1. The values of γ and flag control the write and read enable of the FIFO. Refer to the detailed procedure... Figure 3 As shown, steps 102 and 103 illustrate the interpolation and the specific interpolation method, respectively.
[0053] Step 102: When the flag indicates that the input sampling rate is less than the output sampling rate, the control rate matching module reads data from its FIFO buffer according to the read enable signal and the read pointer. After each read, the read pointer is moved forward by one position, and the difference is accumulated incrementally using the initial value of the difference. When the accumulated difference is greater than or equal to 1, the read pointer remains unchanged and reads again, then the accumulated difference is subtracted by 1. After subtracting 1 from the accumulated difference, after each read, the accumulated difference after subtracting 1 is still accumulated incrementally using the initial value of the difference.
[0054] When the flag is 0, indicating that the input sampling rate is less than the output sampling rate, interpolation is required to satisfy the rate conversion. In this case, on the read side of the FIFO buffer, the difference γ is accumulated based on the read enable (each accumulation uses the original calculated value of γ). When the accumulated value of the difference γ is greater than or equal to 1, the read address remains unchanged for one clock cycle; that is, the address read in the previous clock cycle is read again from the FIFO buffer to achieve the interpolation purpose. Simultaneously, the accumulated value of the difference γ needs to be subtracted by 1, and then accumulation continues. The write side of the FIFO buffer can be processed normally.
[0055] For example, when the input sampling rate is 9 and the output sampling rate is 10, the ratio δ equals 0.9, the difference γ equals 0.1, and the flag equals 0. At this time, the input sampling rate is less than the output sampling rate. During the data reading process from the FIFO buffer, the difference γ is incremented by 0.1 for each data cycle read. When the accumulated value of γ is greater than 1, for example, after reading 10 data cycles, the accumulated value of γ is 1.1. Since the accumulated value of γ is greater than 1, the read pointer keeps the current read address unchanged and reads data from the current address again, thus achieving interpolation.
[0056] Step 103: When the flag indicates that the input sampling rate is greater than or equal to the output sampling rate, the control rate matching module writes data to its FIFO buffer according to the write enable signal and the write pointer. After each write, the write pointer is moved forward by one bit, and the difference is accumulated successively in increments of the initial value of the difference. When the accumulated difference is greater than or equal to 1, the write enable signal is pulled low and the currently written data is discarded. Then, the accumulated difference is subtracted by 1. After subtracting 1 from the accumulated difference, after each write, the accumulated difference after subtracting 1 is still accumulated successively in increments of the initial value of the difference.
[0057] For example, when the flag is 1, meaning the input sampling rate is greater than or equal to the output sampling rate, it indicates that sampling is required to satisfy the rate conversion. In this case, on the write side of the FIFO buffer, the difference γ is accumulated based on the input data validity indication (each accumulation uses the original calculated value of γ). When the accumulated value of the difference γ is greater than or equal to 1, the write enable is pulled low for one clock cycle, meaning one clock cycle of input data is discarded and no data is written, thus achieving the purpose of sampling. Simultaneously, the accumulated value of the difference γ needs to be subtracted by 1, and then accumulation continues. The read side of the FIFO buffer can then process the data according to normal logic.
[0058] For example, when the input sampling rate is 10 and the output sampling rate is 9, the ratio δ equals 1.11, the difference γ equals 0.11, and the flag equals 1. In this case, the input sampling rate is greater than the output sampling rate. During the writing process to the FIFO buffer, the difference γ increments by 0.11 for each data cycle written. When the accumulated value of the difference γ is greater than 1, for example, after writing 10 data cycles, the accumulated value of γ is 1.1. The write enable is then pulled low, and the data to be written in the next cycle is discarded, thus achieving data sampling.
[0059] Furthermore, the method also includes: the rate matching module outputs the data in its FIFO buffer to a polynomial filter, and the data output by the rate matching module is filtered by the polynomial filter. After interpolation by the rate matching module, the data is recovered by the polynomial filter. The expression for the farrow filter using K-order polynomial approximation is as follows:
[0060] (1-1)
[0061] In Equation 1-1, K represents the order of the polynomial filter, L represents the length of the polynomial filter, and Coeff represents the coefficients of the polynomial filter. Denotes convolution, where
[0062] ,
[0063] This refers to the ratio δ of the input and output sampling rates mentioned in the rate matching module. This refers to the output after processing by the rate matching module, which is the signal after being decremented or interpolated by the rate matching module.
[0064] This invention transforms data interpolation / depreciation operations into write-read operations on a FIFO, achieving rate matching by controlling the write-read logic. Compared to traditional solutions, this approach does not rely on high-frequency clocks and can be implemented using a shallow-depth FIFO, significantly reducing chip resource overhead.
[0065] A second embodiment of this application relates to a digital circuit comprising a rate matching module and a polynomial filter. The rate matching module includes a FIFO buffer, which receives data at an input sampling rate, stores it in the FIFO buffer, and outputs data from the FIFO buffer at an output sampling rate. The polynomial filter filters the data output from the FIFO buffer. The rate matching module also includes a control unit that calculates the ratio between the input sampling rate and the output sampling rate and calculates the absolute difference between 1 and the ratio. Furthermore, the control unit can set a flag based on the magnitude relationship between the input and output sampling rates.
[0066] When the flag indicates that the input sampling rate is less than the output sampling rate, the control unit reads data from the FIFO buffer according to the read enable signal and the read pointer. After each read, the read pointer moves forward by one position, and the absolute difference is incremented sequentially by the initial value of the absolute difference. When the accumulated absolute difference is greater than or equal to 1, the control unit keeps the read pointer unchanged and reads again, then subtracts 1 from the accumulated absolute difference. When the flag indicates that the input sampling rate is greater than or equal to the output sampling rate, the control unit writes data to the FIFO buffer according to the write enable signal and the write pointer. After each write, the write pointer moves forward by one position, and the absolute difference is incremented sequentially by the initial value of the absolute difference. When the accumulated absolute difference is greater than or equal to 1, the control unit pulls the write enable signal low and discards the currently written data, then subtracts 1 from the accumulated absolute difference.
[0067] The first embodiment is a method embodiment corresponding to this embodiment. The technical details in the first embodiment can be applied to this embodiment, and the technical details in this embodiment can also be applied to the first embodiment.
[0068] Accordingly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the various method embodiments of this application. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media do not include transient computer-readable media, such as modulated data signals and carrier waves.
[0069] Furthermore, embodiments of this application also provide a system for reducing resource overhead during data resampling, including a memory for storing computer-executable instructions and a processor; the processor is used to implement the steps in the above-described method embodiments when executing the computer-executable instructions in the memory. The processor may be a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP), Microcontroller Unit (MCU), Neural Processing Unit (NPU), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices. The aforementioned memory may be read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or solid-state drive, etc. The steps of the methods disclosed in the embodiments of this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
[0070] Furthermore, embodiments of this application also provide a computer program product, including computer-executable instructions that, when executed by a processor, implement the steps in the above-described method embodiments.
[0071] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded.
[0072] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Claims
1. A method for reducing resource overhead during data resampling, characterized in that, include: Calculate the ratio between the input sampling rate and the output sampling rate of the rate matching module, and calculate the absolute difference between 1 and the ratio; When the input sampling rate is less than the output sampling rate, the rate matching module is controlled to read data from its FIFO buffer according to the read enable signal and the read pointer. After each read, the read pointer is moved forward by one position, and the absolute difference is accumulated successively with the initial value of the absolute difference as the increment. When the accumulated result of the absolute difference is greater than or equal to 1, the read pointer is kept unchanged and read again, and then the accumulated result of the absolute difference is subtracted by 1. When the input sampling rate is greater than or equal to the output sampling rate, the rate matching module is controlled to write data into its FIFO buffer according to the write enable signal and the write pointer. After each write, the write pointer is moved forward by one bit, and the absolute difference is accumulated successively with the initial value of the absolute difference as the increment. When the accumulated result of the absolute difference is greater than or equal to 1, the write enable signal is pulled low and the currently written data is discarded. Then, the accumulated result of the absolute difference is subtracted by 1.
2. The method for reducing resource overhead during data resampling as described in claim 1, characterized in that, Also includes: The rate matching module outputs the data in its FIFO buffer to a polynomial filter, and the data output by the rate matching module is filtered by the polynomial filter.
3. The method for reducing resource overhead during data resampling as described in claim 1, characterized in that, Also includes: A flag is set based on the relationship between the input sampling rate and the output sampling rate.
4. The method for reducing resource overhead during data resampling as described in claim 3, characterized in that, The step of setting the flag based on the relationship between the input sampling rate and the output sampling rate further includes: When the result of the ratio is less than 1, the flag is set to 0 and indicates that the input sampling rate is less than the output sampling rate; When the ratio is greater than or equal to 1, the flag is set to 1 and indicates that the input sampling rate is greater than or equal to the output sampling rate.
5. The method for reducing resource overhead during data resampling as described in claim 1, characterized in that, The difference between the input sampling rate and the output sampling rate is less than a preset threshold.
6. The method for reducing resource overhead during data resampling as described in claim 1, characterized in that, After subtracting 1 from the sum of the absolute differences, the result also includes: After each read or write operation, the accumulated result of the absolute difference after subtracting 1 is still accumulated, using the initial value of the absolute difference as the increment.
7. A digital circuit, characterized in that, Includes a rate matching module and a polynomial filter; The rate matching module includes a FIFO buffer. The rate matching module receives data at an input sampling rate and stores it in the FIFO buffer, and outputs data from the FIFO buffer at an output sampling rate. The polynomial filter performs filtering processing on the data output by the FIFO buffer. The rate matching module further includes a control unit, which calculates the ratio between the input sampling rate and the output sampling rate and calculates the absolute difference between 1 and the ratio. When the input sampling rate is less than the output sampling rate, the control unit reads data from the FIFO buffer according to the read enable signal and the read pointer. After each read, the read pointer is moved forward by one position, and the absolute difference is accumulated successively with the initial value of the absolute difference as the increment. When the accumulated result of the absolute difference is greater than or equal to 1, the control unit keeps the read pointer unchanged and reads again, and then subtracts 1 from the accumulated result of the absolute difference. When the input sampling rate is greater than or equal to the output sampling rate, the control unit writes data into the FIFO buffer according to the write enable signal and the write pointer. After each write, the write pointer is moved forward by one bit, and the absolute difference is accumulated successively with the initial value of the absolute difference as the increment. When the accumulated result of the absolute difference is greater than or equal to 1, the control unit pulls the write enable signal low and discards the currently written data, and then subtracts 1 from the accumulated result of the absolute difference.
8. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the steps of the method as described in any one of claims 1 to 6.
9. A computer program product comprising computer-executable instructions, characterized in that, When executed by a processor, the computer-executable instructions implement the steps of the method according to any one of claims 1 to 6.