Display driving circuit and display panel

Abstract

The invention discloses a display driving circuit and a display panel, the display driving circuit comprises a time schedule controller, a switch module and a display module, the time schedule controller is used for receiving a front-end input signal, the time schedule controller is used for outputting a scanning signal and a first control signal according to the front-end input signal, the switch module comprises an AND gate and a first thin film transistor, the AND gate is electrically connected with the first thin film transistor, the time sequence control module and the display module, the AND gate is used for inputting a second control signal to the first thin film transistor according to the scanning signal and the first control signal, the first thin film transistor is closed according to the second control signal when the front-end input signal is invalid, and the second thin film transistor is closed according to the second control signal when the front-end input signal is invalid. The first thin film transistor is used for being opened according to the second control signal, so that when the front-end input signal is invalid, the sequential control module can close the first thin film transistor through the AND gate to prevent invalid scanning signals from being input into the display module, and abnormal display of the display module is avoided.

Description

Technical Field

[0001] This application relates to the field of display panel technology, specifically to a display driving circuit and a display panel. Background Technology

[0002] In the field of display technology, liquid crystal displays (LCDs) have become widely used in various scenarios such as consumer electronics, automotive displays, and flexible displays due to their mature manufacturing processes, stable display performance, and cost advantages, while organic light-emitting diode (OLED) displays rely on their outstanding characteristics such as high contrast, fast response speed, and wide viewing angle. The pixel architecture of both LCDs and OLEDs relies on the stable scan signal (Scan signal) and data voltage signal (Vdata signal) output by the timing controller (TCON). By controlling the conduction timing of the switch thin-film transistor (Switch TFT), the Vdata signal is accurately written into the pixel capacitor to achieve stable image display. However, the driving circuits of both are highly sensitive to the quality of the input signal. In practical applications, the input signal is easily affected by various interference sources such as power-on voltage fluctuations, electrical fast transient (EFT) tests, electromagnetic interference (EMI) tests, and electrostatic discharge (ESD) tests. This causes the front-end input signal received by the TCON to be disordered, which in turn causes the Scan signal timing to be misaligned. This causes the Switch TFT turn-on timing to deviate from the preset logic, resulting in a series of display abnormalities such as horizontal stripes, flickering, color shift, and image retention. Summary of the Invention

[0003] The purpose of this application is to provide a display driver circuit and a display panel to solve the problem of display abnormalities caused by disordered front-end input signals.

[0004] To achieve the objectives of this application, the following technical solution is provided: In a first aspect, the present invention provides a display driving circuit, comprising: a timing controller for receiving a front-end input signal, the timing controller being configured to output a scan signal and a first control signal according to the front-end input signal; a switching module including an AND gate and a first thin-film transistor, the output terminal of the AND gate being electrically connected to the gate of the first thin-film transistor, the first input terminal of the AND gate being electrically connected to the timing control signal to receive the first control signal, the second input terminal of the AND gate and the source of the first thin-film transistor being both used to input the scan signal, the AND gate being configured to input a second control signal to the first thin-film transistor according to the scan signal and the first control signal; and a display module being electrically connected to the drain of the first thin-film transistor; wherein, when the front-end input signal is invalid, the first thin-film transistor is configured to be turned off according to the second control signal, and when the front-end input signal is invalid, the first thin-film transistor is configured to be turned on according to the second control signal.

[0005] In one embodiment, the timing controller is used to output a data signal according to the front-end input signal; the display module includes an OLED, a second thin-film transistor, a third thin-film transistor, and a first storage capacitor. The gate of the second thin-film transistor is electrically connected to the drain of the first thin-film transistor, the drain of the second thin-film transistor is electrically connected to the gate of the third thin-film transistor, the drain of the third thin-film transistor is electrically connected to the anode of the OLED, the cathode of the OLED is electrically connected to a ground terminal, one end of the first storage capacitor is electrically connected to the source of the third thin-film transistor, and the other end is electrically connected to the gate of the third thin-film transistor. The source of the second thin-film transistor is used to input the data signal, and the source of the third thin-film transistor is used to input a power supply signal. When the front-end input signal is invalid, the second thin-film transistor is turned off; when the front-end input signal is valid, the second thin-film transistor is turned on.

[0006] In one embodiment, the display driving circuit further includes a sustaining module, which is connected to the timing controller, the output of the AND gate, and the anode of the OLED. The sustaining module is used to receive the first control signal, the second control signal, and the data signal. When the input signal is invalid, the sustaining module is used to output the data signal to the anode of the OLED according to the first control signal and the second control signal.

[0007] In one embodiment, the sustaining module includes a fourth thin-film transistor (TFT), a fifth TFT, a sixth TFT, a first resistor, a second resistor, a third resistor, a first capacitor, and a second storage capacitor. The gate of the fourth TFT is electrically connected to the timing controller. The drain of the fourth TFT is electrically connected to the source of both the second and fifth TFTs. The source of the fourth TFT is used to input the data signal. The gates of both the fifth and sixth TFTs are electrically connected to the output of the AND gate. The drain of the fifth TFT is electrically connected to the source of the sixth TFT. The drain of the sixth TFT is electrically connected to the anode of the OLED. The first resistor is connected in series between the timing controller and the gate of the fourth TFT. The second resistor is connected in series between the drain of the fourth TFT and the source of the fifth TFT. One end of the second storage capacitor is electrically connected to the drain of the fifth TFT, and the other end is electrically connected to the third resistor. The end of the third resistor away from the second storage capacitor is electrically connected to the source of the fifth TFT. One end of the first capacitor is electrically connected to the gate of the fourth TFT, and the other end is used to connect to ground.

[0008] In one embodiment, the sustaining module further includes a counter, a fourth resistor, and a seventh thin-film transistor. The counter is electrically connected to both the timing controller and the gate of the seventh thin-film transistor. The source of the seventh thin-film transistor is electrically connected to one end of the third resistor, and the drain of the seventh thin-film transistor is connected to the other end of the third resistor. The fourth resistor is connected in series between the counter and the gate of the fourth thin-film transistor. The timing controller is used to output a third control signal to the counter according to the front-end input signal. The counter is used to output a fourth control signal to the gate of the seventh thin-film transistor according to the third control signal. The seventh thin-film transistor is used to turn on or off according to the fourth control signal.

[0009] In one embodiment, there are multiple display modules, multiple first thin-film transistors, and multiple sustaining modules. The multiple display modules are arranged in a multi-row, multi-column array. The multiple first thin-film transistors are electrically connected to the multiple display modules in a one-to-one correspondence. The multiple sustaining modules are electrically connected to the multiple display modules in a one-to-one correspondence and to the multiple first thin-film transistors in a one-to-one correspondence. At least two first thin-film transistors are electrically connected to the same AND gate.

[0010] In one embodiment, there are multiple display modules arranged in a multi-row, multi-column array, and at least two display modules are electrically connected to the same maintenance module.

[0011] In one embodiment, the timing controller is used to output a data signal according to the front-end input signal; the display module includes a pixel capacitor, a second thin-film transistor and a first storage capacitor, the gate of the second thin-film transistor is electrically connected to the drain of the first thin-film transistor, the drain of the second thin-film transistor is electrically connected to the pixel electrode of the pixel capacitor, the common electrode of the pixel capacitor is used to be electrically connected to a ground terminal, one end of the first storage capacitor is electrically connected to the pixel electrode and the other end is electrically connected to the common electrode, and the source of the second thin-film transistor is used to input the data signal; When the front-end input signal is invalid, the second thin-film transistor is turned off; when the front-end input signal is valid, the second thin-film transistor is turned on.

[0012] In a second aspect, the present invention also provides a display panel, including a gate driver and a display driving circuit according to any one of the embodiments of the first aspect, wherein the gate driver is electrically connected to the timing controller and the source of the first thin-film transistor, and the timing controller is used to control the gate driver to output the scan signal according to the front-end input signal.

[0013] In one embodiment, the display panel further includes a source driver, which is electrically connected to both the timing controller and the display module. The timing controller is used to control the source driver to output a data signal to the display module based on the front-end input signal.

[0014] The display driving circuit provided by this invention includes a timing controller, a switching module, and a display module. The timing controller receives a front-end input signal and outputs a scan signal and a first control signal based on the front-end input signal. The switching module includes an AND gate and a first thin-film transistor (TFT). The output of the AND gate is electrically connected to the gate of the TFT, and the first input of the AND gate is electrically connected to a timing control signal to receive the first control signal. The second input of the AND gate and the source of the TFT are both used to input the scan signal. The AND gate inputs a second control signal to the TFT based on the scan signal and the first control signal. The display module is electrically connected to the drain of the TFT. When the front-end input signal is invalid, the TFT is turned off according to the second control signal; when the front-end input signal is invalid, the TFT is turned on according to the second control signal. This allows the timing control module to turn off the TFT through the AND gate when the front-end input signal is invalid, preventing invalid scan signals from being input to the display module and avoiding abnormal display. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a structural diagram of a display panel according to one embodiment; Figure 2 This is a circuit diagram of a display driver circuit according to one embodiment; Figure 3 This is a circuit diagram of a display driver circuit according to another embodiment; Figure 4 This is a potential diagram of a display driving circuit according to one embodiment; Figure 5 This is a circuit diagram of a display driver circuit according to another embodiment; Figure 6 This is a circuit diagram of a display driver circuit according to another embodiment.

[0017] Explanation of reference numerals in the attached figures: 1000 - Display panel, 100 - Display driver circuit, 10 - Switch module, D1 - AND gate, T1 - First thin-film transistor, 20 - Display module, T2 - Second thin-film transistor, T3 - Third thin-film transistor, C1 - First storage capacitor, P - Pixel capacitor, C2 - Parasitic capacitance, 30 - Holding module, T4 - Fourth thin-film transistor, T5 - Fifth thin-film transistor, T6 - Sixth thin-film transistor, T7 - ​​Seventh thin-film transistor, R1 - First resistor, R2 - Second resistor, R3 - Third resistor, R4 - Fourth resistor, C3 - First capacitor, C4 - Second storage capacitor, D2 - Counter, TCON - Timing controller, GOA - Gate driver, SOC - Source driver, IC - Driver chip, V0 - Front-end input signal, G - Scan signal, S - Data signal, V1 - First control signal, V2 - Second control signal, V3 - Third control signal, V4 - Fourth control signal, Vdd - Power supply signal. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or it can be in a middle component. When a component is said to be "connected" to another component, it can be directly connected to the other component or it may be in a middle component.

[0020] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items.

[0021] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] Please refer to Figure 1This invention provides a display panel 1000, including a gate driver GOA and a display driving circuit 100 according to an embodiment of the invention. The gate driver GOA is electrically connected to a timing controller TCON and the source of a first thin-film transistor T1. The timing controller TCON is used to control the gate driver GOA to output a scan signal G according to a front-end input signal V0. Specifically, the display driving circuit 100 includes multiple display modules 20 arranged in a multi-row, multi-column array. The gate driver GOA outputs scan signals G to the multi-row display modules 20 one-to-one through multiple scan signals extending along the row direction and arranged sequentially along the column direction, so that the multi-row display modules 20 are refreshed row by row.

[0023] In a specific embodiment, the display panel 1000 also includes a source driver SOC. The source driver SOC is electrically connected to both the timing controller TCON and the display module 20. The timing controller TCON controls the source driver SOC to output data signals S to the display module 20 according to the front-end input signal V0. Specifically, the source driver SOC outputs data signals S to the multi-column display modules 20 one-to-one through multiple data signals extending along the column direction and arranged sequentially along the row direction, so that the multi-column display modules 20 write data row by row.

[0024] In a specific embodiment, the display panel 1000 also includes a driver chip IC, which is electrically connected to the timing control module. The driver chip IC is used to output a front-end input signal V0 to the timing control module according to the image information, so that the timing control module controls the gate driver GOA and the source driver SOC to output the corresponding scan signal G and data signal S according to the front-end input signal V0.

[0025] Optionally, the display panel 1000 can be either an OLED panel or an LCD panel, without restriction.

[0026] Please refer to Figures 2 to 4The present invention also provides a display driving circuit 100, which includes a timing controller TCON, a switching module 10, and a display module 20. The timing controller TCON is used to receive a front-end input signal V0 and output a scan signal G and a first control signal V1 according to the front-end input signal V0. The switching module 10 includes an AND gate D1 and a first thin-film transistor T1. The output terminal of the AND gate D1 is electrically connected to the gate of the first thin-film transistor T1. The first input terminal of the AND gate D1 is electrically connected to a timing control signal to receive the first control signal V1. The second input terminal of the AND gate D1 and the source of the first thin-film transistor T1 are both used to input the scan signal G. The AND gate D1 is used to input a second control signal V2 to the first thin-film transistor T1 according to the scan signal G and the first control signal V1. The display module 20 is electrically connected to the drain of the first thin-film transistor T1. When the front-end input signal V0 is invalid, the first thin-film transistor T1 is turned off according to the second control signal V2. When the front-end input signal V0 is invalid, the first thin-film transistor T1 is turned on according to the second control signal V2.

[0027] Specifically, the display driving circuit 100 sequentially passes through the first frame and the second frame. In the first frame, the front-end input signal V0 is a valid signal, and in the second frame, the front-end input signal V0 is an invalid signal. The first thin-film transistor T1 is an N-type thin-film transistor, and the timing controller TCON is used to identify and determine whether the front-end input signal V0 is valid or not. This is provided in the embodiment of the present invention. Figure 3 In the diagram, region A1 corresponds to the potential diagram of the scan signal G and the data signal S when the front-end input signal V0 is invalid, and region A2 corresponds to the potential diagram of the scan signal G and the data signal S when the front-end input signal V0 is valid. This embodiment uses the example of disordered data signal S when the front-end input signal V0 is invalid for illustration.

[0028] In the first frame, when the timing controller TCON detects that the front-end input signal V0 is valid, the timing controller TCON outputs a high-level first control signal V1 to the AND gate D1, and also controls the gate driver GOA to output a valid and high-level scan signal G, and controls the source driver SOC to output a valid data signal S. The AND gate D1 outputs a high-level second control signal V2 to the gate of the first thin-film transistor T1 to turn on the first thin-film transistor, so that the scan signal G can be input to the display module 20 through the first thin-film transistor T1 to refresh the display module 20.

[0029] In the second frame, the front-end input signal V0 fluctuates and becomes disordered due to factors such as electromagnetic interference, signal line crosstalk, or power supply noise. That is, when the aforementioned front-end input signal is invalid, the scan signal G output by the gate driver GOA and the data signal S output by the source driver SOC controlled by the timing control module are different from the target voltage. In other words, both the scan signal G and the data signal S are converted from valid signals to invalid signals.

[0030] At this time, the timing control area detects that the front-end input signal V0 is invalid. The timing controller TCON outputs a low-level first control signal V1 to the AND gate D1, and also controls the gate driver GOA to output an invalid and high-level scan signal G. At the same time, it controls the source driver SOC to output the data signal S for the first frame. The AND gate D1 outputs a low-level second control signal V2 to the gate of the first thin-film transistor T1 to turn off the first thin-film transistor, so that the invalid scan signal G cannot be input to the display module 20 through the first thin-film transistor T1, thereby avoiding abnormal display phenomena such as horizontal stripes, flickering, color shift, and afterimages caused by the display module 20 performing an incorrect refresh process.

[0031] In one implementation, please refer to Figure 2 When the display panel 1000 is an OLED display panel 1000, the display module 20 includes an OLED, a second thin-film transistor T2, a third thin-film transistor T3, and a first storage capacitor C1. The gate of the second thin-film transistor T2 is electrically connected to the drain of the first thin-film transistor T1, the drain of the second thin-film transistor T2 is electrically connected to the gate of the third thin-film transistor T3, the drain of the third thin-film transistor T3 is electrically connected to the anode of the OLED, and the cathode of the OLED is electrically connected to the ground terminal. One end of the first storage capacitor C1 is electrically connected to the source of the third thin-film transistor T3, and the other end is electrically connected to the gate of the third thin-film transistor T3. The source of the second thin-film transistor T2 is used to input the data signal S, and the source of the third thin-film transistor T3 is used to input the power signal Vdd.

[0032] When the current input signal V0 is valid, the first thin-film transistor T1 is turned on, and the scan signal G is input to the gate of the second thin-film transistor T2 through the first thin-film transistor T1 to turn on the second thin-film transistor T2. This allows the data signal S to be input to the third thin-film transistor T3 through the second thin-film transistor T2, causing the third thin-film transistor T3 to turn on according to the data signal S. The OLED receives the power signal Vdd and updates its light-emitting state.

[0033] When the front-end input signal V0 is invalid, the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 are all turned off, so that the invalid scan signal G cannot be input through the first thin-film transistor T1 and the third thin-film transistor T3 is turned off, thereby avoiding erroneous display of the OLED.

[0034] In another implementation, please refer to Figure 3 When the display panel 1000 is an LCD display panel 1000, the display module 20 includes a pixel capacitor P, a second thin-film transistor T2, and a first storage capacitor C1. The gate of the second thin-film transistor T2 is electrically connected to the drain of the first thin-film transistor T1, and the drain of the second thin-film transistor T2 is electrically connected to the pixel electrode of the pixel capacitor P. The common electrode of the pixel capacitor P is used to be electrically connected to a ground terminal. One end of the first storage capacitor C1 is electrically connected to the pixel electrode, and the other end is electrically connected to the common electrode. The source of the second thin-film transistor T2 is used to input a data signal S. Optionally, the display module 20 also includes a parasitic capacitance C2 existing between the pixel electrode and the first thin-film transistor T1.

[0035] In both of the above embodiments, the second thin-film transistor T2 and the third thin-film transistor T3 are both N-type thin-film transistors. When the front-end input signal V0 is valid, the first thin-film transistor T1 is turned on, and the scan signal G is input to the gate of the second thin-film transistor T2 through the first thin-film transistor T1, causing the second thin-film transistor T2 to turn on, so that the data signal S can be input to the pixel electrode through the second thin-film transistor T2. When the front-end input signal V0 is invalid, both the first thin-film transistor T1 and the second thin-film transistor T2 are turned off, so that the invalid data signal S cannot be input to the pixel electrode, thereby avoiding incorrect charging of the pixel capacitor P.

[0036] Furthermore, when the front-end input signal V0 is invalid, causing the display module 20 to fail to refresh and update the display status normally, the first storage capacitor C1 has a limited capacity. Therefore, when the charge stored in the first storage capacitor C1 decreases, the ability of the first storage capacitor C1 to maintain the voltage on the OLED or pixel capacitor P weakens, resulting in a decrease in brightness.

[0037] To solve the above problems, please refer to the following specific implementation method. Figure 2 and Figure 3 The display driving circuit 100 also includes a sustaining module 30, which is connected to the timing controller TCON, the output of AND gate D1 and the anode of the OLED. The sustaining module 30 is used to receive a first control signal V1, a second control signal V2 and a data signal S. When the input signal is invalid, the sustaining module 30 is used to output the data signal S to the anode of the OLED according to the first control signal V1 and the second control signal V2.

[0038] In a specific embodiment, the sustaining module 30 includes a fourth thin-film transistor T4, a fifth thin-film transistor T5, a sixth thin-film transistor T6, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C3, and a second storage capacitor C4. The gate of the fourth thin-film transistor T4 is electrically connected to the timing controller TCON. The drain of the fourth thin-film transistor T4 is electrically connected to the source of the second thin-film transistor T2 and the source of the fifth thin-film transistor T5. The source of the fourth thin-film transistor T4 is used to input the data signal S. The gates of the fifth thin-film transistor T5 and the sixth thin-film transistor T6 are both electrically connected to the output terminal of the AND gate D1. The drain of the fifth thin-film transistor T5 is electrically connected to the source of the second thin-film transistor T2 and the source of the fifth thin-film transistor T6. The source of the sixth thin-film transistor T6 is electrically connected, and the drain of the sixth thin-film transistor T6 is electrically connected to the anode of the OLED. The first resistor R1 is connected in series between the timing controller TCON and the gate of the fourth thin-film transistor T4. The second resistor R2 is connected in series between the drain of the fourth thin-film transistor T4 and the source of the fifth thin-film transistor T5. One end of the second storage capacitor C4 is electrically connected to the drain of the fifth thin-film transistor T5, and the other end is electrically connected to the third resistor R3. The end of the third resistor R3 away from the second storage capacitor C4 is electrically connected to the source of the fifth thin-film transistor T5. One end of the first capacitor C3 is electrically connected to the gate of the fourth thin-film transistor T4, and the other end is used to connect to the ground terminal.

[0039] Among them, the fourth thin-film transistor T4 is an N-type thin-film transistor, while the fifth thin-film transistor T5 and the sixth thin-film transistor T6 are both P-type thin-film transistors.

[0040] In the first frame, when the timing controller TCON recognizes the front-end input signal V0 as a valid signal, the timing controller TCON outputs a high-level first control signal V1 to the AND gate D1 and the gate of the fourth thin-film transistor T4. It also controls the gate driver GOA to output a valid and high-level scan signal G, and simultaneously controls the source driver SOC to output a valid data signal S. The fourth thin-film transistor T4 turns on according to the first control signal V1. Simultaneously, the AND gate D1 outputs a high-level second control signal V2 to the gate of the first thin-film transistor T1, turning on the first thin-film transistor and turning off the fifth and sixth thin-film transistors T5 and T6. The scan signal G is input to the gate of the second thin-film transistor T2 through the first thin-film transistor T1, turning on the second thin-film transistor T2. The valid data signal S is sequentially input to the gate or pixel electrode of the third thin-film transistor T3 through the fourth thin-film transistor T4 and the second thin-film transistor T2, enabling the display module 20 to display normally.

[0041] In the second frame, when the timing controller TCON detects that the front-end input signal V0 is invalid, the timing controller TCON outputs a low-level first control signal V1 to the gates of AND gate D1 and the fourth thin-film transistor T4. It also controls the gate driver GOA to output an invalid and high-level scan signal G, and simultaneously controls the source driver SOC to output the data signal S from the first frame. AND gate D1 outputs a low-level second control signal V2, causing both the first and second thin-film transistors T2 to turn off, and both the fifth and sixth thin-film transistors T5 and T6 to turn on.

[0042] In the first frame, the fourth thin-film transistor T4 turns on upon receiving a high-level first control signal V1, while the first capacitor C3 stores the high-level first control signal V1 during the first frame. In the second frame, the first control signal V1 switches from high to low. Due to the delay effect of the first capacitor C3, the turning-off speed of the fourth thin-film transistor T4 is slowed down, making its turning-off speed slower than that of the first thin-film transistor T1, the second thin-film transistor T2, the fifth thin-film transistor T5, and the sixth thin-film transistor T6.

[0043] The valid data signal S of the first frame is input to the anode or pixel electrode of the OLED through the fourth thin-film transistor T4, the fifth thin-film transistor T5, and the sixth thin-film transistor T6. In another invention, it is also input to the second storage capacitor C4 through the fourth thin-film transistor T4 and the fifth thin-film transistor T5 so that the second storage capacitor C4 stores the valid data signal S of the first frame. When the scan signal G is low, the second control signal V2 output by the AND gate D1 is high, which turns off the fifth thin-film transistor T5 and the sixth thin-film transistor T6. At this time, the second storage capacitor C4 discharges to the OLED or pixel capacitor P to maintain the display state of the display module 20 in the first frame.

[0044] In this process, since there are risks of voltage drop and overcurrent due to the different voltage adaptation ranges between the data signal S and the second storage capacitor C4 when the data signal S is input to the second storage capacitor C4, the second resistor R2 and the third resistor R3 divide the voltage of the data signal S during the process of the data signal S passing through the fourth thin film transistor T4 and the fifth thin film transistor T5. This reduces or amplifies the voltage of the data signal S to the voltage adaptation range of the second storage capacitor C4, thus offsetting the effect of voltage drop and preventing excessive current from damaging the second storage capacitor C4.

[0045] When the front-end input signal V0 is invalid for multiple consecutive frames, the second storage capacitor C4 will receive a valid data signal S from the first frame and charge when both the first control signal V1 and the second control signal V2 are low in each frame. Since the second storage capacitor C4 has residual voltage after the previous charging and discharging, there is a problem of charge amount offset when the second storage capacitor C4 is continuously charged. To solve this problem, in a specific embodiment, the maintenance module 30 further includes a counter D2, a fourth resistor R4, and a seventh thin-film transistor T7. The counter D2 is electrically connected to the timing controller TCON and the gate of the seventh thin-film transistor T7. The source of the seventh thin-film transistor T7 is electrically connected to one end of the third resistor R3, and the drain of the seventh thin-film transistor T7 is connected to the other end of the third resistor R3. The fourth resistor R4 is connected in series between the counter D2 and the gate of the fourth thin-film transistor T4.

[0046] The timing controller TCON is used to output a third control signal V3 to the counter D2 according to the front-end input signal V0. The counter D2 is used to output a fourth control signal V4 to the gate of the seventh thin film transistor T7 according to the third control signal V3. The seventh thin film transistor T7 is used to turn on or off according to the fourth control signal V4.

[0047] Specifically, the seventh thin-film transistor T7 is an N-type thin-film transistor, and the third control signal V3 can be a frame start signal, an STV signal, etc., without restriction. When the timing control signal determines that the front-end input signal V0 is an invalid signal in at least two consecutive frames, the timing control signal outputs the third control signal V3 to the counter D2. The counter D2 outputs a high-level fourth control signal V4 according to the third control signal V3, which turns on the fourth thin-film transistor T4 and the seventh thin-film transistor T7. When the fifth thin-film transistor T5 and the sixth thin-film transistor T6 are turned on, the second storage capacitor C4 releases its charge through the short circuit between the fifth thin-film transistor T5 and the seventh thin-film transistor T7 and the ground terminal, improving the charging accuracy of the second storage capacitor C4.

[0048] In one implementation, please refer to Figure 5The system comprises multiple display modules 20, multiple first thin-film transistors (TFTs) T1, and multiple sustaining modules 30. The display modules 20 are arranged in a multi-row, multi-column array. Each TFT T1 is electrically connected to a corresponding display module 20, and each sustaining module 30 is electrically connected to both the display modules 20 and the TFTs T1. At least two TFTs T1 are electrically connected to the same AND gate D1. Optionally, multiple display modules 20 located in the same row are electrically connected to the output of the same AND gate D1 via corresponding TFTs T1, and the same applies to multiple sustaining modules 30 in the same row. This reduces the number of TFTs T1, decreases the space occupied by non-display module 20 components, and reduces structural design complexity.

[0049] In another implementation, please refer to Figure 6 At least two display modules 20 are electrically connected to the same sustaining module 30. Specifically, the gates of the third thin-film transistors T3 of the multiple display modules 20 electrically connected to the same sustaining module 30 are electrically connected to the drains of the same second thin-film transistors T2 to reduce the number of second thin-film transistors T2. Optionally, multiple display modules 20 located in the same column or row are electrically connected to the same sustaining module 30 without limitation, in order to reduce the space occupied by the sustaining module 30 and the structural complexity of the display driving circuit 100.

[0050] In a specific embodiment, the second thin-film transistor T2, the third thin-film transistor T3, the first storage capacitor C1, the parasitic capacitor C2, the OLED, the pixel capacitor P of the display module 20, and the fourth thin-film transistor T4 and the sixth thin-film transistor T6 of the maintenance module 30 are all disposed within the effective display area of ​​the display panel 1000. The timing controller TCON, the AND gate D1, and other components of the maintenance module 30 are disposed on a circuit board located in the non-display area to reduce the space occupied in the display area and increase the aperture ratio of the display panel 1000.

[0051] The display driving circuit 100 provided by the present invention comprises a timing controller TCON, a switching module 10, and a display module 20. The timing controller TCON receives a front-end input signal V0 and outputs a scan signal G and a first control signal V1 according to the front-end input signal V0. The switching module 10 includes an AND gate D1 and a first thin-film transistor T1. The output terminal of the AND gate D1 is electrically connected to the gate of the first thin-film transistor T1, and the first input terminal of the AND gate D1 is electrically connected to the timing control signal to receive the first control signal V1. The second input terminal of the AND gate D1 and the source of the first thin-film transistor T1 are both used to input the scan signal G. AND gate D1 is used to input the second control signal V2 to the first thin-film transistor T1 according to the scan signal G and the first control signal V1. The display module 20 is electrically connected to the drain of the first thin-film transistor T1. When the front-end input signal V0 is invalid, the first thin-film transistor T1 is turned off according to the second control signal V2. When the front-end input signal V0 is invalid, the first thin-film transistor T1 is turned on according to the second control signal V2. This allows the timing control module to turn off the first thin-film transistor T1 through AND gate D1 when the front-end input signal V0 is invalid, thereby preventing the invalid scan signal G from being input to the display module 20 and avoiding abnormal display by the display module 20.

[0052] In the description of the embodiments of this application, it should be noted that the orientation or positional relationship of the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and other indicators are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0053] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art will understand that all or part of the processes for implementing the above embodiments and equivalent variations made in accordance with the claims of this application are still within the scope of this application.

Claims

1. A display driving circuit, characterized in that, include: A timing controller is used to receive front-end input signals, and the timing controller is used to output a scan signal and a first control signal according to the front-end input signals; A switching module includes an AND gate and a first thin-film transistor. The output of the AND gate is electrically connected to the gate of the first thin-film transistor. The first input of the AND gate is electrically connected to the timing control signal to receive the first control signal. The second input of the AND gate and the source of the first thin-film transistor are both used to input the scan signal. The AND gate is used to input a second control signal to the first thin-film transistor according to the scan signal and the first control signal. The display module is electrically connected to the drain of the first thin-film transistor; Specifically, when the front-end input signal is invalid, the first thin-film transistor is turned off according to the second control signal; when the front-end input signal is invalid, the first thin-film transistor is turned on according to the second control signal.

2. The display driving circuit according to claim 1, characterized in that, The timing controller is used to output data signals according to the front-end input signals; The display module includes an OLED, a second thin-film transistor, a third thin-film transistor, and a first storage capacitor. The gate of the second thin-film transistor is electrically connected to the drain of the first thin-film transistor, the drain of the second thin-film transistor is electrically connected to the gate of the third thin-film transistor, the drain of the third thin-film transistor is electrically connected to the anode of the OLED, and the cathode of the OLED is electrically connected to a ground terminal. One end of the first storage capacitor is electrically connected to the source of the third thin-film transistor, and the other end is electrically connected to the gate of the third thin-film transistor. The source of the second thin-film transistor is used to input the data signal, and the source of the third thin-film transistor is used to input the power signal. When the front-end input signal is invalid, the second thin-film transistor is turned off; when the front-end input signal is valid, the second thin-film transistor is turned on.

3. The display driving circuit according to claim 2, characterized in that, The display driving circuit further includes a sustaining module, which is connected to the timing controller, the output of the AND gate, and the anode of the OLED. The sustaining module is used to receive the first control signal, the second control signal and the data signal. When the terminal input signal is invalid, the sustaining module is used to output the data signal to the anode of the OLED according to the first control signal and the second control signal.

4. The display driving circuit according to claim 3, characterized in that, The sustaining module includes a fourth thin-film transistor (TFT), a fifth TFT, a sixth TFT, a first resistor, a second resistor, a third resistor, a first capacitor, and a second storage capacitor. The gate of the fourth TFT is electrically connected to the timing controller. The drain of the fourth TFT is electrically connected to the source of both the second and fifth TFTs. The source of the fourth TFT is used to input the data signal. The gates of both the fifth and sixth TFTs are electrically connected to the output of the AND gate. The drain of the fifth TFT is electrically connected to the source of the sixth TFT. The drain of the sixth TFT is electrically connected to the anode of the OLED. The first resistor is connected in series between the timing controller and the gate of the fourth TFT. The second resistor is connected in series between the drain of the fourth TFT and the source of the fifth TFT. One end of the second storage capacitor is electrically connected to the drain of the fifth TFT, and the other end is electrically connected to the third resistor. The end of the third resistor furthest from the second storage capacitor is electrically connected to the source of the fifth TFT. One end of the first capacitor is electrically connected to the gate of the fourth TFT, and the other end is used to connect to ground.

5. The display driving circuit according to claim 4, characterized in that, The sustaining module further includes a counter, a fourth resistor, and a seventh thin-film transistor. The counter is electrically connected to both the timing controller and the gate of the seventh thin-film transistor. The source of the seventh thin-film transistor is electrically connected to one end of the third resistor, and the drain of the seventh thin-film transistor is electrically connected to the other end of the third resistor. The fourth resistor is connected in series between the counter and the gate of the fourth thin-film transistor. The timing controller is used to output a third control signal to the counter according to the front-end input signal, the counter is used to output a fourth control signal to the gate of the seventh thin-film transistor according to the third control signal, and the seventh thin-film transistor is used to turn on or off according to the fourth control signal.

6. The display driving circuit according to claim 3, characterized in that, There are multiple display modules, first thin-film transistors, and sustaining modules. The multiple display modules are arranged in a multi-row, multi-column array. The multiple first thin-film transistors are electrically connected to the multiple display modules in a one-to-one correspondence. The multiple sustaining modules are electrically connected to the multiple display modules in a one-to-one correspondence and to the multiple first thin-film transistors in a one-to-one correspondence. At least two first thin-film transistors are electrically connected to the same AND gate.

7. The display driving circuit according to claim 3, characterized in that, There are multiple display modules, which are arranged in a multi-row, multi-column array, and at least two display modules are electrically connected to the same maintenance module.

8. The display driving circuit according to claim 1, characterized in that, The timing controller is used to output data signals according to the front-end input signals; The display module includes a pixel capacitor, a second thin-film transistor, and a first storage capacitor. The gate of the second thin-film transistor is electrically connected to the drain of the first thin-film transistor, and the drain of the second thin-film transistor is electrically connected to the pixel electrode of the pixel capacitor. The common electrode of the pixel capacitor is used to be electrically connected to a ground terminal. One end of the first storage capacitor is electrically connected to the pixel electrode, and the other end is electrically connected to the common electrode. The source of the second thin-film transistor is used to input the data signal. When the front-end input signal is invalid, the second thin-film transistor is turned off; when the front-end input signal is valid, the second thin-film transistor is turned on.

9. A display panel, characterized in that, The device includes a gate driver and a display driving circuit as described in any one of claims 1-8, wherein the gate driver is electrically connected to both the timing controller and the source of the first thin-film transistor, and the timing controller is configured to control the gate driver to output the scan signal according to the front-end input signal.

10. The display panel according to claim 9, characterized in that, The display panel also includes a source driver, which is electrically connected to both the timing controller and the display module. The timing controller is used to control the source driver to output a data signal to the display module according to the front-end input signal.

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